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From: "Zhang, Hawking" <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
To: "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: "Zhu, James" <James.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Date: Wed, 27 Nov 2019 03:24:12 +0000	[thread overview]
Message-ID: <DM5PR12MB1418C276613502A0CD12F1B6FC440@DM5PR12MB1418.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1574796818-11648-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>

[AMD Official Use Only - Internal Distribution Only]

Hi James,

Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.

Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt

Clear SDMA and HDP EDC counter in GPR workarounds.

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
 
 #include "amdgpu_ras.h"
 
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
 #define GFX9_NUM_GFX_RINGS     1
 #define GFX9_MEC_HPD_SIZE 4096
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
    { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+   { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+   { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+   { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
 };
 
 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4

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WARNING: multiple messages have this Message-ID (diff)
From: "Zhang, Hawking" <Hawking.Zhang@amd.com>
To: "Zhu, James" <James.Zhu@amd.com>,
	"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Cc: "Zhu, James" <James.Zhu@amd.com>
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt
Date: Wed, 27 Nov 2019 03:24:12 +0000	[thread overview]
Message-ID: <DM5PR12MB1418C276613502A0CD12F1B6FC440@DM5PR12MB1418.namprd12.prod.outlook.com> (raw)
Message-ID: <20191127032412.NAGOZylKcrbXhDtahasGU-Q5wMYyknAVjdIruE3EhPI@z> (raw)
In-Reply-To: <1574796818-11648-1-git-send-email-James.Zhu@amd.com>

[AMD Official Use Only - Internal Distribution Only]

Hi James,

Arcturus and vg20 have different SDMA instances so that the common edc counter array can't cover both ASICs. The edc counter initialization has to be either keeping in IP specific ecc late init or using different regs array.

Since error injection is not supported by SDMA/HDP/SEM in VG20 and Arcturus, there is actually no way to validate EDC for all the OSS blocks. As you may notice that, driver doesn't log any edc counter for any of OSS blocks and expose this to the users.

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of James Zhu
Sent: 2019年11月27日 3:34
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, James <James.Zhu@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt

Clear SDMA and HDP EDC counter in GPR workarounds.

Signed-off-by: James Zhu <James.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c8ace51..dc38df8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -48,6 +48,8 @@
 
 #include "amdgpu_ras.h"
 
+#include "sdma0/sdma0_4_0_offset.h"
+#include "sdma1/sdma1_4_0_offset.h"
 #define GFX9_NUM_GFX_RINGS     1
 #define GFX9_MEC_HPD_SIZE 4096
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L @@ -4029,6 +4031,9 @@ static const struct soc15_reg_entry sec_ded_counter_registers[] = {
    { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16},
    { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2},
    { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6},
+   { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_EDC_COUNTER), 0, 1, 1},
+   { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_EDC_COUNTER), 0, 1, 1},
+   { SOC15_REG_ENTRY(HDP, 0, mmHDP_EDC_CNT), 0, 1, 1},
 };
 
 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev)
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Chawking.zhang%40amd.com%7C2193a8a493fe48d3100a08d772a78fa0%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637103936326788148&amp;sdata=DeOC5y8ePZv2TxhG9nD2eKKkutMSgtCKC0tINUvXrvg%3D&amp;reserved=0
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  parent reply	other threads:[~2019-11-27  3:24 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-26 19:33 [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt James Zhu
2019-11-26 19:33 ` James Zhu
     [not found] ` <1574796818-11648-1-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2019-11-26 19:33   ` [PATCH 2/2] drm/amdgpu/gfx: Increase dispatch packet number James Zhu
2019-11-26 19:33     ` James Zhu
     [not found]     ` <1574796818-11648-2-git-send-email-James.Zhu-5C7GfCeVMHo@public.gmane.org>
2019-11-27  3:26       ` Zhang, Hawking
2019-11-27  3:26         ` Zhang, Hawking
2019-11-27  3:24   ` Zhang, Hawking [this message]
2019-11-27  3:24     ` [PATCH 1/2] drm/amdgpu/gfx: Clear more EDC cnt Zhang, Hawking
     [not found]     ` <DM5PR12MB1418C276613502A0CD12F1B6FC440-2J9CzHegvk81aAVlcVN8UQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-11-27  3:26       ` Zhang, Hawking
2019-11-27  3:26         ` Zhang, Hawking

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