* [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
@ 2017-01-24 12:55 Xue, Ken
[not found] ` <MWHPR12MB15353C27DEA1B76C7F8DC752FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Xue, Ken @ 2017-01-24 12:55 UTC (permalink / raw)
To: amd-gfx mailing list; +Cc: dl.SRDC_SW_GPUVirtualization
Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
message and after ACK server.
Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
Signed-off-by: Ken Xue <Ken.Xue@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index d2622b6..b2c46db 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
{
u32 reg;
+ int timeout = VI_MAILBOX_TIMEDOUT;
+ u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
reg = RREG32(mmMAILBOX_CONTROL);
reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
WREG32(mmMAILBOX_CONTROL, reg);
+
+ /*Wait for RCV_MSG_VALID to be 0*/
+ reg = RREG32(mmMAILBOX_CONTROL);
+ while (reg & mask) {
+ if (timeout <= 0) {
+ pr_err("RCV_MSG_VALID is not cleared\n");
+ break;
+ }
+ msleep(1);
+ timeout -= 1;
+
+ reg = RREG32(mmMAILBOX_CONTROL);
+ }
}
static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
@@ -351,6 +366,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev,
enum idh_event event)
{
u32 reg;
+ u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
+
+ reg = RREG32(mmMAILBOX_CONTROL);
+ if (!(reg & mask))
+ return -ENOENT;
reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
if (reg != event)
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
[not found] ` <MWHPR12MB15353C27DEA1B76C7F8DC752FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-01-24 14:09 ` Christian König
[not found] ` <48d22063-9ac4-505c-07c5-a22ddf80eab1-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2017-01-24 14:09 UTC (permalink / raw)
To: Xue, Ken, amd-gfx mailing list; +Cc: dl.SRDC_SW_GPUVirtualization
Am 24.01.2017 um 13:55 schrieb Xue, Ken:
> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
> message and after ACK server.
>
> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
> Signed-off-by: Ken Xue <Ken.Xue@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index d2622b6..b2c46db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
> static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
> {
> u32 reg;
> + int timeout = VI_MAILBOX_TIMEDOUT;
> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
>
> reg = RREG32(mmMAILBOX_CONTROL);
> reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
> WREG32(mmMAILBOX_CONTROL, reg);
> +
> + /*Wait for RCV_MSG_VALID to be 0*/
> + reg = RREG32(mmMAILBOX_CONTROL);
> + while (reg & mask) {
> + if (timeout <= 0) {
> + pr_err("RCV_MSG_VALID is not cleared\n");
> + break;
> + }
> + msleep(1);
Are you sure that you want to use msleep() here instead of mdelay() ?
msleep() is horrible inaccurate, e.g. depending on the definition of HZ
you can sleep for 10ms instead of 1ms IIRC.
mdelay() is a busy wait, so the CPU can't do anything else useful while
waiting but I don't think that this will hurt us here.
Regards,
Christian.
> + timeout -= 1;
> +
> + reg = RREG32(mmMAILBOX_CONTROL);
> + }
> }
>
> static void xgpu_vi_mailbox_set_valid(struct amdgpu_device *adev, bool val)
> @@ -351,6 +366,11 @@ static int xgpu_vi_mailbox_rcv_msg(struct amdgpu_device *adev,
> enum idh_event event)
> {
> u32 reg;
> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
> +
> + reg = RREG32(mmMAILBOX_CONTROL);
> + if (!(reg & mask))
> + return -ENOENT;
>
> reg = RREG32(mmMAILBOX_MSGBUF_RCV_DW0);
> if (reg != event)
> --
> 2.7.4
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
[not found] ` <48d22063-9ac4-505c-07c5-a22ddf80eab1-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-01-24 15:05 ` Xue, Ken
[not found] ` <MWHPR12MB1535519B5F1B20F8540EF761FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Xue, Ken @ 2017-01-24 15:05 UTC (permalink / raw)
To: Christian König, amd-gfx mailing list; +Cc: dl.SRDC_SW_GPUVirtualization
> From: Christian König [mailto:deathsimple@vodafone.de]
> Sent: Tuesday, January 24, 2017 10:09 PM
> To: Xue, Ken; amd-gfx mailing list
> Cc: dl.SRDC_SW_GPUVirtualization
> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
> server by mailbox
>
> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
> > Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
> > message and after ACK server.
> >
> > Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
> > Signed-off-by: Ken Xue <Ken.Xue@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > index d2622b6..b2c46db 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> > @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
> amdgpu_device *adev)
> > static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
> > {
> > u32 reg;
> > + int timeout = VI_MAILBOX_TIMEDOUT;
> > + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
> >
> > reg = RREG32(mmMAILBOX_CONTROL);
> > reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
> > WREG32(mmMAILBOX_CONTROL, reg);
> > +
> > + /*Wait for RCV_MSG_VALID to be 0*/
> > + reg = RREG32(mmMAILBOX_CONTROL);
> > + while (reg & mask) {
> > + if (timeout <= 0) {
> > + pr_err("RCV_MSG_VALID is not cleared\n");
> > + break;
> > + }
> > + msleep(1);
>
> Are you sure that you want to use msleep() here instead of mdelay() ?
>
> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you can
> sleep for 10ms instead of 1ms IIRC.
>
> mdelay() is a busy wait, so the CPU can't do anything else useful while waiting
> but I don't think that this will hurt us here.
Thanks for your suggestion.
Currently, msleep may be a correct choice.
1)accuracy is not necessary here
2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, driver may be delayed 5 seconds
3)I followed the same style like other codes in the same file.
Regards,
Ken
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
[not found] ` <MWHPR12MB1535519B5F1B20F8540EF761FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-01-24 19:04 ` Felix Kuehling
[not found] ` <679db0ad-27e5-4533-cb4d-e6e6781f7b85-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Felix Kuehling @ 2017-01-24 19:04 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 17-01-24 10:05 AM, Xue, Ken wrote:
>> From: Christian König [mailto:deathsimple@vodafone.de]
>> Sent: Tuesday, January 24, 2017 10:09 PM
>> To: Xue, Ken; amd-gfx mailing list
>> Cc: dl.SRDC_SW_GPUVirtualization
>> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
>> server by mailbox
>>
>> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
>>> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
>>> message and after ACK server.
>>>
>>> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
>>> Signed-off-by: Ken Xue <Ken.Xue@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> index d2622b6..b2c46db 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
>> amdgpu_device *adev)
>>> static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
>>> {
>>> u32 reg;
>>> + int timeout = VI_MAILBOX_TIMEDOUT;
>>> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
>>>
>>> reg = RREG32(mmMAILBOX_CONTROL);
>>> reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
>>> WREG32(mmMAILBOX_CONTROL, reg);
>>> +
>>> + /*Wait for RCV_MSG_VALID to be 0*/
>>> + reg = RREG32(mmMAILBOX_CONTROL);
>>> + while (reg & mask) {
>>> + if (timeout <= 0) {
>>> + pr_err("RCV_MSG_VALID is not cleared\n");
>>> + break;
>>> + }
>>> + msleep(1);
>> Are you sure that you want to use msleep() here instead of mdelay() ?
>>
>> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you can
>> sleep for 10ms instead of 1ms IIRC.
>>
>> mdelay() is a busy wait, so the CPU can't do anything else useful while waiting
>> but I don't think that this will hurt us here.
> Thanks for your suggestion.
> Currently, msleep may be a correct choice.
> 1)accuracy is not necessary here
> 2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, driver may be delayed 5 seconds
> 3)I followed the same style like other codes in the same file.
If msleep sleeps for 10ms instead of 1ms, then your loop may end up
waiting for 50s instead of 5s.
If you want the total timeout to be more predictable, it may be better
to compare jiffies rather than count loop iterations.
Regards,
Felix
>
>
> Regards,
> Ken
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* 答复: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
[not found] ` <679db0ad-27e5-4533-cb4d-e6e6781f7b85-5C7GfCeVMHo@public.gmane.org>
@ 2017-01-25 5:39 ` Liu, Monk
2017-01-25 9:26 ` Xue, Ken
1 sibling, 0 replies; 6+ messages in thread
From: Liu, Monk @ 2017-01-25 5:39 UTC (permalink / raw)
To: Kuehling, Felix, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 3354 bytes --]
please ignore those patches and we will give a formal patch serial later when confirm good working
BR Monk
________________________________
?件人: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> 代表 Felix Kuehling <felix.kuehling@amd.com>
?送??: 2017年1月25日 3:04:48
收件人: amd-gfx@lists.freedesktop.org
主?: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
On 17-01-24 10:05 AM, Xue, Ken wrote:
>> From: Christian Konig [mailto:deathsimple@vodafone.de]
>> Sent: Tuesday, January 24, 2017 10:09 PM
>> To: Xue, Ken; amd-gfx mailing list
>> Cc: dl.SRDC_SW_GPUVirtualization
>> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
>> server by mailbox
>>
>> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
>>> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
>>> message and after ACK server.
>>>
>>> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
>>> Signed-off-by: Ken Xue <Ken.Xue@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> index d2622b6..b2c46db 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
>>> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
>> amdgpu_device *adev)
>>> static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
>>> {
>>> u32 reg;
>>> + int timeout = VI_MAILBOX_TIMEDOUT;
>>> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
>>>
>>> reg = RREG32(mmMAILBOX_CONTROL);
>>> reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
>>> WREG32(mmMAILBOX_CONTROL, reg);
>>> +
>>> + /*Wait for RCV_MSG_VALID to be 0*/
>>> + reg = RREG32(mmMAILBOX_CONTROL);
>>> + while (reg & mask) {
>>> + if (timeout <= 0) {
>>> + pr_err("RCV_MSG_VALID is not cleared\n");
>>> + break;
>>> + }
>>> + msleep(1);
>> Are you sure that you want to use msleep() here instead of mdelay() ?
>>
>> msleep() is horrible inaccurate, e.g. depending on the definition of HZ you can
>> sleep for 10ms instead of 1ms IIRC.
>>
>> mdelay() is a busy wait, so the CPU can't do anything else useful while waiting
>> but I don't think that this will hurt us here.
> Thanks for your suggestion.
> Currently, msleep may be a correct choice.
> 1)accuracy is not necessary here
> 2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server side, driver may be delayed 5 seconds
> 3)I followed the same style like other codes in the same file.
If msleep sleeps for 10ms instead of 1ms, then your loop may end up
waiting for 50s instead of 5s.
If you want the total timeout to be more predictable, it may be better
to compare jiffies rather than count loop iterations.
Regards,
Felix
>
>
> Regards,
> Ken
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[-- Attachment #1.2: Type: text/html, Size: 6163 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox
[not found] ` <679db0ad-27e5-4533-cb4d-e6e6781f7b85-5C7GfCeVMHo@public.gmane.org>
2017-01-25 5:39 ` 答复: " Liu, Monk
@ 2017-01-25 9:26 ` Xue, Ken
1 sibling, 0 replies; 6+ messages in thread
From: Xue, Ken @ 2017-01-25 9:26 UTC (permalink / raw)
To: Kuehling, Felix, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Regards,
Ken
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Felix Kuehling
> Sent: Wednesday, January 25, 2017 3:05 AM
> To: amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest and
> server by mailbox
>
> On 17-01-24 10:05 AM, Xue, Ken wrote:
> >> From: Christian König [mailto:deathsimple@vodafone.de]
> >> Sent: Tuesday, January 24, 2017 10:09 PM
> >> To: Xue, Ken; amd-gfx mailing list
> >> Cc: dl.SRDC_SW_GPUVirtualization
> >> Subject: Re: [PATCH] drm/amdgpu: Refine the handshake between guest
> >> and server by mailbox
> >>
> >> Am 24.01.2017 um 13:55 schrieb Xue, Ken:
> >>> Add check for bit RCV_MSG_VALID of MAILBOX_CONTROL before reading
> >>> message and after ACK server.
> >>>
> >>> Change-Id: I717a77fd90dfbdfce4dc56e978338ffc5db24fca
> >>> Signed-off-by: Ken Xue <Ken.Xue@amd.com>
> >>> ---
> >>> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 20 ++++++++++++++++++++
> >>> 1 file changed, 20 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> >>> b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> >>> index d2622b6..b2c46db 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> >>> @@ -318,10 +318,25 @@ void xgpu_vi_init_golden_registers(struct
> >> amdgpu_device *adev)
> >>> static void xgpu_vi_mailbox_send_ack(struct amdgpu_device *adev)
> >>> {
> >>> u32 reg;
> >>> + int timeout = VI_MAILBOX_TIMEDOUT;
> >>> + u32 mask = REG_FIELD_MASK(MAILBOX_CONTROL, RCV_MSG_VALID);
> >>>
> >>> reg = RREG32(mmMAILBOX_CONTROL);
> >>> reg = REG_SET_FIELD(reg, MAILBOX_CONTROL, RCV_MSG_ACK, 1);
> >>> WREG32(mmMAILBOX_CONTROL, reg);
> >>> +
> >>> + /*Wait for RCV_MSG_VALID to be 0*/
> >>> + reg = RREG32(mmMAILBOX_CONTROL);
> >>> + while (reg & mask) {
> >>> + if (timeout <= 0) {
> >>> + pr_err("RCV_MSG_VALID is not cleared\n");
> >>> + break;
> >>> + }
> >>> + msleep(1);
> >> Are you sure that you want to use msleep() here instead of mdelay() ?
> >>
> >> msleep() is horrible inaccurate, e.g. depending on the definition of
> >> HZ you can sleep for 10ms instead of 1ms IIRC.
> >>
> >> mdelay() is a busy wait, so the CPU can't do anything else useful
> >> while waiting but I don't think that this will hurt us here.
> > Thanks for your suggestion.
> > Currently, msleep may be a correct choice.
> > 1)accuracy is not necessary here
> > 2)the VI_MAILBOX_TIMEDOUT is 5000. if there is an issue from server
> > side, driver may be delayed 5 seconds 3)I followed the same style like other
> codes in the same file.
>
> If msleep sleeps for 10ms instead of 1ms, then your loop may end up waiting
> for 50s instead of 5s.
>
> If you want the total timeout to be more predictable, it may be better to
> compare jiffies rather than count loop iterations.
Sure.
I will send a new patch.
And I think I also need to replace the rest "msleep" in mxgpu_vi.c for predictable timeout.
Thanks
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-01-25 9:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-24 12:55 [PATCH] drm/amdgpu: Refine the handshake between guest and server by mailbox Xue, Ken
[not found] ` <MWHPR12MB15353C27DEA1B76C7F8DC752FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-24 14:09 ` Christian König
[not found] ` <48d22063-9ac4-505c-07c5-a22ddf80eab1-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-01-24 15:05 ` Xue, Ken
[not found] ` <MWHPR12MB1535519B5F1B20F8540EF761FB750-Gy0DoCVfaSWBoBny4uPPvgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-01-24 19:04 ` Felix Kuehling
[not found] ` <679db0ad-27e5-4533-cb4d-e6e6781f7b85-5C7GfCeVMHo@public.gmane.org>
2017-01-25 5:39 ` 答复: " Liu, Monk
2017-01-25 9:26 ` Xue, Ken
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