All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Chen, Guchun" <Guchun.Chen@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: "Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Pan, Xinhui" <Xinhui.Pan@amd.com>,
	"Koenig, Christian" <Christian.Koenig@amd.com>,
	amd-gfx list <amd-gfx@lists.freedesktop.org>,
	"Zhang, Hawking" <Hawking.Zhang@amd.com>
Subject: RE: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs
Date: Fri, 25 Feb 2022 02:26:21 +0000	[thread overview]
Message-ID: <DM5PR12MB246960DF4323A6DDA78F56F8F13E9@DM5PR12MB2469.namprd12.prod.outlook.com> (raw)
In-Reply-To: <CADnq5_MHoxvwf0Zg+3Wu1w_yq+RTHtBG=f4FRv4H+Pp+kHDiqA@mail.gmail.com>

Hi Alex,

Exactly, I have the same idea, but I need to double confirm the harvest bit settings are correct on all these listed ASICs. Once confirmed, I will drop the redundant check.

Regards,
Guchun

-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com> 
Sent: Thursday, February 24, 2022 11:58 PM
To: Chen, Guchun <Guchun.Chen@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com>
Subject: Re: [PATCH] drm/amdgpu: limit harvest bit read on several ASICs

On Tue, Feb 22, 2022 at 10:07 AM Guchun Chen <guchun.chen@amd.com> wrote:
>
> Due to faulty VBIOS out there, harvest bit setting is not consistently 
> correct especially for display IP. So far, it's hard to work out a 
> solution on all the legacy Navi1x ASICs in a short time, so to avoid 
> regression, limit harvest bit read on several ASICs. Will revisit 
> later once VBIOS has corrected it in long term.
>
> Fixes: b3f4ea887d5f("drm/amdgpu: read harvest bit per IP data on 
> legacy GPUs")
> Signed-off-by: Guchun Chen <guchun.chen@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 11255290f117..2e0ff1ace6fc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1129,12 +1129,20 @@ void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
>          * so read harvest bit per IP data structure to set
>          * harvest configuration.
>          */
> -       if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0))
> -               amdgpu_discovery_read_harvest_bit_per_ip(adev,
> -                                                       &vcn_harvest_count);
> -       else
> +       if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0)) {
> +               if ((adev->pdev->device == 0x731E &&
> +                       (adev->pdev->revision == 0xC6 ||
> +                        adev->pdev->revision == 0xC7)) ||
> +                       (adev->pdev->device == 0x7340 &&
> +                        adev->pdev->revision == 0xC9) ||
> +                       (adev->pdev->device == 0x7360 &&
> +                        adev->pdev->revision == 0xC7))
> +                       amdgpu_discovery_read_harvest_bit_per_ip(adev,
> +                               &vcn_harvest_count);

Now that we have this code in place, can we drop the hardcoded harvest settings below?  E.g.,

        if ((adev->pdev->device == 0x731E &&
             (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
            (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9)  ||
            (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
                adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
                adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
        }

Looks like the same board variants in both places.

Alex

> +       } else {
>                 amdgpu_disocvery_read_from_harvest_table(adev,
> -                                                       &vcn_harvest_count);
> +                       &vcn_harvest_count);
> +       }
>
>         amdgpu_discovery_harvest_config_quirk(adev);
>
> --
> 2.17.1
>

      reply	other threads:[~2022-02-25  2:26 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-22 15:07 [PATCH] drm/amdgpu: limit harvest bit read on several ASICs Guchun Chen
2022-02-22 15:25 ` Deucher, Alexander
2022-02-22 17:00 ` Alex Deucher
2022-02-23  2:29   ` Chen, Guchun
2022-02-23  2:30     ` Deucher, Alexander
2022-02-24 15:58 ` Alex Deucher
2022-02-25  2:26   ` Chen, Guchun [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DM5PR12MB246960DF4323A6DDA78F56F8F13E9@DM5PR12MB2469.namprd12.prod.outlook.com \
    --to=guchun.chen@amd.com \
    --cc=Alexander.Deucher@amd.com \
    --cc=Christian.Koenig@amd.com \
    --cc=Hawking.Zhang@amd.com \
    --cc=Xinhui.Pan@amd.com \
    --cc=alexdeucher@gmail.com \
    --cc=amd-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.