RE: Queries on CAN frame work

[Srinivas Neeli <sneeli@xilinx.com>]

Hi Marc,

> -----Original Message-----
> From: Marc Kleine-Budde <mkl@pengutronix.de>
> Sent: Friday, March 18, 2022 3:31 AM
> To: Srinivas Neeli <sneeli@xilinx.com>
> Cc: Srinivas Goud <sgoud@xilinx.com>; Naveen Kumar Gaddipati
> <naveenku@xilinx.com>; Prasad Beer Prasad <prasadbe@xilinx.com>; linux-
> can <linux-can@vger.kernel.org>; Stefan Mätje <stefan.maetje@esd.eu>;
> Vincent MAILHOL <mailhol.vincent@wanadoo.fr>
> Subject: Re: Queries on CAN frame work
> 
> On 21.02.2022 14:43:57, Srinivas Neeli wrote:
> > > Can you please provide me:
> > > - the bit timing constants of the IP core for the arbitration and data
> > >   phase
> > > - the bit rate for the arbitration and data phase
> > >   (especially where the framework calculates not common prescalers)
> > > - the clock rate of the CAN bus clock
> > >
> > > Can you also provide the hand calculated bit timing parameters for
> > > the above scenarios?
> >
> > Baud rate 1/5Mbps
> > ================
> > root@xilinx-vck190-2021_1:~# ip link set can6 type can bitrate 1000000
> dbitrate 5000000 fd on
> > [   26.837057] xilinx_can ff070000.can can6: bitrate error 0.0%
> > [   26.842731] xilinx_can ff070000.can can6: bitrate error 0.0%
> >  can6 txqroot@xilinx-vck190-2021_1:~# ifconfig can6 txqueuelen 1000
> > root@xilinx-vck190-2021_1:~# ip link set can6 up
> > [   27.340880] IPv6: ADDRCONF(NETDEV_CHANGE): can6: link becomes
> ready
> > root@xilinx-vck190-2021_1:~# ip -d -s link show can6
> >  can6: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP
> mode DEFAULT group default qlen 1000
> >     link/can  promiscuity 0 minmtu 0 maxmtu 0
> >     can <FD> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 0
> > 	  bitrate 999999 sample-point 0.750
> > 	  tq 250 prop-seg 1 phase-seg1 1 phase-seg2 1 sjw 1
> > 	  xilinx_can: tseg1 1..256 tseg2 1..128 sjw 1..128 brp 1..256 brp-inc 1
> > 	  dbitrate 4999999 dsample-point 0.750
> > 	  dtq 50 dprop-seg 1 dphase-seg1 1 dphase-seg2 1 dsjw 1
> > 	  xilinx_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..256 dbrp-inc
> 1
> > 	  clock 79999999
> > 	  re-started bus-errors arbit-lost error-warn error-pass bus-off
> > 	  0          0          0          0          0          0         numtxqueues 1
> numrxqueues 1 gso_max_size 65536 gso_max_segs 65535
> >     RX: bytes  packets  errors  dropped overrun mcast
> >     0          0        0       0       0       0
> >     TX: bytes  packets  errors  dropped carrier collsns
> >     0          0        0       0       0       0
> 
> Are you using the mainline xilinx_can driver? The "ip" command says, you're
> using:

Yes , mainline and internal drivers are same.
Xilinx maintains common driver for multiple CAN and CANFD  IP's.
Xilinx supports below CAN IP's:
xlnx,zynq-can-1.0 (zynq platform & zynqmp platform)
xlnx,axi-can-1.00.a ( Soft IP version 1.00)
xlnx,canfd-1.0 (Soft canfd ip version 1.0)
xlnx,canfd-2.0(Soft canfd ip Version 2.0)
xlnx,canfd2.0 equal to versal canfd ip, so using same compatible string for both.

For each ip sjw_max and brp values are different.
Due to this reason created multiple bit timing structures.

> 
> >  sjw 1..128  brp 1..256
> > dsjw 1..16  dbrp 1..256
> 
> Looking at the mainline xilinx driver, we have:
> 
> | /* CAN Bittiming constants as per Xilinx CAN specs */ static const
> | struct can_bittiming_const xcan_bittiming_const = {
> | 	.name = DRIVER_NAME,
> | 	.tseg1_min = 1,
> | 	.tseg1_max = 16,
> | 	.tseg2_min = 1,
> | 	.tseg2_max = 8,
> | 	.sjw_max = 4,
>                    ^
> Does not match due to "sjw 1..128".
> 
> | 	.brp_min = 1,
> | 	.brp_max = 256,
> | 	.brp_inc = 1,
> | };
> |
> | /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec
> | */ static const struct can_bittiming_const xcan_bittiming_const_canfd = {
> | 	.name = DRIVER_NAME,
> | 	.tseg1_min = 1,
> | 	.tseg1_max = 64,
> | 	.tseg2_min = 1,
> | 	.tseg2_max = 16,
> | 	.sjw_max = 16,
>                    ^^
> Does not match due to "sjw 1..128".
> 
> | 	.brp_min = 1,
> | 	.brp_max = 256,
> | 	.brp_inc = 1,
> | };
> |
> | /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
> | static struct can_bittiming_const xcan_data_bittiming_const_canfd = {
> | 	.name = DRIVER_NAME,
> | 	.tseg1_min = 1,
> | 	.tseg1_max = 16,
> | 	.tseg2_min = 1,
> | 	.tseg2_max = 8,
> | 	.sjw_max = 8,
>                    ^
> Does not match due to "dsjw 1..16"
> 
> | 	.brp_min = 1,
> | 	.brp_max = 256,
> | 	.brp_inc = 1,
> | };
> |
> | /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0
> | spec */ static const struct can_bittiming_const
> xcan_bittiming_const_canfd2 = {
> | 	.name = DRIVER_NAME,
> | 	.tseg1_min = 1,
> | 	.tseg1_max = 256,
> | 	.tseg2_min = 1,
> | 	.tseg2_max = 128,
> | 	.sjw_max = 128,
> | 	.brp_min = 2,
>                    ^
> Does not match due to "brp 1..256".
> 
> | 	.brp_max = 256,
> | 	.brp_inc = 1,
> | };
> |
> | /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
> | static struct can_bittiming_const xcan_data_bittiming_const_canfd2 = {
> | 	.name = DRIVER_NAME,
> | 	.tseg1_min = 1,
> | 	.tseg1_max = 32,
> | 	.tseg2_min = 1,
> | 	.tseg2_max = 16,
> | 	.sjw_max = 16,
> | 	.brp_min = 2,
>                    ^
> Does not match due to "dbrp 1..256".

Versal early silicon we observed bit enlarging issue with brp  =1 in side IP using simulaitons(Not observed on software side) , but it fixed in production silicon.
Plan to revert this patch to support TDC feature(To support higher baud rates we need brp =1).

> 
> | 	.brp_max = 256,
> | 	.brp_inc = 1,
> | };
> 
> Can you send patches to update the xilinx CAN driver?
> 
> I'm continue working on the CAN bittiming code.
> 
> regards,
> Marc
> 
> --
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