[PATCH v2 0/3] clk: clk-axiclgen: add support for ZynqMP

[PATCH v2 0/3] clk: clk-axiclgen: add support for ZynqMP

[Alexandru Ardelean]

Previous set:
 https://lore.kernel.org/linux-clk/20201221144224.50814-1-alexandru.ardelean@analog.com/

Changelog v1 -> v2:
* split patch 'clk: axi-clkgen: add support for ZynqMP (UltraScale)'
  into:
   - clk: axi-clkgen: remove ARCH dependency in Kconfig
   - clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
* essentially removed the 'adi,zynq-axi-clkgen-2.00.a' compat string
* removed architecture dependency on build for driver; the driver should
  be usable also on PCIe setups

Alexandru Ardelean (3):
  clk: axi-clkgen: remove ARCH dependency in Kconfig
  clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
  dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP
    support

 .../devicetree/bindings/clock/adi,axi-clkgen.yaml     |  1 +
 drivers/clk/Kconfig                                   |  1 -
 drivers/clk/clk-axi-clkgen.c                          | 11 +++++++++++
 3 files changed, 12 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig

[Alexandru Ardelean]

The intent is to be able to run this driver to access the IP core in setups
where FPGA board is also connected via a PCIe bus. In such cases the number
of combinations explodes, where the host system can be an x86 with Xilinx
Zynq/ZynqMP/Microblaze board connected via PCIe.
Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.

To accommodate for these cases, this change removes the limitation for this
driver to be compilable only on Zynq/Microblaze architectures.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
 drivers/clk/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 85856cff506c..d8c2d4593926 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,6 @@ config CLK_TWL6040
 
 config COMMON_CLK_AXI_CLKGEN
 	tristate "AXI clkgen driver"
-	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
 	help
 	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
 	  FPGAs. It is commonly used in Analog Devices' reference designs.
-- 
2.17.1

[PATCH v2 2/3] clk: clk-axiclkgen: add ZynqMP PFD and VCO limits

[Alexandru Ardelean]

For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to
support these, this change adds a compatible string (i.e.
'adi,zynqmp-axi-clkgen-2.00.a')  which will take into account for these
limits and apply them.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Mathias Tausen <mta@gomspace.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
 drivers/clk/clk-axi-clkgen.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index ad86e031ba3e..9d1b0fc56c73 100644
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -108,6 +108,13 @@ static uint32_t axi_clkgen_lookup_lock(unsigned int m)
 	return 0x1f1f00fa;
 }
 
+static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
+	.fpfd_min = 10000,
+	.fpfd_max = 450000,
+	.fvco_min = 800000,
+	.fvco_max = 1600000,
+};
+
 static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
 	.fpfd_min = 10000,
 	.fpfd_max = 300000,
@@ -560,6 +567,10 @@ static int axi_clkgen_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id axi_clkgen_ids[] = {
+	{
+		.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
+		.data = &axi_clkgen_zynqmp_default_limits,
+	},
 	{
 		.compatible = "adi,axi-clkgen-2.00.a",
 		.data = &axi_clkgen_zynq_default_limits,
-- 
2.17.1

[PATCH v2 3/3] dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support

[Alexandru Ardelean]

The axi-clkgen driver now supports ZynqMP (UltraScale) as well, however the
driver needs to use different PFD & VCO limits.

For ZynqMP, these needs to be selected by using the
'adi,zynqmp-axi-clkgen-2.00.a' string.

Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
 Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
index 0d06387184d6..983033fe5b17 100644
--- a/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
+++ b/Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml
@@ -20,6 +20,7 @@ properties:
   compatible:
     enum:
       - adi,axi-clkgen-2.00.a
+      - adi,zynqmp-axi-clkgen-2.00.a
 
   clocks:
     description:
-- 
2.17.1

Re: [PATCH v2 0/3] clk: clk-axiclgen: add support for ZynqMP

[Tom Rix]

On 1/26/21 3:08 AM, Alexandru Ardelean wrote:
> Previous set:
>  https://lore.kernel.org/linux-clk/20201221144224.50814-1-alexandru.ardelean@analog.com/
>
> Changelog v1 -> v2:
> * split patch 'clk: axi-clkgen: add support for ZynqMP (UltraScale)'
>   into:
>    - clk: axi-clkgen: remove ARCH dependency in Kconfig
>    - clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
> * essentially removed the 'adi,zynq-axi-clkgen-2.00.a' compat string
> * removed architecture dependency on build for driver; the driver should
>   be usable also on PCIe setups
>
> Alexandru Ardelean (3):
>   clk: axi-clkgen: remove ARCH dependency in Kconfig
>   clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
>   dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP
>     support
>
>  .../devicetree/bindings/clock/adi,axi-clkgen.yaml     |  1 +
>  drivers/clk/Kconfig                                   |  1 -
>  drivers/clk/clk-axi-clkgen.c                          | 11 +++++++++++
>  3 files changed, 12 insertions(+), 1 deletion(-)

This whole set looks fine.

Reviewed-by: Tom Rix <trix@redhat.com>

Re: [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig

[Moritz Fischer]

Alexandru,

On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
> 
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> 
> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
>  drivers/clk/Kconfig | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 85856cff506c..d8c2d4593926 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -247,7 +247,6 @@ config CLK_TWL6040
>  
>  config COMMON_CLK_AXI_CLKGEN
>  	tristate "AXI clkgen driver"
> -	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
Umhhh ... no dependencies? How are you accessing your registers? You
seem to be using device tree, probably:

	depends on HAS_IOMEM || COMPILE_TEST
	depends on OF

at least? Please double check your dependencies.
>  	help
>  	  Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
>  	  FPGAs. It is commonly used in Analog Devices' reference designs.
> -- 
> 2.17.1
> 

- Moritz

RE: [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig

[Ardelean, Alexandru]

> -----Original Message-----
> From: Moritz Fischer <mdf@kernel.org>
> Sent: Wednesday, January 27, 2021 4:39 AM
> To: Ardelean, Alexandru <alexandru.Ardelean@analog.com>
> Cc: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; mturquette@baylibre.com; sboyd@kernel.org;
> robh+dt@kernel.org; lars@metafoo.de; linux-fpga@vger.kernel.org;
> mdf@kernel.org; Bogdan, Dragos <Dragos.Bogdan@analog.com>
> Subject: Re: [PATCH v2 1/3] clk: axi-clkgen: remove ARCH dependency in Kconfig
> 
> Alexandru,
> 
> On Tue, Jan 26, 2021 at 01:08:24PM +0200, Alexandru Ardelean wrote:
> > The intent is to be able to run this driver to access the IP core in
> > setups where FPGA board is also connected via a PCIe bus. In such
> > cases the number of combinations explodes, where the host system can
> > be an x86 with Xilinx Zynq/ZynqMP/Microblaze board connected via PCIe.
> > Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
> >
> > To accommodate for these cases, this change removes the limitation for
> > this driver to be compilable only on Zynq/Microblaze architectures.
> >
> > Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> >  drivers/clk/Kconfig | 1 -
> >  1 file changed, 1 deletion(-)
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > 85856cff506c..d8c2d4593926 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -247,7 +247,6 @@ config CLK_TWL6040
> >
> >  config COMMON_CLK_AXI_CLKGEN
> >  	tristate "AXI clkgen driver"
> > -	depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> Umhhh ... no dependencies? How are you accessing your registers? You seem to
> be using device tree, probably:
> 
> 	depends on HAS_IOMEM || COMPILE_TEST
> 	depends on OF
> 
> at least? Please double check your dependencies.

Agreed.
Will re-spin.
This is a n00b mistake on my part

Thanks

> >  	help
> >  	  Support for the Analog Devices axi-clkgen pcore clock generator for
> Xilinx
> >  	  FPGAs. It is commonly used in Analog Devices' reference designs.
> > --
> > 2.17.1
> >
> 
> - Moritz