* [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 10:01 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
` (17 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps user space to establish the hardware protected session
and manage the status of each alive software session, as well as
the life cycle of each session.
By design PXP will expose ioctl so allow user space to create, set,
and destroy each session. It will also provide the communication
chanel to TEE (Trusted Execution Environment) for the protected
hardware session creation.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 19 ++++++++++++++++
drivers/gpu/drm/i915/Makefile | 4 ++++
drivers/gpu/drm/i915/i915_drv.c | 4 ++++
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 25 +++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 33 ++++++++++++++++++++++++++++
6 files changed, 89 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..f82ccc901b1e 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ select INTEL_MEI_PXP
+ default n
+ help
+ This option selects INTEL_MEI_ME if it isn't already selected to
+ enabled full PXP Services on Intel platforms.
+
+ PXP is an i915 componment, available on Gen12+, that helps user
+ space to establish the hardware protected session and manage the
+ status of each alive software session, as well as the life cycle
+ of each session.
+
+ PXP expose ioctl so allow user space to create, set, and destroy
+ each session. It will also provide the communication chanel to
+ TEE (Trusted Execution Environment) for the protected hardware
+ session creation.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e5574e506a5c..a53ea3c88f71 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -254,6 +254,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 320856b665a1..1e5ecaff571f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -889,6 +889,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (ret)
goto out_cleanup_gem;
+ intel_pxp_init(i915);
+
i915_driver_register(i915);
enable_rpm_wakeref_asserts(&i915->runtime_pm);
@@ -938,6 +940,8 @@ void i915_driver_remove(struct drm_i915_private *i915)
/* Flush any external code that still may be under the RCU lock */
synchronize_rcu();
+ intel_pxp_uninit(i915);
+
i915_gem_suspend(i915);
drm_atomic_helper_shutdown(&i915->drm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fecb5899cbac..33a3f5c387b0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -105,6 +105,8 @@
#include "intel_region_lmem.h"
+#include "pxp/intel_pxp.h"
+
/* General customization:
*/
@@ -1215,6 +1217,8 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct intel_pxp pxp;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..3de4593ca495
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "i915_drv.h"
+#include "intel_pxp.h"
+
+int intel_pxp_init(struct drm_i915_private *i915)
+{
+ if (!i915)
+ return -EINVAL;
+
+ /* PXP only available for GEN12+ */
+ if (INTEL_GEN(i915) < 12)
+ return 0;
+
+ drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
+
+ return 0;
+}
+
+void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..0b83d33045f3
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include <drm/drm_file.h>
+
+struct pxp_context;
+
+struct intel_pxp {
+ struct pxp_context *ctx;
+};
+
+struct drm_i915_private;
+
+#ifdef CONFIG_DRM_I915_PXP
+int intel_pxp_init(struct drm_i915_private *i915);
+void intel_pxp_uninit(struct drm_i915_private *i915);
+#else
+static inline int intel_pxp_init(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static inline void intel_pxp_uninit(struct drm_i915_private *i915)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2020-12-07 10:01 ` Joonas Lahtinen
2020-12-07 18:25 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 10:01 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:19)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps user space to establish the hardware protected session
> and manage the status of each alive software session, as well as
> the life cycle of each session.
>
> By design PXP will expose ioctl so allow user space to create, set,
> and destroy each session. It will also provide the communication
> chanel to TEE (Trusted Execution Environment) for the protected
> hardware session creation.
Description is no more true for single-session only.
<SNIP>
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP is an i915 componment, available on Gen12+, that helps user
> + space to establish the hardware protected session and manage the
> + status of each alive software session, as well as the life cycle
> + of each session.
> +
> + PXP expose ioctl so allow user space to create, set, and destroy
> + each session. It will also provide the communication chanel to
> + TEE (Trusted Execution Environment) for the protected hardware
> + session creation.
Same here, needs updating.
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -105,6 +105,8 @@
>
> #include "intel_region_lmem.h"
>
> +#include "pxp/intel_pxp.h"
Repeating the same comment as on previous review, avoid including
anything in i915_drv.h and only include in the relevant files that
require to touch the internals of the structs.
> +
> /* General customization:
> */
>
> @@ -1215,6 +1217,8 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct intel_pxp pxp;
I think this should instead go as part of intel_gt, not here.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +
> +int intel_pxp_init(struct drm_i915_private *i915)
We should aim to only take struct intel_pxp as parameter for intel_pxp_*
functions.
> +{
> + if (!i915)
> + return -EINVAL;
This would be either a major kernel programmer error or the memory would
be seriously corrupt. No point leaving such checks to production code,
so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug
builds.
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(i915) < 12)
> + return 0;
I think -ENODEV would be more appropriate return value. Also, we should
look into returning this error value from inside the actual init code.
We want the user to be able to differentiate between kernel does not
support and hardware does not support status.
> + drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
We shouldn't be printing the pointer values, especially not in INFO
level messages. INFO level messages should be useful for the end-user to
read. This is not very useful, we should instead consider something
along the lines of:
"Protected Xe Path (PXP) protected content support initialized"
Also, we have not really initialized anything so it's really premature
to print anything in this patch.
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct drm_i915_private *i915)
Same here, we really want to tighten the scope to intel_pxp and call
this from intel_gt_fini(), so signature should look like:
void intel_pxp_fini(struct intel_pxp *pxp)
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
2020-12-07 10:01 ` Joonas Lahtinen
@ 2020-12-07 18:25 ` Huang, Sean Z
2020-12-07 18:48 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 18:25 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Hi Joonas,
Thanks for the details review. I have apply the modification according to the review, and will update as rev2.
> Description is no more true for single-session only
DONE
> Same here, needs updating.
DONE
>Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
DONE
> I think this should instead go as part of intel_gt, not here.
DONE
> We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
DONE, I think the suggestion is reasonable. I expect that will modify the code significantly in the future commits, but let me try intel_pxp_* instead of i915
> This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
DONE, I just remove the error check
> Also, we have not really initialized anything so it's really premature to print anything in this patch.
DONE, remove the print
> Same here, we really want to tighten the scope to intel_pxp and call this from intel_gt_fini(), so signature should look like: void intel_pxp_fini(struct intel_pxp *pxp)
DONE
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 2:01 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
Quoting Huang, Sean Z (2020-12-07 02:21:19)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps user space to establish the hardware protected session and
> manage the status of each alive software session, as well as the life
> cycle of each session.
>
> By design PXP will expose ioctl so allow user space to create, set,
> and destroy each session. It will also provide the communication
> chanel to TEE (Trusted Execution Environment) for the protected
> hardware session creation.
Description is no more true for single-session only.
<SNIP>
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP is an i915 componment, available on Gen12+, that helps user
> + space to establish the hardware protected session and manage the
> + status of each alive software session, as well as the life cycle
> + of each session.
> +
> + PXP expose ioctl so allow user space to create, set, and destroy
> + each session. It will also provide the communication chanel to
> + TEE (Trusted Execution Environment) for the protected hardware
> + session creation.
Same here, needs updating.
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -105,6 +105,8 @@
>
> #include "intel_region_lmem.h"
>
> +#include "pxp/intel_pxp.h"
Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
> +
> /* General customization:
> */
>
> @@ -1215,6 +1217,8 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct intel_pxp pxp;
I think this should instead go as part of intel_gt, not here.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +
> +int intel_pxp_init(struct drm_i915_private *i915)
We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
> +{
> + if (!i915)
> + return -EINVAL;
This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(i915) < 12)
> + return 0;
I think -ENODEV would be more appropriate return value. Also, we should look into returning this error value from inside the actual init code.
We want the user to be able to differentiate between kernel does not support and hardware does not support status.
> + drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n",
> + i915);
We shouldn't be printing the pointer values, especially not in INFO level messages. INFO level messages should be useful for the end-user to read. This is not very useful, we should instead consider something along the lines of:
"Protected Xe Path (PXP) protected content support initialized"
Also, we have not really initialized anything so it's really premature to print anything in this patch.
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct drm_i915_private *i915)
Same here, we really want to tighten the scope to intel_pxp and call this from intel_gt_fini(), so signature should look like:
void intel_pxp_fini(struct intel_pxp *pxp)
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
2020-12-07 18:25 ` Huang, Sean Z
@ 2020-12-07 18:48 ` Huang, Sean Z
2020-12-10 9:02 ` Joonas Lahtinen
0 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 18:48 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
>Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
I would still need to include i915_drv.h for macro INTEL_GEN(), hopefully it's acceptable.
-----Original Message-----
From: Huang, Sean Z
Sent: Monday, December 7, 2020 10:26 AM
To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Intel-gfx@lists.freedesktop.org
Subject: RE: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
Hi Joonas,
Thanks for the details review. I have apply the modification according to the review, and will update as rev2.
> Description is no more true for single-session only
DONE
> Same here, needs updating.
DONE
>Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
DONE
> I think this should instead go as part of intel_gt, not here.
DONE
> We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
DONE, I think the suggestion is reasonable. I expect that will modify the code significantly in the future commits, but let me try intel_pxp_* instead of i915
> This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
DONE, I just remove the error check
> Also, we have not really initialized anything so it's really premature to print anything in this patch.
DONE, remove the print
> Same here, we really want to tighten the scope to intel_pxp and call
> this from intel_gt_fini(), so signature should look like: void
> intel_pxp_fini(struct intel_pxp *pxp)
DONE
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 2:01 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
Quoting Huang, Sean Z (2020-12-07 02:21:19)
> PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> that helps user space to establish the hardware protected session and
> manage the status of each alive software session, as well as the life
> cycle of each session.
>
> By design PXP will expose ioctl so allow user space to create, set,
> and destroy each session. It will also provide the communication
> chanel to TEE (Trusted Execution Environment) for the protected
> hardware session creation.
Description is no more true for single-session only.
<SNIP>
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + select INTEL_MEI_PXP
> + default n
> + help
> + This option selects INTEL_MEI_ME if it isn't already selected to
> + enabled full PXP Services on Intel platforms.
> +
> + PXP is an i915 componment, available on Gen12+, that helps user
> + space to establish the hardware protected session and manage the
> + status of each alive software session, as well as the life cycle
> + of each session.
> +
> + PXP expose ioctl so allow user space to create, set, and destroy
> + each session. It will also provide the communication chanel to
> + TEE (Trusted Execution Environment) for the protected hardware
> + session creation.
Same here, needs updating.
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -105,6 +105,8 @@
>
> #include "intel_region_lmem.h"
>
> +#include "pxp/intel_pxp.h"
Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
> +
> /* General customization:
> */
>
> @@ -1215,6 +1217,8 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct intel_pxp pxp;
I think this should instead go as part of intel_gt, not here.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,25 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +
> +int intel_pxp_init(struct drm_i915_private *i915)
We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
> +{
> + if (!i915)
> + return -EINVAL;
This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
> + /* PXP only available for GEN12+ */
> + if (INTEL_GEN(i915) < 12)
> + return 0;
I think -ENODEV would be more appropriate return value. Also, we should look into returning this error value from inside the actual init code.
We want the user to be able to differentiate between kernel does not support and hardware does not support status.
> + drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n",
> + i915);
We shouldn't be printing the pointer values, especially not in INFO level messages. INFO level messages should be useful for the end-user to read. This is not very useful, we should instead consider something along the lines of:
"Protected Xe Path (PXP) protected content support initialized"
Also, we have not really initialized anything so it's really premature to print anything in this patch.
> +
> + return 0;
> +}
> +
> +void intel_pxp_uninit(struct drm_i915_private *i915)
Same here, we really want to tighten the scope to intel_pxp and call this from intel_gt_fini(), so signature should look like:
void intel_pxp_fini(struct intel_pxp *pxp)
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
2020-12-07 18:48 ` Huang, Sean Z
@ 2020-12-10 9:02 ` Joonas Lahtinen
0 siblings, 0 replies; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-10 9:02 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 20:48:55)
>
> >Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
>
> I would still need to include i915_drv.h for macro INTEL_GEN(), hopefully it's acceptable.
That is fine. I was referring to the opposite, do not include
"intel_pxp.h" from i915_drv.h.
It's instead better to add "intel_pxp_types.h" etc. (look for *_types.h
files from i915 source) and minimize what is included by each file.
Regards, Joonas
>
> -----Original Message-----
> From: Huang, Sean Z
> Sent: Monday, December 7, 2020 10:26 AM
> To: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Intel-gfx@lists.freedesktop.org
> Subject: RE: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
>
> Hi Joonas,
>
> Thanks for the details review. I have apply the modification according to the review, and will update as rev2.
> > Description is no more true for single-session only
> DONE
>
> > Same here, needs updating.
> DONE
>
> >Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
> DONE
>
> > I think this should instead go as part of intel_gt, not here.
> DONE
>
> > We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
> DONE, I think the suggestion is reasonable. I expect that will modify the code significantly in the future commits, but let me try intel_pxp_* instead of i915
>
> > This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
> DONE, I just remove the error check
>
> > Also, we have not really initialized anything so it's really premature to print anything in this patch.
> DONE, remove the print
>
> > Same here, we really want to tighten the scope to intel_pxp and call
> > this from intel_gt_fini(), so signature should look like: void
> > intel_pxp_fini(struct intel_pxp *pxp)
> DONE
>
> Best regards,
> Sean
>
> -----Original Message-----
> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Sent: Monday, December 7, 2020 2:01 AM
> To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component
>
> Quoting Huang, Sean Z (2020-12-07 02:21:19)
> > PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
> > that helps user space to establish the hardware protected session and
> > manage the status of each alive software session, as well as the life
> > cycle of each session.
> >
> > By design PXP will expose ioctl so allow user space to create, set,
> > and destroy each session. It will also provide the communication
> > chanel to TEE (Trusted Execution Environment) for the protected
> > hardware session creation.
>
> Description is no more true for single-session only.
>
> <SNIP>
>
> > +++ b/drivers/gpu/drm/i915/Kconfig
> > @@ -130,6 +130,25 @@ config DRM_I915_GVT_KVMGT
> > Choose this option if you want to enable KVMGT support for
> > Intel GVT-g.
> >
> > +config DRM_I915_PXP
> > + bool "Enable Intel PXP support for Intel Gen12+ platform"
> > + depends on DRM_I915
> > + select INTEL_MEI_PXP
> > + default n
> > + help
> > + This option selects INTEL_MEI_ME if it isn't already selected to
> > + enabled full PXP Services on Intel platforms.
> > +
> > + PXP is an i915 componment, available on Gen12+, that helps user
> > + space to establish the hardware protected session and manage the
> > + status of each alive software session, as well as the life cycle
> > + of each session.
> > +
> > + PXP expose ioctl so allow user space to create, set, and destroy
> > + each session. It will also provide the communication chanel to
> > + TEE (Trusted Execution Environment) for the protected hardware
> > + session creation.
>
> Same here, needs updating.
>
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -105,6 +105,8 @@
> >
> > #include "intel_region_lmem.h"
> >
> > +#include "pxp/intel_pxp.h"
>
> Repeating the same comment as on previous review, avoid including anything in i915_drv.h and only include in the relevant files that require to touch the internals of the structs.
>
> > +
> > /* General customization:
> > */
> >
> > @@ -1215,6 +1217,8 @@ struct drm_i915_private {
> > /* Mutex to protect the above hdcp component related values. */
> > struct mutex hdcp_comp_mutex;
> >
> > + struct intel_pxp pxp;
>
> I think this should instead go as part of intel_gt, not here.
>
> > +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> > @@ -0,0 +1,25 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright(c) 2020 Intel Corporation.
> > + */
> > +
> > +#include "i915_drv.h"
> > +#include "intel_pxp.h"
> > +
> > +int intel_pxp_init(struct drm_i915_private *i915)
>
> We should aim to only take struct intel_pxp as parameter for intel_pxp_* functions.
>
> > +{
> > + if (!i915)
> > + return -EINVAL;
>
> This would be either a major kernel programmer error or the memory would be seriously corrupt. No point leaving such checks to production code, so GEM_BUG_ON(!i915) would be enough to run the checks in CI and debug builds.
>
> > + /* PXP only available for GEN12+ */
> > + if (INTEL_GEN(i915) < 12)
> > + return 0;
>
> I think -ENODEV would be more appropriate return value. Also, we should look into returning this error value from inside the actual init code.
> We want the user to be able to differentiate between kernel does not support and hardware does not support status.
>
> > + drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n",
> > + i915);
>
> We shouldn't be printing the pointer values, especially not in INFO level messages. INFO level messages should be useful for the end-user to read. This is not very useful, we should instead consider something along the lines of:
>
> "Protected Xe Path (PXP) protected content support initialized"
>
> Also, we have not really initialized anything so it's really premature to print anything in this patch.
>
> > +
> > + return 0;
> > +}
> > +
> > +void intel_pxp_uninit(struct drm_i915_private *i915)
>
> Same here, we really want to tighten the scope to intel_pxp and call this from intel_gt_fini(), so signature should look like:
>
> void intel_pxp_fini(struct intel_pxp *pxp)
>
> Regards, Joonas
_______________________________________________
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 10:21 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states Huang, Sean Z
` (16 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 88 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 36 +++++++++++
4 files changed, 129 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 257063a57101..d64013d0afb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_gt_irq.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5375b219cc3b..c3b9ca142539 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7943,6 +7943,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3de4593ca495..07faaadb0031 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,58 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
+{
+ /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
+ intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask << 16);
+}
+
+static void intel_pxp_unmask_irq(struct intel_gt *gt)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, 0);
+}
+
+static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
+{
+ lockdep_assert_held(>->irq_lock);
+
+ intel_pxp_write_irq_mask_reg(gt->i915, mask);
+}
+
+static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr), irq_work);
+ struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915), pxp);
+ u32 events = 0;
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ events = fetch_and_zero(&pxp_ptr->current_events);
+ spin_unlock_irq(&i915->gt.irq_lock);
+
+ if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
+ events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
+ intel_pxp_teardown_required_callback(i915);
+
+ if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
+ intel_pxp_global_terminate_complete_callback(i915);
+
+ spin_lock_irq(&i915->gt.irq_lock);
+ intel_pxp_unmask_irq(&i915->gt);
+ spin_unlock_irq(&i915->gt.irq_lock);
+}
+
int intel_pxp_init(struct drm_i915_private *i915)
{
if (!i915)
@@ -17,9 +69,45 @@ int intel_pxp_init(struct drm_i915_private *i915)
drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
+
+ i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
+ PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
+ PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
+
return 0;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+/**
+ * intel_pxp_irq_handler - Proxies KCR interrupts to PXP.
+ * @gt: valid GT instance
+ * @iir: GT interrupt vector associated with the interrupt
+ *
+ * Dispatches each vector element into an IRQ to PXP.
+ */
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+ struct drm_i915_private *i915;
+ const u32 events = iir & i915->pxp.handled_irr;
+
+ if (!gt || !gt->i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ i915 = gt->i915;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!events)) {
+ drm_err(&i915->drm, "%s returned due to iir=[0x%04x]\n", __func__, iir);
+ return;
+ }
+
+ intel_pxp_mask_irq(gt, i915->pxp.handled_irr);
+
+ i915->pxp.current_events |= events;
+ schedule_work(&i915->pxp.irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 0b83d33045f3..7966dc275b54 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -8,18 +8,54 @@
#include <drm/drm_file.h>
+#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
+#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
+#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+
+enum pxp_sm_session_req {
+ /* Request KMD to allocate session id and move it to IN INIT */
+ PXP_SM_REQ_SESSION_ID_INIT = 0x0,
+ /* Inform KMD that UMD has completed the initialization */
+ PXP_SM_REQ_SESSION_IN_PLAY,
+ /* Request KMD to terminate the session */
+ PXP_SM_REQ_SESSION_TERMINATE
+};
+
struct pxp_context;
struct intel_pxp {
+ struct work_struct irq_work;
+ u32 handled_irr;
+ u32 current_events;
+
struct pxp_context *ctx;
};
+struct intel_gt;
struct drm_i915_private;
#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
+int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
+int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
+
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
#else
+static inline void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
+{
+}
+
+static inline int i915_pxp_teardown_required_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
+static inline int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
+{
+ return 0;
+}
+
static inline int intel_pxp_init(struct drm_i915_private *i915)
{
return 0;
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2020-12-07 10:21 ` Joonas Lahtinen
2020-12-08 0:34 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 10:21 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:20)
> Create the irq worker that serves as callback handler, those
> callback stubs should be called while the hardware key teardown
> occurs.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_gt_irq.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir)
> {
> @@ -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(gt, iir);
We should take >->pxp as the first parameter and keep a tight scope.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,58 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
>
> +static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
Again, we should be taking intel_pxp as parameter to tighten the scope.
> +{
> + /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
> + intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK, mask << 16);
Instead of writing to register that is indicated to be "reserved"
(RSVD), we should properly document the register in i915_reg.h and the
comment should not be needed.
> +static void intel_pxp_irq_work(struct work_struct *work)
> +{
> + struct intel_pxp *pxp_ptr = container_of(work, typeof(*pxp_ptr), irq_work);
_ptr is a tautology, we can already see it's apointer.
> + struct drm_i915_private *i915 = container_of(pxp_ptr, typeof(*i915), pxp);
We should go from intel_pxp to intel_gt to i915 here, once the struct
intel_pxp member is moved inside intel_gt
> + u32 events = 0;
> +
> + spin_lock_irq(&i915->gt.irq_lock);
> + events = fetch_and_zero(&pxp_ptr->current_events);
> + spin_unlock_irq(&i915->gt.irq_lock);
> +
> + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
> + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
> + intel_pxp_teardown_required_callback(i915);
> +
> + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
> + intel_pxp_global_terminate_complete_callback(i915);
The mapping between the callbacks and the hardware events are unclear.
These all seem like display related events, so we probably need a split
between the GT and display PXP code.
It's hard to review as this only adds stubs and no actual flow. I think
teardown interrupt handling should come later in the series after init
and other code has been added.
> @@ -17,9 +69,45 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
This INFO message is wrongly placed, either it should say "initializing"
and be at the beginning or "initialized" and be at the end. Also see
previous patch for more comments.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -8,18 +8,54 @@
>
> #include <drm/drm_file.h>
>
> +#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1)
> +#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> +#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
> +
> +enum pxp_sm_session_req {
> + /* Request KMD to allocate session id and move it to IN INIT */
> + PXP_SM_REQ_SESSION_ID_INIT = 0x0,
> + /* Inform KMD that UMD has completed the initialization */
> + PXP_SM_REQ_SESSION_IN_PLAY,
> + /* Request KMD to terminate the session */
> + PXP_SM_REQ_SESSION_TERMINATE
> +};
This enum here feels like a misplaced hunk. We should be adding the
enums and structs only when they are used in the patch. Reviewing the
logic and looking for dead code is much harder when structs are
introduced way earlier than they are used.
We should be adding the base structs at most and extending them as we
add more functionality as we go.
Regards, Joonas
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub
2020-12-07 10:21 ` Joonas Lahtinen
@ 2020-12-08 0:34 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-08 0:34 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Hi Joonas,
All the modification will be included in rev2. Thanks!
> We should take >->pxp as the first parameter and keep a tight scope.
DONE
> Again, we should be taking intel_pxp as parameter to tighten the scope.
DONE
>Instead of writing to register that is indicated to be "reserved" (RSVD), we should properly document the register in i915_reg.h and the comment should not be needed.
DONE, remove RSVD from its name and add document in i915_reg.h
> This INFO message is wrongly placed, either it should say "initializing" and be at the beginning or "initialized" and be at the end. Also see previous patch for more comments.
DONE,
>_ptr is a tautology, we can already see it's apointer.
DONE, remove the "_ptr"
> We should go from intel_pxp to intel_gt to i915 here, once the struct intel_pxp member is moved inside intel_gt
DONE, yes now pxp is in intel_gt
>The mapping between the callbacks and the hardware events are unclear.
>These all seem like display related events, so we probably need a split between the GT and display PXP code.
>It's hard to review as this only adds stubs and no actual flow. I think teardown interrupt handling should come later in the series after init and other code has been added.
Personally I would still prefer to put this in gt instead of display, because when teardown happen it means the "crypto engine" (This should belong to gt) has loss the key for display.
>This INFO message is wrongly placed, either it should say "initializing"
>and be at the beginning or "initialized" and be at the end. Also see previous patch for more comments.
DONE, change the log as "Protected Xe Path (PXP) protected content support initialized " at the end.
>This enum here feels like a misplaced hunk. We should be adding the enums and structs only when they are used in the patch. Reviewing the logic and looking for dead code is much harder when structs are introduced way earlier than they are used.
>We should be adding the base structs at most and extending them as we add more functionality as we go.
DONE, Thanks for capturing this, this enum is for session management only and I have removed this.
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 2:21 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub
Quoting Huang, Sean Z (2020-12-07 02:21:20)
> Create the irq worker that serves as callback handler, those callback
> stubs should be called while the hardware key teardown occurs.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -13,6 +13,7 @@
> #include "intel_gt_irq.h"
> #include "intel_uncore.h"
> #include "intel_rps.h"
> +#include "pxp/intel_pxp.h"
>
> static void guc_irq_handler(struct intel_guc *guc, u16 iir) { @@
> -106,6 +107,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(>->rps, iir);
>
> + if (instance == OTHER_KCR_INSTANCE)
> + return intel_pxp_irq_handler(gt, iir);
We should take >->pxp as the first parameter and keep a tight scope.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,58 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
>
> +static void intel_pxp_write_irq_mask_reg(struct drm_i915_private
> +*i915, u32 mask)
Again, we should be taking intel_pxp as parameter to tighten the scope.
> +{
> + /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
> + intel_uncore_write(&i915->uncore, GEN11_CRYPTO_RSVD_INTR_MASK,
> +mask << 16);
Instead of writing to register that is indicated to be "reserved"
(RSVD), we should properly document the register in i915_reg.h and the comment should not be needed.
> +static void intel_pxp_irq_work(struct work_struct *work) {
> + struct intel_pxp *pxp_ptr = container_of(work,
> +typeof(*pxp_ptr), irq_work);
_ptr is a tautology, we can already see it's apointer.
> + struct drm_i915_private *i915 = container_of(pxp_ptr,
> + typeof(*i915), pxp);
We should go from intel_pxp to intel_gt to i915 here, once the struct intel_pxp member is moved inside intel_gt
> + u32 events = 0;
> +
> + spin_lock_irq(&i915->gt.irq_lock);
> + events = fetch_and_zero(&pxp_ptr->current_events);
> + spin_unlock_irq(&i915->gt.irq_lock);
> +
> + if (events & PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED ||
> + events & PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ)
> + intel_pxp_teardown_required_callback(i915);
> +
> + if (events & PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE)
> + intel_pxp_global_terminate_complete_callback(i915);
The mapping between the callbacks and the hardware events are unclear.
These all seem like display related events, so we probably need a split between the GT and display PXP code.
It's hard to review as this only adds stubs and no actual flow. I think teardown interrupt handling should come later in the series after init and other code has been added.
> @@ -17,9 +69,45 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n",
> i915);
This INFO message is wrongly placed, either it should say "initializing"
and be at the beginning or "initialized" and be at the end. Also see previous patch for more comments.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -8,18 +8,54 @@
>
> #include <drm/drm_file.h>
>
> +#define PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED BIT(1) #define
> +PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2) #define
> +PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
> +
> +enum pxp_sm_session_req {
> + /* Request KMD to allocate session id and move it to IN INIT */
> + PXP_SM_REQ_SESSION_ID_INIT = 0x0,
> + /* Inform KMD that UMD has completed the initialization */
> + PXP_SM_REQ_SESSION_IN_PLAY,
> + /* Request KMD to terminate the session */
> + PXP_SM_REQ_SESSION_TERMINATE
> +};
This enum here feels like a misplaced hunk. We should be adding the enums and structs only when they are used in the patch. Reviewing the logic and looking for dead code is much harder when structs are introduced way earlier than they are used.
We should be adding the base structs at most and extending them as we add more functionality as we go.
Regards, Joonas
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states.
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 01/16] drm/i915/pxp: Introduce Intel PXP component Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 02/16] drm/i915/pxp: Enable PXP irq worker and callback stub Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 10:50 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
` (15 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Add PXP context which represents combined view
of driver and logical HW states.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 ++++++++++++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp_context.c | 45 ++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_context.h | 44 +++++++++++++++++++
5 files changed, 122 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_context.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a53ea3c88f71..99efac469cc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,7 +256,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_context.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 07faaadb0031..769bfd9bc6b8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_context.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
{
@@ -28,12 +29,28 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+
+ i915->pxp.ctx->global_state_attacked = true;
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+
return 0;
}
static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
{
- return 0;
+ int ret = 0;
+
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_attacked)
+ i915->pxp.ctx->global_state_attacked = false;
+
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+
+ return ret;
}
static void intel_pxp_irq_work(struct work_struct *work)
@@ -69,6 +86,12 @@ int intel_pxp_init(struct drm_i915_private *i915)
drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
+ i915->pxp.ctx = intel_pxp_create_ctx(i915);
+ if (!i915->pxp.ctx) {
+ drm_err(&i915->drm, "Failed to create pxp ctx\n");
+ return -EFAULT;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -80,6 +103,10 @@ int intel_pxp_init(struct drm_i915_private *i915)
void intel_pxp_uninit(struct drm_i915_private *i915)
{
+ if (!i915 || INTEL_GEN(i915) < 12)
+ return;
+
+ intel_pxp_destroy_ctx(i915);
}
/**
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 7966dc275b54..eb0ec4a07d3d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define MAX_TYPE0_SESSIONS 16
+#define MAX_TYPE1_SESSIONS 6
+
enum pxp_sm_session_req {
/* Request KMD to allocate session id and move it to IN INIT */
PXP_SM_REQ_SESSION_ID_INIT = 0x0,
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.c b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
new file mode 100644
index 000000000000..c340c375daac
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp_context.h"
+
+/**
+ * intel_pxp_create_ctx - To create a new pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: pointer to new_ctx, NULL for failure
+ */
+struct pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915)
+{
+ struct pxp_context *new_ctx = NULL;
+
+ new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
+ if (!new_ctx)
+ return NULL;
+
+ get_random_bytes(&new_ctx->ctx_id, sizeof(new_ctx->ctx_id));
+
+ new_ctx->global_state_attacked = false;
+
+ mutex_init(&new_ctx->ctx_mutex);
+
+ INIT_LIST_HEAD(&new_ctx->active_pxp_type0_sessions);
+ INIT_LIST_HEAD(&new_ctx->active_pxp_type1_sessions);
+ INIT_LIST_HEAD(&new_ctx->user_ctx_list);
+
+ return new_ctx;
+}
+
+/**
+ * intel_pxp_destroy_ctx - To destroy the pxp context.
+ * @i915: i915 device handle.
+ *
+ * Return: return 0 for success, failure otherwise.
+ */
+void intel_pxp_destroy_ctx(struct drm_i915_private *i915)
+{
+ kfree(i915->pxp.ctx);
+ i915->pxp.ctx = NULL;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_context.h b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
new file mode 100644
index 000000000000..e0794dfb548d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CONTEXT_H__
+#define __INTEL_PXP_CONTEXT_H__
+
+#include <linux/list.h>
+#include "i915_drv.h"
+#include "pxp/intel_pxp.h"
+
+/* struct pxp_context - Represents combined view of driver and logical HW states. */
+struct pxp_context {
+ /** @ctx_mutex: mutex to protect the pxp context */
+ struct mutex ctx_mutex;
+
+ struct list_head active_pxp_type0_sessions;
+ struct list_head active_pxp_type1_sessions;
+
+ struct list_head user_ctx_list;
+
+ u32 type0_session_pxp_tag[MAX_TYPE0_SESSIONS];
+ u32 type1_session_pxp_tag[MAX_TYPE1_SESSIONS];
+
+ int ctx_id;
+
+ bool global_state_attacked;
+ bool global_state_in_suspend;
+ bool flag_display_hm_surface_keys;
+};
+
+struct pxp_user_ctx {
+ /** @listhead: linked list infrastructure, do not change its order. */
+ struct list_head listhead;
+
+ /** @user_ctx: user space context id */
+ u32 user_ctx;
+};
+
+struct pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915);
+void intel_pxp_destroy_ctx(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_CONTEXT_H__ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states.
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states Huang, Sean Z
@ 2020-12-07 10:50 ` Joonas Lahtinen
2020-12-08 20:11 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 10:50 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:21)
> Add PXP context which represents combined view
> of driver and logical HW states.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "intel_pxp.h"
> +#include "intel_pxp_context.h"
>
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
> {
> @@ -28,12 +29,28 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
>
> static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
> {
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> +
> + i915->pxp.ctx->global_state_attacked = true;
> + i915->pxp.ctx->flag_display_hm_surface_keys = false;
> +
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
This should really have its own function intel_pxp_context_foobar()
that is called from this point. Also, as you see "ctx_mutex" is tautology
and "mutex" is enough when it's member of "ctx".
We seem to have two separate interrupts at the top level handler. Either
we should handle the interrupts separately or just have a single variable
"teardown_requested" that is flagged from here.
The effects of setting these variables can't be reviewed as not even the
initialization sequence has been added by the series, so this should
definitely be much more towards the end of the series.
> +
> return 0;
> }
>
> static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
> {
> - return 0;
> + int ret = 0;
> +
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> +
> + if (i915->pxp.ctx->global_state_attacked)
> + i915->pxp.ctx->global_state_attacked = false;
The if() check is pointless. Again, we should not directly poke such
deeply, but wrap it in a function.
> +
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
> +
> + return ret;
> }
>
> static void intel_pxp_irq_work(struct work_struct *work)
> @@ -69,6 +86,12 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n", i915);
>
> + i915->pxp.ctx = intel_pxp_create_ctx(i915);
> + if (!i915->pxp.ctx) {
> + drm_err(&i915->drm, "Failed to create pxp ctx\n");
> + return -EFAULT;
I think this should be -ENOMEM.
> + }
As we only intend to support a single context, we should avoid a pointer
+ alloc here and just use intel_pxp_context_init(&pxp->ctx)
> @@ -80,6 +103,10 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> void intel_pxp_uninit(struct drm_i915_private *i915)
> {
> + if (!i915 || INTEL_GEN(i915) < 12)
> + return;
> +
> + intel_pxp_destroy_ctx(i915);
intel_pxp_context_fini(&pxp->ctx);
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -12,6 +12,9 @@
> #define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> #define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
>
> +#define MAX_TYPE0_SESSIONS 16
> +#define MAX_TYPE1_SESSIONS 6
These should be prefixed with PXP_ also, we should not need these at all
if we only intend to support single-session.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +
> +/**
> + * intel_pxp_create_ctx - To create a new pxp context.
> + * @i915: i915 device handle.
> + *
> + * Return: pointer to new_ctx, NULL for failure
> + */
> +struct pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915)
> +{
> + struct pxp_context *new_ctx = NULL;
Adding "new_" is tautology here. Also, we try to separate the allocation
and init to separate functions so that we can embed, like I suggested
above to embed the singleton context to intel_pxp as member, not
pointer.
> +
> + new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
> + if (!new_ctx)
> + return NULL;
> +
> + get_random_bytes(&new_ctx->ctx_id, sizeof(new_ctx->ctx_id));
"ctx_id" is again repeating as it's member of "ctx", so "id" should be
fine for member name.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/list.h>
> +#include "i915_drv.h"
> +#include "pxp/intel_pxp.h"
> +
> +/* struct pxp_context - Represents combined view of driver and logical HW states. */
> +struct pxp_context {
> + /** @ctx_mutex: mutex to protect the pxp context */
> + struct mutex ctx_mutex;
> +
> + struct list_head active_pxp_type0_sessions;
> + struct list_head active_pxp_type1_sessions;
We shouldn't need any session tracking as we only have single session.
> + struct list_head user_ctx_list;
> +
> + u32 type0_session_pxp_tag[MAX_TYPE0_SESSIONS];
> + u32 type1_session_pxp_tag[MAX_TYPE1_SESSIONS];
We shouldn't need any of these arrays as we only have single session.
> +
> + int ctx_id;
> +
> + bool global_state_attacked;
> + bool global_state_in_suspend;
> + bool flag_display_hm_surface_keys;
We should only add each variable only when the handler code is
introduced. For now the names don't really give a good hint about
what their usage model will be, so can't recommend better names.
> +};
> +
> +struct pxp_user_ctx {
> + /** @listhead: linked list infrastructure, do not change its order. */
> + struct list_head listhead;
> +
> + /** @user_ctx: user space context id */
> + u32 user_ctx;
> +};
In this series, there will be no user space context ID, but only a
singleton implicit session. So we should not need any tracking code.
Regards, Joonas
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states.
2020-12-07 10:50 ` Joonas Lahtinen
@ 2020-12-08 20:11 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-08 20:11 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Hi Joonas,
> This should really have its own function intel_pxp_context_foobar() that is called from this point.
DONE, remove global_state_attacked and flag_display_hm_surface_keys from this patch and only added them if necessary.
> Also, as you see "ctx_mutex" is tautology and "mutex" is enough when it's member of "ctx".
DONE
> We seem to have two separate interrupts at the top level handler. Either we should handle the interrupts separately or just have a single variable "teardown_requested" that is flagged from here.
I would prefer to handle them separately because they are indeed coming from different irq, having different handler would be more readable.
> The effects of setting these variables can't be reviewed as not even the initialization sequence has been added by the series, so this should definitely be much more towards the end of the series.
DONE, got it, let me re-order the commit sequence and move this patch to the tail.
> The if() check is pointless. Again, we should not directly poke such deeply, but wrap it in a function.
DONE
> I think this should be -ENOMEM.
DONE, no need to allocate or return error.
> As we only intend to support a single context, we should avoid a pointer
> + alloc here and just use intel_pxp_context_init(&pxp->ctx)
DONE
> intel_pxp_context_fini(&pxp->ctx);
DONE
> These should be prefixed with PXP_ also, we should not need these at all if we only intend to support single-session.
DONE, remove them since not required by single session usage.
> Adding "new_" is tautology here. Also, we try to separate the allocation and init to separate functions so that we can embed, like I suggested above to embed the singleton context to intel_pxp as member, not pointer.
DONE
> "ctx_id" is again repeating as it's member of "ctx", so "id" should be fine for member name.
DONE
> We shouldn't need any session tracking as we only have single session.
I have trimmed the code only for single session usage only, but hopefully we could have at least one tag for this single session.
> We should only add each variable only when the handler code is introduced. For now the names don't really give a good hint about what their usage model will be, so can't recommend better names.
DONE
> In this series, there will be no user space context ID, but only a singleton implicit session. So we should not need any tracking code.
DONE
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 2:51 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states.
Quoting Huang, Sean Z (2020-12-07 02:21:21)
> Add PXP context which represents combined view of driver and logical
> HW states.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "intel_pxp.h"
> +#include "intel_pxp_context.h"
>
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private
> *i915, u32 mask) { @@ -28,12 +29,28 @@ static void
> intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
>
> static int intel_pxp_teardown_required_callback(struct
> drm_i915_private *i915) {
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> +
> + i915->pxp.ctx->global_state_attacked = true;
> + i915->pxp.ctx->flag_display_hm_surface_keys = false;
> +
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
This should really have its own function intel_pxp_context_foobar() that is called from this point. Also, as you see "ctx_mutex" is tautology and "mutex" is enough when it's member of "ctx".
We seem to have two separate interrupts at the top level handler. Either we should handle the interrupts separately or just have a single variable "teardown_requested" that is flagged from here.
The effects of setting these variables can't be reviewed as not even the initialization sequence has been added by the series, so this should definitely be much more towards the end of the series.
> +
> return 0;
> }
>
> static int intel_pxp_global_terminate_complete_callback(struct
> drm_i915_private *i915) {
> - return 0;
> + int ret = 0;
> +
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> +
> + if (i915->pxp.ctx->global_state_attacked)
> + i915->pxp.ctx->global_state_attacked = false;
The if() check is pointless. Again, we should not directly poke such deeply, but wrap it in a function.
> +
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
> +
> + return ret;
> }
>
> static void intel_pxp_irq_work(struct work_struct *work) @@ -69,6
> +86,12 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> drm_info(&i915->drm, "i915 PXP is inited with i915=[%p]\n",
> i915);
>
> + i915->pxp.ctx = intel_pxp_create_ctx(i915);
> + if (!i915->pxp.ctx) {
> + drm_err(&i915->drm, "Failed to create pxp ctx\n");
> + return -EFAULT;
I think this should be -ENOMEM.
> + }
As we only intend to support a single context, we should avoid a pointer
+ alloc here and just use intel_pxp_context_init(&pxp->ctx)
> @@ -80,6 +103,10 @@ int intel_pxp_init(struct drm_i915_private *i915)
>
> void intel_pxp_uninit(struct drm_i915_private *i915) {
> + if (!i915 || INTEL_GEN(i915) < 12)
> + return;
> +
> + intel_pxp_destroy_ctx(i915);
intel_pxp_context_fini(&pxp->ctx);
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -12,6 +12,9 @@
> #define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2) #define
> PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
>
> +#define MAX_TYPE0_SESSIONS 16
> +#define MAX_TYPE1_SESSIONS 6
These should be prefixed with PXP_ also, we should not need these at all if we only intend to support single-session.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.c
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp_context.h"
> +
> +/**
> + * intel_pxp_create_ctx - To create a new pxp context.
> + * @i915: i915 device handle.
> + *
> + * Return: pointer to new_ctx, NULL for failure */ struct
> +pxp_context *intel_pxp_create_ctx(struct drm_i915_private *i915) {
> + struct pxp_context *new_ctx = NULL;
Adding "new_" is tautology here. Also, we try to separate the allocation and init to separate functions so that we can embed, like I suggested above to embed the singleton context to intel_pxp as member, not pointer.
> +
> + new_ctx = kzalloc(sizeof(*new_ctx), GFP_KERNEL);
> + if (!new_ctx)
> + return NULL;
> +
> + get_random_bytes(&new_ctx->ctx_id, sizeof(new_ctx->ctx_id));
"ctx_id" is again repeating as it's member of "ctx", so "id" should be fine for member name.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_context.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_CONTEXT_H__
> +#define __INTEL_PXP_CONTEXT_H__
> +
> +#include <linux/list.h>
> +#include "i915_drv.h"
> +#include "pxp/intel_pxp.h"
> +
> +/* struct pxp_context - Represents combined view of driver and
> +logical HW states. */ struct pxp_context {
> + /** @ctx_mutex: mutex to protect the pxp context */
> + struct mutex ctx_mutex;
> +
> + struct list_head active_pxp_type0_sessions;
> + struct list_head active_pxp_type1_sessions;
We shouldn't need any session tracking as we only have single session.
> + struct list_head user_ctx_list;
> +
> + u32 type0_session_pxp_tag[MAX_TYPE0_SESSIONS];
> + u32 type1_session_pxp_tag[MAX_TYPE1_SESSIONS];
We shouldn't need any of these arrays as we only have single session.
> +
> + int ctx_id;
> +
> + bool global_state_attacked;
> + bool global_state_in_suspend;
> + bool flag_display_hm_surface_keys;
We should only add each variable only when the handler code is introduced. For now the names don't really give a good hint about what their usage model will be, so can't recommend better names.
> +};
> +
> +struct pxp_user_ctx {
> + /** @listhead: linked list infrastructure, do not change its order. */
> + struct list_head listhead;
> +
> + /** @user_ctx: user space context id */
> + u32 user_ctx;
> +};
In this series, there will be no user space context ID, but only a singleton implicit session. So we should not need any tracking code.
Regards, Joonas
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (2 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 03/16] drm/i915/pxp: Add PXP context for logical hardware states Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 11:10 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state Huang, Sean Z
` (14 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Set the KCR init during the boot time, which is required by
hardware, to allow us doing further protection operation such
as sending commands to GPU or TEE
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/pxp/intel_pxp.c | 11 ++++++-
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 38 +++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 20 +++++++++++++
4 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 99efac469cc2..131bd8921565 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -257,7 +257,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
- pxp/intel_pxp_context.o
+ pxp/intel_pxp_context.o \
+ pxp/intel_pxp_sm.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 769bfd9bc6b8..d74a32b29716 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
{
@@ -77,6 +78,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
int intel_pxp_init(struct drm_i915_private *i915)
{
+ int ret;
+
if (!i915)
return -EINVAL;
@@ -92,13 +95,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
return -EFAULT;
}
+ ret = pxp_sm_set_kcr_init_reg(i915);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to set kcr init reg\n");
+ return ret;
+ }
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ |
PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE);
- return 0;
+ return ret;
}
void intel_pxp_uninit(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
new file mode 100644
index 000000000000..a2c9c71d2372
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_context.h"
+
+static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915)
+ return -EINVAL;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+
+ intel_uncore_write(&i915->uncore, reg_offset, regval);
+ }
+
+ return 0;
+}
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
+{
+ int ret;
+
+ ret = pxp_reg_write(i915, KCR_INIT.reg, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
+ if (ret)
+ drm_err(&i915->drm, "Failed to write()\n");
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
new file mode 100644
index 000000000000..d061f395aa16
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SM_H__
+#define __INTEL_PXP_SM_H__
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+#define KCR_INIT_MASK_SHIFT (16)
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+
+int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2020-12-07 11:10 ` Joonas Lahtinen
2020-12-09 4:01 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 11:10 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:22)
> Set the KCR init during the boot time, which is required by
> hardware, to allow us doing further protection operation such
> as sending commands to GPU or TEE
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_sm.h"
>
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
> {
> @@ -77,6 +78,8 @@ static void intel_pxp_irq_work(struct work_struct *work)
>
> int intel_pxp_init(struct drm_i915_private *i915)
> {
> + int ret;
> +
> if (!i915)
> return -EINVAL;
>
> @@ -92,13 +95,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
> return -EFAULT;
> }
>
> + ret = pxp_sm_set_kcr_init_reg(i915);
I think this should just be intel_pxp_sm_init() and then do whatever it
needs to initialize. Also as we plan on having only a single session, I
don't see why would we want a separate session management file/header.
So I would be inclined to just inline the KCR_INIT macro write here. If
this is moved to appropriate spot during intel_gt initialization, we
should have the hardware wakeref, so would be just a single
intel_uncore_write.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_sm.h"
> +#include "intel_pxp_context.h"
> +
> +static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
> +{
> + intel_wakeref_t wakeref;
> +
> + if (!i915)
> + return -EINVAL;
Again, GEM_BUG_ON(!i915) should suffice.
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> + i915_reg_t reg_offset = {offset};
See below, here we convert from u32 to i915_reg_t.
> +
> + intel_uncore_write(&i915->uncore, reg_offset, regval);
> + }
I don't think we want to grab the wakeref at a low level reg_write
function but at a higher levels to clearly distinct functions that need
to access hardware and those who don't.
> + return 0;
> +}
> +
> +int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
> +{
> + int ret;
> +
> + ret = pxp_reg_write(i915, KCR_INIT.reg, KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
See above related to offset. Here we convert to u32. We shouldn't escape
the protection offered by _MMIO macro.
Based on the register name this feels like it should somehow be related
to display init?
> + if (ret)
> + drm_err(&i915->drm, "Failed to write()\n");
There is an error message in the upper level function, so one of these
becomes redundant.
After this has been moved to intel_gt init, the hardware wakeref is
definitely held
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_SM_H__
> +#define __INTEL_PXP_SM_H__
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
If this is only used from single place, it should go to the .c file
that uses it.
Regards, Joonas
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time
2020-12-07 11:10 ` Joonas Lahtinen
@ 2020-12-09 4:01 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-09 4:01 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Hi Joonas,
> I think this should just be intel_pxp_sm_init() and then do whatever it needs to initialize. Also as we plan on having only a single session, I don't see why would we want a separate session management file/header.
> So I would be inclined to just inline the KCR_INIT macro write here. If this is moved to appropriate spot during intel_gt initialization, we should have the hardware wakeref, so would be just a single intel_uncore_write.
DONE, move to intel_gt so don't need the wakeref anymore, good suggestion, thanks!
> Again, GEM_BUG_ON(!i915) should suffice.
DONE, remove the check
> I don't think we want to grab the wakeref at a low level reg_write function but at a higher levels to clearly distinct functions that need to access hardware and those who don't.
DONE.
> There is an error message in the upper level function, so one of these becomes redundant.
> After this has been moved to intel_gt init, the hardware wakeref is definitely held
DONE
> See above related to offset. Here we convert to u32. We shouldn't escape the protection offered by _MMIO macro.
DONE
> Based on the register name this feels like it should somehow be related to display init?
This register is more like a PXP related reg rather than display, so I prefer still keep this in here.
> If this is only used from single place, it should go to the .c file that uses it.
DONE
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 3:11 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time
Quoting Huang, Sean Z (2020-12-07 02:21:22)
> Set the KCR init during the boot time, which is required by hardware,
> to allow us doing further protection operation such as sending
> commands to GPU or TEE
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,7 @@
> #include "i915_drv.h"
> #include "intel_pxp.h"
> #include "intel_pxp_context.h"
> +#include "intel_pxp_sm.h"
>
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private
> *i915, u32 mask) { @@ -77,6 +78,8 @@ static void
> intel_pxp_irq_work(struct work_struct *work)
>
> int intel_pxp_init(struct drm_i915_private *i915) {
> + int ret;
> +
> if (!i915)
> return -EINVAL;
>
> @@ -92,13 +95,19 @@ int intel_pxp_init(struct drm_i915_private *i915)
> return -EFAULT;
> }
>
> + ret = pxp_sm_set_kcr_init_reg(i915);
I think this should just be intel_pxp_sm_init() and then do whatever it needs to initialize. Also as we plan on having only a single session, I don't see why would we want a separate session management file/header.
So I would be inclined to just inline the KCR_INIT macro write here. If this is moved to appropriate spot during intel_gt initialization, we should have the hardware wakeref, so would be just a single intel_uncore_write.
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_sm.h"
> +#include "intel_pxp_context.h"
> +
> +static int pxp_reg_write(struct drm_i915_private *i915, u32 offset,
> +u32 regval) {
> + intel_wakeref_t wakeref;
> +
> + if (!i915)
> + return -EINVAL;
Again, GEM_BUG_ON(!i915) should suffice.
> +
> + with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> + i915_reg_t reg_offset = {offset};
See below, here we convert from u32 to i915_reg_t.
> +
> + intel_uncore_write(&i915->uncore, reg_offset, regval);
> + }
I don't think we want to grab the wakeref at a low level reg_write function but at a higher levels to clearly distinct functions that need to access hardware and those who don't.
> + return 0;
> +}
> +
> +int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915) {
> + int ret;
> +
> + ret = pxp_reg_write(i915, KCR_INIT.reg,
> + KCR_INIT_ALLOW_DISPLAY_ME_WRITES);
See above related to offset. Here we convert to u32. We shouldn't escape the protection offered by _MMIO macro.
Based on the register name this feels like it should somehow be related to display init?
> + if (ret)
> + drm_err(&i915->drm, "Failed to write()\n");
There is an error message in the upper level function, so one of these becomes redundant.
After this has been moved to intel_gt init, the hardware wakeref is definitely held
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_SM_H__
> +#define __INTEL_PXP_SM_H__
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +#define KCR_INIT_MASK_SHIFT (16)
> +/* Setting KCR Init bit is required after system boot */ #define
> +KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) <<
> +KCR_INIT_MASK_SHIFT))
If this is only used from single place, it should go to the .c file that uses it.
Regards, Joonas
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (3 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 04/16] drm/i915/pxp: set KCR reg init during the boot time Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 11:44 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
` (13 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Implement the functions to check the hardware protected session
state via reading the hardware register session in play.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 177 ++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 51 +++++++
3 files changed, 231 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index eb0ec4a07d3d..308d8d312a6d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -12,6 +12,9 @@
#define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
#define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
+#define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index a2c9c71d2372..6413f401d939 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -10,6 +10,21 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
+{
+ intel_wakeref_t wakeref;
+
+ if (!i915 || !regval)
+ return -EINVAL;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ i915_reg_t reg_offset = {offset};
+ *regval = intel_uncore_read(&i915->uncore, reg_offset);
+ }
+
+ return 0;
+}
+
static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
{
intel_wakeref_t wakeref;
@@ -26,6 +41,168 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
return 0;
}
+/**
+ * is_sw_session_active - Check if the given sw session id is active.
+ * @i915: i915 device handle.
+ * @session_type: Specified session type
+ * @session_index: Numeric session identifier.
+ * @is_in_play: Set false to return true if the specified session is active.
+ * Set true to also check if the session is active and in_play.
+ * @protection_mode: get the protection mode of specified session.
+ *
+ * The caller needs to use ctx_mutex lock to protect the session_list
+ * inside this function.
+ *
+ * Return : true if session with the same identifier is active (and in_play).
+ */
+static bool is_sw_session_active(struct drm_i915_private *i915, int session_type,
+ int session_index, bool is_in_play, int *protection_mode)
+{
+ struct pxp_protected_session *current_session;
+
+ lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
+
+ list_for_each_entry(current_session, pxp_session_list(i915, session_type), session_list) {
+ if (current_session->session_index == session_index) {
+ if (protection_mode)
+ *protection_mode = current_session->protection_mode;
+
+ if (is_in_play && !current_session->session_is_in_play)
+ return false;
+
+ return true;
+ }
+ }
+
+ /* session id not found. return false */
+ return false;
+}
+
+static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int session_index)
+{
+ u32 regval_sip = 0;
+ u32 reg_session_id_mask;
+ bool hw_session_is_in_play = false;
+ int ret = 0;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, ®val_sip);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int session_index)
+{
+ int ret = 0;
+ u32 regval_tsip_low = 0;
+ u32 regval_tsip_high = 0;
+ u64 reg_session_id_mask;
+ u64 regval_tsip;
+ bool hw_session_is_in_play = false;
+
+ if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS)
+ goto end;
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, ®val_tsip_low);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_HIGH.reg, ®val_tsip_high);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to pxp_sm_reg_read()\n");
+ goto end;
+ }
+
+ reg_session_id_mask = (1 << session_index);
+ regval_tsip = ((u64)regval_tsip_high << 32) | regval_tsip_low;
+ hw_session_is_in_play = (bool)(regval_tsip & reg_session_id_mask);
+end:
+ return hw_session_is_in_play;
+}
+
+static bool is_hw_session_in_play(struct drm_i915_private *i915,
+ int session_type, int session_index)
+{
+ bool is_in_play = false;
+
+ if (session_type == SESSION_TYPE_TYPE0)
+ is_in_play = is_hw_type0_session_in_play(i915, session_index);
+ else if (session_type == SESSION_TYPE_TYPE1)
+ is_in_play = is_hw_type1_session_in_play(i915, session_index);
+ else
+ drm_err(&i915->drm, "Failed to %s invalid session_type=[%d]\n",
+ __func__, session_type);
+
+ return is_in_play;
+}
+
+/* check hw session in play reg if match the current sw state */
+static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, int session_type)
+{
+ const int max_retry = 10;
+ const int ms_delay = 10;
+ int retry = 0;
+ int ret;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ ret = -EINVAL;
+ for (retry = 0; retry < max_retry; retry++) {
+ if (is_hw_session_in_play(i915, session_type, session_index) ==
+ is_sw_session_active(i915, session_type, session_index, true, NULL)) {
+ ret = 0;
+ break;
+ }
+
+ msleep(ms_delay);
+ }
+
+ return ret;
+}
+
+/**
+ * check_if_protected_type0_sessions_are_attacked - To check if type0 active sessions are attacked.
+ * @i915: i915 device handle.
+ *
+ * Return: true if HW shows protected sessions are attacked, false otherwise.
+ */
+static bool check_if_protected_type0_sessions_are_attacked(struct drm_i915_private *i915)
+{
+ i915_reg_t kcr_status_reg = KCR_STATUS_1;
+ u32 reg_value = 0;
+ u32 mask = 0x80000000;
+ int ret;
+
+ if (!i915)
+ return false;
+
+ if (i915->pxp.ctx->global_state_attacked)
+ return true;
+
+ ret = pxp_sm_reg_read(i915, kcr_status_reg.reg, ®_value);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to pxp_sm_reg_read\n");
+ goto end;
+ }
+
+ if (reg_value & mask)
+ return true;
+end:
+ return false;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index d061f395aa16..222a879be96d 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -15,6 +15,57 @@
/* Setting KCR Init bit is required after system boot */
#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
+#define KCR_STATUS_1 _MMIO(0x320f4)
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
+#define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31 */
+#define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play 32-63 */
+
+enum pxp_session_types {
+ SESSION_TYPE_TYPE0 = 0,
+ SESSION_TYPE_TYPE1 = 1,
+
+ SESSION_TYPE_MAX
+};
+
+enum pxp_protection_modes {
+ PROTECTION_MODE_NONE = 0,
+ PROTECTION_MODE_LM = 2,
+ PROTECTION_MODE_HM = 3,
+ PROTECTION_MODE_SM = 6,
+
+ PROTECTION_MODE_ALL
+};
+
+/**
+ * struct pxp_protected_session - linked list to track all active sessions.
+ */
+struct pxp_protected_session {
+ /** @session_list: linked list infrastructure, do not change its order. */
+ struct list_head session_list;
+
+ /** @session_index: Numeric identifier for this protected session */
+ int session_index;
+ /** @session_type: Type of session */
+ int session_type;
+ /** @protection_mode: mode of protection requested */
+ int protection_mode;
+ /** @context_id: context identifier of the protected session requestor */
+ int context_id;
+ /** @pid: pid of this session's creator */
+ int pid;
+ /** @drmfile: pointer to drm_file, which is allocated on device file open() call */
+ struct drm_file *drmfile;
+
+ /**
+ * @session_is_in_play: indicates whether the session has been established
+ * in the HW root of trust if this flag is false, it
+ * indicates an application has reserved this session,
+ * but has not * established the session in the
+ * hardware yet.
+ */
+ bool session_is_in_play;
+};
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
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^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state Huang, Sean Z
@ 2020-12-07 11:44 ` Joonas Lahtinen
0 siblings, 0 replies; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 11:44 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:23)
> Implement the functions to check the hardware protected session
> state via reading the hardware register session in play.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
<SNIP>
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -12,6 +12,9 @@
> #define PXP_IRQ_VECTOR_DISPLAY_APP_TERM_PER_FW_REQ BIT(2)
> #define PXP_IRQ_VECTOR_PXP_DISP_STATE_RESET_COMPLETE BIT(3)
>
> +#define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \
> + &(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions)
Definitely should be inline function with proper scope, and not taking
i915 directly. But we should only ever need a single session, so the
lists should not be needed.
> +
> #define MAX_TYPE0_SESSIONS 16
> #define MAX_TYPE1_SESSIONS 6
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> index a2c9c71d2372..6413f401d939 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -10,6 +10,21 @@
> #include "intel_pxp_sm.h"
> #include "intel_pxp_context.h"
>
> +static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
See previous patch, has all the same problems as the write func.
> @@ -26,6 +41,168 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
> return 0;
> }
>
> +/**
> + * is_sw_session_active - Check if the given sw session id is active.
> + * @i915: i915 device handle.
> + * @session_type: Specified session type
> + * @session_index: Numeric session identifier.
> + * @is_in_play: Set false to return true if the specified session is active.
> + * Set true to also check if the session is active and in_play.
> + * @protection_mode: get the protection mode of specified session.
> + *
> + * The caller needs to use ctx_mutex lock to protect the session_list
> + * inside this function.
> + *
> + * Return : true if session with the same identifier is active (and in_play).
> + */
> +static bool is_sw_session_active(struct drm_i915_private *i915, int session_type,
> + int session_index, bool is_in_play, int *protection_mode)
By my understanding we only have a singleton session. Would expect
the same protection mode always, so this should be greatly simplified.
> +{
> + struct pxp_protected_session *current_session;
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + list_for_each_entry(current_session, pxp_session_list(i915, session_type), session_list) {
> + if (current_session->session_index == session_index) {
This is an extremely slow way of finding a session. But as we only
expect a single session, I think this whole function becomes
unnecessary.
> + if (protection_mode)
> + *protection_mode = current_session->protection_mode;
> +
> + if (is_in_play && !current_session->session_is_in_play)
> + return false;
> +
> + return true;
> + }
> + }
> +
> + /* session id not found. return false */
> + return false;
> +}
> +
> +static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int session_index)
> +{
> + u32 regval_sip = 0;
> + u32 reg_session_id_mask;
> + bool hw_session_is_in_play = false;
> + int ret = 0;
> +
> + if (!i915 || session_index < 0 || session_index >= MAX_TYPE0_SESSIONS)
> + goto end;
> +
> + ret = pxp_sm_reg_read(i915, GEN12_KCR_SIP.reg, ®val_sip);
As mentioned in previous patch, we should not wrap the MMIO read macros,
but hold the wakeref at higher level.
> + if (ret) {
> + drm_err(&i915->drm, "Failed to read()\n");
I don't think these will be worthy ERROR message. We should collate
multiple error checks and at a top level emit an error message if
something failed.
> + goto end;
> + }
> +
> + reg_session_id_mask = (1 << session_index);
> + hw_session_is_in_play = (bool)(regval_sip & reg_session_id_mask);
All this should follow existing programming conventions and use existing
macros, so this function should not be much more than:
kcr_sip = intel_uncore_read(uncore, GEN12_KCR_SIP);
return kcr_sip & BIT(index);
> +end:
> + return hw_session_is_in_play;
> +}
> +
> +static bool is_hw_type1_session_in_play(struct drm_i915_private *i915, int session_index)
> +{
> + int ret = 0;
> + u32 regval_tsip_low = 0;
> + u32 regval_tsip_high = 0;
> + u64 reg_session_id_mask;
> + u64 regval_tsip;
> + bool hw_session_is_in_play = false;
> +
> + if (!i915 || session_index < 0 || session_index >= MAX_TYPE1_SESSIONS)
> + goto end;
> +
> + ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_LOW.reg, ®val_tsip_low);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to pxp_sm_reg_read()\n");
> + goto end;
> + }
> +
> + ret = pxp_sm_reg_read(i915, GEN12_KCR_TSIP_HIGH.reg, ®val_tsip_high);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to pxp_sm_reg_read()\n");
> + goto end;
> + }
> +
> + reg_session_id_mask = (1 << session_index);
> + regval_tsip = ((u64)regval_tsip_high << 32) | regval_tsip_low;
> + hw_session_is_in_play = (bool)(regval_tsip & reg_session_id_mask);
By using existing intel_uncore_read64 this becomes a two-liner like the
previous function. We should embrace the existing functions and _MMIO
protection across the codebase, and not use per-domain read/write funcs.
> +end:
> + return hw_session_is_in_play;
> +}
> +
> +static bool is_hw_session_in_play(struct drm_i915_private *i915,
> + int session_type, int session_index)
> +{
> + bool is_in_play = false;
> +
> + if (session_type == SESSION_TYPE_TYPE0)
> + is_in_play = is_hw_type0_session_in_play(i915, session_index);
> + else if (session_type == SESSION_TYPE_TYPE1)
> + is_in_play = is_hw_type1_session_in_play(i915, session_index);
> + else
> + drm_err(&i915->drm, "Failed to %s invalid session_type=[%d]\n",
> + __func__, session_type);
This would be a kernel programmer level error, so definitely should not
be ERROR level message. In other places, like the macro at the top, we
assume there to only be two types.
Type0 and Type1 are terrible names to be used for variables, so we
should use something that better matches the difference between the two.
This difference should also be explained when the two different types
are added.
> +
> + return is_in_play;
> +}
> +
> +/* check hw session in play reg if match the current sw state */
> +static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, int session_type)
The function name gives an impression as if it would do something to
synchronize, when actually it just waits, so it should be named *_wait_*
appropriately.
> +{
> + const int max_retry = 10;
> + const int ms_delay = 10;
> + int retry = 0;
> + int ret;
> +
> + if (!i915 || session_type >= SESSION_TYPE_MAX)
> + return -EINVAL;
> +
> + ret = -EINVAL;
> + for (retry = 0; retry < max_retry; retry++) {
> + if (is_hw_session_in_play(i915, session_type, session_index) ==
> + is_sw_session_active(i915, session_type, session_index, true, NULL)) {
> + ret = 0;
> + break;
> + }
> +
> + msleep(ms_delay);
> + }
We already have existing wait_for_* helper macros and those should be
used.
> +
> + return ret;
> +}
> +
> +/**
> + * check_if_protected_type0_sessions_are_attacked - To check if type0 active sessions are attacked.
> + * @i915: i915 device handle.
> + *
> + * Return: true if HW shows protected sessions are attacked, false otherwise.
> + */
> +static bool check_if_protected_type0_sessions_are_attacked(struct drm_i915_private *i915)
> +{
> + i915_reg_t kcr_status_reg = KCR_STATUS_1;
> + u32 reg_value = 0;
> + u32 mask = 0x80000000;
The different registers touched should be at the top of the .c file.
We shouldn't hardcode the mask here, but we should document them at the
time of _MMIO define just like we do for the rest of the registers.
> + int ret;
> +
> + if (!i915)
> + return false;
> +
> + if (i915->pxp.ctx->global_state_attacked)
> + return true;
> +
> + ret = pxp_sm_reg_read(i915, kcr_status_reg.reg, ®_value);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to pxp_sm_reg_read\n");
> + goto end;
> + }
> +
> + if (reg_value & mask)
> + return true;
The meaning of the mask should be defined like for other regs. Again
this just becomes a check for:
value = intel_uncore_read(uncore, KCR_STATUS_1);
return value & KCR_STATUS_SOMETHING;
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -15,6 +15,57 @@
> /* Setting KCR Init bit is required after system boot */
> #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES (BIT(14) | (BIT(14) << KCR_INIT_MASK_SHIFT))
>
> +#define KCR_STATUS_1 _MMIO(0x320f4)
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR type0 session in play 0-31 */
> +#define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31 */
> +#define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play 32-63 */
> +
> +enum pxp_session_types {
> + SESSION_TYPE_TYPE0 = 0,
> + SESSION_TYPE_TYPE1 = 1,
Difference between the two is not explained.
> + SESSION_TYPE_MAX
> +};
> +
> +enum pxp_protection_modes {
> + PROTECTION_MODE_NONE = 0,
> + PROTECTION_MODE_LM = 2,
> + PROTECTION_MODE_HM = 3,
> + PROTECTION_MODE_SM = 6,
Difference between each should be explained, if we're only having a
singleton session, why would we need such enumeration?
> + PROTECTION_MODE_ALL
> +};
These protection modes are not used at all, so they should not be
introduced.
> +
> +/**
> + * struct pxp_protected_session - linked list to track all active sessions.
> + */
> +struct pxp_protected_session {
> + /** @session_list: linked list infrastructure, do not change its order. */
> + struct list_head session_list;
We only need to track single session, so no list is needed. "session_" is
tautology as this is part of struct with "session" in it.
> + /** @session_index: Numeric identifier for this protected session */
> + int session_index;
"session_" is tautology in all other names too.
> + /** @context_id: context identifier of the protected session requestor */
> + int context_id;
> + /** @pid: pid of this session's creator */
> + int pid;
> + /** @drmfile: pointer to drm_file, which is allocated on device file open() call */
> + struct drm_file *drmfile;
These memebers are never needed for singleton session.
Each member should only be added by a patch that also makes full use of
it.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (4 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 05/16] drm/i915/pxp: Read register to check hardware session state Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 1:45 ` kernel test robot
2020-12-07 11:52 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
` (12 subsequent siblings)
18 siblings, 2 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Implement the functions to get/set the PXP tag, which is 32-bit
bitwise value containing the hardware session info, such as its
session id, protection mode or whether it's enabled.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 125 ++++++++++++++++++------
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 18 ++++
2 files changed, 112 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 6413f401d939..38c8b6d08b61 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,16 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
return 0;
}
+static u8 pxp_get_session_id(int session_index, int session_type)
+{
+ u8 session_id = session_index & SESSION_ID_MASK;
+
+ if (session_type == SESSION_TYPE_TYPE1)
+ session_id |= SESSION_TYPE_MASK;
+
+ return session_id;
+}
+
/**
* is_sw_session_active - Check if the given sw session id is active.
* @i915: i915 device handle.
@@ -78,6 +88,90 @@ static bool is_sw_session_active(struct drm_i915_private *i915, int session_type
return false;
}
+static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
+ int session_idx, int protection_mode)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx < MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx < MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(&i915->drm, "Failed to %s, bad params session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ switch (protection_mode) {
+ case PROTECTION_MODE_NONE:
+ {
+ pxp_tag->enable = false;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ break;
+ }
+ case PROTECTION_MODE_LM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = false;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_HM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = false;
+ pxp_tag->instance_id++;
+ break;
+ }
+ case PROTECTION_MODE_SM:
+ {
+ pxp_tag->enable = true;
+ pxp_tag->hm = true;
+ pxp_tag->sm = true;
+ pxp_tag->instance_id++;
+ break;
+ }
+ default:
+ drm_err(&i915->drm, "Failed to %s, bad params protection_mode=[%d]\n",
+ __func__, protection_mode);
+ return -EINVAL;
+ }
+
+ pxp_tag->session_id = pxp_get_session_id(session_idx, session_type);
+ return 0;
+}
+
+u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
+ int session_type, u32 *session_is_alive)
+{
+ struct pxp_tag *pxp_tag;
+
+ if (!i915 || session_type >= SESSION_TYPE_MAX)
+ return -EINVAL;
+
+ if (session_type == SESSION_TYPE_TYPE0 && session_idx < MAX_TYPE0_SESSIONS) {
+ pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type0_session_pxp_tag[session_idx];
+ } else if (session_type == SESSION_TYPE_TYPE1 && session_idx < MAX_TYPE1_SESSIONS) {
+ pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type1_session_pxp_tag[session_idx];
+ } else {
+ drm_err(&i915->drm, "Failed to %s, bad params session_type=[%d], session_idx=[%d]\n",
+ __func__, session_type, session_idx);
+ return -EINVAL;
+ }
+
+ if (session_is_alive)
+ *session_is_alive = pxp_tag->enable;
+
+ return pxp_tag->value;
+}
+
static bool is_hw_type0_session_in_play(struct drm_i915_private *i915, int session_index)
{
u32 regval_sip = 0;
@@ -172,37 +266,6 @@ static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, in
return ret;
}
-/**
- * check_if_protected_type0_sessions_are_attacked - To check if type0 active sessions are attacked.
- * @i915: i915 device handle.
- *
- * Return: true if HW shows protected sessions are attacked, false otherwise.
- */
-static bool check_if_protected_type0_sessions_are_attacked(struct drm_i915_private *i915)
-{
- i915_reg_t kcr_status_reg = KCR_STATUS_1;
- u32 reg_value = 0;
- u32 mask = 0x80000000;
- int ret;
-
- if (!i915)
- return false;
-
- if (i915->pxp.ctx->global_state_attacked)
- return true;
-
- ret = pxp_sm_reg_read(i915, kcr_status_reg.reg, ®_value);
- if (ret) {
- drm_err(&i915->drm, "Failed to pxp_sm_reg_read\n");
- goto end;
- }
-
- if (reg_value & mask)
- return true;
-end:
- return false;
-}
-
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 222a879be96d..b5012948f971 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -20,6 +20,9 @@
#define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31 */
#define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play 32-63 */
+#define SESSION_TYPE_MASK BIT(7)
+#define SESSION_ID_MASK (BIT(7) - 1)
+
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
@@ -36,6 +39,21 @@ enum pxp_protection_modes {
PROTECTION_MODE_ALL
};
+struct pxp_tag {
+ union {
+ u32 value;
+ struct {
+ u32 session_id : 8;
+ u32 instance_id : 8;
+ u32 enable : 1;
+ u32 hm : 1;
+ u32 reserved_1 : 1;
+ u32 sm : 1;
+ u32 reserved_2 : 12;
+ };
+ };
+};
+
/**
* struct pxp_protected_session - linked list to track all active sessions.
*/
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
@ 2020-12-07 1:45 ` kernel test robot
2020-12-07 11:52 ` Joonas Lahtinen
1 sibling, 0 replies; 41+ messages in thread
From: kernel test robot @ 2020-12-07 1:45 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3309 bytes --]
Hi Sean,
[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on next-20201204]
[also build test WARNING on v5.10-rc7]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.10-rc6 v5.10-rc5 v5.10-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Huang-Sean-Z/Introduce-Intel-PXP-component-Mesa-single-session/20201207-082410
base: 2996bd3f6ca9ea529b40c369a94b247657abdb4d
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/854165091719fb6cb1176f2a5e52cee22e2a3ffb
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Huang-Sean-Z/Introduce-Intel-PXP-component-Mesa-single-session/20201207-082410
git checkout 854165091719fb6cb1176f2a5e52cee22e2a3ffb
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:151:5: warning: no previous prototype for 'intel_pxp_get_pxp_tag' [-Wmissing-prototypes]
151 | u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
| ^~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:245:12: warning: 'sync_hw_sw_state' defined but not used [-Wunused-function]
245 | static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, int session_type)
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c:91:12: warning: 'pxp_set_pxp_tag' defined but not used [-Wunused-function]
91 | static int pxp_set_pxp_tag(struct drm_i915_private *i915, int session_type,
| ^~~~~~~~~~~~~~~
vim +/intel_pxp_get_pxp_tag +151 drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
150
> 151 u32 intel_pxp_get_pxp_tag(struct drm_i915_private *i915, int session_idx,
152 int session_type, u32 *session_is_alive)
153 {
154 struct pxp_tag *pxp_tag;
155
156 if (!i915 || session_type >= SESSION_TYPE_MAX)
157 return -EINVAL;
158
159 if (session_type == SESSION_TYPE_TYPE0 && session_idx < MAX_TYPE0_SESSIONS) {
160 pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type0_session_pxp_tag[session_idx];
161 } else if (session_type == SESSION_TYPE_TYPE1 && session_idx < MAX_TYPE1_SESSIONS) {
162 pxp_tag = (struct pxp_tag *)&i915->pxp.ctx->type1_session_pxp_tag[session_idx];
163 } else {
164 drm_err(&i915->drm, "Failed to %s, bad params session_type=[%d], session_idx=[%d]\n",
165 __func__, session_type, session_idx);
166 return -EINVAL;
167 }
168
169 if (session_is_alive)
170 *session_is_alive = pxp_tag->enable;
171
172 return pxp_tag->value;
173 }
174
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 77645 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
2020-12-07 1:45 ` kernel test robot
@ 2020-12-07 11:52 ` Joonas Lahtinen
2020-12-09 2:57 ` Huang, Sean Z
1 sibling, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 11:52 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:24)
> Implement the functions to get/set the PXP tag, which is 32-bit
> bitwise value containing the hardware session info, such as its
> session id, protection mode or whether it's enabled.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
By my understanding, this patch should not be needed at all for
singleton session? So I'm mostly skipping review here.
<SNIP>
> -/**
> - * check_if_protected_type0_sessions_are_attacked - To check if type0 active sessions are attacked.
> - * @i915: i915 device handle.
> - *
> - * Return: true if HW shows protected sessions are attacked, false otherwise.
> - */
> -static bool check_if_protected_type0_sessions_are_attacked(struct drm_i915_private *i915)
> -{
> - i915_reg_t kcr_status_reg = KCR_STATUS_1;
> - u32 reg_value = 0;
> - u32 mask = 0x80000000;
> - int ret;
> -
> - if (!i915)
> - return false;
> -
> - if (i915->pxp.ctx->global_state_attacked)
> - return true;
> -
> - ret = pxp_sm_reg_read(i915, kcr_status_reg.reg, ®_value);
> - if (ret) {
> - drm_err(&i915->drm, "Failed to pxp_sm_reg_read\n");
> - goto end;
> - }
> -
> - if (reg_value & mask)
> - return true;
> -end:
> - return false;
> -}
Removal of code added previously in the series?
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
> {
> int ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> index 222a879be96d..b5012948f971 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -20,6 +20,9 @@
> #define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31 */
> #define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play 32-63 */
>
> +#define SESSION_TYPE_MASK BIT(7)
> +#define SESSION_ID_MASK (BIT(7) - 1)
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -36,6 +39,21 @@ enum pxp_protection_modes {
> PROTECTION_MODE_ALL
> };
>
> +struct pxp_tag {
> + union {
> + u32 value;
> + struct {
> + u32 session_id : 8;
> + u32 instance_id : 8;
> + u32 enable : 1;
> + u32 hm : 1;
> + u32 reserved_1 : 1;
> + u32 sm : 1;
> + u32 reserved_2 : 12;
> + };
It is not obvious if this is a software-only field. If it's software
only, we should just make these into normal variables. If it's hardware
related, it should be documented as a bitfield, like other hardware
writes. We avoid using this construct in i915.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
2020-12-07 11:52 ` Joonas Lahtinen
@ 2020-12-09 2:57 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-09 2:57 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Hi Joonas,
Yes, I have removed this commit for single session patch series.
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 3:52 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag
Quoting Huang, Sean Z (2020-12-07 02:21:24)
> Implement the functions to get/set the PXP tag, which is 32-bit
> bitwise value containing the hardware session info, such as its
> session id, protection mode or whether it's enabled.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
By my understanding, this patch should not be needed at all for singleton session? So I'm mostly skipping review here.
<SNIP>
> -/**
> - * check_if_protected_type0_sessions_are_attacked - To check if type0 active sessions are attacked.
> - * @i915: i915 device handle.
> - *
> - * Return: true if HW shows protected sessions are attacked, false otherwise.
> - */
> -static bool check_if_protected_type0_sessions_are_attacked(struct
> drm_i915_private *i915) -{
> - i915_reg_t kcr_status_reg = KCR_STATUS_1;
> - u32 reg_value = 0;
> - u32 mask = 0x80000000;
> - int ret;
> -
> - if (!i915)
> - return false;
> -
> - if (i915->pxp.ctx->global_state_attacked)
> - return true;
> -
> - ret = pxp_sm_reg_read(i915, kcr_status_reg.reg, ®_value);
> - if (ret) {
> - drm_err(&i915->drm, "Failed to pxp_sm_reg_read\n");
> - goto end;
> - }
> -
> - if (reg_value & mask)
> - return true;
> -end:
> - return false;
> -}
Removal of code added previously in the series?
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915) {
> int ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> index 222a879be96d..b5012948f971 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -20,6 +20,9 @@
> #define GEN12_KCR_TSIP_LOW _MMIO(0x32264) /* KCR type1 session in play 0-31 */
> #define GEN12_KCR_TSIP_HIGH _MMIO(0x32268) /* KCR type1 session in play 32-63 */
>
> +#define SESSION_TYPE_MASK BIT(7)
> +#define SESSION_ID_MASK (BIT(7) - 1)
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -36,6 +39,21 @@ enum pxp_protection_modes {
> PROTECTION_MODE_ALL
> };
>
> +struct pxp_tag {
> + union {
> + u32 value;
> + struct {
> + u32 session_id : 8;
> + u32 instance_id : 8;
> + u32 enable : 1;
> + u32 hm : 1;
> + u32 reserved_1 : 1;
> + u32 sm : 1;
> + u32 reserved_2 : 12;
> + };
It is not obvious if this is a software-only field. If it's software only, we should just make these into normal variables. If it's hardware related, it should be documented as a bitfield, like other hardware writes. We avoid using this construct in i915.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (5 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 06/16] drm/i915/pxp: Implement funcs to get/set PXP tag Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 11:55 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
` (11 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Currently ring3 driver sends the TEE commands directly to TEE, but
later, as our design, we would like to make ring3 sending the TEE
commands via the ring0 PXP ioctl action instead of TEE ioctl, so
we can centralize those protection operations at ring0 PXP.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 5 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 127 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 +++
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++
8 files changed, 201 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 131bd8921565..3cc5fc250b33 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,7 +258,8 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
- pxp/intel_pxp_sm.o
+ pxp/intel_pxp_sm.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1e5ecaff571f..64399386292f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -322,6 +322,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 33a3f5c387b0..32e9cce925d1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1219,6 +1219,12 @@ struct drm_i915_private {
struct intel_pxp pxp;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index d74a32b29716..332d9baff29f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -7,6 +7,7 @@
#include "intel_pxp.h"
#include "intel_pxp_context.h"
#include "intel_pxp_sm.h"
+#include "intel_pxp_tee.h"
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
{
@@ -101,6 +102,8 @@ int intel_pxp_init(struct drm_i915_private *i915)
return ret;
}
+ intel_pxp_tee_component_init(i915);
+
INIT_WORK(&i915->pxp.irq_work, intel_pxp_irq_work);
i915->pxp.handled_irr = (PXP_IRQ_VECTOR_DISPLAY_PXP_STATE_TERMINATED |
@@ -115,6 +118,8 @@ void intel_pxp_uninit(struct drm_i915_private *i915)
if (!i915 || INTEL_GEN(i915) < 12)
return;
+ intel_pxp_tee_component_fini(i915);
+
intel_pxp_destroy_ctx(i915);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..fa617546bdd4
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "intel_pxp.h"
+#include "intel_pxp_context.h"
+#include "intel_pxp_tee.h"
+
+static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size)
+{
+ int ret;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+
+ if (!pxp_tee_master || !msg_in || !msg_out || !msg_out_size_ptr)
+ return -EINVAL;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE input message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_in, msg_in_size, true);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return -EFAULT;
+ }
+
+ ret = pxp_tee_master->ops->receive(pxp_tee_master->tee_dev, msg_out, msg_out_buf_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return -EFAULT;
+ }
+
+ if (ret > msg_out_buf_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -EFAULT;
+ }
+
+ *msg_out_size_ptr = ret;
+ ret = 0;
+
+ if (drm_debug_enabled(DRM_UT_DRIVER))
+ print_hex_dump(KERN_DEBUG, "TEE output message binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, msg_out, *msg_out_size_ptr, true);
+
+ return ret;
+}
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return -EPERM;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ if (!i915 || !tee_kdev || !data)
+ return;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+void intel_pxp_tee_component_init(struct drm_i915_private *i915)
+{
+ int ret;
+
+ if (!i915)
+ return;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed at component add(%d)\n", ret);
+ return;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+void intel_pxp_tee_component_fini(struct drm_i915_private *i915)
+{
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..0d0fbd0ed018
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "i915_drv.h"
+
+void intel_pxp_tee_component_init(struct drm_i915_private *i915);
+void intel_pxp_tee_component_fini(struct drm_i915_private *i915);
+
+#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..3999e255e145
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*receive)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2020-12-07 11:55 ` Joonas Lahtinen
2020-12-09 5:10 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 11:55 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:25)
> Currently ring3 driver sends the TEE commands directly to TEE, but
> later, as our design, we would like to make ring3 sending the TEE
> commands via the ring0 PXP ioctl action instead of TEE ioctl, so
> we can centralize those protection operations at ring0 PXP.
Kernel vs. userspace nomenclature to be used.
The description feels incorrect given no IOCTL will be exposed.
This is missing an explanation as to why it would be needed for
singleton session, so I think this patch should not be included in the
series.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel
2020-12-07 11:55 ` Joonas Lahtinen
@ 2020-12-09 5:10 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-09 5:10 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
Thanks, Yes for single session there is no ioctl exposed so I correct the commit description.
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 3:56 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel
Quoting Huang, Sean Z (2020-12-07 02:21:25)
> Currently ring3 driver sends the TEE commands directly to TEE, but
> later, as our design, we would like to make ring3 sending the TEE
> commands via the ring0 PXP ioctl action instead of TEE ioctl, so we
> can centralize those protection operations at ring0 PXP.
Kernel vs. userspace nomenclature to be used.
The description feels incorrect given no IOCTL will be exposed.
This is missing an explanation as to why it would be needed for singleton session, so I think this patch should not be included in the series.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (6 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 07/16] drm/i915/pxp: Implement funcs to create the TEE channel Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 12:00 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
` (10 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session needs to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 47 ++++++-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 165 +++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 8 ++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 11 ++
6 files changed, 271 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 332d9baff29f..10f4b1de07c4 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -9,6 +9,43 @@
#include "intel_pxp_sm.h"
#include "intel_pxp_tee.h"
+int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ struct pxp_tag pxptag;
+ int ret;
+
+ lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->flag_display_hm_surface_keys) {
+ drm_err(&i915->drm, "%s: arb session is alive so skipping the creation\n",
+ __func__);
+ return 0;
+ }
+
+ ret = intel_pxp_sm_reserve_arb_session(i915, &pxptag.value);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to reserve session\n");
+ goto end;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(i915);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send tee cmd for arb session creation\n");
+ goto end;
+ }
+
+ ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE, pxptag.session_id);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to mark session status in play\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = true;
+
+end:
+ return ret;
+}
+
static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
{
/* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
@@ -47,9 +84,17 @@ static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private
mutex_lock(&i915->pxp.ctx->ctx_mutex);
- if (i915->pxp.ctx->global_state_attacked)
+ if (i915->pxp.ctx->global_state_attacked) {
i915->pxp.ctx->global_state_attacked = false;
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(i915);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session\n");
+ goto end;
+ }
+ }
+end:
mutex_unlock(&i915->pxp.ctx->ctx_mutex);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 308d8d312a6d..e5f6e2b1bdfd 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -41,6 +41,8 @@ struct intel_gt;
struct drm_i915_private;
#ifdef CONFIG_DRM_I915_PXP
+int intel_pxp_create_arb_session(struct drm_i915_private *i915);
+
void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
@@ -48,6 +50,11 @@ int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
#else
+static inline int intel_pxp_create_arb_session(struct drm_i915_private *i915)
+{
+ return 0;
+};
+
static inline void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
{
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 38c8b6d08b61..056f65fbaf4e 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -41,6 +41,18 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
return 0;
}
+static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
+ int *session_index_out, int *session_type_out)
+{
+ if (!session_index_out || !session_type_out)
+ return -EINVAL;
+
+ *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1 : SESSION_TYPE_TYPE0;
+ *session_index_out = pxp_tag & SESSION_ID_MASK;
+
+ return 0;
+}
+
static u8 pxp_get_session_id(int session_index, int session_type)
{
u8 session_id = session_index & SESSION_ID_MASK;
@@ -266,6 +278,159 @@ static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, in
return ret;
}
+/**
+ * create_new_session_entry - Create a new session entry with provided info.
+ * @i915: i915 device handle.
+ * @drmfile: pointer to drm_file
+ * @context_id: Numeric identifier of the context created by the caller.
+ * @session_type: Type of the session requested. One of enum pxp_session_types.
+ * @protection_mode: Type of protection requested for the session.
+ * One of the enum pxp_protection_modes.
+ * @session_index: Numeric session identifier.
+ *
+ * Return: status. 0 means creation is successful.
+ */
+static int create_new_session_entry(struct drm_i915_private *i915, struct drm_file *drmfile,
+ int context_id, int session_type, int protection_mode,
+ int session_index)
+{
+ struct pxp_protected_session *new_session = NULL;
+ int pid = 0;
+
+ if (drmfile)
+ pid = pid_nr(drmfile->pid);
+
+ new_session = kzalloc(sizeof(*new_session), GFP_KERNEL);
+ if (!new_session)
+ return -ENOMEM;
+
+ new_session->context_id = context_id;
+ new_session->session_type = session_type;
+ new_session->protection_mode = protection_mode;
+ new_session->session_index = session_index;
+ new_session->session_is_in_play = false;
+ new_session->drmfile = drmfile;
+ new_session->pid = pid;
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ /* check to make sure the session id is within allowed range */
+ if (session_index < 0 || session_index >= MAX_TYPE0_SESSIONS) {
+ /* session id out of range.. free the new entry and return error */
+ kfree(new_session);
+ drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type0_sessions);
+ break;
+
+ case SESSION_TYPE_TYPE1:
+ /* check to make sure the session id is within allowed range */
+ if (session_index < 0 || session_index >= MAX_TYPE1_SESSIONS) {
+ /* session id out of range.. free the new entry and return error */
+ kfree(new_session);
+ drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type1_sessions);
+ break;
+
+ default:
+ /* session type is invalid... free new entry and return error. */
+ kfree(new_session);
+ drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag)
+{
+ int ret;
+
+ lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
+
+ if (!pxp_tag || !i915)
+ return -EINVAL;
+
+ ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
+ if (unlikely(ret))
+ goto end;
+
+ ret = create_new_session_entry(i915, NULL, 0, ARB_SESSION_TYPE,
+ ARB_PROTECTION_MODE, ARB_SESSION_INDEX);
+ if (unlikely(ret))
+ goto end;
+
+ ret = pxp_set_pxp_tag(i915, ARB_SESSION_TYPE, ARB_SESSION_INDEX, ARB_PROTECTION_MODE);
+
+end:
+ if (ret == 0)
+ *pxp_tag = intel_pxp_get_pxp_tag(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE, NULL);
+
+ return ret;
+}
+
+/**
+ * pxp_sm_mark_protected_session_in_play - To put an reserved protected session to "in_play" state
+ * @i915: i915 device handle.
+ * @session_type: Type of the session to be updated. One of enum pxp_session_types.
+ * @session_id: Session id identifier of the protected session.
+ *
+ * Return: status. 0 means update is successful.
+ */
+int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
+ u32 session_id)
+{
+ int ret;
+ int session_index;
+ int session_type_in_id;
+ struct pxp_protected_session *current_session;
+
+ ret = pxp_get_session_index(i915, session_id, &session_index, &session_type_in_id);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to pxp_get_session_index\n");
+ return ret;
+ }
+
+ if (session_type != session_type_in_id) {
+ drm_err(&i915->drm, "Failed to session_type and session_type_in_id don't match\n");
+ return -EINVAL;
+ }
+
+ lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
+
+ switch (session_type) {
+ case SESSION_TYPE_TYPE0:
+ list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type0_sessions,
+ session_list) {
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ return 0;
+ }
+ }
+ break;
+ case SESSION_TYPE_TYPE1:
+ list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type1_sessions,
+ session_list) {
+ if (current_session->session_index == session_index) {
+ current_session->session_is_in_play = true;
+ return 0;
+ }
+ }
+ break;
+ default:
+ /* invalid session type */
+ return -EINVAL;
+ }
+
+ drm_err(&i915->drm, "Failed to %s couldn't find active session\n", __func__);
+ return -EINVAL;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index b5012948f971..6eb5efd083a9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -23,6 +23,11 @@
#define SESSION_TYPE_MASK BIT(7)
#define SESSION_ID_MASK (BIT(7) - 1)
+/* Arbitrary session */
+#define ARB_SESSION_INDEX 0xf
+#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
+#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
+
enum pxp_session_types {
SESSION_TYPE_TYPE0 = 0,
SESSION_TYPE_TYPE1 = 1,
@@ -84,6 +89,9 @@ struct pxp_protected_session {
bool session_is_in_play;
};
+int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag);
+int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
+ u32 session_id);
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
#endif /* __INTEL_PXP_SM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index fa617546bdd4..b2dff433073c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -67,6 +67,7 @@ static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
if (!i915 || !tee_kdev || !data)
@@ -77,6 +78,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ ret = intel_pxp_create_arb_session(i915);
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -125,3 +136,26 @@ void intel_pxp_tee_component_fini(struct drm_i915_private *i915)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private *i915)
+{
+ int ret;
+ u32 msg_out_size_received = 0;
+ u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN;
+ u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0};
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(i915,
+ &msg_in,
+ sizeof(msg_in),
+ &msg_out, &msg_out_size_received,
+ sizeof(msg_out));
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send/receive tee message\n");
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 0d0fbd0ed018..6cc9517701ea 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,15 @@
void intel_pxp_tee_component_init(struct drm_i915_private *i915);
void intel_pxp_tee_component_fini(struct drm_i915_private *i915);
+int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
+ void __user *msg_in_user_ptr, u32 msg_in_size,
+ void __user *msg_out_user_ptr, u32 *msg_out_size_ptr,
+ u32 msg_out_buf_size);
+
+int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private *i915);
+
+/* TEE command to create the arbitrary session */
+#define PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008, 0x00000002, 0x0000000f}
+#define PXP_TEE_ARB_CMD_DW_LEN (6)
+
#endif /* __INTEL_PXP_TEE_H__ */
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2020-12-07 12:00 ` Joonas Lahtinen
2020-12-09 5:11 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 12:00 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:26)
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session needs to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Creating the arbitary (default) session only utilizes a minimal amount
of the session management related code introduced by this and previous
patches.
All of that dead code needs to be eliminated first, then we need to look
at what level of complexity can be eliminated from the patches.
If you can address the review comments from the earlier patch and
re-order the series according to the given guidance, that'll make the
review much more efficient going forward when the code is only added
when it used
Regards, Joonas
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 47 ++++++-
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 165 +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 11 ++
> 6 files changed, 271 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 332d9baff29f..10f4b1de07c4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -9,6 +9,43 @@
> #include "intel_pxp_sm.h"
> #include "intel_pxp_tee.h"
>
> +int intel_pxp_create_arb_session(struct drm_i915_private *i915)
> +{
> + struct pxp_tag pxptag;
> + int ret;
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + if (i915->pxp.ctx->flag_display_hm_surface_keys) {
> + drm_err(&i915->drm, "%s: arb session is alive so skipping the creation\n",
> + __func__);
> + return 0;
> + }
> +
> + ret = intel_pxp_sm_reserve_arb_session(i915, &pxptag.value);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to reserve session\n");
> + goto end;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(i915);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send tee cmd for arb session creation\n");
> + goto end;
> + }
> +
> + ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE, pxptag.session_id);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to mark session status in play\n");
> + goto end;
> + }
> +
> + i915->pxp.ctx->flag_display_hm_surface_keys = true;
> +
> +end:
> + return ret;
> +}
> +
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private *i915, u32 mask)
> {
> /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */
> @@ -47,9 +84,17 @@ static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private
>
> mutex_lock(&i915->pxp.ctx->ctx_mutex);
>
> - if (i915->pxp.ctx->global_state_attacked)
> + if (i915->pxp.ctx->global_state_attacked) {
> i915->pxp.ctx->global_state_attacked = false;
>
> + /* Re-create the arb session after teardown handle complete */
> + ret = intel_pxp_create_arb_session(i915);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session\n");
> + goto end;
> + }
> + }
> +end:
> mutex_unlock(&i915->pxp.ctx->ctx_mutex);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 308d8d312a6d..e5f6e2b1bdfd 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -41,6 +41,8 @@ struct intel_gt;
> struct drm_i915_private;
>
> #ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_create_arb_session(struct drm_i915_private *i915);
> +
> void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir);
> int i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
> int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
> @@ -48,6 +50,11 @@ int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
> int intel_pxp_init(struct drm_i915_private *i915);
> void intel_pxp_uninit(struct drm_i915_private *i915);
> #else
> +static inline int intel_pxp_create_arb_session(struct drm_i915_private *i915)
> +{
> + return 0;
> +};
> +
> static inline void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
> {
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> index 38c8b6d08b61..056f65fbaf4e 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -41,6 +41,18 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
> return 0;
> }
>
> +static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
> + int *session_index_out, int *session_type_out)
> +{
> + if (!session_index_out || !session_type_out)
> + return -EINVAL;
> +
> + *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1 : SESSION_TYPE_TYPE0;
> + *session_index_out = pxp_tag & SESSION_ID_MASK;
> +
> + return 0;
> +}
> +
> static u8 pxp_get_session_id(int session_index, int session_type)
> {
> u8 session_id = session_index & SESSION_ID_MASK;
> @@ -266,6 +278,159 @@ static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, in
> return ret;
> }
>
> +/**
> + * create_new_session_entry - Create a new session entry with provided info.
> + * @i915: i915 device handle.
> + * @drmfile: pointer to drm_file
> + * @context_id: Numeric identifier of the context created by the caller.
> + * @session_type: Type of the session requested. One of enum pxp_session_types.
> + * @protection_mode: Type of protection requested for the session.
> + * One of the enum pxp_protection_modes.
> + * @session_index: Numeric session identifier.
> + *
> + * Return: status. 0 means creation is successful.
> + */
> +static int create_new_session_entry(struct drm_i915_private *i915, struct drm_file *drmfile,
> + int context_id, int session_type, int protection_mode,
> + int session_index)
> +{
> + struct pxp_protected_session *new_session = NULL;
> + int pid = 0;
> +
> + if (drmfile)
> + pid = pid_nr(drmfile->pid);
> +
> + new_session = kzalloc(sizeof(*new_session), GFP_KERNEL);
> + if (!new_session)
> + return -ENOMEM;
> +
> + new_session->context_id = context_id;
> + new_session->session_type = session_type;
> + new_session->protection_mode = protection_mode;
> + new_session->session_index = session_index;
> + new_session->session_is_in_play = false;
> + new_session->drmfile = drmfile;
> + new_session->pid = pid;
> +
> + switch (session_type) {
> + case SESSION_TYPE_TYPE0:
> + /* check to make sure the session id is within allowed range */
> + if (session_index < 0 || session_index >= MAX_TYPE0_SESSIONS) {
> + /* session id out of range.. free the new entry and return error */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type0_sessions);
> + break;
> +
> + case SESSION_TYPE_TYPE1:
> + /* check to make sure the session id is within allowed range */
> + if (session_index < 0 || session_index >= MAX_TYPE1_SESSIONS) {
> + /* session id out of range.. free the new entry and return error */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type1_sessions);
> + break;
> +
> + default:
> + /* session type is invalid... free new entry and return error. */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag)
> +{
> + int ret;
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + if (!pxp_tag || !i915)
> + return -EINVAL;
> +
> + ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
> + if (unlikely(ret))
> + goto end;
> +
> + ret = create_new_session_entry(i915, NULL, 0, ARB_SESSION_TYPE,
> + ARB_PROTECTION_MODE, ARB_SESSION_INDEX);
> + if (unlikely(ret))
> + goto end;
> +
> + ret = pxp_set_pxp_tag(i915, ARB_SESSION_TYPE, ARB_SESSION_INDEX, ARB_PROTECTION_MODE);
> +
> +end:
> + if (ret == 0)
> + *pxp_tag = intel_pxp_get_pxp_tag(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE, NULL);
> +
> + return ret;
> +}
> +
> +/**
> + * pxp_sm_mark_protected_session_in_play - To put an reserved protected session to "in_play" state
> + * @i915: i915 device handle.
> + * @session_type: Type of the session to be updated. One of enum pxp_session_types.
> + * @session_id: Session id identifier of the protected session.
> + *
> + * Return: status. 0 means update is successful.
> + */
> +int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
> + u32 session_id)
> +{
> + int ret;
> + int session_index;
> + int session_type_in_id;
> + struct pxp_protected_session *current_session;
> +
> + ret = pxp_get_session_index(i915, session_id, &session_index, &session_type_in_id);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to pxp_get_session_index\n");
> + return ret;
> + }
> +
> + if (session_type != session_type_in_id) {
> + drm_err(&i915->drm, "Failed to session_type and session_type_in_id don't match\n");
> + return -EINVAL;
> + }
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + switch (session_type) {
> + case SESSION_TYPE_TYPE0:
> + list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type0_sessions,
> + session_list) {
> + if (current_session->session_index == session_index) {
> + current_session->session_is_in_play = true;
> + return 0;
> + }
> + }
> + break;
> + case SESSION_TYPE_TYPE1:
> + list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type1_sessions,
> + session_list) {
> + if (current_session->session_index == session_index) {
> + current_session->session_is_in_play = true;
> + return 0;
> + }
> + }
> + break;
> + default:
> + /* invalid session type */
> + return -EINVAL;
> + }
> +
> + drm_err(&i915->drm, "Failed to %s couldn't find active session\n", __func__);
> + return -EINVAL;
> +}
> +
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
> {
> int ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> index b5012948f971..6eb5efd083a9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -23,6 +23,11 @@
> #define SESSION_TYPE_MASK BIT(7)
> #define SESSION_ID_MASK (BIT(7) - 1)
>
> +/* Arbitrary session */
> +#define ARB_SESSION_INDEX 0xf
> +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
> +#define ARB_PROTECTION_MODE PROTECTION_MODE_HM
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -84,6 +89,9 @@ struct pxp_protected_session {
> bool session_is_in_play;
> };
>
> +int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag);
> +int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
> + u32 session_id);
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
>
> #endif /* __INTEL_PXP_SM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index fa617546bdd4..b2dff433073c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -67,6 +67,7 @@ static int intel_pxp_tee_io_message(struct drm_i915_private *i915,
> static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> struct device *tee_kdev, void *data)
> {
> + int ret;
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
>
> if (!i915 || !tee_kdev || !data)
> @@ -77,6 +78,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> i915->pxp_tee_master->tee_dev = tee_kdev;
> mutex_unlock(&i915->pxp_tee_comp_mutex);
>
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> + /* Create arb session only if tee is ready, during system boot or sleep/resume */
> + ret = intel_pxp_create_arb_session(i915);
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
> +
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -125,3 +136,26 @@ void intel_pxp_tee_component_fini(struct drm_i915_private *i915)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
> }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private *i915)
> +{
> + int ret;
> + u32 msg_out_size_received = 0;
> + u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN;
> + u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0};
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> +
> + ret = intel_pxp_tee_io_message(i915,
> + &msg_in,
> + sizeof(msg_in),
> + &msg_out, &msg_out_size_received,
> + sizeof(msg_out));
> +
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + if (ret)
> + drm_err(&i915->drm, "Failed to send/receive tee message\n");
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> index 0d0fbd0ed018..6cc9517701ea 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,15 @@
> void intel_pxp_tee_component_init(struct drm_i915_private *i915);
> void intel_pxp_tee_component_fini(struct drm_i915_private *i915);
>
> +int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
> + void __user *msg_in_user_ptr, u32 msg_in_size,
> + void __user *msg_out_user_ptr, u32 *msg_out_size_ptr,
> + u32 msg_out_buf_size);
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private *i915);
> +
> +/* TEE command to create the arbitrary session */
> +#define PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008, 0x00000002, 0x0000000f}
> +#define PXP_TEE_ARB_CMD_DW_LEN (6)
> +
> #endif /* __INTEL_PXP_TEE_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot
2020-12-07 12:00 ` Joonas Lahtinen
@ 2020-12-09 5:11 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-09 5:11 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
I have removed the dead code that specific for multi-session, and will upload the new version soon.
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 4:01 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot
Quoting Huang, Sean Z (2020-12-07 02:21:26)
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session needs to be re-created after
> teardown or power event because hardware encryption key won't be valid
> after such cases.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Creating the arbitary (default) session only utilizes a minimal amount of the session management related code introduced by this and previous patches.
All of that dead code needs to be eliminated first, then we need to look at what level of complexity can be eliminated from the patches.
If you can address the review comments from the earlier patch and re-order the series according to the given guidance, that'll make the review much more efficient going forward when the code is only added when it used
Regards, Joonas
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 47 ++++++-
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 165 +++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 8 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 34 +++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 11 ++
> 6 files changed, 271 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 332d9baff29f..10f4b1de07c4 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -9,6 +9,43 @@
> #include "intel_pxp_sm.h"
> #include "intel_pxp_tee.h"
>
> +int intel_pxp_create_arb_session(struct drm_i915_private *i915) {
> + struct pxp_tag pxptag;
> + int ret;
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + if (i915->pxp.ctx->flag_display_hm_surface_keys) {
> + drm_err(&i915->drm, "%s: arb session is alive so skipping the creation\n",
> + __func__);
> + return 0;
> + }
> +
> + ret = intel_pxp_sm_reserve_arb_session(i915, &pxptag.value);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to reserve session\n");
> + goto end;
> + }
> +
> + ret = intel_pxp_tee_cmd_create_arb_session(i915);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to send tee cmd for arb session creation\n");
> + goto end;
> + }
> +
> + ret = pxp_sm_mark_protected_session_in_play(i915, ARB_SESSION_TYPE, pxptag.session_id);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to mark session status in play\n");
> + goto end;
> + }
> +
> + i915->pxp.ctx->flag_display_hm_surface_keys = true;
> +
> +end:
> + return ret;
> +}
> +
> static void intel_pxp_write_irq_mask_reg(struct drm_i915_private
> *i915, u32 mask) {
> /* crypto mask is in bit31-16 (Engine1 Interrupt Mask) */ @@
> -47,9 +84,17 @@ static int
> intel_pxp_global_terminate_complete_callback(struct drm_i915_private
>
> mutex_lock(&i915->pxp.ctx->ctx_mutex);
>
> - if (i915->pxp.ctx->global_state_attacked)
> + if (i915->pxp.ctx->global_state_attacked) {
> i915->pxp.ctx->global_state_attacked = false;
>
> + /* Re-create the arb session after teardown handle complete */
> + ret = intel_pxp_create_arb_session(i915);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session\n");
> + goto end;
> + }
> + }
> +end:
> mutex_unlock(&i915->pxp.ctx->ctx_mutex);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index 308d8d312a6d..e5f6e2b1bdfd 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -41,6 +41,8 @@ struct intel_gt;
> struct drm_i915_private;
>
> #ifdef CONFIG_DRM_I915_PXP
> +int intel_pxp_create_arb_session(struct drm_i915_private *i915);
> +
> void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir); int
> i915_pxp_teardown_required_callback(struct drm_i915_private *i915);
> int i915_pxp_global_terminate_complete_callback(struct
> drm_i915_private *i915); @@ -48,6 +50,11 @@ int
> i915_pxp_global_terminate_complete_callback(struct drm_i915_private
> *i915); int intel_pxp_init(struct drm_i915_private *i915); void
> intel_pxp_uninit(struct drm_i915_private *i915); #else
> +static inline int intel_pxp_create_arb_session(struct
> +drm_i915_private *i915) {
> + return 0;
> +};
> +
> static inline void intel_pxp_irq_handler(struct intel_gt *gt, u16
> iir) { } diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> index 38c8b6d08b61..056f65fbaf4e 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -41,6 +41,18 @@ static int pxp_reg_write(struct drm_i915_private *i915, u32 offset, u32 regval)
> return 0;
> }
>
> +static int pxp_get_session_index(struct drm_i915_private *i915, u32 pxp_tag,
> + int *session_index_out, int
> +*session_type_out) {
> + if (!session_index_out || !session_type_out)
> + return -EINVAL;
> +
> + *session_type_out = (pxp_tag & SESSION_TYPE_MASK) ? SESSION_TYPE_TYPE1 : SESSION_TYPE_TYPE0;
> + *session_index_out = pxp_tag & SESSION_ID_MASK;
> +
> + return 0;
> +}
> +
> static u8 pxp_get_session_id(int session_index, int session_type) {
> u8 session_id = session_index & SESSION_ID_MASK; @@ -266,6
> +278,159 @@ static int sync_hw_sw_state(struct drm_i915_private *i915, int session_index, in
> return ret;
> }
>
> +/**
> + * create_new_session_entry - Create a new session entry with provided info.
> + * @i915: i915 device handle.
> + * @drmfile: pointer to drm_file
> + * @context_id: Numeric identifier of the context created by the caller.
> + * @session_type: Type of the session requested. One of enum pxp_session_types.
> + * @protection_mode: Type of protection requested for the session.
> + * One of the enum pxp_protection_modes.
> + * @session_index: Numeric session identifier.
> + *
> + * Return: status. 0 means creation is successful.
> + */
> +static int create_new_session_entry(struct drm_i915_private *i915, struct drm_file *drmfile,
> + int context_id, int session_type, int protection_mode,
> + int session_index) {
> + struct pxp_protected_session *new_session = NULL;
> + int pid = 0;
> +
> + if (drmfile)
> + pid = pid_nr(drmfile->pid);
> +
> + new_session = kzalloc(sizeof(*new_session), GFP_KERNEL);
> + if (!new_session)
> + return -ENOMEM;
> +
> + new_session->context_id = context_id;
> + new_session->session_type = session_type;
> + new_session->protection_mode = protection_mode;
> + new_session->session_index = session_index;
> + new_session->session_is_in_play = false;
> + new_session->drmfile = drmfile;
> + new_session->pid = pid;
> +
> + switch (session_type) {
> + case SESSION_TYPE_TYPE0:
> + /* check to make sure the session id is within allowed range */
> + if (session_index < 0 || session_index >= MAX_TYPE0_SESSIONS) {
> + /* session id out of range.. free the new entry and return error */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type0_sessions);
> + break;
> +
> + case SESSION_TYPE_TYPE1:
> + /* check to make sure the session id is within allowed range */
> + if (session_index < 0 || session_index >= MAX_TYPE1_SESSIONS) {
> + /* session id out of range.. free the new entry and return error */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + list_add(&new_session->session_list, &i915->pxp.ctx->active_pxp_type1_sessions);
> + break;
> +
> + default:
> + /* session type is invalid... free new entry and return error. */
> + kfree(new_session);
> + drm_err(&i915->drm, "Failed to %s, bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915,
> +u32 *pxp_tag) {
> + int ret;
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + if (!pxp_tag || !i915)
> + return -EINVAL;
> +
> + ret = sync_hw_sw_state(i915, ARB_SESSION_INDEX, ARB_SESSION_TYPE);
> + if (unlikely(ret))
> + goto end;
> +
> + ret = create_new_session_entry(i915, NULL, 0, ARB_SESSION_TYPE,
> + ARB_PROTECTION_MODE, ARB_SESSION_INDEX);
> + if (unlikely(ret))
> + goto end;
> +
> + ret = pxp_set_pxp_tag(i915, ARB_SESSION_TYPE,
> + ARB_SESSION_INDEX, ARB_PROTECTION_MODE);
> +
> +end:
> + if (ret == 0)
> + *pxp_tag = intel_pxp_get_pxp_tag(i915,
> +ARB_SESSION_INDEX, ARB_SESSION_TYPE, NULL);
> +
> + return ret;
> +}
> +
> +/**
> + * pxp_sm_mark_protected_session_in_play - To put an reserved
> +protected session to "in_play" state
> + * @i915: i915 device handle.
> + * @session_type: Type of the session to be updated. One of enum pxp_session_types.
> + * @session_id: Session id identifier of the protected session.
> + *
> + * Return: status. 0 means update is successful.
> + */
> +int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
> + u32 session_id) {
> + int ret;
> + int session_index;
> + int session_type_in_id;
> + struct pxp_protected_session *current_session;
> +
> + ret = pxp_get_session_index(i915, session_id, &session_index, &session_type_in_id);
> + if (ret) {
> + drm_err(&i915->drm, "Failed to pxp_get_session_index\n");
> + return ret;
> + }
> +
> + if (session_type != session_type_in_id) {
> + drm_err(&i915->drm, "Failed to session_type and session_type_in_id don't match\n");
> + return -EINVAL;
> + }
> +
> + lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
> +
> + switch (session_type) {
> + case SESSION_TYPE_TYPE0:
> + list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type0_sessions,
> + session_list) {
> + if (current_session->session_index == session_index) {
> + current_session->session_is_in_play = true;
> + return 0;
> + }
> + }
> + break;
> + case SESSION_TYPE_TYPE1:
> + list_for_each_entry(current_session, &i915->pxp.ctx->active_pxp_type1_sessions,
> + session_list) {
> + if (current_session->session_index == session_index) {
> + current_session->session_is_in_play = true;
> + return 0;
> + }
> + }
> + break;
> + default:
> + /* invalid session type */
> + return -EINVAL;
> + }
> +
> + drm_err(&i915->drm, "Failed to %s couldn't find active session\n", __func__);
> + return -EINVAL;
> +}
> +
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915) {
> int ret;
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> index b5012948f971..6eb5efd083a9 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
> @@ -23,6 +23,11 @@
> #define SESSION_TYPE_MASK BIT(7)
> #define SESSION_ID_MASK (BIT(7) - 1)
>
> +/* Arbitrary session */
> +#define ARB_SESSION_INDEX 0xf
> +#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0 #define
> +ARB_PROTECTION_MODE PROTECTION_MODE_HM
> +
> enum pxp_session_types {
> SESSION_TYPE_TYPE0 = 0,
> SESSION_TYPE_TYPE1 = 1,
> @@ -84,6 +89,9 @@ struct pxp_protected_session {
> bool session_is_in_play;
> };
>
> +int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915,
> +u32 *pxp_tag); int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
> + u32 session_id);
> int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
>
> #endif /* __INTEL_PXP_SM_H__ */
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index fa617546bdd4..b2dff433073c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -67,6 +67,7 @@ static int intel_pxp_tee_io_message(struct
> drm_i915_private *i915, static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> struct device *tee_kdev, void
> *data) {
> + int ret;
> struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
>
> if (!i915 || !tee_kdev || !data) @@ -77,6 +78,16 @@ static int
> i915_pxp_tee_component_bind(struct device *i915_kdev,
> i915->pxp_tee_master->tee_dev = tee_kdev;
> mutex_unlock(&i915->pxp_tee_comp_mutex);
>
> + mutex_lock(&i915->pxp.ctx->ctx_mutex);
> + /* Create arb session only if tee is ready, during system boot or sleep/resume */
> + ret = intel_pxp_create_arb_session(i915);
> + mutex_unlock(&i915->pxp.ctx->ctx_mutex);
> +
> + if (ret) {
> + drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
> + return ret;
> + }
> +
> return 0;
> }
>
> @@ -125,3 +136,26 @@ void intel_pxp_tee_component_fini(struct
> drm_i915_private *i915)
>
> component_del(i915->drm.dev, &i915_pxp_tee_component_ops); }
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private
> +*i915) {
> + int ret;
> + u32 msg_out_size_received = 0;
> + u32 msg_in[PXP_TEE_ARB_CMD_DW_LEN] = PXP_TEE_ARB_CMD_BIN;
> + u32 msg_out[PXP_TEE_ARB_CMD_DW_LEN] = {0};
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> +
> + ret = intel_pxp_tee_io_message(i915,
> + &msg_in,
> + sizeof(msg_in),
> + &msg_out, &msg_out_size_received,
> + sizeof(msg_out));
> +
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + if (ret)
> + drm_err(&i915->drm, "Failed to send/receive tee
> + message\n");
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> index 0d0fbd0ed018..6cc9517701ea 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> @@ -11,4 +11,15 @@
> void intel_pxp_tee_component_init(struct drm_i915_private *i915);
> void intel_pxp_tee_component_fini(struct drm_i915_private *i915);
>
> +int pxp_tee_ioctl_io_message(struct drm_i915_private *i915,
> + void __user *msg_in_user_ptr, u32 msg_in_size,
> + void __user *msg_out_user_ptr, u32 *msg_out_size_ptr,
> + u32 msg_out_buf_size);
> +
> +int intel_pxp_tee_cmd_create_arb_session(struct drm_i915_private
> +*i915);
> +
> +/* TEE command to create the arbitrary session */ #define
> +PXP_TEE_ARB_CMD_BIN {0x00040000, 0x0000001e, 0x00000000, 0x00000008,
> +0x00000002, 0x0000000f} #define PXP_TEE_ARB_CMD_DW_LEN (6)
> +
> #endif /* __INTEL_PXP_TEE_H__ */
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (7 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 08/16] drm/i915/pxp: Create the arbitrary session after boot Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 12:21 ` Joonas Lahtinen
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
` (9 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 150 ++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index 056f65fbaf4e..c88243e02a3c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -3,13 +3,163 @@
* Copyright(c) 2020, Intel Corporation. All rights reserved.
*/
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
#include "gt/intel_context.h"
+#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_engine_pm.h"
#include "intel_pxp.h"
#include "intel_pxp_sm.h"
#include "intel_pxp_context.h"
+static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
+ struct intel_context *ce,
+ struct intel_gt_buffer_pool_node *pool,
+ u32 *cmd_buf, int cmd_size_in_dw)
+{
+ struct i915_vma *batch = ERR_PTR(-EINVAL);
+ u32 *cmd;
+
+ if (!ce || !ce->engine || !cmd_buf)
+ return ERR_PTR(-EINVAL);
+
+ if (cmd_size_in_dw * 4 > PAGE_SIZE) {
+ drm_err(&i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
+ __func__, cmd_size_in_dw);
+ return ERR_PTR(-EINVAL);
+ }
+
+ cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
+ if (IS_ERR(cmd)) {
+ drm_err(&i915->drm, "Failed to i915_gem_object_pin_map()\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ i915_gem_object_unpin_map(pool->obj);
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ drm_err(&i915->drm, "Failed to i915_vma_instance()\n");
+ return batch;
+ }
+
+ return batch;
+}
+
+static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int cmd_size_in_dw)
+{
+ int err = -EINVAL;
+ struct i915_vma *batch;
+ struct i915_request *rq;
+ struct intel_context *ce = NULL;
+ bool is_engine_pm_get = false;
+ bool is_batch_vma_pin = false;
+ bool is_skip_req_on_err = false;
+ bool is_engine_get_pool = false;
+ struct intel_gt_buffer_pool_node *pool = NULL;
+ struct intel_gt *gt = NULL;
+
+ if (!i915 || !HAS_ENGINE(&i915->gt, VCS0) ||
+ !i915->gt.engine[VCS0]->kernel_context) {
+ err = -EINVAL;
+ goto end;
+ }
+
+ if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
+ drm_err(&i915->drm, "Failed to %s bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ gt = &i915->gt;
+ ce = i915->gt.engine[VCS0]->kernel_context;
+
+ intel_engine_pm_get(ce->engine);
+ is_engine_pm_get = true;
+
+ pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
+ if (IS_ERR(pool)) {
+ drm_err(&i915->drm, "Failed to intel_engine_get_pool()\n");
+ goto end;
+ }
+ is_engine_get_pool = true;
+
+ batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
+ if (IS_ERR(batch)) {
+ drm_err(&i915->drm, "Failed to pxp_get_batch()\n");
+ goto end;
+ }
+
+ err = i915_vma_pin(batch, 0, 0, PIN_USER);
+ if (err) {
+ drm_err(&i915->drm, "Failed to i915_vma_pin()\n");
+ goto end;
+ }
+ is_batch_vma_pin = true;
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ drm_err(&i915->drm, "Failed to intel_context_create_request()\n");
+ goto end;
+ }
+ is_skip_req_on_err = true;
+
+ err = intel_gt_buffer_pool_mark_active(pool, rq);
+ if (err) {
+ drm_err(&i915->drm, "Failed to intel_engine_pool_mark_active()\n");
+ goto end;
+ }
+
+ i915_vma_lock(batch);
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ i915_vma_unlock(batch);
+ if (err) {
+ drm_err(&i915->drm, "Failed to i915_request_await_object()\n");
+ goto end;
+ }
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err) {
+ drm_err(&i915->drm, "Failed to emit_init_breadcrumb()\n");
+ goto end;
+ }
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err) {
+ drm_err(&i915->drm, "Failed to emit_bb_start()\n");
+ goto end;
+ }
+
+ i915_request_add(rq);
+
+end:
+ if (unlikely(err) && is_skip_req_on_err)
+ i915_request_set_error_once(rq, err);
+
+ if (is_batch_vma_pin)
+ i915_vma_unpin(batch);
+
+ if (is_engine_get_pool)
+ intel_gt_buffer_pool_put(pool);
+
+ if (is_engine_pm_get)
+ intel_engine_pm_put(ce->engine);
+
+ return err;
+}
+
static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
{
intel_wakeref_t wakeref;
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2020-12-07 12:21 ` Joonas Lahtinen
2020-12-09 5:16 ` Huang, Sean Z
0 siblings, 1 reply; 41+ messages in thread
From: Joonas Lahtinen @ 2020-12-07 12:21 UTC (permalink / raw)
To: Huang, Sean Z, Intel-gfx
Quoting Huang, Sean Z (2020-12-07 02:21:27)
> Implement the functions to allow PXP to send a GPU command, in
> order to terminate the hardware session, so hardware can recycle
> this session slot for the next usage.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
As we only have a singleton session support in this series, maybe this
patch is not needed?
I don't think we should add functions to arbitarily inject commands to VCS0
from another driver. We should add proper functions for the commands in i915
and call them on demand and add EXPORT_SYMBOL for them.
Regards, Joonas
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 150 ++++++++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> index 056f65fbaf4e..c88243e02a3c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -3,13 +3,163 @@
> * Copyright(c) 2020, Intel Corporation. All rights reserved.
> */
>
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_context.h"
> +#include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_engine_pm.h"
>
> #include "intel_pxp.h"
> #include "intel_pxp_sm.h"
> #include "intel_pxp_context.h"
>
> +static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int cmd_size_in_dw)
> +{
> + struct i915_vma *batch = ERR_PTR(-EINVAL);
> + u32 *cmd;
> +
> + if (!ce || !ce->engine || !cmd_buf)
> + return ERR_PTR(-EINVAL);
> +
> + if (cmd_size_in_dw * 4 > PAGE_SIZE) {
> + drm_err(&i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
> + __func__, cmd_size_in_dw);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
> + if (IS_ERR(cmd)) {
> + drm_err(&i915->drm, "Failed to i915_gem_object_pin_map()\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
> + }
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + drm_err(&i915->drm, "Failed to i915_vma_instance()\n");
> + return batch;
> + }
> +
> + return batch;
> +}
> +
> +static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd, int cmd_size_in_dw)
> +{
> + int err = -EINVAL;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + struct intel_context *ce = NULL;
> + bool is_engine_pm_get = false;
> + bool is_batch_vma_pin = false;
> + bool is_skip_req_on_err = false;
> + bool is_engine_get_pool = false;
> + struct intel_gt_buffer_pool_node *pool = NULL;
> + struct intel_gt *gt = NULL;
> +
> + if (!i915 || !HAS_ENGINE(&i915->gt, VCS0) ||
> + !i915->gt.engine[VCS0]->kernel_context) {
> + err = -EINVAL;
> + goto end;
> + }
> +
> + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
> + drm_err(&i915->drm, "Failed to %s bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + gt = &i915->gt;
> + ce = i915->gt.engine[VCS0]->kernel_context;
> +
> + intel_engine_pm_get(ce->engine);
> + is_engine_pm_get = true;
> +
> + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
> + if (IS_ERR(pool)) {
> + drm_err(&i915->drm, "Failed to intel_engine_get_pool()\n");
> + goto end;
> + }
> + is_engine_get_pool = true;
> +
> + batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
> + if (IS_ERR(batch)) {
> + drm_err(&i915->drm, "Failed to pxp_get_batch()\n");
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(&i915->drm, "Failed to i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(&i915->drm, "Failed to intel_context_create_request()\n");
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(&i915->drm, "Failed to intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(&i915->drm, "Failed to i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(&i915->drm, "Failed to emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(&i915->drm, "Failed to emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> +
> static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset, u32 *regval)
> {
> intel_wakeref_t wakeref;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination
2020-12-07 12:21 ` Joonas Lahtinen
@ 2020-12-09 5:16 ` Huang, Sean Z
0 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-09 5:16 UTC (permalink / raw)
To: Joonas Lahtinen, Intel-gfx
> As we only have a singleton session support in this series, maybe this patch is not needed?
We still need this patch even for single session. The reason is during the power event or teardown event hardware will lost all the encryption key.
During this flow we need to gracefully send out the GPU command to terminate the session and recreate the arb session again.
> I don't think we should add functions to arbitarily inject commands to VCS0 from another driver. We should add proper functions for the commands in i915 and call them on demand and add EXPORT_SYMBOL for them.
Please share some source code or example commit doing so if it's necessary. Thanks.
Best regards,
Sean
-----Original Message-----
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Sent: Monday, December 7, 2020 4:21 AM
To: Huang, Sean Z <sean.z.huang@intel.com>; Intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination
Quoting Huang, Sean Z (2020-12-07 02:21:27)
> Implement the functions to allow PXP to send a GPU command, in order
> to terminate the hardware session, so hardware can recycle this
> session slot for the next usage.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
As we only have a singleton session support in this series, maybe this patch is not needed?
I don't think we should add functions to arbitarily inject commands to VCS0 from another driver. We should add proper functions for the commands in i915 and call them on demand and add EXPORT_SYMBOL for them.
Regards, Joonas
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 150
> ++++++++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> index 056f65fbaf4e..c88243e02a3c 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
> @@ -3,13 +3,163 @@
> * Copyright(c) 2020, Intel Corporation. All rights reserved.
> */
>
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_context.h"
> +#include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_engine_pm.h"
>
> #include "intel_pxp.h"
> #include "intel_pxp_sm.h"
> #include "intel_pxp_context.h"
>
> +static struct i915_vma *pxp_get_batch(struct drm_i915_private *i915,
> + struct intel_context *ce,
> + struct intel_gt_buffer_pool_node *pool,
> + u32 *cmd_buf, int
> +cmd_size_in_dw) {
> + struct i915_vma *batch = ERR_PTR(-EINVAL);
> + u32 *cmd;
> +
> + if (!ce || !ce->engine || !cmd_buf)
> + return ERR_PTR(-EINVAL);
> +
> + if (cmd_size_in_dw * 4 > PAGE_SIZE) {
> + drm_err(&i915->drm, "Failed to %s, invalid cmd_size_id_dw=[%d]\n",
> + __func__, cmd_size_in_dw);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + cmd = i915_gem_object_pin_map(pool->obj, I915_MAP_FORCE_WC);
> + if (IS_ERR(cmd)) {
> + drm_err(&i915->drm, "Failed to i915_gem_object_pin_map()\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + memcpy(cmd, cmd_buf, cmd_size_in_dw * 4);
> +
> + if (drm_debug_enabled(DRM_UT_DRIVER)) {
> + print_hex_dump(KERN_DEBUG, "cmd binaries:",
> + DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
> + }
> +
> + i915_gem_object_unpin_map(pool->obj);
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + drm_err(&i915->drm, "Failed to i915_vma_instance()\n");
> + return batch;
> + }
> +
> + return batch;
> +}
> +
> +static int pxp_submit_cmd(struct drm_i915_private *i915, u32 *cmd,
> +int cmd_size_in_dw) {
> + int err = -EINVAL;
> + struct i915_vma *batch;
> + struct i915_request *rq;
> + struct intel_context *ce = NULL;
> + bool is_engine_pm_get = false;
> + bool is_batch_vma_pin = false;
> + bool is_skip_req_on_err = false;
> + bool is_engine_get_pool = false;
> + struct intel_gt_buffer_pool_node *pool = NULL;
> + struct intel_gt *gt = NULL;
> +
> + if (!i915 || !HAS_ENGINE(&i915->gt, VCS0) ||
> + !i915->gt.engine[VCS0]->kernel_context) {
> + err = -EINVAL;
> + goto end;
> + }
> +
> + if (!cmd || (cmd_size_in_dw * 4) > PAGE_SIZE) {
> + drm_err(&i915->drm, "Failed to %s bad params\n", __func__);
> + return -EINVAL;
> + }
> +
> + gt = &i915->gt;
> + ce = i915->gt.engine[VCS0]->kernel_context;
> +
> + intel_engine_pm_get(ce->engine);
> + is_engine_pm_get = true;
> +
> + pool = intel_gt_get_buffer_pool(gt, PAGE_SIZE);
> + if (IS_ERR(pool)) {
> + drm_err(&i915->drm, "Failed to intel_engine_get_pool()\n");
> + goto end;
> + }
> + is_engine_get_pool = true;
> +
> + batch = pxp_get_batch(i915, ce, pool, cmd, cmd_size_in_dw);
> + if (IS_ERR(batch)) {
> + drm_err(&i915->drm, "Failed to pxp_get_batch()\n");
> + goto end;
> + }
> +
> + err = i915_vma_pin(batch, 0, 0, PIN_USER);
> + if (err) {
> + drm_err(&i915->drm, "Failed to i915_vma_pin()\n");
> + goto end;
> + }
> + is_batch_vma_pin = true;
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + drm_err(&i915->drm, "Failed to intel_context_create_request()\n");
> + goto end;
> + }
> + is_skip_req_on_err = true;
> +
> + err = intel_gt_buffer_pool_mark_active(pool, rq);
> + if (err) {
> + drm_err(&i915->drm, "Failed to intel_engine_pool_mark_active()\n");
> + goto end;
> + }
> +
> + i915_vma_lock(batch);
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + i915_vma_unlock(batch);
> + if (err) {
> + drm_err(&i915->drm, "Failed to i915_request_await_object()\n");
> + goto end;
> + }
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err) {
> + drm_err(&i915->drm, "Failed to emit_init_breadcrumb()\n");
> + goto end;
> + }
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err) {
> + drm_err(&i915->drm, "Failed to emit_bb_start()\n");
> + goto end;
> + }
> +
> + i915_request_add(rq);
> +
> +end:
> + if (unlikely(err) && is_skip_req_on_err)
> + i915_request_set_error_once(rq, err);
> +
> + if (is_batch_vma_pin)
> + i915_vma_unpin(batch);
> +
> + if (is_engine_get_pool)
> + intel_gt_buffer_pool_put(pool);
> +
> + if (is_engine_pm_get)
> + intel_engine_pm_put(ce->engine);
> +
> + return err;
> +}
> +
> static int pxp_sm_reg_read(struct drm_i915_private *i915, u32 offset,
> u32 *regval) {
> intel_wakeref_t wakeref;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (8 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 09/16] drm/i915/pxp: Func to send hardware session termination Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 11/16] drm/i915/pxp: Enable PXP power management Huang, Sean Z
` (8 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 6 +-
drivers/gpu/drm/i915/pxp/intel_pxp.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_sm.c | 207 ++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_sm.h | 17 ++
4 files changed, 232 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 10f4b1de07c4..48a0eb16f1d9 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -68,14 +68,18 @@ static void intel_pxp_mask_irq(struct intel_gt *gt, u32 mask)
static int intel_pxp_teardown_required_callback(struct drm_i915_private *i915)
{
+ int ret;
+
mutex_lock(&i915->pxp.ctx->ctx_mutex);
i915->pxp.ctx->global_state_attacked = true;
i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915, SESSION_TYPE_TYPE0);
+
mutex_unlock(&i915->pxp.ctx->ctx_mutex);
- return 0;
+ return ret;
}
static int intel_pxp_global_terminate_complete_callback(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e5f6e2b1bdfd..425cafe24392 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -15,6 +15,9 @@
#define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \
&(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions)
+#define pxp_session_max(session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \
+ MAX_TYPE0_SESSIONS : MAX_TYPE1_SESSIONS)
+
#define MAX_TYPE0_SESSIONS 16
#define MAX_TYPE1_SESSIONS 6
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
index c88243e02a3c..f8bb5248247f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.c
@@ -581,6 +581,213 @@ int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int ses
return -EINVAL;
}
+static int add_pxp_prolog(struct drm_i915_private *i915, u32 *cmd, int session_type,
+ int session_index)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_prolog = cmd;
+ const int cmd_prolog_size_in_dw = 10;
+
+ if (!cmd)
+ return cmd_prolog_size_in_dw;
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_prolog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MI_SET_APPID */
+ if (session_type == SESSION_TYPE_TYPE1) {
+ if (session_index >= MAX_TYPE1_SESSIONS) {
+ drm_err(&i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_TYPE1_APP |
+ MI_SET_APPID_SESSION_ID(session_index));
+ } else {
+ if (session_index >= MAX_TYPE0_SESSIONS) {
+ drm_err(&i915->drm, "Failed to %s invalid session_index\n", __func__);
+ goto end;
+ }
+
+ *cmd_prolog++ = (MI_SET_APPID | MI_SET_APPID_SESSION_ID(session_index));
+ }
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_FLUSH_DW - pxp on */
+ *cmd_prolog++ = (MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE); /* DW0 */
+ *cmd_prolog++ = 0; /* DW1 */
+ *cmd_prolog++ = 0; /* DW2 */
+
+ /* MFX_WAIT */
+ *cmd_prolog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ increased_size_in_dw = (cmd_prolog - cmd);
+end:
+ return increased_size_in_dw;
+}
+
+static int add_pxp_epilog(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_epilog = cmd;
+ const int cmd_epilog_size_in_dw = 5;
+
+ if (!cmd)
+ return cmd_epilog_size_in_dw;
+
+ /* MI_FLUSH_DW - pxp off */
+ *cmd_epilog++ = MI_FLUSH_DW; /* DW0 */
+ *cmd_epilog++ = 0; /* DW1 */
+ *cmd_epilog++ = 0; /* DW2 */
+
+ /* MFX_WAIT - stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+ *cmd_epilog++ = (MFX_WAIT | MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG |
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG);
+
+ /* MI_BATCH_BUFFER_END */
+ *cmd_epilog++ = MI_BATCH_BUFFER_END;
+
+ increased_size_in_dw = (cmd_epilog - cmd);
+ return increased_size_in_dw;
+}
+
+static int add_pxp_inline_termination(u32 *cmd)
+{
+ u32 increased_size_in_dw = 0;
+ u32 *cmd_termin = cmd;
+ const int cmd_termin_size_in_dw = 2;
+
+ if (!cmd)
+ return cmd_termin_size_in_dw;
+
+ /* CRYPTO_KEY_EXCHANGE - session inline termination */
+ *cmd_termin++ = CRYPTO_KEY_EXCHANGE; /* DW0 */
+ *cmd_termin++ = 0; /* DW1 */
+
+ increased_size_in_dw = (cmd_termin - cmd);
+ return increased_size_in_dw;
+}
+
+static int terminate_all_hw_sessions_with_global_termination(struct drm_i915_private *i915,
+ int session_type)
+{
+ u32 *cmd = NULL;
+ u32 *cmd_ptr = NULL;
+ int cmd_size_in_dw = 0;
+ int ret;
+ int session_index;
+ const int session_num_max = pxp_session_max(session_type);
+
+ if (!i915)
+ return -EINVAL;
+
+ /* Calculate how many bytes need to be alloc */
+ for (session_index = 0; session_index < session_num_max; session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_size_in_dw += add_pxp_prolog(i915, NULL, session_type, session_index);
+ cmd_size_in_dw += add_pxp_inline_termination(NULL);
+ }
+ }
+ cmd_size_in_dw += add_pxp_epilog(NULL);
+
+ cmd = kzalloc(cmd_size_in_dw * 4, GFP_KERNEL);
+ if (!cmd)
+ return -ENOMEM;
+
+ /* Program the command */
+ cmd_ptr = cmd;
+ for (session_index = 0; session_index < session_num_max; session_index++) {
+ if (is_hw_session_in_play(i915, session_type, session_index)) {
+ cmd_ptr += add_pxp_prolog(i915, cmd_ptr, session_type, session_index);
+ cmd_ptr += add_pxp_inline_termination(cmd_ptr);
+ }
+ }
+ cmd_ptr += add_pxp_epilog(cmd_ptr);
+
+ if (cmd_size_in_dw != (cmd_ptr - cmd)) {
+ ret = -EINVAL;
+ drm_err(&i915->drm, "Failed to %s\n", __func__);
+ goto end;
+ }
+
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ print_hex_dump(KERN_DEBUG, "global termination cmd binaries:",
+ DUMP_PREFIX_OFFSET, 4, 4, cmd, cmd_size_in_dw * 4, true);
+ }
+
+ ret = pxp_submit_cmd(i915, cmd, cmd_size_in_dw);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to pxp_submit_cmd()\n");
+ goto end;
+ }
+
+end:
+ kfree(cmd);
+ return ret;
+}
+
+static int intel_pxp_sm_destroy_all_sw_sessions(struct drm_i915_private *i915, int session_type)
+{
+ int ret = 0;
+ struct pxp_protected_session *current_session, *n;
+
+ list_for_each_entry_safe(current_session, n, pxp_session_list(i915, session_type),
+ session_list) {
+ ret = pxp_set_pxp_tag(i915, session_type, current_session->session_index,
+ PROTECTION_MODE_NONE);
+ if (ret)
+ drm_err(&i915->drm, "Failed to pxp_set_pxp_tag()\n");
+
+ list_del(¤t_session->session_list);
+ kfree(current_session);
+ }
+
+ return ret;
+}
+
+/**
+ * intel_pxp_sm_terminate_all_active_sessions - Terminate all active HW sessions and their entries.
+ * @i915: i915 device handle.
+ * @session_type: Type of the sessions to be terminated.
+ * One of enum pxp_session_types.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * ctx_mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_sm_terminate_all_active_sessions(struct drm_i915_private *i915, int session_type)
+{
+ int ret;
+
+ lockdep_assert_held(&i915->pxp.ctx->ctx_mutex);
+
+ /* terminate the hw sessions */
+ ret = terminate_all_hw_sessions_with_global_termination(i915, session_type);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to terminate_all_hw_sessions_with_global_termination\n");
+ return ret;
+ }
+
+ ret = intel_pxp_sm_destroy_all_sw_sessions(i915, session_type);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to intel_pxp_sm_destroy_all_sw_sessions\n");
+ return ret;
+ }
+
+ return ret;
+}
+
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915)
{
int ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
index 6eb5efd083a9..fd738f61e10f 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_sm.h
@@ -23,6 +23,22 @@
#define SESSION_TYPE_MASK BIT(7)
#define SESSION_ID_MASK (BIT(7) - 1)
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_TYPE1_APP BIT(7)
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
/* Arbitrary session */
#define ARB_SESSION_INDEX 0xf
#define ARB_SESSION_TYPE SESSION_TYPE_TYPE0
@@ -92,6 +108,7 @@ struct pxp_protected_session {
int intel_pxp_sm_reserve_arb_session(struct drm_i915_private *i915, u32 *pxp_tag);
int pxp_sm_mark_protected_session_in_play(struct drm_i915_private *i915, int session_type,
u32 session_id);
+int intel_pxp_sm_terminate_all_active_sessions(struct drm_i915_private *i915, int session_type);
int pxp_sm_set_kcr_init_reg(struct drm_i915_private *i915);
#endif /* __INTEL_PXP_SM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 11/16] drm/i915/pxp: Enable PXP power management
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (9 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 10/16] drm/i915/pxp: Destroy arb session upon teardown Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 12/16] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
` (7 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_drv.c | 8 +++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 70 +++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 31 +++++++++++
4 files changed, 110 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3cc5fc250b33..11309f2634f1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -258,6 +258,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_context.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_sm.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 64399386292f..e0c31c1b0b36 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -68,6 +68,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drv.h"
#include "i915_ioc32.h"
@@ -1093,6 +1095,8 @@ static int i915_drm_prepare(struct drm_device *dev)
*/
i915_gem_suspend(i915);
+ intel_pxp_pm_prepare_suspend(i915);
+
return 0;
}
@@ -1278,6 +1282,8 @@ static int i915_drm_resume(struct drm_device *dev)
intel_gvt_resume(dev_priv);
+ intel_pxp_pm_resume(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return 0;
@@ -1349,6 +1355,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(dev_priv);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..454351a70565
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp_context.h"
+#include "intel_pxp_sm.h"
+#include "intel_pxp_pm.h"
+
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+
+ /* Disable PXP-IOCTLs */
+ i915->pxp.ctx->global_state_in_suspend = true;
+
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+}
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+ if (!i915->pxp.ctx)
+ return;
+
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ /* reset the attacked flag even there was a pending */
+ i915->pxp.ctx->global_state_attacked = false;
+
+ i915->pxp.ctx->flag_display_hm_surface_keys = false;
+ }
+
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+}
+
+int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ int ret = 0;
+
+ if (!i915->pxp.ctx)
+ return 0;
+
+ mutex_lock(&i915->pxp.ctx->ctx_mutex);
+
+ /* Re-enable PXP-IOCTLs */
+ if (i915->pxp.ctx->global_state_in_suspend) {
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915, SESSION_TYPE_TYPE0);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to intel_pxp_sm_terminate_all_active_sessions with type0\n");
+ goto end;
+ }
+
+ ret = intel_pxp_sm_terminate_all_active_sessions(i915, SESSION_TYPE_TYPE1);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to intel_pxp_sm_terminate_all_active_sessions with type1\n");
+ goto end;
+ }
+
+ i915->pxp.ctx->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&i915->pxp.ctx->ctx_mutex);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..b66b7e95e211
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915);
+
+void intel_pxp_pm_resume_early(struct drm_i915_private *i915);
+int intel_pxp_pm_resume(struct drm_i915_private *i915);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct drm_i915_private *i915)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct drm_i915_private *i915)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct drm_i915_private *i915)
+{
+ return 0;
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 12/16] drm/i915/pxp: Expose session state for display protection flip
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (10 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 11/16] drm/i915/pxp: Enable PXP power management Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 13/16] mei: pxp: export pavp client to me client bus Huang, Sean Z
` (6 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8 ++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 48a0eb16f1d9..0fbdd7eecefe 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -201,3 +201,11 @@ void intel_pxp_irq_handler(struct intel_gt *gt, u16 iir)
i915->pxp.current_events |= events;
schedule_work(&i915->pxp.irq_work);
}
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ if (i915->pxp.ctx && i915->pxp.ctx->flag_display_hm_surface_keys)
+ return true;
+ else
+ return false;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index 425cafe24392..88919f8a2403 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -52,6 +52,8 @@ int i915_pxp_global_terminate_complete_callback(struct drm_i915_private *i915);
int intel_pxp_init(struct drm_i915_private *i915);
void intel_pxp_uninit(struct drm_i915_private *i915);
+
+bool intel_pxp_gem_object_status(struct drm_i915_private *i915);
#else
static inline int intel_pxp_create_arb_session(struct drm_i915_private *i915)
{
@@ -80,6 +82,11 @@ static inline int intel_pxp_init(struct drm_i915_private *i915)
static inline void intel_pxp_uninit(struct drm_i915_private *i915)
{
}
+
+static inline bool intel_pxp_gem_object_status(struct drm_i915_private *i915)
+{
+ return false;
+}
#endif
#endif /* __INTEL_PXP_PM_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 13/16] mei: pxp: export pavp client to me client bus
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (11 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 12/16] drm/i915/pxp: Expose session state for display protection flip Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 14/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
` (5 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx; +Cc: Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index c06581ffa7bd..36884b0a6395 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -57,3 +57,5 @@ config INTEL_MEI_VIRTIO
device over virtio.
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index 52aefaab5c1b..cab19c96ba7a 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -29,3 +29,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..5bd61fe445e3
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .receive = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 14/16] drm/i915/uapi: introduce drm_i915_gem_create_ext
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (12 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 13/16] mei: pxp: export pavp client to me client bus Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 15/16] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
` (4 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx; +Cc: Joonas, Bommu Krishnaiah, Matthew
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
Cc: Matthew Auld matthew.auld@intel.com
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 42 ++++++++++++++++++++++++++++-
include/uapi/drm/i915_drm.h | 47 +++++++++++++++++++++++++++++++++
3 files changed, 89 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e0c31c1b0b36..14b0fa04ed14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1742,7 +1742,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58276694c848..41698a823737 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -53,6 +53,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
+#include "i915_user_extensions.h"
#include "intel_pm.h"
@@ -260,6 +261,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -271,10 +301,20 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index fa1f3d62f9a6..2c1ce2761d55 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -391,6 +391,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -728,6 +729,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1698,6 +1720,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull<<32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 15/16] drm/i915/pxp: User interface for Protected buffer
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (13 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 14/16] drm/i915/uapi: introduce drm_i915_gem_create_ext Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support Huang, Sean Z
` (3 subsequent siblings)
18 siblings, 0 replies; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah, Huang Sean Z, Kondapally Kalyan
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++++++++++--
drivers/gpu/drm/i915/gem/i915_gem_context.h | 10 ++++++++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 ++++
drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++----
include/uapi/drm/i915_drm.h | 19 +++++++++++++++
6 files changed, 67 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6299da64de4..dd5d24a13cb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2060,12 +2060,23 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
- else if (args->value)
- i915_gem_context_set_recoverable(ctx);
+ else if (args->value) {
+ if (!i915_gem_context_is_protected(ctx))
+ i915_gem_context_set_recoverable(ctx);
+ else
+ ret = -EPERM;
+ }
else
i915_gem_context_clear_recoverable(ctx);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ if (args->size)
+ ret = -EINVAL;
+ else if (args->value)
+ i915_gem_context_set_protected(ctx);
+ break;
+
case I915_CONTEXT_PARAM_PRIORITY:
ret = set_priority(ctx, args);
break;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index a133f92bbedb..5897e7ca11a8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -70,6 +70,16 @@ static inline void i915_gem_context_set_recoverable(struct i915_gem_context *ctx
set_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
}
+static inline void i915_gem_context_set_protected(struct i915_gem_context *ctx)
+{
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
+static inline bool i915_gem_context_is_protected(struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
static inline void i915_gem_context_clear_recoverable(struct i915_gem_context *ctx)
{
clear_bit(UCONTEXT_RECOVERABLE, &ctx->user_flags);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index ae14ca24a11f..81ae94c2be86 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -135,7 +135,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
-
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
*/
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index e2d9b7e1e152..90ac955463f4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -161,6 +161,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 41698a823737..6a791fd24eaa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -184,7 +184,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -204,6 +205,8 @@ i915_gem_create(struct drm_file *file,
if (IS_ERR(obj))
return PTR_ERR(obj);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -258,11 +261,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
- struct drm_i915_private *i915;
+ struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -273,6 +277,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -318,7 +333,7 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
static int
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2c1ce2761d55..fab00bfbbdee 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1715,6 +1715,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) PAVP content protection is enabled.
+ * When enabled, the context is marked unrecoverable and may
+ * become invalid due to PAVP teardown event or other error.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -1734,6 +1743,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull<<32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (14 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 15/16] drm/i915/pxp: User interface for Protected buffer Huang, Sean Z
@ 2020-12-07 0:21 ` Huang, Sean Z
2020-12-07 6:21 ` Anshuman Gupta
2020-12-07 0:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session Patchwork
` (2 subsequent siblings)
18 siblings, 1 reply; 41+ messages in thread
From: Huang, Sean Z @ 2020-12-07 0:21 UTC (permalink / raw)
To: Intel-gfx; +Cc: Bommu Krishnaiah
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 019a2d6d807a..158c8dea0930 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_gem_object_status(dev_priv) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c3b9ca142539..ebb66fbab7d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7208,6 +7208,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2020-12-07 6:21 ` Anshuman Gupta
0 siblings, 0 replies; 41+ messages in thread
From: Anshuman Gupta @ 2020-12-07 6:21 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: Bommu Krishnaiah, Intel-gfx
Could u please add the change details in patch as below
v3:
Chnage in API intel_pxp_gem_object_status()
On 2020-12-06 at 16:21:34 -0800, Huang, Sean Z wrote:
> From: Anshuman Gupta <anshuman.gupta@intel.com>
>
> Add support to enable/disable PLANE_SURF Decryption Request bit.
> It requires only to enable plane decryption support when following
> condition met.
> 1. PAVP session is enabled.
for uniformity PAVP -> pxp here too.
Thanks,
Anshuman Gupta.
> 2. Buffer object is protected.
>
> v2:
> - Rebased to libva_cp-drm-tip_tgl_cp tree.
> - Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
>
> Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Cc: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 19 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 019a2d6d807a..158c8dea0930 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -39,6 +39,8 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_rect.h>
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drv.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> @@ -752,6 +754,11 @@ icl_program_input_csc(struct intel_plane *plane,
> PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
> }
>
> +static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
> +{
> + return obj->user_flags & I915_BO_PROTECTED ? true : false;
> +}
> +
> static void
> skl_plane_async_flip(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -788,6 +795,7 @@ skl_program_plane(struct intel_plane *plane,
> u32 surf_addr = plane_state->color_plane[color_plane].offset;
> u32 stride = skl_plane_stride(plane_state, color_plane);
> const struct drm_framebuffer *fb = plane_state->hw.fb;
> + const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> int aux_plane = intel_main_to_aux_plane(fb, color_plane);
> int crtc_x = plane_state->uapi.dst.x1;
> int crtc_y = plane_state->uapi.dst.y1;
> @@ -798,7 +806,7 @@ skl_program_plane(struct intel_plane *plane,
> u8 alpha = plane_state->hw.alpha >> 8;
> u32 plane_color_ctl = 0, aux_dist = 0;
> unsigned long irqflags;
> - u32 keymsk, keymax;
> + u32 keymsk, keymax, plane_surf;
> u32 plane_ctl = plane_state->ctl;
>
> plane_ctl |= skl_plane_ctl_crtc(crtc_state);
> @@ -874,8 +882,15 @@ skl_program_plane(struct intel_plane *plane,
> * the control register just before the surface register.
> */
> intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> - intel_plane_ggtt_offset(plane_state) + surf_addr);
> + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
> +
> + if (intel_pxp_gem_object_status(dev_priv) &&
> + intel_fb_obj_protected(obj))
> + plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
> + else
> + plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
> +
> + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
>
> if (plane_state->scaler_id >= 0)
> skl_program_scaler(plane, crtc_state, plane_state);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c3b9ca142539..ebb66fbab7d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7208,6 +7208,7 @@ enum {
> #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
> #define PLANE_SURF(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
> +#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
>
> #define _PLANE_OFFSET_1_B 0x711a4
> #define _PLANE_OFFSET_2_B 0x712a4
> --
> 2.17.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (15 preceding siblings ...)
2020-12-07 0:21 ` [Intel-gfx] [RFC-v1 16/16] drm/i915/pxp: Add plane decryption support Huang, Sean Z
@ 2020-12-07 0:42 ` Patchwork
2020-12-07 1:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-07 4:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
18 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2020-12-07 0:42 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
56ffa1e5dc43 drm/i915/pxp: Introduce Intel PXP component
-:108: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#108:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 125 lines checked
900074c203b4 drm/i915/pxp: Enable PXP irq worker and callback stub
a44a71ee8f7a drm/i915/pxp: Add PXP context for logical hardware states.
-:106: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#106:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 165 lines checked
dbe74e292313 drm/i915/pxp: set KCR reg init during the boot time
-:69: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#69:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 102 lines checked
1f58bdf3d44d drm/i915/pxp: Read register to check hardware session state
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#19: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.h:15:
+#define pxp_session_list(i915, session_type) (((session_type) == SESSION_TYPE_TYPE0) ? \
+ &(i915)->pxp.ctx->active_pxp_type0_sessions : &(i915)->pxp.ctx->active_pxp_type1_sessions)
total: 0 errors, 0 warnings, 1 checks, 255 lines checked
21ed306a5303 drm/i915/pxp: Implement funcs to get/set PXP tag
6535c3768f7b drm/i915/pxp: Implement funcs to create the TEE channel
-:87: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#87:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 244 lines checked
dce0eab4952c drm/i915/pxp: Create the arbitrary session after boot
f3d2af9143ce drm/i915/pxp: Func to send hardware session termination
8d1a900379e7 drm/i915/pxp: Destroy arb session upon teardown
f363d53b2c55 drm/i915/pxp: Enable PXP power management
-:67: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#67:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 140 lines checked
61c300f2e8e9 drm/i915/pxp: Expose session state for display protection flip
ad81178c888f mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
cb5b82433cec drm/i915/uapi: introduce drm_i915_gem_create_ext
-:12: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Joonas Lahtinen joonas.lahtinen@linux.intel.com'
#12:
Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com
-:13: ERROR:BAD_SIGN_OFF: Unrecognized email address: 'Matthew Auld matthew.auld@intel.com'
#13:
Cc: Matthew Auld matthew.auld@intel.com
-:46: ERROR:CODE_INDENT: code indent should use tabs where possible
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:46: WARNING:LEADING_SPACE: please, no spaces at the start of a line
#46: FILE: drivers/gpu/drm/i915/i915_gem.c:265:
+ struct drm_i915_private *i915;$
-:50: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#50: FILE: drivers/gpu/drm/i915/i915_gem.c:269:
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
-:95: CHECK:LINE_SPACING: Please don't use multiple blank lines
#95: FILE: drivers/gpu/drm/i915/i915_gem.c:317:
+
+
-:107: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#107: FILE: include/uapi/drm/i915_drm.h:394:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
-:155: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#155: FILE: include/uapi/drm/i915_drm.h:1735:
+#define I915_OBJECT_PARAM (1ull<<32)
^
total: 3 errors, 2 warnings, 3 checks, 136 lines checked
835fa00f2104 drm/i915/pxp: User interface for Protected buffer
2c2a5ec977c5 drm/i915/pxp: Add plane decryption support
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP component - Mesa single session
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (16 preceding siblings ...)
2020-12-07 0:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP component - Mesa single session Patchwork
@ 2020-12-07 1:15 ` Patchwork
2020-12-07 4:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
18 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2020-12-07 1:15 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4879 bytes --]
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9451 -> Patchwork_19073
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/index.html
New tests
---------
New tests have been introduced between CI_DRM_9451 and Patchwork_19073:
### New CI tests (1) ###
* boot:
- Statuses : 1 fail(s) 38 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19073 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [PASS][1] -> [DMESG-WARN][2] ([i915#402])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@execlists:
- fi-kbl-7500u: [PASS][3] -> [INCOMPLETE][4] ([i915#1037] / [i915#794])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-kbl-7500u/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-kbl-7500u/igt@i915_selftest@live@execlists.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@gem_ctx_exec@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@gem_ctx_exec@basic.html
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][7] ([i915#2411] / [i915#402]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [FAIL][9] ([i915#579]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-tgl-y: [DMESG-FAIL][11] ([i915#2601]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/fi-tgl-y/igt@i915_selftest@live@gt_heartbeat.html
[i915#1037]: https://gitlab.freedesktop.org/drm/intel/issues/1037
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2601]: https://gitlab.freedesktop.org/drm/intel/issues/2601
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (43 -> 39)
------------------------------
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9451 -> Patchwork_19073
CI-20190529: 20190529
CI_DRM_9451: e5d4ddd912799f4fdaeadfc50507b3150e1ae9e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5882: 47f770e8e544831ae5a984b2083df73f71067762 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19073: 2c2a5ec977c5c0462ecd664e07527d1017464105 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2c2a5ec977c5 drm/i915/pxp: Add plane decryption support
835fa00f2104 drm/i915/pxp: User interface for Protected buffer
cb5b82433cec drm/i915/uapi: introduce drm_i915_gem_create_ext
ad81178c888f mei: pxp: export pavp client to me client bus
61c300f2e8e9 drm/i915/pxp: Expose session state for display protection flip
f363d53b2c55 drm/i915/pxp: Enable PXP power management
8d1a900379e7 drm/i915/pxp: Destroy arb session upon teardown
f3d2af9143ce drm/i915/pxp: Func to send hardware session termination
dce0eab4952c drm/i915/pxp: Create the arbitrary session after boot
6535c3768f7b drm/i915/pxp: Implement funcs to create the TEE channel
21ed306a5303 drm/i915/pxp: Implement funcs to get/set PXP tag
1f58bdf3d44d drm/i915/pxp: Read register to check hardware session state
dbe74e292313 drm/i915/pxp: set KCR reg init during the boot time
a44a71ee8f7a drm/i915/pxp: Add PXP context for logical hardware states.
900074c203b4 drm/i915/pxp: Enable PXP irq worker and callback stub
56ffa1e5dc43 drm/i915/pxp: Introduce Intel PXP component
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Intel PXP component - Mesa single session
2020-12-07 0:21 [Intel-gfx] [RFC-v1 00/16] Introduce Intel PXP component - Mesa single session Huang, Sean Z
` (17 preceding siblings ...)
2020-12-07 1:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-12-07 4:01 ` Patchwork
18 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2020-12-07 4:01 UTC (permalink / raw)
To: Huang, Sean Z; +Cc: intel-gfx
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== Series Details ==
Series: Introduce Intel PXP component - Mesa single session
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9451_full -> Patchwork_19073_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19073_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19073_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19073_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc.html
New tests
---------
New tests have been introduced between CI_DRM_9451_full and Patchwork_19073_full:
### New CI tests (1) ###
* boot:
- Statuses : 174 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19073_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][3] -> [FAIL][4] ([i915#2597])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb1/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen:
- shard-glk: [PASS][5] -> [DMESG-WARN][6] ([i915#118] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-snb: [PASS][7] -> [DMESG-WARN][8] ([i915#42])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-snb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [PASS][9] -> [FAIL][10] ([i915#54])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk8/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#79])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible@c-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#407])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl9/igt@kms_flip@dpms-vs-vblank-race-interruptible@c-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl5/igt@kms_flip@dpms-vs-vblank-race-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#79])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][21] -> [INCOMPLETE][22] ([i915#155] / [i915#180])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#2122])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145] / [i915#265])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
* igt@perf@blocking:
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#1542])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl5/igt@perf@blocking.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl1/igt@perf@blocking.html
#### Possible fixes ####
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [INCOMPLETE][31] ([i915#151]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl10/igt@i915_pm_rpm@system-suspend.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl1/igt@i915_pm_rpm@system-suspend.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [FAIL][33] ([i915#2521]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl5/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [FAIL][35] ([i915#129]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl2/igt@kms_color@pipe-a-ctm-red-to-blue.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl2/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_color@pipe-b-ctm-0-25:
- shard-skl: [DMESG-WARN][37] ([i915#1982]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl7/igt@kms_color@pipe-b-ctm-0-25.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl10/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding:
- shard-skl: [FAIL][39] ([i915#54]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-256x85-sliding.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge:
- shard-glk: [FAIL][41] ([i915#70]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk8/igt@kms_cursor_edge_walk@pipe-b-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][43] ([i915#2346]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-tglb: [FAIL][45] ([i915#2346]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb5/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip_tiling@flip-changes-tiling-y@edp-1-pipe-a:
- shard-skl: [FAIL][47] -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl2/igt@kms_flip_tiling@flip-changes-tiling-y@edp-1-pipe-a.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl2/igt@kms_flip_tiling@flip-changes-tiling-y@edp-1-pipe-a.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-skl: [FAIL][49] ([i915#49]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][51] ([i915#1188]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl5/igt@kms_hdr@bpc-switch.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl1/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][53] ([fdo#108145] / [i915#265]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][55] ([fdo#109441]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@prime_vgem@sync@rcs0:
- shard-iclb: [INCOMPLETE][57] ([i915#409]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb3/igt@prime_vgem@sync@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb3/igt@prime_vgem@sync@rcs0.html
#### Warnings ####
* igt@runner@aborted:
- shard-kbl: ([FAIL][59], [FAIL][60]) ([i915#2283] / [i915#2295] / [i915#2722]) -> ([FAIL][61], [FAIL][62], [FAIL][63]) ([i915#2283] / [i915#2295] / [i915#2722] / [i915#483])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-kbl7/igt@runner@aborted.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-kbl7/igt@runner@aborted.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-kbl1/igt@runner@aborted.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-kbl6/igt@runner@aborted.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-kbl2/igt@runner@aborted.html
- shard-iclb: ([FAIL][64], [FAIL][65], [FAIL][66], [FAIL][67]) ([i915#1814] / [i915#2283] / [i915#2295] / [i915#2426] / [i915#2722] / [i915#409] / [i915#483]) -> ([FAIL][68], [FAIL][69], [FAIL][70]) ([i915#1814] / [i915#2283] / [i915#2295] / [i915#2722] / [i915#483])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb6/igt@runner@aborted.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb4/igt@runner@aborted.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb7/igt@runner@aborted.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-iclb3/igt@runner@aborted.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb2/igt@runner@aborted.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb3/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-iclb8/igt@runner@aborted.html
- shard-glk: ([FAIL][71], [FAIL][72], [FAIL][73], [FAIL][74]) ([i915#1814] / [i915#2283] / [i915#2295] / [i915#2722] / [i915#483] / [k.org#202321]) -> ([FAIL][75], [FAIL][76], [FAIL][77], [FAIL][78]) ([i915#1814] / [i915#2283] / [i915#2295] / [i915#2722] / [k.org#202321])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk1/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk1/igt@runner@aborted.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk2/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-glk3/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk9/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk9/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk6/igt@runner@aborted.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-glk5/igt@runner@aborted.html
- shard-tglb: ([FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82]) ([i915#1602] / [i915#1814] / [i915#2295] / [i915#2426] / [i915#2722] / [k.org#205379]) -> ([FAIL][83], [FAIL][84], [FAIL][85]) ([i915#1602] / [i915#2295] / [i915#2722])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb3/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb5/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb2/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-tglb1/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb3/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb5/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-tglb8/igt@runner@aborted.html
- shard-skl: ([FAIL][86], [FAIL][87]) ([i915#2283] / [i915#2295] / [i915#2722] / [i915#483]) -> [FAIL][88] ([i915#2295] / [i915#2722])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl5/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9451/shard-skl1/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/shard-skl2/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#129]: https://gitlab.freedesktop.org/drm/intel/issues/129
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2597]: https://gitlab.freedesktop.org/drm/intel/issues/2597
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#407]: https://gitlab.freedesktop.org/drm/intel/issues/407
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
[k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9451 -> Patchwork_19073
CI-20190529: 20190529
CI_DRM_9451: e5d4ddd912799f4fdaeadfc50507b3150e1ae9e8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5882: 47f770e8e544831ae5a984b2083df73f71067762 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19073: 2c2a5ec977c5c0462ecd664e07527d1017464105 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19073/index.html
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