* Re: [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware
@ 2021-04-06 11:52 Hans Verkuil (hansverk)
0 siblings, 0 replies; 5+ messages in thread
From: Hans Verkuil (hansverk) @ 2021-04-06 11:52 UTC (permalink / raw)
To: Benjamin Gaignard, ezequiel; +Cc: linux-media, kernel
On 01/04/2021 18:00, Benjamin Gaignard wrote:
> > Split VPU node in two: one for G1 and one for G2 since they are
Split -> Split the
> > different hardware blocks.
> > Add syscon for hardware control block.
for -> for the
> > Remove reg-names property that is useless.
Remove -> Remove the
> > Each VPU node only need one interrupt.
need -> needs
> > Change G2 assigned clock to match to the specifications.
to the specifications -> the specification
> > In the both nodes all the clocks need to assigned to make
In the -> In
need to -> need to be
> > sure that control block will be correctly clocked even if
that -> that the
> > only one device node is enabled.
Regards,
Hans
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware
2021-04-01 15:59 [PATCH v8 00/13] Add HANTRO G2/HEVC decoder support for IMX8MQ Benjamin Gaignard
2021-04-01 16:00 ` Benjamin Gaignard
(?)
@ 2021-04-01 16:00 ` Benjamin Gaignard
0 siblings, 0 replies; 5+ messages in thread
From: Benjamin Gaignard @ 2021-04-01 16:00 UTC (permalink / raw)
To: ezequiel, p.zabel, mchehab, robh+dt, shawnguo, s.hauer, festevam,
lee.jones, gregkh, mripard, paul.kocialkowski, wens,
jernej.skrabec, hverkuil-cisco, emil.l.velikov
Cc: kernel, linux-imx, linux-media, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, devel, kernel, Benjamin Gaignard
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++-----
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e12c2e..65158414d255 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
- vpu: video-codec@38300000 {
+ vpu_ctrl: syscon@38320000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
@@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 {
<&clk IMX8MQ_VPU_PLL_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <600000000>, <600000000>,
+ assigned-clock-rates = <600000000>, <300000000>,
+ <800000000>, <0>;
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <600000000>, <300000000>,
<800000000>, <0>;
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
pcie0: pcie@33800000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware
@ 2021-04-01 16:00 ` Benjamin Gaignard
0 siblings, 0 replies; 5+ messages in thread
From: Benjamin Gaignard @ 2021-04-01 16:00 UTC (permalink / raw)
To: ezequiel, p.zabel, mchehab, robh+dt, shawnguo, s.hauer, festevam,
lee.jones, gregkh, mripard, paul.kocialkowski, wens,
jernej.skrabec, hverkuil-cisco, emil.l.velikov
Cc: devel, devicetree, Benjamin Gaignard, linux-kernel,
linux-rockchip, linux-imx, kernel, kernel, linux-arm-kernel,
linux-media
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++-----
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e12c2e..65158414d255 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
- vpu: video-codec@38300000 {
+ vpu_ctrl: syscon@38320000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
@@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 {
<&clk IMX8MQ_VPU_PLL_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <600000000>, <600000000>,
+ assigned-clock-rates = <600000000>, <300000000>,
+ <800000000>, <0>;
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <600000000>, <300000000>,
<800000000>, <0>;
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
pcie0: pcie@33800000 {
--
2.25.1
_______________________________________________
devel mailing list
devel@linuxdriverproject.org
http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware
@ 2021-04-01 16:00 ` Benjamin Gaignard
0 siblings, 0 replies; 5+ messages in thread
From: Benjamin Gaignard @ 2021-04-01 16:00 UTC (permalink / raw)
To: ezequiel, p.zabel, mchehab, robh+dt, shawnguo, s.hauer, festevam,
lee.jones, gregkh, mripard, paul.kocialkowski, wens,
jernej.skrabec, hverkuil-cisco, emil.l.velikov
Cc: kernel, linux-imx, linux-media, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, devel, kernel, Benjamin Gaignard
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++-----
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e12c2e..65158414d255 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
- vpu: video-codec@38300000 {
+ vpu_ctrl: syscon@38320000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
@@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 {
<&clk IMX8MQ_VPU_PLL_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <600000000>, <600000000>,
+ assigned-clock-rates = <600000000>, <300000000>,
+ <800000000>, <0>;
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <600000000>, <300000000>,
<800000000>, <0>;
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
pcie0: pcie@33800000 {
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware
@ 2021-04-01 16:00 ` Benjamin Gaignard
0 siblings, 0 replies; 5+ messages in thread
From: Benjamin Gaignard @ 2021-04-01 16:00 UTC (permalink / raw)
To: ezequiel, p.zabel, mchehab, robh+dt, shawnguo, s.hauer, festevam,
lee.jones, gregkh, mripard, paul.kocialkowski, wens,
jernej.skrabec, hverkuil-cisco, emil.l.velikov
Cc: kernel, linux-imx, linux-media, linux-rockchip, devicetree,
linux-arm-kernel, linux-kernel, devel, kernel, Benjamin Gaignard
Split VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for hardware control block.
Remove reg-names property that is useless.
Each VPU node only need one interrupt.
Change G2 assigned clock to match to the specifications.
In the both nodes all the clocks need to assigned to make
sure that control block will be correctly clocked even if
only one device node is enabled.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
version 7:
- use nxp,imx8m-vpu-ctrl as phandle syscon property name
version 5:
- use syscon instead of VPU reset
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++-----
1 file changed, 34 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 17c449e12c2e..65158414d255 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 {
status = "disabled";
};
- vpu: video-codec@38300000 {
+ vpu_ctrl: syscon@38320000 {
+ compatible = "nxp,imx8mq-vpu-ctrl", "syscon";
+ reg = <0x38320000 0x10000>;
+ };
+
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
@@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 {
<&clk IMX8MQ_VPU_PLL_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <600000000>, <600000000>,
+ assigned-clock-rates = <600000000>, <300000000>,
+ <800000000>, <0>;
+ power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
+ <&clk IMX8MQ_CLK_VPU_G2>,
+ <&clk IMX8MQ_CLK_VPU_BUS>,
+ <&clk IMX8MQ_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_VPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VPU_PLL>;
+ assigned-clock-rates = <600000000>, <300000000>,
<800000000>, <0>;
power-domains = <&pgc_vpu>;
+ nxp,imx8m-vpu-ctrl = <&vpu_ctrl>;
};
pcie0: pcie@33800000 {
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-04-06 11:55 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2021-04-06 11:52 [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware Hans Verkuil (hansverk)
-- strict thread matches above, loose matches on Subject: below --
2021-04-01 15:59 [PATCH v8 00/13] Add HANTRO G2/HEVC decoder support for IMX8MQ Benjamin Gaignard
2021-04-01 16:00 ` [PATCH v8 13/13] arm64: dts: imx8mq: Add node to G2 hardware Benjamin Gaignard
2021-04-01 16:00 ` Benjamin Gaignard
2021-04-01 16:00 ` Benjamin Gaignard
2021-04-01 16:00 ` Benjamin Gaignard
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