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* [PATCH] drm/amdgpu: revise the mode2 reset for vangogh
@ 2020-12-23  2:07 Huang Rui
  2020-12-23  7:28 ` Quan, Evan
  0 siblings, 1 reply; 2+ messages in thread
From: Huang Rui @ 2020-12-23  2:07 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher, Jinzhou . Su, Huang Rui

PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 22 +++++++++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c        | 42 ++++++++++---------
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h        |  2 +
 3 files changed, 46 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 49864efdeffe..93328eaec0da 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -888,9 +888,29 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
 	return 0;
 }
 
+static int vangogh_mode_reset(struct smu_context *smu, int type)
+{
+	int ret = 0, index = 0;
+
+	index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+					       SMU_MSG_GfxDeviceDriverReset);
+	if (index < 0)
+		return index == -EACCES ? 0 : index;
+
+	mutex_lock(&smu->message_lock);
+
+	ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
+
+	mutex_unlock(&smu->message_lock);
+
+	mdelay(10);
+
+	return ret;
+}
+
 static int vangogh_mode2_reset(struct smu_context *smu)
 {
-	return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
+	return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
 }
 
 static const struct pptable_funcs vangogh_ppt_funcs = {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 76ca41653354..39d5edb8c16b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -68,14 +68,6 @@ static const char *smu_get_message_name(struct smu_context *smu,
 	return __smu_message_names[type];
 }
 
-static void smu_cmn_send_msg_without_waiting(struct smu_context *smu,
-					     uint16_t msg)
-{
-	struct amdgpu_device *adev = smu->adev;
-
-	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
-}
-
 static void smu_cmn_read_arg(struct smu_context *smu,
 			     uint32_t *arg)
 {
@@ -104,6 +96,26 @@ static int smu_cmn_wait_for_response(struct smu_context *smu)
 	return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
 }
 
+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+				     uint16_t msg, uint32_t param)
+{
+	struct amdgpu_device *adev = smu->adev;
+	int ret;
+
+	ret = smu_cmn_wait_for_response(smu);
+	if (ret) {
+		dev_err(adev->dev, "Msg issuing pre-check failed and "
+		       "SMU may be not in the right state!\n");
+		return ret;
+	}
+
+	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+
+	return 0;
+}
+
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 				    enum smu_message_type msg,
 				    uint32_t param,
@@ -122,18 +134,10 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 		return index == -EACCES ? 0 : index;
 
 	mutex_lock(&smu->message_lock);
-	ret = smu_cmn_wait_for_response(smu);
-	if (ret) {
-		dev_err(adev->dev, "Msg issuing pre-check failed and "
-		       "SMU may be not in the right state!\n");
-		goto out;
-	}
-
-	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
-	WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
-
-	smu_cmn_send_msg_without_waiting(smu, (uint16_t)index);
+	ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, param);
+	if (ret)
+		goto out;
 
 	ret = smu_cmn_wait_for_response(smu);
 	if (ret) {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index 01e825d83d8d..08ccf2d3257c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -26,6 +26,8 @@
 #include "amdgpu_smu.h"
 
 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+				     uint16_t msg, uint32_t param);
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 				    enum smu_message_type msg,
 				    uint32_t param,
-- 
2.25.1

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu: revise the mode2 reset for vangogh
  2020-12-23  2:07 [PATCH] drm/amdgpu: revise the mode2 reset for vangogh Huang Rui
@ 2020-12-23  7:28 ` Quan, Evan
  0 siblings, 0 replies; 2+ messages in thread
From: Quan, Evan @ 2020-12-23  7:28 UTC (permalink / raw)
  To: Huang, Ray, amd-gfx; +Cc: Deucher, Alexander, Su, Jinzhou (Joe), Huang, Ray

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Evan Quan <evan.quan@amd.com>

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Huang Rui
Sent: Wednesday, December 23, 2020 10:08 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Su, Jinzhou (Joe) <Jinzhou.Su@amd.com>; Huang, Ray <Ray.Huang@amd.com>
Subject: [PATCH] drm/amdgpu: revise the mode2 reset for vangogh

PCIE MMIO bar needs to be restored firstly after the reset event
triggers. So it's unable to access the registers to wait for response
from SMU. Becasue the value of mmMP1_SMN_C2PMSG_90 is invalid at that
moment.

Signed-off-by: Huang Rui <ray.huang@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 22 +++++++++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c        | 42 ++++++++++---------
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h        |  2 +
 3 files changed, 46 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 49864efdeffe..93328eaec0da 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -888,9 +888,29 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
 return 0;
 }

+static int vangogh_mode_reset(struct smu_context *smu, int type)
+{
+int ret = 0, index = 0;
+
+index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+       SMU_MSG_GfxDeviceDriverReset);
+if (index < 0)
+return index == -EACCES ? 0 : index;
+
+mutex_lock(&smu->message_lock);
+
+ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
+
+mutex_unlock(&smu->message_lock);
+
+mdelay(10);
+
+return ret;
+}
+
 static int vangogh_mode2_reset(struct smu_context *smu)
 {
-return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_2, NULL);
+return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
 }

 static const struct pptable_funcs vangogh_ppt_funcs = {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 76ca41653354..39d5edb8c16b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -68,14 +68,6 @@ static const char *smu_get_message_name(struct smu_context *smu,
 return __smu_message_names[type];
 }

-static void smu_cmn_send_msg_without_waiting(struct smu_context *smu,
-     uint16_t msg)
-{
-struct amdgpu_device *adev = smu->adev;
-
-WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
-}
-
 static void smu_cmn_read_arg(struct smu_context *smu,
      uint32_t *arg)
 {
@@ -104,6 +96,26 @@ static int smu_cmn_wait_for_response(struct smu_context *smu)
 return RREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 : -EIO;
 }

+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+     uint16_t msg, uint32_t param)
+{
+struct amdgpu_device *adev = smu->adev;
+int ret;
+
+ret = smu_cmn_wait_for_response(smu);
+if (ret) {
+dev_err(adev->dev, "Msg issuing pre-check failed and "
+       "SMU may be not in the right state!\n");
+return ret;
+}
+
+WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
+WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
+WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
+
+return 0;
+}
+
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
     enum smu_message_type msg,
     uint32_t param,
@@ -122,18 +134,10 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
 return index == -EACCES ? 0 : index;

 mutex_lock(&smu->message_lock);
-ret = smu_cmn_wait_for_response(smu);
-if (ret) {
-dev_err(adev->dev, "Msg issuing pre-check failed and "
-       "SMU may be not in the right state!\n");
-goto out;
-}
-
-WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

-WREG32_SOC15_NO_KIQ(MP1, 0, mmMP1_SMN_C2PMSG_82, param);
-
-smu_cmn_send_msg_without_waiting(smu, (uint16_t)index);
+ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, param);
+if (ret)
+goto out;

 ret = smu_cmn_wait_for_response(smu);
 if (ret) {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index 01e825d83d8d..08ccf2d3257c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -26,6 +26,8 @@
 #include "amdgpu_smu.h"

 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
+int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
+     uint16_t msg, uint32_t param);
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
     enum smu_message_type msg,
     uint32_t param,
--
2.25.1

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2020-12-23  2:07 [PATCH] drm/amdgpu: revise the mode2 reset for vangogh Huang Rui
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