[PATCH 00/27] DC Patchset for October 15

[PATCH 00/27] DC Patchset for October 15

[Agustin Gutierrez]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Cc: Mark Broadworth <mark.broadworth@amd.com>

Agustin Gutierrez (2):
  Revert "drm/amd/display: Fix error in dmesg at boot"
  Revert "drm/amd/display: Add helper for blanking all dp displays"

Anthony Koo (2):
  drm/amd/display: Change initializer to single brace
  drm/amd/display: [FW Promotion] Release 0.0.88

Aric Cyr (2):
  drm/amd/display: Validate plane rects before use
  drm/amd/display: 3.2.157

Eric Yang (1):
  drm/amd/display: increase Z9 latency to workaround underflow in Z9

Hansen (1):
  drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

Jake Wang (6):
  drm/amd/display: Disable dpp root clock when not being used
  drm/amd/display: Disable dsc root clock when not being used
  drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
  drm/amd/display: Removed z10 save after dsc disable
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Disable hdmistream and hdmichar clocks

Jimmy Kizito (2):
  drm/amd/display: Clear encoder assignment for copied streams
  drm/amd/display: Do not skip link training on DP quick hot plug

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Lai, Derek (1):
  drm/amd/display: Removed power down on boot from DCN31

Michael Strauss (1):
  drm/amd/display: Clean Up VPG Low Mem Power

Mikita Lipski (1):
  drm/amd/display: Add missing PSR state

Nevenko Stupar (1):
  drm/amd/display: Add bios parser support for latest firmware_info

Nicholas Kazlauskas (2):
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Require immediate flip support for DCN3.1 planes

Nikola Cornij (2):
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amd/display: Increase watermark latencies for DCN3.1

Wenjing Liu (2):
  drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream
  drm/amd/display: correct apg audio channel enable golden value

 .../drm/amd/display/dc/bios/bios_parser2.c    |  90 ++++++-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  10 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 +----
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  32 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |   9 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |   1 -
 drivers/gpu/drm/amd/display/dc/dc_types.h     |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  24 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  49 +++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  39 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +++++++++++++++++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 114 +++++----
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  17 +-
 .../dc/dml/dcn31/display_mode_vba_31.c        |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   9 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../include/asic_reg/dcn/dcn_3_1_2_offset.h   |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   8 +
 29 files changed, 643 insertions(+), 185 deletions(-)

-- 
2.25.1

[PATCH 01/27] drm/amd/display: Disable dpp root clock when not being used

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Disable root clock for dpp when not being used.

Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  5 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 41 ++++++++++++++++++-
 2 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index d7bf9283dc90..3fae1f1f028d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -219,14 +219,17 @@ static void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
 		update_dispclk = true;
 	}
 
-	/* TODO: add back DTO programming when DPPCLK restore is fixed in FSDL*/
 	if (dpp_clock_lowered) {
 		// increase per DPP DTO before lowering global dppclk
+		dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 		dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
 	} else {
 		// increase global DPPCLK before lowering per DPP DTO
 		if (update_dppclk || update_dispclk)
 			dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
+		// always update dtos unless clock is lowered and not safe to lower
+		if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
+			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
 	}
 
 	// notify DMCUB of latest clocks
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 9896adf67425..582c500ecb49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -42,6 +42,45 @@
 #define DC_LOGGER \
 	dccg->ctx->logger
 
+static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (dccg->ref_dppclk && req_dppclk) {
+		int ref_dppclk = dccg->ref_dppclk;
+		int modulo, phase;
+
+		// phase / modulo = dpp pipe clk / dpp global clk
+		modulo = 0xff;   // use FF at the end
+		phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
+
+		if (phase > 0xff) {
+			ASSERT(false);
+			phase = 0xff;
+		}
+
+		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+				DPPCLK0_DTO_PHASE, phase,
+				DPPCLK0_DTO_MODULO, modulo);
+		REG_UPDATE(DPPCLK_DTO_CTRL,
+				DPPCLK_DTO_ENABLE[dpp_inst], 1);
+	} else {
+		//DTO must be enabled to generate a 0Hz clock output
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {
+			REG_UPDATE(DPPCLK_DTO_CTRL,
+					DPPCLK_DTO_ENABLE[dpp_inst], 1);
+			REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
+					DPPCLK0_DTO_PHASE, 0,
+					DPPCLK0_DTO_MODULO, 1);
+		} else {
+			REG_UPDATE(DPPCLK_DTO_CTRL,
+					DPPCLK_DTO_ENABLE[dpp_inst], 0);
+		}
+	}
+	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
+}
+
+
 void dccg31_set_dpstreamclk(
 		struct dccg *dccg,
 		enum hdmistreamclk_source src,
@@ -401,7 +440,7 @@ void dccg31_init(struct dccg *dccg)
 }
 
 static const struct dccg_funcs dccg31_funcs = {
-	.update_dpp_dto = dccg2_update_dpp_dto,
+	.update_dpp_dto = dccg31_update_dpp_dto,
 	.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
 	.dccg_init = dccg31_init,
 	.set_dpstreamclk = dccg31_set_dpstreamclk,
-- 
2.25.1

[PATCH 02/27] drm/amd/display: Clear encoder assignment for copied streams

[Agustin Gutierrez]

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
When copying a stream, the encoder assigned to it is copied too.
Encoder assignment should only happen when executing the encoder
assignment function link_encs_assign().

[How]
Clear the link encoder pointer for copied stream.

Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index f0f54f4d3d9b..57cf4cb82370 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -202,6 +202,10 @@ struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream)
 	new_stream->stream_id = new_stream->ctx->dc_stream_id_count;
 	new_stream->ctx->dc_stream_id_count++;
 
+	/* If using dynamic encoder assignment, wait till stream committed to assign encoder. */
+	if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign)
+		new_stream->link_enc = NULL;
+
 	kref_init(&new_stream->refcount);
 
 	return new_stream;
-- 
2.25.1

[PATCH 03/27] drm/amd/display: Do not skip link training on DP quick hot plug

[Agustin Gutierrez]

From: Jimmy Kizito <Jimmy.Kizito@amd.com>

[Why]
When rapidly plugging and unplugging a DP sink, detection link
training can be mistakenly skipped.

This is due to the hotplug processing occurring before the
encoder assignment logic has had a chance to process the removal
of a stream. The encoder that would be used for detection link
training is then erroneously reported as already in use and
detection link training is skipped.

[How]
During hot plug processing, only determine a link encoder to be
unavailable for a particular link if it has been assigned to a
different link.

Reviewed-by: Meenakshikumar Somasundaram <Meenakshikumar.Somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jimmy Kizito <Jimmy.Kizito@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c      | 2 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c | 9 ++++++---
 drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h     | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 54662d74c65a..8e0b40c7a1ee 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2863,7 +2863,7 @@ bool dp_verify_link_cap(
 		link->verified_link_cap = *known_limit_link_setting;
 		return true;
 	} else if (link->link_enc && link->dc->res_pool->funcs->link_encs_assign &&
-			!link_enc_cfg_is_link_enc_avail(link->ctx->dc, link->link_enc->preferred_engine)) {
+			!link_enc_cfg_is_link_enc_avail(link->ctx->dc, link->link_enc->preferred_engine, link)) {
 		link->verified_link_cap = initial_link_settings;
 		return true;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
index 1cab4bf06abe..72b0f8594b4a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c
@@ -488,16 +488,19 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(
 	return link_enc;
 }
 
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id)
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link)
 {
 	bool is_avail = true;
 	int i;
 
-	/* Add assigned encoders to list. */
+	/* An encoder is not available if it has already been assigned to a different endpoint. */
 	for (i = 0; i < MAX_PIPES; i++) {
 		struct link_enc_assignment assignment = get_assignment(dc, i);
+		struct display_endpoint_id ep_id = (struct display_endpoint_id) {
+				.link_id = link->link_id,
+				.ep_type = link->ep_type};
 
-		if (assignment.valid && assignment.eng_id == eng_id) {
+		if (assignment.valid && assignment.eng_id == eng_id && !are_ep_ids_equal(&ep_id, &assignment.ep_id)) {
 			is_avail = false;
 			break;
 		}
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
index 83b2199b2c83..10dcf6a5e9b1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_enc_cfg.h
@@ -97,7 +97,7 @@ struct link_encoder *link_enc_cfg_get_link_enc_used_by_stream(
 		const struct dc_stream_state *stream);
 
 /* Return true if encoder available to use. */
-bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id);
+bool link_enc_cfg_is_link_enc_avail(struct dc *dc, enum engine_id eng_id, struct dc_link *link);
 
 /* Returns true if encoder assignments in supplied state pass validity checks. */
 bool link_enc_cfg_validate(struct dc *dc, struct dc_state *state);
-- 
2.25.1

[PATCH 04/27] drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream

[Agustin Gutierrez]

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
Some DP2.0 RX requires us to set MST_EN even for SST configuration.
We added this debug option so we can configure this temporary workaround
for the RX.

Reviewed-by: George Shen <george.shen@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 ++++++-
 drivers/gpu/drm/amd/display/dc/dc.h           | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index ca5dc3c168ec..fa11a2b094ba 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1869,8 +1869,13 @@ static enum dc_status enable_link_dp(struct dc_state *state,
 		do_fallback = true;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+	/*
+	 * Temporary w/a to get DP2.0 link rates to work with SST.
+	 * TODO DP2.0 - Workaround: Remove w/a if and when the issue is resolved.
+	 */
 	if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING &&
-			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
+			pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&
+			link->dc->debug.set_mst_en_for_sst) {
 		dp_enable_mst_on_sink(link, true);
 	}
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index dd995905b0cb..254b760ae91f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -664,6 +664,7 @@ struct dc_debug_options {
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 	/* TODO - remove once tested */
 	bool legacy_dp2_lt;
+	bool set_mst_en_for_sst;
 #endif
 	union mem_low_power_enable_options enable_mem_low_power;
 	union root_clock_optimization_options root_clock_optimization;
-- 
2.25.1

[PATCH 05/27] drm/amd/display: Clean Up VPG Low Mem Power

[Agustin Gutierrez]

From: Michael Strauss <michael.strauss@amd.com>

[WHAT]
One of the current VPG power on calls is unnecessary

Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c            | 10 ----------
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c  | 13 +++++++++++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_resource.c   |  4 ----
 3 files changed, 13 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f9876e429f26..8be04be19124 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -71,8 +71,6 @@
 
 #include "dmub/dmub_srv.h"
 
-#include "dcn30/dcn30_vpg.h"
-
 #include "i2caux_interface.h"
 #include "dce/dmub_hw_lock_mgr.h"
 
@@ -2674,9 +2672,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
 		enum surface_update_type update_type,
 		struct dc_state *context)
 {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-	struct vpg *vpg;
-#endif
 	int j;
 
 	// Stream updates
@@ -2697,11 +2692,6 @@ static void commit_planes_do_stream_update(struct dc *dc,
 					stream_update->vrr_infopacket ||
 					stream_update->vsc_infopacket ||
 					stream_update->vsp_infopacket) {
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-				vpg = pipe_ctx->stream_res.stream_enc->vpg;
-				if (vpg && vpg->funcs->vpg_poweron)
-					vpg->funcs->vpg_poweron(vpg);
-#endif
 				resource_build_info_frame(pipe_ctx);
 				dc->hwss.update_info_frame(pipe_ctx);
 			}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 18e33ef3d217..968b8825dec7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -49,6 +49,7 @@
 #include "inc/link_dpcd.h"
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "inc/link_enc_cfg.h"
+#include "dcn30/dcn30_vpg.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -126,6 +127,18 @@ void dcn31_init_hw(struct dc *dc)
 		REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1);
 	}
 
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) {
+		// Power down VPGs
+		for (i = 0; i < dc->res_pool->stream_enc_count; i++)
+			dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
+#if defined(CONFIG_DRM_AMD_DC_DP2_0)
+		for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
+			dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
+#endif
+	}
+#endif
+
 	if (dc->ctx->dc_bios->fw_info_valid) {
 		res_pool->ref_clocks.xtalin_clock_inKhz =
 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 7cb7604a35eb..20b4202bda13 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1312,10 +1312,6 @@ static struct vpg *dcn31_vpg_create(
 			&vpg_shift,
 			&vpg_mask);
 
-	// Will re-enable hw block when we enable stream
-	// Check for enabled stream before powering down?
-	vpg31_powerdown(&vpg31->base);
-
 	return &vpg31->base;
 }
 
-- 
2.25.1

[PATCH 06/27] drm/amd/display: do not compare integers of different widths

[Agustin Gutierrez]

From: Josip Pavic <Josip.Pavic@amd.com>

[Why & How]
Increase width of some variables to avoid comparing integers of
different widths

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fa11a2b094ba..d54592b573e9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3439,7 +3439,7 @@ enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	struct fixed31_32 avg_time_slots_per_mtp;
 	struct fixed31_32 pbn;
 	struct fixed31_32 pbn_per_slot;
-	uint8_t i;
+	int i;
 	enum act_return_status ret;
 	DC_LOGGER_INIT(link->ctx->logger);
 
@@ -3531,7 +3531,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
 	struct dp_mst_stream_allocation_table proposed_table = {0};
 	struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
-	uint8_t i;
+	int i;
 	bool mst_mode = (link->type == dc_connection_mst_branch);
 	DC_LOGGER_INIT(link->ctx->logger);
 
-- 
2.25.1

[PATCH 07/27] drm/amd/display: correct apg audio channel enable golden value

[Agustin Gutierrez]

From: Wenjing Liu <wenjing.liu@amd.com>

Hardware team has recommended to generically hard code this register to
0xFF as part of the effort to eventually remove this control.  However
we set it to 0xF instead.
This causes 4 of audio 8ch to be muted.

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
index 6bd7a0626665..de5e18c2a3ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_apg.c
@@ -129,7 +129,7 @@ static void apg31_se_audio_setup(
 
 	/* When running in "pair mode", pairs of audio channels have their own enable
 	 * this is for really old audio drivers */
-	REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xF);
+	REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, 0xFF);
 	// REG_UPDATE(APG_DBG_GEN_CONTROL, APG_DBG_AUDIO_CHANNEL_ENABLE, channels);
 
 	/* Disable forced mem power off */
-- 
2.25.1

[PATCH 08/27] drm/amd/display: Validate plane rects before use

[Agustin Gutierrez]

From: Aric Cyr <aric.cyr@amd.com>

[Why]
Calculation of scaling ratio can result in a crash due to zero'd src or
dst plane rects.

[How]
Validate that src and dst rects are valid before using for scaling
calculations.

Reviewed-by: Josip Pavic <Josip.Pavic@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 561c10a92bb5..9e83fd54e2ca 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3009,6 +3009,11 @@ enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *pla
 {
 	enum dc_status res = DC_OK;
 
+	/* check if surface has invalid dimensions */
+	if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
+		plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
+		return DC_FAIL_SURFACE_VALIDATE;
+
 	/* TODO For now validates pixel format only */
 	if (dc->res_pool->funcs->validate_plane)
 		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
-- 
2.25.1

[PATCH 09/27] drm/amd/display: Removed power down on boot from DCN31

[Agustin Gutierrez]

From: "Lai, Derek" <Derek.Lai@amd.com>

[Why]
Error message on Linux when booting.

[How]
Removed power down on boot from DCN31 HW init
to match DCN10 HW init.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Derek Lai <derek.lai@amd.com>
---
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 43 -------------------
 1 file changed, 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 968b8825dec7..52947c03be31 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -73,7 +73,6 @@ void dcn31_init_hw(struct dc *dc)
 	struct resource_pool *res_pool = dc->res_pool;
 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 	int i;
-	int edp_num;
 
 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -209,48 +208,6 @@ void dcn31_init_hw(struct dc *dc)
 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
 	}
 
-	/* In headless boot cases, DIG may be turned
-	 * on which causes HW/SW discrepancies.
-	 * To avoid this, power down hardware on boot
-	 * if DIG is turned on and seamless boot not enabled
-	 */
-	if (dc->config.power_down_display_on_boot) {
-		struct dc_link *edp_links[MAX_NUM_EDP];
-		struct dc_link *edp_link;
-		bool power_down = false;
-
-		get_edp_links(dc, edp_links, &edp_num);
-		if (edp_num) {
-			for (i = 0; i < edp_num; i++) {
-				edp_link = edp_links[i];
-				if (edp_link->link_enc->funcs->is_dig_enabled &&
-						edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) &&
-						dc->hwss.edp_backlight_control &&
-						dc->hwss.power_down &&
-						dc->hwss.edp_power_control) {
-					dc->hwss.edp_backlight_control(edp_link, false);
-					dc->hwss.power_down(dc);
-					dc->hwss.edp_power_control(edp_link, false);
-					power_down = true;
-				}
-			}
-		}
-		if (!power_down) {
-			for (i = 0; i < dc->link_count; i++) {
-				struct dc_link *link = dc->links[i];
-
-				if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
-						link->link_enc->funcs->is_dig_enabled &&
-						link->link_enc->funcs->is_dig_enabled(link->link_enc) &&
-						dc->hwss.power_down) {
-					dc->hwss.power_down(dc);
-					break;
-				}
-
-			}
-		}
-	}
-
 	for (i = 0; i < res_pool->audio_count; i++) {
 		struct audio *audio = res_pool->audios[i];
 
-- 
2.25.1

[PATCH 10/27] drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1

[Agustin Gutierrez]

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
The requirement is that image width up to 4096 shall be supported

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 20b4202bda13..a2e40405c97d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -998,7 +998,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.disable_dcc = DCC_ENABLE,
 	.vsr_support = true,
 	.performance_trace = false,
-	.max_downscale_src_width = 3840,/*upto 4K*/
+	.max_downscale_src_width = 4096,/*upto true 4K*/
 	.disable_pplib_wm_range = false,
 	.scl_reset_length10 = true,
 	.sanity_checks = false,
-- 
2.25.1

[PATCH 11/27] drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

[Agustin Gutierrez]

From: Hansen <Hansen.Dsouza@amd.com>

Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 582c500ecb49..152adb597d48 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -26,6 +26,7 @@
 #include "reg_helper.h"
 #include "core_types.h"
 #include "dcn31_dccg.h"
+#include "dal_asic_id.h"
 
 #define TO_DCN_DCCG(dccg)\
 	container_of(dccg, struct dcn_dccg, base)
@@ -80,6 +81,18 @@ static void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl
 	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
 }
 
+static enum phyd32clk_clock_source get_phy_mux_symclk(
+		struct dcn_dccg *dccg_dcn,
+		enum phyd32clk_clock_source src)
+{
+	if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
+		if (src == PHYD32CLKC)
+			src = PHYD32CLKF;
+		if (src == PHYD32CLKD)
+			src = PHYD32CLKG;
+	}
+	return src;
+}
 
 void dccg31_set_dpstreamclk(
 		struct dccg *dccg,
@@ -119,6 +132,8 @@ void dccg31_enable_symclk32_se(
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+	phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk);
+
 	/* select one of the PHYD32CLKs as the source for symclk32_se */
 	switch (hpo_se_inst) {
 	case 0:
@@ -188,6 +203,8 @@ void dccg31_enable_symclk32_le(
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
+	phyd32clk = get_phy_mux_symclk(dccg_dcn, phyd32clk);
+
 	/* select one of the PHYD32CLKs as the source for symclk32_le */
 	switch (hpo_le_inst) {
 	case 0:
-- 
2.25.1

[PATCH 12/27] drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1

[Agustin Gutierrez]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
Prefetch BW calculated is lower than the DML reference because of a
porting error that's excluding cursor and row bandwidth from the
pixel data bandwidth.

[How]
Change the dml_max4 to dml_max3 and include cursor and row bandwidth
in the same calculation as the rest of the pixel data during vactive.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 .../gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index ce55c9caf9a2..d58925cff420 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5398,9 +5398,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
 					v->MaximumReadBandwidthWithPrefetch =
 							v->MaximumReadBandwidthWithPrefetch
-									+ dml_max4(
-											v->VActivePixelBandwidth[i][j][k],
-											v->VActiveCursorBandwidth[i][j][k]
+									+ dml_max3(
+											v->VActivePixelBandwidth[i][j][k]
+													+ v->VActiveCursorBandwidth[i][j][k]
 													+ v->NoOfDPP[i][j][k]
 															* (v->meta_row_bandwidth[i][j][k]
 																	+ v->dpte_row_bandwidth[i][j][k]),
-- 
2.25.1

[PATCH 13/27] drm/amd/display: Add missing PSR state

[Agustin Gutierrez]

From: Mikita Lipski <mikita.lipski@amd.com>

[why]
PSR_STATE2b was introduced on DMCUB side, but not on the driver side,
which caused convert_psr_state helper function to return
PSR_STATE_INVALID. That caused visual lagging during state transition.

[how]
Add PSR_STATE2b to dc_psr_state and convert_psr_state

Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_types.h     | 1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 15c353c389d8..388457ffc0a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -653,6 +653,7 @@ enum dc_psr_state {
 	PSR_STATE1a,
 	PSR_STATE2,
 	PSR_STATE2a,
+	PSR_STATE2b,
 	PSR_STATE3,
 	PSR_STATE3Init,
 	PSR_STATE4,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index aa8403bc4c83..05d96ca80512 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -50,6 +50,8 @@ static enum dc_psr_state convert_psr_state(uint32_t raw_state)
 		state = PSR_STATE2;
 	else if (raw_state == 0x21)
 		state = PSR_STATE2a;
+	else if (raw_state == 0x22)
+		state = PSR_STATE2b;
 	else if (raw_state == 0x30)
 		state = PSR_STATE3;
 	else if (raw_state == 0x31)
-- 
2.25.1

[PATCH 14/27] drm/amd/display: Disable dsc root clock when not being used

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Disable root clock for dsc when not being used.

Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 16 ++++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 72 +++++++++++++++++++
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h | 18 ++++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 17 +++++
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |  9 +++
 5 files changed, 129 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index ede65100a050..f6f2d48a70c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -169,7 +169,17 @@
 	type DTBCLK_DTO_DIV[MAX_PIPES];\
 	type DCCG_AUDIO_DTO_SEL;\
 	type DCCG_AUDIO_DTO0_SOURCE_SEL;\
-	type DENTIST_DISPCLK_CHG_MODE;
+	type DENTIST_DISPCLK_CHG_MODE;\
+	type DSCCLK0_DTO_PHASE;\
+	type DSCCLK0_DTO_MODULO;\
+	type DSCCLK1_DTO_PHASE;\
+	type DSCCLK1_DTO_MODULO;\
+	type DSCCLK2_DTO_PHASE;\
+	type DSCCLK2_DTO_MODULO;\
+	type DSCCLK0_DTO_ENABLE;\
+	type DSCCLK1_DTO_ENABLE;\
+	type DSCCLK2_DTO_ENABLE;
+
 
 struct dccg_shift {
 	DCCG_REG_FIELD_LIST(uint8_t)
@@ -205,6 +215,10 @@ struct dccg_registers {
 	uint32_t SYMCLK32_SE_CNTL;
 	uint32_t SYMCLK32_LE_CNTL;
 	uint32_t DENTIST_DISPCLK_CNTL;
+	uint32_t DSCCLK_DTO_CTRL;
+	uint32_t DSCCLK0_DTO_PARAM;
+	uint32_t DSCCLK1_DTO_PARAM;
+	uint32_t DSCCLK2_DTO_PARAM;
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 152adb597d48..3a325e4afe2f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -247,6 +247,76 @@ void dccg31_disable_symclk32_le(
 	}
 }
 
+static void dccg31_disable_dscclk(struct dccg *dccg, int inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+		return;
+	//DTO must be enabled to generate a 0 Hz clock output
+	switch (inst) {
+	case 0:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK0_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+				DSCCLK0_DTO_PHASE, 0,
+				DSCCLK0_DTO_MODULO, 1);
+		break;
+	case 1:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK1_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+				DSCCLK1_DTO_PHASE, 0,
+				DSCCLK1_DTO_MODULO, 1);
+		break;
+	case 2:
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK2_DTO_ENABLE, 1);
+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+				DSCCLK2_DTO_PHASE, 0,
+				DSCCLK2_DTO_MODULO, 1);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+static void dccg31_enable_dscclk(struct dccg *dccg, int inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc)
+		return;
+	//Disable DTO
+	switch (inst) {
+	case 0:
+		REG_UPDATE_2(DSCCLK0_DTO_PARAM,
+				DSCCLK0_DTO_PHASE, 0,
+				DSCCLK0_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK0_DTO_ENABLE, 0);
+		break;
+	case 1:
+		REG_UPDATE_2(DSCCLK1_DTO_PARAM,
+				DSCCLK1_DTO_PHASE, 0,
+				DSCCLK1_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK1_DTO_ENABLE, 0);
+		break;
+	case 2:
+		REG_UPDATE_2(DSCCLK2_DTO_PARAM,
+				DSCCLK2_DTO_PHASE, 0,
+				DSCCLK2_DTO_MODULO, 0);
+		REG_UPDATE(DSCCLK_DTO_CTRL,
+				DSCCLK2_DTO_ENABLE, 0);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
 void dccg31_set_physymclk(
 		struct dccg *dccg,
 		int phy_inst,
@@ -469,6 +539,8 @@ static const struct dccg_funcs dccg31_funcs = {
 	.set_dtbclk_dto = dccg31_set_dtbclk_dto,
 	.set_audio_dtbclk_dto = dccg31_set_audio_dtbclk_dto,
 	.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
+	.disable_dsc = dccg31_disable_dscclk,
+	.enable_dsc = dccg31_enable_dscclk,
 };
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 1e5aabcb7799..61b457ab790d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -61,7 +61,11 @@
 	SR(DCCG_AUDIO_DTBCLK_DTO_MODULO),\
 	SR(DCCG_AUDIO_DTBCLK_DTO_PHASE),\
 	SR(DCCG_AUDIO_DTO_SOURCE),\
-	SR(DENTIST_DISPCLK_CNTL)
+	SR(DENTIST_DISPCLK_CNTL),\
+	SR(DSCCLK0_DTO_PARAM),\
+	SR(DSCCLK1_DTO_PARAM),\
+	SR(DSCCLK2_DTO_PARAM),\
+	SR(DSCCLK_DTO_CTRL)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -119,7 +123,17 @@
 	DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, DIV, 3, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 	DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
-	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh)
+	DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh), \
+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\
+	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh)
+
 
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 52947c03be31..fee385e37c9b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -270,6 +270,12 @@ void dcn31_dsc_pg_control(
 	if (hws->ctx->dc->debug.disable_dsc_power_gate)
 		return;
 
+	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc &&
+		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc &&
+		power_on)
+		hws->ctx->dc->res_pool->dccg->funcs->enable_dsc(
+			hws->ctx->dc->res_pool->dccg, dsc_inst);
+
 	REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 	if (org_ip_request_cntl == 0)
 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
@@ -306,6 +312,17 @@ void dcn31_dsc_pg_control(
 
 	if (org_ip_request_cntl == 0)
 		REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
+
+	if (hws->ctx->dc->debug.root_clock_optimization.bits.dsc) {
+		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
+			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
+				hws->ctx->dc->res_pool->dccg, dsc_inst);
+
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+		dc_z10_save_init(hws->ctx->dc);
+#endif
+	}
+
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 09237d5819f4..c940fdfda144 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -123,6 +123,15 @@ struct dccg_funcs {
 	void (*set_dispclk_change_mode)(
 			struct dccg *dccg,
 			enum dentist_dispclk_change_mode change_mode);
+
+	void (*disable_dsc)(
+		struct dccg *dccg,
+		int inst);
+
+	void (*enable_dsc)(
+		struct dccg *dccg,
+		int inst);
+
 };
 
 #endif //__DAL_DCCG_H__
-- 
2.25.1

[PATCH 15/27] drm/amd/display: Require immediate flip support for DCN3.1 planes

[Agustin Gutierrez]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
Immediate flip can be enabled dynamically and has higher BW requirements
when validating which voltage mode to use.

If we validate when it's not set then potentially DCFCLK will be too low
and we will underflow.

[How]
DM always requires support so always require it as part of DML input
parameters.

This can't be enabled unconditionally on older ASIC because it blocks
some expected modes so only target DCN3.1 for now.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index a2e40405c97d..c9d3d691f4c6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -1778,6 +1778,13 @@ static int dcn31_populate_dml_pipes_from_context(
 		pipe = &res_ctx->pipe_ctx[i];
 		timing = &pipe->stream->timing;
 
+		/*
+		 * Immediate flip can be set dynamically after enabling the plane.
+		 * We need to require support for immediate flip or underflow can be
+		 * intermittently experienced depending on peak b/w requirements.
+		 */
+		pipes[pipe_cnt].pipe.src.immediate_flip = true;
+
 		pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
 		pipes[pipe_cnt].pipe.src.gpuvm = true;
 		pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
-- 
2.25.1

[PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

[Agustin Gutierrez]

From: Eric Yang <Eric.Yang2@amd.com>

[Why]
Z9 latency is higher than when we originally tuned the watermark
parameters, causing underflow. Increasing the value until the latency
issues is resolved.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index c9d3d691f4c6..12ebd9f8912f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 	.num_states = 5,
 	.sr_exit_time_us = 9.0,
 	.sr_enter_plus_exit_time_us = 11.0,
-	.sr_exit_z8_time_us = 402.0,
-	.sr_enter_plus_exit_z8_time_us = 520.0,
+	.sr_exit_z8_time_us = 442.0,
+	.sr_enter_plus_exit_z8_time_us = 560.0,
 	.writeback_latency_us = 12.0,
 	.dram_channel_width_bytes = 4,
 	.round_trip_ping_latency_dcfclk_cycles = 106,
-- 
2.25.1

Re: [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

[Mike Lothian]

This patch seems to change z8 - not that I know what z8 or z9 are

On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez
<agustin.gutierrez@amd.com> wrote:
>
> From: Eric Yang <Eric.Yang2@amd.com>
>
> [Why]
> Z9 latency is higher than when we originally tuned the watermark
> parameters, causing underflow. Increasing the value until the latency
> issues is resolved.
>
> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
> Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> index c9d3d691f4c6..12ebd9f8912f 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
> @@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
>         .num_states = 5,
>         .sr_exit_time_us = 9.0,
>         .sr_enter_plus_exit_time_us = 11.0,
> -       .sr_exit_z8_time_us = 402.0,
> -       .sr_enter_plus_exit_z8_time_us = 520.0,
> +       .sr_exit_z8_time_us = 442.0,
> +       .sr_enter_plus_exit_z8_time_us = 560.0,
>         .writeback_latency_us = 12.0,
>         .dram_channel_width_bytes = 4,
>         .round_trip_ping_latency_dcfclk_cycles = 106,
> --
> 2.25.1
>

Re: [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

[Kazlauskas, Nicholas]

On 2021-10-15 7:53 p.m., Mike Lothian wrote:
> This patch seems to change z8 - not that I know what z8 or z9 are

It's a little misleading but the patch and terminology is correct.

Z9 is the usecase for these watermarks even if the calculation is shared 
with Z8/Z9.

Regards,
Nicholas Kazlauskas

> 
> On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez
> <agustin.gutierrez@amd.com> wrote:
>>
>> From: Eric Yang <Eric.Yang2@amd.com>
>>
>> [Why]
>> Z9 latency is higher than when we originally tuned the watermark
>> parameters, causing underflow. Increasing the value until the latency
>> issues is resolved.
>>
>> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
>> Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>> index c9d3d691f4c6..12ebd9f8912f 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>> @@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
>>          .num_states = 5,
>>          .sr_exit_time_us = 9.0,
>>          .sr_enter_plus_exit_time_us = 11.0,
>> -       .sr_exit_z8_time_us = 402.0,
>> -       .sr_enter_plus_exit_z8_time_us = 520.0,
>> +       .sr_exit_z8_time_us = 442.0,
>> +       .sr_enter_plus_exit_z8_time_us = 560.0,
>>          .writeback_latency_us = 12.0,
>>          .dram_channel_width_bytes = 4,
>>          .round_trip_ping_latency_dcfclk_cycles = 106,
>> --
>> 2.25.1
>>

Re: [PATCH 16/27] drm/amd/display: increase Z9 latency to workaround underflow in Z9

[Paul Menzel]

Dear Nicholas, dear Eric, dear Augustin,


Am 18.10.21 um 19:14 schrieb Kazlauskas, Nicholas:
> On 2021-10-15 7:53 p.m., Mike Lothian wrote:
>> This patch seems to change z8 - not that I know what z8 or z9 are
> 
> It's a little misleading but the patch and terminology is correct.
> 
> Z9 is the usecase for these watermarks even if the calculation is shared 
> with Z8/Z9.

It’d be great to have that in the commit message.


Kind regards,

Paul

>> On Fri, 15 Oct 2021 at 19:44, Agustin Gutierrez wrote:
>>>
>>> From: Eric Yang <Eric.Yang2@amd.com>
>>>
>>> [Why]
>>> Z9 latency is higher than when we originally tuned the watermark
>>> parameters, causing underflow. Increasing the value until the latency
>>> issues is resolved.
>>>
>>> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
>>> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
>>> Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c 
>>> b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>>> index c9d3d691f4c6..12ebd9f8912f 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
>>> @@ -222,8 +222,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
>>>          .num_states = 5,
>>>          .sr_exit_time_us = 9.0,
>>>          .sr_enter_plus_exit_time_us = 11.0,
>>> -       .sr_exit_z8_time_us = 402.0,
>>> -       .sr_enter_plus_exit_z8_time_us = 520.0,
>>> +       .sr_exit_z8_time_us = 442.0,
>>> +       .sr_enter_plus_exit_z8_time_us = 560.0,
>>>          .writeback_latency_us = 12.0,
>>>          .dram_channel_width_bytes = 4,
>>>          .round_trip_ping_latency_dcfclk_cycles = 106,
>>> -- 
>>> 2.25.1
>>>
> 

[PATCH 17/27] drm/amd/display: Increase watermark latencies for DCN3.1

[Agustin Gutierrez]

From: Nikola Cornij <nikola.cornij@amd.com>

[why]
The original latencies were causing underflow in some modes

[how]
Replace with the up-to-date watermark values based on new measurments

Reviewed-by: Ahmad Othman <ahmad.othman@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
---
 .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 3fae1f1f028d..0088dff441da 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -371,32 +371,32 @@ static struct wm_table lpddr5_wm_table = {
 			.wm_inst = WM_A,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 5.32,
-			.sr_enter_plus_exit_time_us = 6.38,
+			.sr_exit_time_us = 11.5,
+			.sr_enter_plus_exit_time_us = 14.5,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_B,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 9.82,
-			.sr_enter_plus_exit_time_us = 11.196,
+			.sr_exit_time_us = 11.5,
+			.sr_enter_plus_exit_time_us = 14.5,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_C,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 9.89,
-			.sr_enter_plus_exit_time_us = 11.24,
+			.sr_exit_time_us = 11.5,
+			.sr_enter_plus_exit_time_us = 14.5,
 			.valid = true,
 		},
 		{
 			.wm_inst = WM_D,
 			.wm_type = WM_TYPE_PSTATE_CHG,
 			.pstate_latency_us = 11.65333,
-			.sr_exit_time_us = 9.748,
-			.sr_enter_plus_exit_time_us = 11.102,
+			.sr_exit_time_us = 11.5,
+			.sr_enter_plus_exit_time_us = 14.5,
 			.valid = true,
 		},
 	}
-- 
2.25.1

Re: [PATCH 17/27] drm/amd/display: Increase watermark latencies for DCN3.1

[Paul Menzel]

Dear Nikola, dear Augustin,


Am 15.10.21 um 20:43 schrieb Agustin Gutierrez:
> From: Nikola Cornij <nikola.cornij@amd.com>
> 
> [why]
> The original latencies were causing underflow in some modes

Which modes exactly? On what hardware? How can it be reproduced?

> [how]
> Replace with the up-to-date watermark values based on new measurments

measurements

How can these measurements be done?


Kind regards,

Paul


> Reviewed-by: Ahmad Othman <ahmad.othman@amd.com>
> Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
> Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
> ---
>   .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c | 16 ++++++++--------
>   1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
> index 3fae1f1f028d..0088dff441da 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
> @@ -371,32 +371,32 @@ static struct wm_table lpddr5_wm_table = {
>   			.wm_inst = WM_A,
>   			.wm_type = WM_TYPE_PSTATE_CHG,
>   			.pstate_latency_us = 11.65333,
> -			.sr_exit_time_us = 5.32,
> -			.sr_enter_plus_exit_time_us = 6.38,
> +			.sr_exit_time_us = 11.5,
> +			.sr_enter_plus_exit_time_us = 14.5,
>   			.valid = true,
>   		},
>   		{
>   			.wm_inst = WM_B,
>   			.wm_type = WM_TYPE_PSTATE_CHG,
>   			.pstate_latency_us = 11.65333,
> -			.sr_exit_time_us = 9.82,
> -			.sr_enter_plus_exit_time_us = 11.196,
> +			.sr_exit_time_us = 11.5,
> +			.sr_enter_plus_exit_time_us = 14.5,
>   			.valid = true,
>   		},
>   		{
>   			.wm_inst = WM_C,
>   			.wm_type = WM_TYPE_PSTATE_CHG,
>   			.pstate_latency_us = 11.65333,
> -			.sr_exit_time_us = 9.89,
> -			.sr_enter_plus_exit_time_us = 11.24,
> +			.sr_exit_time_us = 11.5,
> +			.sr_enter_plus_exit_time_us = 14.5,
>   			.valid = true,
>   		},
>   		{
>   			.wm_inst = WM_D,
>   			.wm_type = WM_TYPE_PSTATE_CHG,
>   			.pstate_latency_us = 11.65333,
> -			.sr_exit_time_us = 9.748,
> -			.sr_enter_plus_exit_time_us = 11.102,
> +			.sr_exit_time_us = 11.5,
> +			.sr_enter_plus_exit_time_us = 14.5,
>   			.valid = true,
>   		},
>   	}
> 

[PATCH 18/27] drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.

Reviewed-by: Ariel Bernstein <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  15 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 107 ++++++++++++++++--
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  19 +++-
 3 files changed, 130 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index f6f2d48a70c1..4098669a0c1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -178,7 +178,16 @@
 	type DSCCLK2_DTO_MODULO;\
 	type DSCCLK0_DTO_ENABLE;\
 	type DSCCLK1_DTO_ENABLE;\
-	type DSCCLK2_DTO_ENABLE;
+	type DSCCLK2_DTO_ENABLE;\
+	type SYMCLK32_ROOT_SE0_GATE_DISABLE;\
+	type SYMCLK32_ROOT_SE1_GATE_DISABLE;\
+	type SYMCLK32_ROOT_SE2_GATE_DISABLE;\
+	type SYMCLK32_ROOT_SE3_GATE_DISABLE;\
+	type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
+	type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
+	type DPSTREAMCLK_ROOT_GATE_DISABLE;\
+	type DPSTREAMCLK_GATE_DISABLE;
+
 
 
 struct dccg_shift {
@@ -219,6 +228,10 @@ struct dccg_registers {
 	uint32_t DSCCLK0_DTO_PARAM;
 	uint32_t DSCCLK1_DTO_PARAM;
 	uint32_t DSCCLK2_DTO_PARAM;
+	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
+	uint32_t DPSTREAMCLK_GATE_DISABLE;
+	uint32_t DCCG_GATE_DISABLE_CNTL3;
+
 };
 
 struct dcn_dccg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
index 3a325e4afe2f..815481a3ef54 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c
@@ -94,10 +94,7 @@ static enum phyd32clk_clock_source get_phy_mux_symclk(
 	return src;
 }
 
-void dccg31_set_dpstreamclk(
-		struct dccg *dccg,
-		enum hdmistreamclk_source src,
-		int otg_inst)
+static void dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst)
 {
 	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
 
@@ -105,24 +102,69 @@ void dccg31_set_dpstreamclk(
 	switch (otg_inst) {
 	case 0:
 		REG_UPDATE(DPSTREAMCLK_CNTL,
-				DPSTREAMCLK_PIPE0_EN, (src == REFCLK) ? 0 : 1);
+				DPSTREAMCLK_PIPE0_EN, 1);
 		break;
 	case 1:
 		REG_UPDATE(DPSTREAMCLK_CNTL,
-				DPSTREAMCLK_PIPE1_EN, (src == REFCLK) ? 0 : 1);
+				DPSTREAMCLK_PIPE1_EN, 1);
 		break;
 	case 2:
 		REG_UPDATE(DPSTREAMCLK_CNTL,
-				DPSTREAMCLK_PIPE2_EN, (src == REFCLK) ? 0 : 1);
+				DPSTREAMCLK_PIPE2_EN, 1);
 		break;
 	case 3:
 		REG_UPDATE(DPSTREAMCLK_CNTL,
-				DPSTREAMCLK_PIPE3_EN, (src == REFCLK) ? 0 : 1);
+				DPSTREAMCLK_PIPE3_EN, 1);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
 		return;
 	}
+	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+			DPSTREAMCLK_ROOT_GATE_DISABLE, 1);
+}
+
+static void dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst)
+{
+	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
+		REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+				DPSTREAMCLK_ROOT_GATE_DISABLE, 0);
+
+	switch (otg_inst) {
+	case 0:
+		REG_UPDATE(DPSTREAMCLK_CNTL,
+				DPSTREAMCLK_PIPE0_EN, 0);
+		break;
+	case 1:
+		REG_UPDATE(DPSTREAMCLK_CNTL,
+				DPSTREAMCLK_PIPE1_EN, 0);
+		break;
+	case 2:
+		REG_UPDATE(DPSTREAMCLK_CNTL,
+				DPSTREAMCLK_PIPE2_EN, 0);
+		break;
+	case 3:
+		REG_UPDATE(DPSTREAMCLK_CNTL,
+				DPSTREAMCLK_PIPE3_EN, 0);
+		break;
+	default:
+		BREAK_TO_DEBUGGER();
+		return;
+	}
+}
+
+void dccg31_set_dpstreamclk(
+		struct dccg *dccg,
+		enum hdmistreamclk_source src,
+		int otg_inst)
+{
+	if (src == REFCLK)
+		dccg31_disable_dpstreamclk(dccg, otg_inst);
+	else
+		dccg31_enable_dpstreamclk(dccg, otg_inst);
 }
 
 void dccg31_enable_symclk32_se(
@@ -137,21 +179,33 @@ void dccg31_enable_symclk32_se(
 	/* select one of the PHYD32CLKs as the source for symclk32_se */
 	switch (hpo_se_inst) {
 	case 0:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE0_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE0_SRC_SEL, phyd32clk,
 				SYMCLK32_SE0_EN, 1);
 		break;
 	case 1:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE1_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE1_SRC_SEL, phyd32clk,
 				SYMCLK32_SE1_EN, 1);
 		break;
 	case 2:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE2_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE2_SRC_SEL, phyd32clk,
 				SYMCLK32_SE2_EN, 1);
 		break;
 	case 3:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE3_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE3_SRC_SEL, phyd32clk,
 				SYMCLK32_SE3_EN, 1);
@@ -174,21 +228,33 @@ void dccg31_disable_symclk32_se(
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE0_SRC_SEL, 0,
 				SYMCLK32_SE0_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE0_GATE_DISABLE, 0);
 		break;
 	case 1:
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE1_SRC_SEL, 0,
 				SYMCLK32_SE1_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE1_GATE_DISABLE, 0);
 		break;
 	case 2:
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE2_SRC_SEL, 0,
 				SYMCLK32_SE2_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE2_GATE_DISABLE, 0);
 		break;
 	case 3:
 		REG_UPDATE_2(SYMCLK32_SE_CNTL,
 				SYMCLK32_SE3_SRC_SEL, 0,
 				SYMCLK32_SE3_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_SE3_GATE_DISABLE, 0);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
@@ -208,11 +274,17 @@ void dccg31_enable_symclk32_le(
 	/* select one of the PHYD32CLKs as the source for symclk32_le */
 	switch (hpo_le_inst) {
 	case 0:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_LE0_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_LE_CNTL,
 				SYMCLK32_LE0_SRC_SEL, phyd32clk,
 				SYMCLK32_LE0_EN, 1);
 		break;
 	case 1:
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_LE1_GATE_DISABLE, 1);
 		REG_UPDATE_2(SYMCLK32_LE_CNTL,
 				SYMCLK32_LE1_SRC_SEL, phyd32clk,
 				SYMCLK32_LE1_EN, 1);
@@ -235,11 +307,17 @@ void dccg31_disable_symclk32_le(
 		REG_UPDATE_2(SYMCLK32_LE_CNTL,
 				SYMCLK32_LE0_SRC_SEL, 0,
 				SYMCLK32_LE0_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_LE0_GATE_DISABLE, 0);
 		break;
 	case 1:
 		REG_UPDATE_2(SYMCLK32_LE_CNTL,
 				SYMCLK32_LE1_SRC_SEL, 0,
 				SYMCLK32_LE1_EN, 0);
+		if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le)
+			REG_UPDATE(DCCG_GATE_DISABLE_CNTL3,
+					SYMCLK32_ROOT_LE1_GATE_DISABLE, 0);
 		break;
 	default:
 		BREAK_TO_DEBUGGER();
@@ -524,6 +602,19 @@ void dccg31_init(struct dccg *dccg)
 	dccg31_disable_symclk32_se(dccg, 1);
 	dccg31_disable_symclk32_se(dccg, 2);
 	dccg31_disable_symclk32_se(dccg, 3);
+
+	if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) {
+		dccg31_disable_symclk32_le(dccg, 0);
+		dccg31_disable_symclk32_le(dccg, 1);
+	}
+
+	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) {
+		dccg31_disable_dpstreamclk(dccg, 0);
+		dccg31_disable_dpstreamclk(dccg, 1);
+		dccg31_disable_dpstreamclk(dccg, 2);
+		dccg31_disable_dpstreamclk(dccg, 3);
+	}
+
 }
 
 static const struct dccg_funcs dccg31_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 61b457ab790d..602bf461298b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -65,7 +65,8 @@
 	SR(DSCCLK0_DTO_PARAM),\
 	SR(DSCCLK1_DTO_PARAM),\
 	SR(DSCCLK2_DTO_PARAM),\
-	SR(DSCCLK_DTO_CTRL)
+	SR(DSCCLK_DTO_CTRL),\
+	SR(DCCG_GATE_DISABLE_CNTL3)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -132,7 +133,16 @@
 	DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\
 	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_DTO_ENABLE, mask_sh),\
 	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_DTO_ENABLE, mask_sh),\
-	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh)
+	DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_DTO_ENABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_ROOT_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, DPSTREAMCLK_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh)
+
 
 
 
@@ -144,6 +154,11 @@ struct dccg *dccg31_create(
 
 void dccg31_init(struct dccg *dccg);
 
+void dccg31_set_dpstreamclk(
+		struct dccg *dccg,
+		enum hdmistreamclk_source src,
+		int otg_inst);
+
 void dccg31_enable_symclk32_se(
 		struct dccg *dccg,
 		int hpo_se_inst,
-- 
2.25.1

[PATCH 19/27] drm/amd/display: Removed z10 save after dsc disable

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Z10 save is done during PSR and bootup.
DSC disable does not need to save for Z10.

Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index fee385e37c9b..65f66687af4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -317,10 +317,6 @@ void dcn31_dsc_pg_control(
 		if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on)
 			hws->ctx->dc->res_pool->dccg->funcs->disable_dsc(
 				hws->ctx->dc->res_pool->dccg, dsc_inst);
-
-#if defined(CONFIG_DRM_AMD_DC_DCN)
-		dc_z10_save_init(hws->ctx->dc);
-#endif
 	}
 
 }
-- 
2.25.1

[PATCH 20/27] drm/amd/display: Moved dccg init to after bios golden init

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why]
bios_golden_init will override dccg_init during init_hw.

[How]
Move dccg_init to after bios_golden_init.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 65f66687af4c..186d08aec812 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -77,10 +77,6 @@ void dcn31_init_hw(struct dc *dc)
 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 
-	// Initialize the dccg
-	if (res_pool->dccg->funcs->dccg_init)
-		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
-
 	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 
 		REG_WRITE(REFCLK_CNTL, 0);
@@ -107,6 +103,9 @@ void dcn31_init_hw(struct dc *dc)
 		hws->funcs.bios_golden_init(dc);
 		hws->funcs.disable_vga(dc->hwseq);
 	}
+	// Initialize the dccg
+	if (res_pool->dccg->funcs->dccg_init)
+		res_pool->dccg->funcs->dccg_init(res_pool->dccg);
 
 	if (dc->debug.enable_mem_low_power.bits.dmcu) {
 		// Force ERAM to shutdown if DMCU is not enabled
-- 
2.25.1

[PATCH 21/27] drm/amd/display: Disable hdmistream and hdmichar clocks

[Agustin Gutierrez]

From: Jake Wang <haonan.wang2@amd.com>

[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.

Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h        | 9 +++++++--
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h        | 9 +++++----
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h  | 2 ++
 .../gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h | 8 ++++++++
 4 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 4098669a0c1f..f98aba308028 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -186,8 +186,11 @@
 	type SYMCLK32_ROOT_LE0_GATE_DISABLE;\
 	type SYMCLK32_ROOT_LE1_GATE_DISABLE;\
 	type DPSTREAMCLK_ROOT_GATE_DISABLE;\
-	type DPSTREAMCLK_GATE_DISABLE;
-
+	type DPSTREAMCLK_GATE_DISABLE;\
+	type HDMISTREAMCLK0_DTO_PHASE;\
+	type HDMISTREAMCLK0_DTO_MODULO;\
+	type HDMICHARCLK0_GATE_DISABLE;\
+	type HDMICHARCLK0_ROOT_GATE_DISABLE;
 
 
 struct dccg_shift {
@@ -231,6 +234,8 @@ struct dccg_registers {
 	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
 	uint32_t DPSTREAMCLK_GATE_DISABLE;
 	uint32_t DCCG_GATE_DISABLE_CNTL3;
+	uint32_t HDMISTREAMCLK0_DTO_PARAM;
+	uint32_t DCCG_GATE_DISABLE_CNTL4;
 
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
index 602bf461298b..a013a32bbaf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h
@@ -66,7 +66,8 @@
 	SR(DSCCLK1_DTO_PARAM),\
 	SR(DSCCLK2_DTO_PARAM),\
 	SR(DSCCLK_DTO_CTRL),\
-	SR(DCCG_GATE_DISABLE_CNTL3)
+	SR(DCCG_GATE_DISABLE_CNTL3),\
+	SR(HDMISTREAMCLK0_DTO_PARAM)
 
 
 #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -141,9 +142,9 @@
 	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\
 	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\
 	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\
-	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh)
-
-
+	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\
+	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)
 
 
 struct dccg *dccg31_create(
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
index 312c50ea30f3..f268d33c4744 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h
@@ -436,6 +436,8 @@
 #define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2
 #define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a
 #define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2
+#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b
+#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2
 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061
 #define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2
 #define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
index a9d553ef26c0..1f21f313bd1d 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h
@@ -1438,6 +1438,14 @@
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L
 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L
+//HDMISTREAMCLK0_DTO_PARAM
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L
+#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L
+
 //DCCG_AUDIO_DTBCLK_DTO_PHASE
 #define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0
 #define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL
-- 
2.25.1

[PATCH 22/27] drm/amd/display: Change initializer to single brace

[Agustin Gutierrez]

From: Anthony Koo <Anthony.Koo@amd.com>

Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  7 ++---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 30 +++++++++----------
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  8 ++---
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  4 +--
 5 files changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index d54592b573e9..6db611f9f554 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -674,13 +674,13 @@ static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 
 static void read_current_link_settings_on_detect(struct dc_link *link)
 {
-	union lane_count_set lane_count_set = { {0} };
+	union lane_count_set lane_count_set = {0};
 	uint8_t link_bw_set;
 	uint8_t link_rate_set;
 	uint32_t read_dpcd_retry_cnt = 10;
 	enum dc_status status = DC_ERROR_UNEXPECTED;
 	int i;
-	union max_down_spread max_down_spread = { {0} };
+	union max_down_spread max_down_spread = {0};
 
 	// Read DPCD 00101h to find out the number of lanes currently set
 	for (i = 0; i < read_dpcd_retry_cnt; i++) {
@@ -3279,8 +3279,7 @@ static void update_mst_stream_alloc_table(
 	struct stream_encoder *stream_enc,
 	const struct dp_mst_stream_allocation_table *proposed_table)
 {
-	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
-			{ 0 } };
+	struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 0 };
 	struct link_mst_stream_allocation *dc_alloc;
 
 	int i;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index b0f1cd7268c8..471a67a64299 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -763,7 +763,7 @@ void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
 	dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
 			sizeof(offset), &tmds_config, sizeof(tmds_config));
 	if (tmds_config & 0x1) {
-		union hdmi_scdc_status_flags_data status_data = { {0} };
+		union hdmi_scdc_status_flags_data status_data = {0};
 		uint8_t scramble_status = 0;
 
 		offset = HDMI_SCDC_SCRAMBLER_STATUS;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8e0b40c7a1ee..296b0defcd1c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -259,7 +259,7 @@ static void dpcd_set_training_pattern(
 	struct dc_link *link,
 	enum dc_dp_training_pattern training_pattern)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 
 	dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
 			dc_dp_training_pattern_to_dpcd_training_pattern(
@@ -401,8 +401,8 @@ enum dc_status dpcd_set_link_settings(
 	uint8_t rate;
 	enum dc_status status;
 
-	union down_spread_ctrl downspread = { {0} };
-	union lane_count_set lane_count_set = { {0} };
+	union down_spread_ctrl downspread = {0};
+	union lane_count_set lane_count_set = {0};
 
 	downspread.raw = (uint8_t)
 	(lt_settings->link_settings.link_spread);
@@ -520,7 +520,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
 	uint32_t dpcd_base_lt_offset;
 
 	uint8_t dpcd_lt_buffer[5] = {0};
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = { 0 };
 	uint32_t size_in_bytes;
 	bool edp_workaround = false; /* TODO link_prop.INTERNAL */
 	dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;
@@ -1266,8 +1266,8 @@ static enum link_training_result perform_channel_equalization_sequence(
 	uint32_t retries_ch_eq;
 	uint32_t wait_time_microsec;
 	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 
 	/* Note: also check that TPS4 is a supported feature*/
 
@@ -1487,7 +1487,7 @@ static inline enum link_training_result dp_transition_to_video_idle(
 	struct link_training_settings *lt_settings,
 	enum link_training_result status)
 {
-	union lane_count_set lane_count_set = { {0} };
+	union lane_count_set lane_count_set = {0};
 
 	/* 4. mainlink output idle pattern*/
 	dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
@@ -1800,7 +1800,7 @@ static enum dc_status configure_lttpr_mode_non_transparent(
 
 static void repeater_training_done(struct dc_link *link, uint32_t offset)
 {
-	union dpcd_training_pattern dpcd_pattern = { {0} };
+	union dpcd_training_pattern dpcd_pattern = {0};
 
 	const uint32_t dpcd_base_lt_offset =
 			DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
@@ -2078,8 +2078,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 	uint32_t aux_rd_interval = 0;
 	uint32_t wait_time = 0;
 	struct link_training_settings req_settings;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 	enum link_training_result status = LINK_TRAINING_SUCCESS;
 
 	/* Transmit 128b/132b_TPS1 over Main-Link and Set TRAINING_PATTERN_SET to 01h */
@@ -2149,8 +2149,8 @@ static enum link_training_result dp_perform_128b_132b_cds_done_sequence(
 	/* Assumption: assume hardware has transmitted eq pattern */
 	enum link_training_result status = LINK_TRAINING_SUCCESS;
 	struct link_training_settings req_settings;
-	union lane_align_status_updated dpcd_lane_status_updated = { {0} };
-	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };
+	union lane_align_status_updated dpcd_lane_status_updated = {0};
+	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = {0};
 	uint32_t wait_time = 0;
 
 	/* initiate CDS done sequence */
@@ -4065,8 +4065,8 @@ void dc_link_dp_handle_link_loss(struct dc_link *link)
 bool dc_link_handle_hpd_rx_irq(struct dc_link *link, union hpd_irq_data *out_hpd_irq_dpcd_data, bool *out_link_loss,
 							bool defer_handling, bool *has_left_work)
 {
-	union hpd_irq_data hpd_irq_dpcd_data = { { { {0} } } };
-	union device_service_irq device_service_clear = { { 0 } };
+	union hpd_irq_data hpd_irq_dpcd_data = {0};
+	union device_service_irq device_service_clear = {0};
 	enum dc_status result;
 	bool status = false;
 
@@ -5939,7 +5939,7 @@ bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timin
 	uint8_t link_bw_set;
 	uint8_t link_rate_set;
 	uint32_t req_bw;
-	union lane_count_set lane_count_set = { {0} };
+	union lane_count_set lane_count_set = {0};
 
 	ASSERT(link || crtc_timing); // invalid input
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index bc3ec05bf34b..aa2d430f2a1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2304,8 +2304,8 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
 {
 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
-	struct vm_system_aperture_param apt = { {{ 0 } } };
-	struct vm_context0_param vm0 = { { { 0 } } };
+	struct vm_system_aperture_param apt = {0};
+	struct vm_context0_param vm0 = {0};
 
 	mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
 	mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
@@ -2478,7 +2478,7 @@ void dcn10_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
 void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
-	struct mpcc_blnd_cfg blnd_cfg = {{0}};
+	struct mpcc_blnd_cfg blnd_cfg = {0};
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
 	int mpcc_id;
 	struct mpcc *new_mpcc;
@@ -3635,7 +3635,7 @@ void dcn10_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
 void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
 		struct dc_link_settings *link_settings)
 {
-	struct encoder_unblank_param params = { { 0 } };
+	struct encoder_unblank_param params = {0};
 	struct dc_stream_state *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->link;
 	struct dce_hwseq *hws = link->dc->hwseq;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index fc83744149d9..cfee456c6c9a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -2123,7 +2123,7 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
 		struct dc_link_settings *link_settings)
 {
-	struct encoder_unblank_param params = { { 0 } };
+	struct encoder_unblank_param params = {0};
 	struct dc_stream_state *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->link;
 	struct dce_hwseq *hws = link->dc->hwseq;
@@ -2298,7 +2298,7 @@ void dcn20_update_visual_confirm_color(struct dc *dc, struct pipe_ctx *pipe_ctx,
 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
 {
 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
-	struct mpcc_blnd_cfg blnd_cfg = { {0} };
+	struct mpcc_blnd_cfg blnd_cfg = {0};
 	bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
 	int mpcc_id;
 	struct mpcc *new_mpcc;
-- 
2.25.1

[PATCH 23/27] drm/amd/display: 3.2.157

[Agustin Gutierrez]

From: Aric Cyr <aric.cyr@amd.com>

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 254b760ae91f..fc3f0fd1f068 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -47,7 +47,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.156"
+#define DC_VER "3.2.157"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.25.1

[PATCH 24/27] drm/amd/display: Add bios parser support for latest firmware_info

[Agustin Gutierrez]

From: Nevenko Stupar <Nevenko.Stupar@amd.com>

[Why]
V3_4 is latest in use.

[How]
Add bios parser support for firmware_info_v3_4 along
with some relevant fields it is also retrieving from dce_info
and smu_info.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
---
 .../drm/amd/display/dc/bios/bios_parser2.c    | 90 ++++++++++++++++++-
 1 file changed, 89 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index cdb5c027411a..c17732fba039 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -99,6 +99,10 @@ static enum bp_result get_firmware_info_v3_2(
 	struct bios_parser *bp,
 	struct dc_firmware_info *info);
 
+static enum bp_result get_firmware_info_v3_4(
+	struct bios_parser *bp,
+	struct dc_firmware_info *info);
+
 static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
 		struct atom_display_object_path_v2 *object);
 
@@ -1426,8 +1430,10 @@ static enum bp_result bios_parser_get_firmware_info(
 				break;
 			case 2:
 			case 3:
-			case 4:
 				result = get_firmware_info_v3_2(bp, info);
+                                break;
+			case 4:
+				result = get_firmware_info_v3_4(bp, info);
 				break;
 			default:
 				break;
@@ -1575,6 +1581,88 @@ static enum bp_result get_firmware_info_v3_2(
 	return BP_RESULT_OK;
 }
 
+static enum bp_result get_firmware_info_v3_4(
+	struct bios_parser *bp,
+	struct dc_firmware_info *info)
+{
+	struct atom_firmware_info_v3_4 *firmware_info;
+	struct atom_common_table_header *header;
+	struct atom_data_revision revision;
+	struct atom_display_controller_info_v4_1 *dce_info_v4_1 = NULL;
+	struct atom_display_controller_info_v4_4 *dce_info_v4_4 = NULL;
+	if (!info)
+		return BP_RESULT_BADINPUT;
+
+	firmware_info = GET_IMAGE(struct atom_firmware_info_v3_4,
+			DATA_TABLES(firmwareinfo));
+
+	if (!firmware_info)
+		return BP_RESULT_BADBIOSTABLE;
+
+	memset(info, 0, sizeof(*info));
+
+	header = GET_IMAGE(struct atom_common_table_header,
+					DATA_TABLES(dce_info));
+
+	get_atom_data_table_revision(header, &revision);
+
+	switch (revision.major) {
+	case 4:
+		switch (revision.minor) {
+		case 4:
+			dce_info_v4_4 = GET_IMAGE(struct atom_display_controller_info_v4_4,
+							DATA_TABLES(dce_info));
+
+			if (!dce_info_v4_4)
+				return BP_RESULT_BADBIOSTABLE;
+
+			/* 100MHz expected */
+			info->pll_info.crystal_frequency = dce_info_v4_4->dce_refclk_10khz * 10;
+			info->dp_phy_ref_clk             = dce_info_v4_4->dpphy_refclk_10khz * 10;
+			/* 50MHz expected */
+			info->i2c_engine_ref_clk         = dce_info_v4_4->i2c_engine_refclk_10khz * 10;
+
+			/* Get SMU Display PLL VCO Frequency in KHz*/
+			info->smu_gpu_pll_output_freq =	dce_info_v4_4->dispclk_pll_vco_freq * 10;
+			break;
+
+		default:
+			/* should not come here, keep as backup, as was before */
+			dce_info_v4_1 = GET_IMAGE(struct atom_display_controller_info_v4_1,
+							DATA_TABLES(dce_info));
+
+			if (!dce_info_v4_1)
+				return BP_RESULT_BADBIOSTABLE;
+
+			info->pll_info.crystal_frequency = dce_info_v4_1->dce_refclk_10khz * 10;
+			info->dp_phy_ref_clk             = dce_info_v4_1->dpphy_refclk_10khz * 10;
+			info->i2c_engine_ref_clk         = dce_info_v4_1->i2c_engine_refclk_10khz * 10;
+			break;
+		}
+		break;
+
+	default:
+		ASSERT(0);
+		break;
+	}
+
+	header = GET_IMAGE(struct atom_common_table_header,
+					DATA_TABLES(smu_info));
+	get_atom_data_table_revision(header, &revision);
+
+	 // We need to convert from 10KHz units into KHz units.
+	info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
+
+	if (firmware_info->board_i2c_feature_id == 0x2) {
+		info->oem_i2c_present = true;
+		info->oem_i2c_obj_id = firmware_info->board_i2c_feature_gpio_id;
+	} else {
+		info->oem_i2c_present = false;
+	}
+
+	return BP_RESULT_OK;
+}
+
 static enum bp_result bios_parser_get_encoder_cap_info(
 	struct dc_bios *dcb,
 	struct graphics_object_id object_id,
-- 
2.25.1

[PATCH 25/27] drm/amd/display: [FW Promotion] Release 0.0.88

[Agustin Gutierrez]

From: Anthony Koo <Anthony.Koo@amd.com>

Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b37a485fcba5..bfe052afc518 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -47,10 +47,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0xf0c64c97
+#define DMUB_FW_VERSION_GIT_HASH 0xd146258f
 #define DMUB_FW_VERSION_MAJOR 0
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 87
+#define DMUB_FW_VERSION_REVISION 88
 #define DMUB_FW_VERSION_TEST 0
 #define DMUB_FW_VERSION_VBIOS 0
 #define DMUB_FW_VERSION_HOTFIX 0
-- 
2.25.1

[PATCH 26/27] Revert "drm/amd/display: Fix error in dmesg at boot"

[Agustin Gutierrez]

This reverts commit 4e605d4b6a510f751b22df4d13829aefb8a0ccec.
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 6db611f9f554..c01309a1cbf2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1999,7 +1999,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
 
 		if ((signal == SIGNAL_TYPE_EDP) ||
 			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
-			if (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL) {
+			if (hw_init && signal != SIGNAL_TYPE_EDP) {
 				/* DP 2.0 spec requires that we read LTTPR caps first */
 				dp_retrieve_lttpr_cap(dc->links[i]);
 				/* if any of the displays are lit up turn them off */
@@ -2025,7 +2025,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
 				}
 
 				if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
-					(hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL))
+					(hw_init && signal != SIGNAL_TYPE_EDP))
 					dp_receiver_power_ctrl(dc->links[i], false);
 			}
 		}
-- 
2.25.1

Re: [PATCH 26/27] Revert "drm/amd/display: Fix error in dmesg at boot"

[Paul Menzel]

Dear Augustin,


Am 15.10.21 um 20:43 schrieb Agustin Gutierrez:
> This reverts commit 4e605d4b6a510f751b22df4d13829aefb8a0ccec.

Why?

(Do revert commits need a Signed-off-by line?)


Kind regards,

Paul


> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 6db611f9f554..c01309a1cbf2 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1999,7 +1999,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
>   
>   		if ((signal == SIGNAL_TYPE_EDP) ||
>   			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
> -			if (hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL) {
> +			if (hw_init && signal != SIGNAL_TYPE_EDP) {
>   				/* DP 2.0 spec requires that we read LTTPR caps first */
>   				dp_retrieve_lttpr_cap(dc->links[i]);
>   				/* if any of the displays are lit up turn them off */
> @@ -2025,7 +2025,7 @@ void blank_all_dp_displays(struct dc *dc, bool hw_init)
>   				}
>   
>   				if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
> -					(hw_init && signal != SIGNAL_TYPE_EDP && dc->links[i]->priv != NULL))
> +					(hw_init && signal != SIGNAL_TYPE_EDP))
>   					dp_receiver_power_ctrl(dc->links[i], false);
>   			}
>   		}
> 

[PATCH 27/27] Revert "drm/amd/display: Add helper for blanking all dp displays"

[Agustin Gutierrez]

This reverts commit 50ac5b14c74c5706796cb6378f25a2121dba5b2d.

This patch introduced a couple of dmesg warnings, this is not a valid
approach anymore. For this reason, we are reverting this patch, and we
need to revert the workaround patch.

Cc: Hanghong Ma <hanghong.ma@amd.com>
Cc: Mark Broadworth <mark.broadworth@amd.com>
Signed-off-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 -------------------
 drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 -
 .../display/dc/dce110/dce110_hw_sequencer.c   | 24 ++++++++--
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 +++++++++++++++--
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 39 ++++++++++++++--
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 40 +++++++++++++++--
 6 files changed, 131 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c01309a1cbf2..e5d6cbd7ea78 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1988,51 +1988,6 @@ static enum dc_status enable_link_dp_mst(
 	return enable_link_dp(state, pipe_ctx);
 }
 
-void blank_all_dp_displays(struct dc *dc, bool hw_init)
-{
-	unsigned int i, j, fe;
-	uint8_t dpcd_power_state = '\0';
-	enum dc_status status = DC_ERROR_UNEXPECTED;
-
-	for (i = 0; i < dc->link_count; i++) {
-		enum signal_type signal = dc->links[i]->connector_signal;
-
-		if ((signal == SIGNAL_TYPE_EDP) ||
-			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
-			if (hw_init && signal != SIGNAL_TYPE_EDP) {
-				/* DP 2.0 spec requires that we read LTTPR caps first */
-				dp_retrieve_lttpr_cap(dc->links[i]);
-				/* if any of the displays are lit up turn them off */
-				status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
-							&dpcd_power_state, sizeof(dpcd_power_state));
-			}
-
-			if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
-					(!hw_init && dc->links[i]->link_enc &&
-					dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
-				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
-					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
-					if (fe == ENGINE_ID_UNKNOWN)
-						continue;
-
-					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
-						if (fe == dc->res_pool->stream_enc[j]->id) {
-							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
-									dc->res_pool->stream_enc[j]);
-							break;
-						}
-					}
-				}
-
-				if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
-					(hw_init && signal != SIGNAL_TYPE_EDP))
-					dp_receiver_power_ctrl(dc->links[i], false);
-			}
-		}
-	}
-
-}
-
 static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
 		enum engine_id eng_id,
 		struct ext_hdmi_settings *settings)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 69b008bafbbc..a73d64b1fd33 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -277,7 +277,6 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
 		struct psr_context *psr_context);
 
 void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
-void blank_all_dp_displays(struct dc *dc, bool hw_init);
 
 /* Request DC to detect if there is a Panel connected.
  * boot - If this call is during initial boot.
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 8108f9ae2638..af3e68d3e747 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1649,13 +1649,31 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 
 static void power_down_encoders(struct dc *dc)
 {
-	int i;
-
-	blank_all_dp_displays(dc, false);
+	int i, j;
 
 	for (i = 0; i < dc->link_count; i++) {
 		enum signal_type signal = dc->links[i]->connector_signal;
 
+		if ((signal == SIGNAL_TYPE_EDP) ||
+			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
+			if (dc->links[i]->link_enc->funcs->get_dig_frontend &&
+				dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc)) {
+				unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
+									dc->links[i]->link_enc);
+
+				for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+					if (fe == dc->res_pool->stream_enc[j]->id) {
+						dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+									dc->res_pool->stream_enc[j]);
+						break;
+					}
+				}
+			}
+
+			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
+				dp_receiver_power_ctrl(dc->links[i], false);
+		}
+
 		if (signal != SIGNAL_TYPE_EDP)
 			signal = SIGNAL_TYPE_NONE;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index aa2d430f2a1a..44d27579d898 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1366,7 +1366,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 
 void dcn10_init_hw(struct dc *dc)
 {
-	int i;
+	int i, j;
 	struct abm *abm = dc->res_pool->abm;
 	struct dmcu *dmcu = dc->res_pool->dmcu;
 	struct dce_hwseq *hws = dc->hwseq;
@@ -1462,8 +1462,43 @@ void dcn10_init_hw(struct dc *dc)
 		dmub_enable_outbox_notification(dc);
 
 	/* we want to turn off all dp displays before doing detection */
-	if (dc->config.power_down_display_on_boot)
-		blank_all_dp_displays(dc, true);
+	if (dc->config.power_down_display_on_boot) {
+		uint8_t dpcd_power_state = '\0';
+		enum dc_status status = DC_ERROR_UNEXPECTED;
+
+		for (i = 0; i < dc->link_count; i++) {
+			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
+				continue;
+
+			/* DP 2.0 requires that LTTPR Caps be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
+
+			/*
+			 * If any of the displays are lit up turn them off.
+			 * The reason is that some MST hubs cannot be turned off
+			 * completely until we tell them to do so.
+			 * If not turned off, then displays connected to MST hub
+			 * won't light up.
+			 */
+			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+							&dpcd_power_state, sizeof(dpcd_power_state));
+			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
+				/* blank dp stream before power off receiver*/
+				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
+					unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
+
+					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+						if (fe == dc->res_pool->stream_enc[j]->id) {
+							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+										dc->res_pool->stream_enc[j]);
+							break;
+						}
+					}
+				}
+				dp_receiver_power_ctrl(dc->links[i], false);
+			}
+		}
+	}
 
 	/* If taking control over from VBIOS, we may want to optimize our first
 	 * mode set, so we need to skip powering down pipes until we know which
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 2936a334cd64..df2717116604 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -437,7 +437,7 @@ void dcn30_init_hw(struct dc *dc)
 	struct dce_hwseq *hws = dc->hwseq;
 	struct dc_bios *dcb = dc->ctx->dc_bios;
 	struct resource_pool *res_pool = dc->res_pool;
-	int i;
+	int i, j;
 	int edp_num;
 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
 
@@ -534,8 +534,41 @@ void dcn30_init_hw(struct dc *dc)
 			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
 
 	/* we want to turn off all dp displays before doing detection */
-	if (dc->config.power_down_display_on_boot)
-		blank_all_dp_displays(dc, true);
+	if (dc->config.power_down_display_on_boot) {
+		uint8_t dpcd_power_state = '\0';
+		enum dc_status status = DC_ERROR_UNEXPECTED;
+
+		for (i = 0; i < dc->link_count; i++) {
+			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
+				continue;
+			/* DP 2.0 states that LTTPR regs must be read first */
+			dp_retrieve_lttpr_cap(dc->links[i]);
+
+			/* if any of the displays are lit up turn them off */
+			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+						     &dpcd_power_state, sizeof(dpcd_power_state));
+			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
+				/* blank dp stream before power off receiver*/
+				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
+					unsigned int fe;
+
+					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
+										dc->links[i]->link_enc);
+					if (fe == ENGINE_ID_UNKNOWN)
+						continue;
+
+					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+						if (fe == dc->res_pool->stream_enc[j]->id) {
+							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+										dc->res_pool->stream_enc[j]);
+							break;
+						}
+					}
+				}
+				dp_receiver_power_ctrl(dc->links[i], false);
+			}
+		}
+	}
 
 	/* If taking control over from VBIOS, we may want to optimize our first
 	 * mode set, so we need to skip powering down pipes until we know which
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 186d08aec812..7308c4c744ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -72,7 +72,8 @@ void dcn31_init_hw(struct dc *dc)
 	struct dc_bios *dcb = dc->ctx->dc_bios;
 	struct resource_pool *res_pool = dc->res_pool;
 	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
-	int i;
+	int i, j;
+	int edp_num;
 
 	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
 		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
@@ -190,9 +191,40 @@ void dcn31_init_hw(struct dc *dc)
 		dmub_enable_outbox_notification(dc);
 
 	/* we want to turn off all dp displays before doing detection */
-	if (dc->config.power_down_display_on_boot)
-		blank_all_dp_displays(dc, true);
-
+	if (dc->config.power_down_display_on_boot) {
+		uint8_t dpcd_power_state = '\0';
+		enum dc_status status = DC_ERROR_UNEXPECTED;
+
+		for (i = 0; i < dc->link_count; i++) {
+			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
+				continue;
+
+			/* if any of the displays are lit up turn them off */
+			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
+						     &dpcd_power_state, sizeof(dpcd_power_state));
+			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
+				/* blank dp stream before power off receiver*/
+				if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
+						dc->links[i]->link_enc->funcs->get_dig_frontend) {
+					unsigned int fe;
+
+					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
+										dc->links[i]->link_enc);
+					if (fe == ENGINE_ID_UNKNOWN)
+						continue;
+
+					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
+						if (fe == dc->res_pool->stream_enc[j]->id) {
+							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
+										dc->res_pool->stream_enc[j]);
+							break;
+						}
+					}
+				}
+				dp_receiver_power_ctrl(dc->links[i], false);
+			}
+		}
+	}
 
 	/* If taking control over from VBIOS, we may want to optimize our first
 	 * mode set, so we need to skip powering down pipes until we know which
-- 
2.25.1

Re: [PATCH 27/27] Revert "drm/amd/display: Add helper for blanking all dp displays"

[Paul Menzel]

Dear Augustin,


Am 15.10.21 um 20:43 schrieb Agustin Gutierrez:
> This reverts commit 50ac5b14c74c5706796cb6378f25a2121dba5b2d.
> 
> This patch introduced a couple of dmesg warnings,

Please give one example warning for people searching through the git 
history.

> this is not a valid approach anymore.

Nit: Please make it it’s own sentence.

> For this reason, we are reverting this patch, and we need to revert
> the workaround patch.
What is the workaround patch?


Kind regards,

Paul

> Cc: Hanghong Ma <hanghong.ma@amd.com>
> Cc: Mark Broadworth <mark.broadworth@amd.com>
> Signed-off-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 45 -------------------
>   drivers/gpu/drm/amd/display/dc/dc_link.h      |  1 -
>   .../display/dc/dce110/dce110_hw_sequencer.c   | 24 ++++++++--
>   .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 41 +++++++++++++++--
>   .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    | 39 ++++++++++++++--
>   .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 40 +++++++++++++++--
>   6 files changed, 131 insertions(+), 59 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index c01309a1cbf2..e5d6cbd7ea78 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -1988,51 +1988,6 @@ static enum dc_status enable_link_dp_mst(
>   	return enable_link_dp(state, pipe_ctx);
>   }
>   
> -void blank_all_dp_displays(struct dc *dc, bool hw_init)
> -{
> -	unsigned int i, j, fe;
> -	uint8_t dpcd_power_state = '\0';
> -	enum dc_status status = DC_ERROR_UNEXPECTED;
> -
> -	for (i = 0; i < dc->link_count; i++) {
> -		enum signal_type signal = dc->links[i]->connector_signal;
> -
> -		if ((signal == SIGNAL_TYPE_EDP) ||
> -			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
> -			if (hw_init && signal != SIGNAL_TYPE_EDP) {
> -				/* DP 2.0 spec requires that we read LTTPR caps first */
> -				dp_retrieve_lttpr_cap(dc->links[i]);
> -				/* if any of the displays are lit up turn them off */
> -				status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
> -							&dpcd_power_state, sizeof(dpcd_power_state));
> -			}
> -
> -			if ((signal != SIGNAL_TYPE_EDP && status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) ||
> -					(!hw_init && dc->links[i]->link_enc &&
> -					dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc))) {
> -				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
> -					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
> -					if (fe == ENGINE_ID_UNKNOWN)
> -						continue;
> -
> -					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
> -						if (fe == dc->res_pool->stream_enc[j]->id) {
> -							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
> -									dc->res_pool->stream_enc[j]);
> -							break;
> -						}
> -					}
> -				}
> -
> -				if (!dc->links[i]->wa_flags.dp_keep_receiver_powered ||
> -					(hw_init && signal != SIGNAL_TYPE_EDP))
> -					dp_receiver_power_ctrl(dc->links[i], false);
> -			}
> -		}
> -	}
> -
> -}
> -
>   static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
>   		enum engine_id eng_id,
>   		struct ext_hdmi_settings *settings)
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
> index 69b008bafbbc..a73d64b1fd33 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_link.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
> @@ -277,7 +277,6 @@ bool dc_link_setup_psr(struct dc_link *dc_link,
>   		struct psr_context *psr_context);
>   
>   void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency);
> -void blank_all_dp_displays(struct dc *dc, bool hw_init);
>   
>   /* Request DC to detect if there is a Panel connected.
>    * boot - If this call is during initial boot.
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index 8108f9ae2638..af3e68d3e747 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -1649,13 +1649,31 @@ static enum dc_status apply_single_controller_ctx_to_hw(
>   
>   static void power_down_encoders(struct dc *dc)
>   {
> -	int i;
> -
> -	blank_all_dp_displays(dc, false);
> +	int i, j;
>   
>   	for (i = 0; i < dc->link_count; i++) {
>   		enum signal_type signal = dc->links[i]->connector_signal;
>   
> +		if ((signal == SIGNAL_TYPE_EDP) ||
> +			(signal == SIGNAL_TYPE_DISPLAY_PORT)) {
> +			if (dc->links[i]->link_enc->funcs->get_dig_frontend &&
> +				dc->links[i]->link_enc->funcs->is_dig_enabled(dc->links[i]->link_enc)) {
> +				unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
> +									dc->links[i]->link_enc);
> +
> +				for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
> +					if (fe == dc->res_pool->stream_enc[j]->id) {
> +						dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
> +									dc->res_pool->stream_enc[j]);
> +						break;
> +					}
> +				}
> +			}
> +
> +			if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
> +				dp_receiver_power_ctrl(dc->links[i], false);
> +		}
> +
>   		if (signal != SIGNAL_TYPE_EDP)
>   			signal = SIGNAL_TYPE_NONE;
>   
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index aa2d430f2a1a..44d27579d898 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -1366,7 +1366,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
>   
>   void dcn10_init_hw(struct dc *dc)
>   {
> -	int i;
> +	int i, j;
>   	struct abm *abm = dc->res_pool->abm;
>   	struct dmcu *dmcu = dc->res_pool->dmcu;
>   	struct dce_hwseq *hws = dc->hwseq;
> @@ -1462,8 +1462,43 @@ void dcn10_init_hw(struct dc *dc)
>   		dmub_enable_outbox_notification(dc);
>   
>   	/* we want to turn off all dp displays before doing detection */
> -	if (dc->config.power_down_display_on_boot)
> -		blank_all_dp_displays(dc, true);
> +	if (dc->config.power_down_display_on_boot) {
> +		uint8_t dpcd_power_state = '\0';
> +		enum dc_status status = DC_ERROR_UNEXPECTED;
> +
> +		for (i = 0; i < dc->link_count; i++) {
> +			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
> +				continue;
> +
> +			/* DP 2.0 requires that LTTPR Caps be read first */
> +			dp_retrieve_lttpr_cap(dc->links[i]);
> +
> +			/*
> +			 * If any of the displays are lit up turn them off.
> +			 * The reason is that some MST hubs cannot be turned off
> +			 * completely until we tell them to do so.
> +			 * If not turned off, then displays connected to MST hub
> +			 * won't light up.
> +			 */
> +			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
> +							&dpcd_power_state, sizeof(dpcd_power_state));
> +			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
> +				/* blank dp stream before power off receiver*/
> +				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
> +					unsigned int fe = dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
> +
> +					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
> +						if (fe == dc->res_pool->stream_enc[j]->id) {
> +							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
> +										dc->res_pool->stream_enc[j]);
> +							break;
> +						}
> +					}
> +				}
> +				dp_receiver_power_ctrl(dc->links[i], false);
> +			}
> +		}
> +	}
>   
>   	/* If taking control over from VBIOS, we may want to optimize our first
>   	 * mode set, so we need to skip powering down pipes until we know which
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index 2936a334cd64..df2717116604 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -437,7 +437,7 @@ void dcn30_init_hw(struct dc *dc)
>   	struct dce_hwseq *hws = dc->hwseq;
>   	struct dc_bios *dcb = dc->ctx->dc_bios;
>   	struct resource_pool *res_pool = dc->res_pool;
> -	int i;
> +	int i, j;
>   	int edp_num;
>   	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
>   
> @@ -534,8 +534,41 @@ void dcn30_init_hw(struct dc *dc)
>   			hws->funcs.dsc_pg_control(hws, res_pool->dscs[i]->inst, false);
>   
>   	/* we want to turn off all dp displays before doing detection */
> -	if (dc->config.power_down_display_on_boot)
> -		blank_all_dp_displays(dc, true);
> +	if (dc->config.power_down_display_on_boot) {
> +		uint8_t dpcd_power_state = '\0';
> +		enum dc_status status = DC_ERROR_UNEXPECTED;
> +
> +		for (i = 0; i < dc->link_count; i++) {
> +			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
> +				continue;
> +			/* DP 2.0 states that LTTPR regs must be read first */
> +			dp_retrieve_lttpr_cap(dc->links[i]);
> +
> +			/* if any of the displays are lit up turn them off */
> +			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
> +						     &dpcd_power_state, sizeof(dpcd_power_state));
> +			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
> +				/* blank dp stream before power off receiver*/
> +				if (dc->links[i]->link_enc->funcs->get_dig_frontend) {
> +					unsigned int fe;
> +
> +					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
> +										dc->links[i]->link_enc);
> +					if (fe == ENGINE_ID_UNKNOWN)
> +						continue;
> +
> +					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
> +						if (fe == dc->res_pool->stream_enc[j]->id) {
> +							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
> +										dc->res_pool->stream_enc[j]);
> +							break;
> +						}
> +					}
> +				}
> +				dp_receiver_power_ctrl(dc->links[i], false);
> +			}
> +		}
> +	}
>   
>   	/* If taking control over from VBIOS, we may want to optimize our first
>   	 * mode set, so we need to skip powering down pipes until we know which
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
> index 186d08aec812..7308c4c744ba 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
> @@ -72,7 +72,8 @@ void dcn31_init_hw(struct dc *dc)
>   	struct dc_bios *dcb = dc->ctx->dc_bios;
>   	struct resource_pool *res_pool = dc->res_pool;
>   	uint32_t backlight = MAX_BACKLIGHT_LEVEL;
> -	int i;
> +	int i, j;
> +	int edp_num;
>   
>   	if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
>   		dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
> @@ -190,9 +191,40 @@ void dcn31_init_hw(struct dc *dc)
>   		dmub_enable_outbox_notification(dc);
>   
>   	/* we want to turn off all dp displays before doing detection */
> -	if (dc->config.power_down_display_on_boot)
> -		blank_all_dp_displays(dc, true);
> -
> +	if (dc->config.power_down_display_on_boot) {
> +		uint8_t dpcd_power_state = '\0';
> +		enum dc_status status = DC_ERROR_UNEXPECTED;
> +
> +		for (i = 0; i < dc->link_count; i++) {
> +			if (dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)
> +				continue;
> +
> +			/* if any of the displays are lit up turn them off */
> +			status = core_link_read_dpcd(dc->links[i], DP_SET_POWER,
> +						     &dpcd_power_state, sizeof(dpcd_power_state));
> +			if (status == DC_OK && dpcd_power_state == DP_POWER_STATE_D0) {
> +				/* blank dp stream before power off receiver*/
> +				if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY &&
> +						dc->links[i]->link_enc->funcs->get_dig_frontend) {
> +					unsigned int fe;
> +
> +					fe = dc->links[i]->link_enc->funcs->get_dig_frontend(
> +										dc->links[i]->link_enc);
> +					if (fe == ENGINE_ID_UNKNOWN)
> +						continue;
> +
> +					for (j = 0; j < dc->res_pool->stream_enc_count; j++) {
> +						if (fe == dc->res_pool->stream_enc[j]->id) {
> +							dc->res_pool->stream_enc[j]->funcs->dp_blank(dc->links[i],
> +										dc->res_pool->stream_enc[j]);
> +							break;
> +						}
> +					}
> +				}
> +				dp_receiver_power_ctrl(dc->links[i], false);
> +			}
> +		}
> +	}
>   
>   	/* If taking control over from VBIOS, we may want to optimize our first
>   	 * mode set, so we need to skip powering down pipes until we know which
> 

RE: [PATCH 00/27] DC Patchset for October 15

[Wheeler, Daniel]

[Public]

Hi all,
 
This week this patchset was tested on the following systems:
 
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
AMD Ryzen 9 5900H, with the following display types: eDP 1080p 60hz, 4k 60hz  (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
 
Sapphire Pulse RX5700XT with the following display types:
4k 60hz  (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Reference AMD RX6800 with the following display types:
4k 60hz  (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
 
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems.
 
 
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
 
 
Thank you,
 
Dan Wheeler
Technologist  |  AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook |  Twitter |  amd.com  

-----Original Message-----
From: Gutierrez, Agustin <Agustin.Gutierrez@amd.com> 
Sent: October 15, 2021 2:43 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Lipski, Mikita <Mikita.Lipski@amd.com>; Li, Roman <Roman.Li@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Broadworth, Mark <Mark.Broadworth@amd.com>
Subject: [PATCH 00/27] DC Patchset for October 15

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Cc: Mark Broadworth <mark.broadworth@amd.com>

Agustin Gutierrez (2):
  Revert "drm/amd/display: Fix error in dmesg at boot"
  Revert "drm/amd/display: Add helper for blanking all dp displays"

Anthony Koo (2):
  drm/amd/display: Change initializer to single brace
  drm/amd/display: [FW Promotion] Release 0.0.88

Aric Cyr (2):
  drm/amd/display: Validate plane rects before use
  drm/amd/display: 3.2.157

Eric Yang (1):
  drm/amd/display: increase Z9 latency to workaround underflow in Z9

Hansen (1):
  drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

Jake Wang (6):
  drm/amd/display: Disable dpp root clock when not being used
  drm/amd/display: Disable dsc root clock when not being used
  drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
  drm/amd/display: Removed z10 save after dsc disable
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Disable hdmistream and hdmichar clocks

Jimmy Kizito (2):
  drm/amd/display: Clear encoder assignment for copied streams
  drm/amd/display: Do not skip link training on DP quick hot plug

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Lai, Derek (1):
  drm/amd/display: Removed power down on boot from DCN31

Michael Strauss (1):
  drm/amd/display: Clean Up VPG Low Mem Power

Mikita Lipski (1):
  drm/amd/display: Add missing PSR state

Nevenko Stupar (1):
  drm/amd/display: Add bios parser support for latest firmware_info

Nicholas Kazlauskas (2):
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Require immediate flip support for DCN3.1 planes

Nikola Cornij (2):
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amd/display: Increase watermark latencies for DCN3.1

Wenjing Liu (2):
  drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream
  drm/amd/display: correct apg audio channel enable golden value

 .../drm/amd/display/dc/bios/bios_parser2.c    |  90 ++++++-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  10 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 +----
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  32 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |   9 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |   1 -
 drivers/gpu/drm/amd/display/dc/dc_types.h     |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  24 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  49 +++-  .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  39 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +++++++++++++++++-  .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 114 +++++----
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  17 +-
 .../dc/dml/dcn31/display_mode_vba_31.c        |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   9 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../include/asic_reg/dcn/dcn_3_1_2_offset.h   |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   8 +
 29 files changed, 643 insertions(+), 185 deletions(-)

--
2.25.1

[PATCH 00/27] DC patchset for October 15

[Agustin Gutierrez]

This DC patchset brings improvements in multiple areas. In summary, we
highlight:

* Fix some issues such as DP2 problem, prefetch bandwidth calculation
for DCN3.1 and others.
* Increased Z9 latency and removed z10 save after dsc disable.
* Revert a couple of bad changes.
* Added missing PSR state patch.

Cc: Daniel Wheeler <daniel.wheeler@amd.com>
Cc: Mark Broadworth <mark.broadworth@amd.com>

Agustin Gutierrez (2):
  Revert "drm/amd/display: Fix error in dmesg at boot"
  Revert "drm/amd/display: Add helper for blanking all dp displays"

Anthony Koo (2):
  drm/amd/display: Change initializer to single brace
  drm/amd/display: [FW Promotion] Release 0.0.88

Aric Cyr (2):
  drm/amd/display: Validate plane rects before use
  drm/amd/display: 3.2.157

Eric Yang (1):
  drm/amd/display: increase Z9 latency to workaround underflow in Z9

Hansen (1):
  drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY

Jake Wang (6):
  drm/amd/display: Disable dpp root clock when not being used
  drm/amd/display: Disable dsc root clock when not being used
  drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
  drm/amd/display: Removed z10 save after dsc disable
  drm/amd/display: Moved dccg init to after bios golden init
  drm/amd/display: Disable hdmistream and hdmichar clocks

Jimmy Kizito (2):
  drm/amd/display: Clear encoder assignment for copied streams
  drm/amd/display: Do not skip link training on DP quick hot plug

Josip Pavic (1):
  drm/amd/display: do not compare integers of different widths

Lai, Derek (1):
  drm/amd/display: Removed power down on boot from DCN31

Michael Strauss (1):
  drm/amd/display: Clean Up VPG Low Mem Power

Mikita Lipski (1):
  drm/amd/display: Add missing PSR state

Nevenko Stupar (1):
  drm/amd/display: Add bios parser support for latest firmware_info

Nicholas Kazlauskas (2):
  drm/amd/display: Fix prefetch bandwidth calculation for DCN3.1
  drm/amd/display: Require immediate flip support for DCN3.1 planes

Nikola Cornij (2):
  drm/amd/display: Limit display scaling to up to true 4k for DCN 3.1
  drm/amd/display: Increase watermark latencies for DCN3.1

Wenjing Liu (2):
  drm/amd/display: add DP2.0 debug option to set MST_EN for SST stream
  drm/amd/display: correct apg audio channel enable golden value

 .../drm/amd/display/dc/bios/bios_parser2.c    |  90 ++++++-
 .../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c  |  21 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  10 -
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  63 +----
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  32 +--
 .../drm/amd/display/dc/core/dc_link_enc_cfg.c |   9 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |   5 +
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   3 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h      |   1 -
 drivers/gpu/drm/amd/display/dc/dc_types.h     |   1 +
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   2 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  24 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  49 +++-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |   4 +-
 .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  39 ++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_apg.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.c | 237 +++++++++++++++++-
 .../gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h |  34 ++-
 .../drm/amd/display/dc/dcn31/dcn31_hwseq.c    | 114 +++++----
 .../drm/amd/display/dc/dcn31/dcn31_resource.c |  17 +-
 .../dc/dml/dcn31/display_mode_vba_31.c        |   6 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h  |   9 +
 .../gpu/drm/amd/display/dc/inc/link_enc_cfg.h |   2 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |   4 +-
 .../include/asic_reg/dcn/dcn_3_1_2_offset.h   |   2 +
 .../include/asic_reg/dcn/dcn_3_1_2_sh_mask.h  |   8 +
 29 files changed, 643 insertions(+), 185 deletions(-)

-- 
2.25.1