* RE: [PATCH 00/21] DC Patches Mar 7, 2022
2022-03-07 20:59 [PATCH 00/21] DC Patches Mar 7, 2022 Alan Liu
@ 2022-03-07 14:25 ` Wheeler, Daniel
2022-03-07 20:59 ` [PATCH 01/21] drm/amd/display: fix deep color ratio Alan Liu
1 sibling, 0 replies; 3+ messages in thread
From: Wheeler, Daniel @ 2022-03-07 14:25 UTC (permalink / raw)
To: Liu, HaoPing (Alan), amd-gfx
Cc: Wang, Chao-kai (Stylon), Liu, HaoPing (Alan),
Cyr, Aric, Li, Sun peng (Leo),
Lakha, Bhawanpreet, Zhuo, Qingqing (Lillian),
Siqueira, Rodrigo, Li, Roman, Chiu, Solomon, Pillai, Aurabindo,
Lin, Wayne, Wentland, Harry, Gutierrez, Agustin, Kotarac, Pavle
[AMD Official Use Only]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Lenovo Thinkpad T14s Gen2 with AMD Ryzen 5 5650U, with the following display types: eDP 1080p 60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI), 1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
Sapphire Pulse RX5700XT with the following display types:
4k 60hz (via DP/HDMI), 1440p 144hz (via DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Reference AMD RX6800 with the following display types:
4k 60hz (via DP/HDMI and USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI and USB-C to DP/HDMI), 1680*1050 60hz (via DP to DVI/VGA)
Included testing using a Startech DP 1.4 MST hub at 2x 4k 60hz, and 3x 1080p 60hz on all systems. Also tested DSC via USB-C to DP DSC Hub with 3x 4k 60hz on Ryzen 9 5900h and Ryzen 5 4500u.
Tested on Ubuntu 20.04.4 with Kernel Version 5.16 and ChromeOS
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Thank you,
Dan Wheeler
Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alan Liu
Sent: March 7, 2022 3:59 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Chao-kai (Stylon) <Stylon.Wang@amd.com>; Liu, HaoPing (Alan) <HaoPing.Liu@amd.com>; Cyr, Aric <Aric.Cyr@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Chiu, Solomon <Solomon.Chiu@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lin, Wayne <Wayne.Lin@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; Gutierrez, Agustin <Agustin.Gutierrez@amd.com>; Kotarac, Pavle <Pavle.Kotarac@amd.com>
Subject: [PATCH 00/21] DC Patches Mar 7, 2022
This DC patchset brings improvements in multiple areas. In summary, we have:
* Remove FPU-related code from dcn20/21/303 to dml folder;
* Fixes related to clock_source_create;
* Several enhancements in DC/DMUB;
This version brings along following fixes:
- move FPU operations from dcn21 to dml/dcn20 folder
- move FPU-related code from dcn20 to dml folder
- Fix compile error from TO_CLK_MGR_INTERNAL
- Fix double free during GPU reset on DC streams
- Add NULL check
- [FW Promotion] Release 0.0.107.0
- enable dcn315/316 s0i2 support
- handle DP2.0 RX with UHBR20 but not UHBR13.5 support
- disable HPD SW timer for passive dongle type 1 only
- add gamut coefficient set A and B
- merge two duplicated clock_source_create
- Add link dp trace support
- move FPU associated DCN303 code to DML folder
- Release AUX engine after failed acquire
- Add minimal pipe split transition state
- Clean up fixed VS PHY test w/a function
- fix the clock source contruct for dcn315
- cleaning up smu_if to add future flexibility
- fix deep color ratio
- add debug option to bypass ssinfo from bios for dcn315
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.107.0
Aric Cyr (1):
drm/amd/display: 3.2.176
Charlene Liu (3):
drm/amd/display: fix the clock source contruct for dcn315
drm/amd/display: merge two duplicated clock_source_create
drm/amd/display: enable dcn315/316 s0i2 support
Chris Park (1):
drm/amd/display: Add NULL check
Dhillon, Jasdeep (1):
drm/amd/display: move FPU associated DCN303 code to DML folder
Dillon Varone (1):
drm/amd/display: Add minimal pipe split transition state
George Shen (1):
drm/amd/display: Clean up fixed VS PHY test w/a function
Hansen Dsouza (1):
drm/amd/display: fix deep color ratio
Jingwen Zhu (1):
drm/amd/display: add gamut coefficient set A and B
Leo (Hanghong) Ma (1):
drm/amd/display: Add link dp trace support
Leo Li (1):
drm/amd/display: Fix compile error from TO_CLK_MGR_INTERNAL
Leung, Martin (1):
drm/amd/display: cleaning up smu_if to add future flexibility
Melissa Wen (2):
drm/amd/display: move FPU operations from dcn21 to dml/dcn20 folder
drm/amd/display: move FPU code from dcn10 to dml/dcn10 folder
Melissa·Wen· (1):
drm/amd/display: move FPU-related code from dcn20 to dml folder
Nicholas Kazlauskas (1):
drm/amd/display: Fix double free during GPU reset on DC streams
Sung Joon Kim (1):
drm/amd/display: disable HPD SW timer for passive dongle type 1 only
Wenjing Liu (1):
drm/amd/display: handle DP2.0 RX with UHBR20 but not UHBR13.5 support
Wyatt Wood (1):
drm/amd/display: Release AUX engine after failed acquire
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +-
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 13 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 9 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 67 +-
.../dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h | 74 +
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 8 +-
.../display/dc/clk_mgr/dcn316/dcn316_smu.c | 26 +
.../display/dc/clk_mgr/dcn316/dcn316_smu.h | 2 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 128 +-
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 7 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 36 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
.../drm/amd/display/dc/dce/dce_clock_source.c | 117 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 9 +
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 62 -
.../drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 25 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 1369 +-----------
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 31 +-
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 25 -
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 564 +----
.../drm/amd/display/dc/dcn21/dcn21_resource.h | 11 +
.../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 7 +
.../gpu/drm/amd/display/dc/dcn303/Makefile | 26 -
.../amd/display/dc/dcn303/dcn303_resource.c | 327 +--
.../amd/display/dc/dcn303/dcn303_resource.h | 3 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 6 +-
.../amd/display/dc/dcn315/dcn315_resource.c | 37 +-
.../amd/display/dc/dcn316/dcn316_resource.c | 37 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +
.../drm/amd/display/dc/dml/dcn10/dcn10_fpu.c | 123 ++
.../drm/amd/display/dc/dml/dcn10/dcn10_fpu.h | 30 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1922 +++++++++++++++++
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 51 +
.../amd/display/dc/dml/dcn303/dcn303_fpu.c | 362 ++++
.../amd/display/dc/dml/dcn303/dcn303_fpu.h | 32 +
.../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 5 +
drivers/gpu/drm/amd/display/dc/link/Makefile | 2 +-
.../drm/amd/display/dc/link/link_dp_trace.c | 146 ++
.../drm/amd/display/dc/link/link_dp_trace.h | 57 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +-
.../amd/display/include/ddc_service_types.h | 1 +
.../display/include/grph_object_ctrl_defs.h | 22 -
50 files changed, 3213 insertions(+), 2616 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_trace.c
create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_trace.h
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 00/21] DC Patches Mar 7, 2022
@ 2022-03-07 20:59 Alan Liu
2022-03-07 14:25 ` Wheeler, Daniel
2022-03-07 20:59 ` [PATCH 01/21] drm/amd/display: fix deep color ratio Alan Liu
0 siblings, 2 replies; 3+ messages in thread
From: Alan Liu @ 2022-03-07 20:59 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Alan Liu, Aric Cyr, Sunpeng.Li, Harry.Wentland,
qingqing.zhuo, Rodrigo.Siqueira, roman.li, solomon.chiu,
Aurabindo.Pillai, wayne.lin, Bhawanpreet.Lakha,
agustin.gutierrez, pavle.kotarac
This DC patchset brings improvements in multiple areas. In summary, we have:
* Remove FPU-related code from dcn20/21/303 to dml folder;
* Fixes related to clock_source_create;
* Several enhancements in DC/DMUB;
This version brings along following fixes:
- move FPU operations from dcn21 to dml/dcn20 folder
- move FPU-related code from dcn20 to dml folder
- Fix compile error from TO_CLK_MGR_INTERNAL
- Fix double free during GPU reset on DC streams
- Add NULL check
- [FW Promotion] Release 0.0.107.0
- enable dcn315/316 s0i2 support
- handle DP2.0 RX with UHBR20 but not UHBR13.5 support
- disable HPD SW timer for passive dongle type 1 only
- add gamut coefficient set A and B
- merge two duplicated clock_source_create
- Add link dp trace support
- move FPU associated DCN303 code to DML folder
- Release AUX engine after failed acquire
- Add minimal pipe split transition state
- Clean up fixed VS PHY test w/a function
- fix the clock source contruct for dcn315
- cleaning up smu_if to add future flexibility
- fix deep color ratio
- add debug option to bypass ssinfo from bios for dcn315
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.107.0
Aric Cyr (1):
drm/amd/display: 3.2.176
Charlene Liu (3):
drm/amd/display: fix the clock source contruct for dcn315
drm/amd/display: merge two duplicated clock_source_create
drm/amd/display: enable dcn315/316 s0i2 support
Chris Park (1):
drm/amd/display: Add NULL check
Dhillon, Jasdeep (1):
drm/amd/display: move FPU associated DCN303 code to DML folder
Dillon Varone (1):
drm/amd/display: Add minimal pipe split transition state
George Shen (1):
drm/amd/display: Clean up fixed VS PHY test w/a function
Hansen Dsouza (1):
drm/amd/display: fix deep color ratio
Jingwen Zhu (1):
drm/amd/display: add gamut coefficient set A and B
Leo (Hanghong) Ma (1):
drm/amd/display: Add link dp trace support
Leo Li (1):
drm/amd/display: Fix compile error from TO_CLK_MGR_INTERNAL
Leung, Martin (1):
drm/amd/display: cleaning up smu_if to add future flexibility
Melissa Wen (2):
drm/amd/display: move FPU operations from dcn21 to dml/dcn20 folder
drm/amd/display: move FPU code from dcn10 to dml/dcn10 folder
Melissa·Wen· (1):
drm/amd/display: move FPU-related code from dcn20 to dml folder
Nicholas Kazlauskas (1):
drm/amd/display: Fix double free during GPU reset on DC streams
Sung Joon Kim (1):
drm/amd/display: disable HPD SW timer for passive dongle type 1 only
Wenjing Liu (1):
drm/amd/display: handle DP2.0 RX with UHBR20 but not UHBR13.5 support
Wyatt Wood (1):
drm/amd/display: Release AUX engine after failed acquire
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +-
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 13 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.c | 9 +-
.../dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.h | 67 +-
.../dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h | 74 +
.../dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
.../dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 8 +-
.../display/dc/clk_mgr/dcn316/dcn316_smu.c | 26 +
.../display/dc/clk_mgr/dcn316/dcn316_smu.h | 2 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +
.../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 2 +
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 128 +-
.../drm/amd/display/dc/core/dc_link_enc_cfg.c | 7 +
.../gpu/drm/amd/display/dc/core/dc_resource.c | 3 +
drivers/gpu/drm/amd/display/dc/dc.h | 3 +-
drivers/gpu/drm/amd/display/dc/dc_link.h | 36 +
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
.../drm/amd/display/dc/dce/dce_clock_source.c | 117 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 9 +
.../drm/amd/display/dc/dcn10/dcn10_resource.c | 62 -
.../drm/amd/display/dc/dcn10/dcn10_resource.h | 4 +
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 25 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 1369 +-----------
.../drm/amd/display/dc/dcn20/dcn20_resource.h | 31 +-
drivers/gpu/drm/amd/display/dc/dcn21/Makefile | 25 -
.../drm/amd/display/dc/dcn21/dcn21_resource.c | 564 +----
.../drm/amd/display/dc/dcn21/dcn21_resource.h | 11 +
.../drm/amd/display/dc/dcn30/dcn30_dpp_cm.c | 2 +-
.../drm/amd/display/dc/dcn30/dcn30_resource.c | 7 +
.../gpu/drm/amd/display/dc/dcn303/Makefile | 26 -
.../amd/display/dc/dcn303/dcn303_resource.c | 327 +--
.../amd/display/dc/dcn303/dcn303_resource.h | 3 +
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 6 +-
.../amd/display/dc/dcn315/dcn315_resource.c | 37 +-
.../amd/display/dc/dcn316/dcn316_resource.c | 37 +-
drivers/gpu/drm/amd/display/dc/dml/Makefile | 4 +
.../drm/amd/display/dc/dml/dcn10/dcn10_fpu.c | 123 ++
.../drm/amd/display/dc/dml/dcn10/dcn10_fpu.h | 30 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 1922 +++++++++++++++++
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 51 +
.../amd/display/dc/dml/dcn303/dcn303_fpu.c | 362 ++++
.../amd/display/dc/dml/dcn303/dcn303_fpu.h | 32 +
.../gpu/drm/amd/display/dc/inc/link_enc_cfg.h | 5 +
drivers/gpu/drm/amd/display/dc/link/Makefile | 2 +-
.../drm/amd/display/dc/link/link_dp_trace.c | 146 ++
.../drm/amd/display/dc/link/link_dp_trace.h | 57 +
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 +-
.../amd/display/include/ddc_service_types.h | 1 +
.../display/include/grph_object_ctrl_defs.h | 22 -
50 files changed, 3213 insertions(+), 2616 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_smu11_driver_if.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn10/dcn10_fpu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dml/dcn303/dcn303_fpu.h
create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_trace.c
create mode 100644 drivers/gpu/drm/amd/display/dc/link/link_dp_trace.h
--
2.25.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 01/21] drm/amd/display: fix deep color ratio
2022-03-07 20:59 [PATCH 00/21] DC Patches Mar 7, 2022 Alan Liu
2022-03-07 14:25 ` Wheeler, Daniel
@ 2022-03-07 20:59 ` Alan Liu
1 sibling, 0 replies; 3+ messages in thread
From: Alan Liu @ 2022-03-07 20:59 UTC (permalink / raw)
To: amd-gfx
Cc: stylon.wang, Charlene Liu, Hansen Dsouza, Sunpeng.Li,
Harry.Wentland, qingqing.zhuo, Rodrigo.Siqueira, roman.li,
Alan Liu, solomon.chiu, Aurabindo.Pillai, wayne.lin,
Bhawanpreet.Lakha, agustin.gutierrez, pavle.kotarac
From: Hansen Dsouza <Hansen.Dsouza@amd.com>
Fix enum mapping for deep color ratio
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com>
---
.../drm/amd/display/dc/dce/dce_clock_source.c | 100 ++++++++++++++++++
.../drm/amd/display/dc/dce/dce_clock_source.h | 9 ++
.../drm/amd/display/dc/dcn31/dcn31_resource.c | 2 +-
.../amd/display/dc/dcn316/dcn316_resource.c | 2 +-
4 files changed, 111 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 2c7eb982eabc..9285bdeca270 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -971,6 +971,81 @@ static bool dce112_program_pix_clk(
return true;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+static bool dcn31_program_pix_clk(
+ struct clock_source *clock_source,
+ struct pixel_clk_params *pix_clk_params,
+ struct pll_settings *pll_settings)
+{
+ struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
+ struct bp_pixel_clock_parameters bp_pc_params = {0};
+ enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+
+ if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
+ unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
+ unsigned dp_dto_ref_100hz = 7000000;
+ unsigned clock_100hz = pll_settings->actual_pix_clk_100hz;
+
+ /* Set DTO values: phase = target clock, modulo = reference clock */
+ REG_WRITE(PHASE[inst], clock_100hz);
+ REG_WRITE(MODULO[inst], dp_dto_ref_100hz);
+
+ /* Enable DTO */
+ REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
+ return true;
+ }
+
+ /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
+ bp_pc_params.controller_id = pix_clk_params->controller_id;
+ bp_pc_params.pll_id = clock_source->id;
+ bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz;
+ bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
+ bp_pc_params.signal_type = pix_clk_params->signal_type;
+
+ // Make sure we send the correct color depth to DMUB for HDMI
+ if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
+ switch (pix_clk_params->color_depth) {
+ case COLOR_DEPTH_888:
+ bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+ break;
+ case COLOR_DEPTH_101010:
+ bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30;
+ break;
+ case COLOR_DEPTH_121212:
+ bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36;
+ break;
+ case COLOR_DEPTH_161616:
+ bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48;
+ break;
+ default:
+ bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;
+ break;
+ }
+ bp_pc_params.color_depth = bp_pc_colour_depth;
+ }
+
+ if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
+ bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
+ pll_settings->use_external_clk;
+ bp_pc_params.flags.SET_XTALIN_REF_SRC =
+ !pll_settings->use_external_clk;
+ if (pix_clk_params->flags.SUPPORT_YCBCR420) {
+ bp_pc_params.flags.SUPPORT_YUV_420 = 1;
+ }
+ }
+ if (clk_src->bios->funcs->set_pixel_clock(
+ clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
+ return false;
+ /* Resync deep color DTO */
+ if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
+ dce112_program_pixel_clk_resync(clk_src,
+ pix_clk_params->signal_type,
+ pix_clk_params->color_depth,
+ pix_clk_params->flags.SUPPORT_YCBCR420);
+
+ return true;
+}
+#endif
static bool dce110_clock_source_power_down(
struct clock_source *clk_src)
@@ -1205,6 +1280,13 @@ static const struct clock_source_funcs dcn3_clk_src_funcs = {
.get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
.get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
};
+
+static const struct clock_source_funcs dcn31_clk_src_funcs = {
+ .cs_power_down = dce110_clock_source_power_down,
+ .program_pix_clk = dcn31_program_pix_clk,
+ .get_pix_clk_dividers = dcn3_get_pix_clk_dividers,
+ .get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz
+};
#endif
/*****************************************/
/* Constructor */
@@ -1609,6 +1691,24 @@ bool dcn3_clk_src_construct(
}
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+bool dcn31_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask)
+{
+ bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask);
+
+ clk_src->base.funcs = &dcn31_clk_src_funcs;
+
+ return ret;
+}
+#endif
+
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool dcn301_clk_src_construct(
struct dce110_clk_src *clk_src,
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index 692fa23ca02b..069de7649c8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -292,6 +292,15 @@ bool dcn301_clk_src_construct(
const struct dce110_clk_src_regs *regs,
const struct dce110_clk_src_shift *cs_shift,
const struct dce110_clk_src_mask *cs_mask);
+
+bool dcn31_clk_src_construct(
+ struct dce110_clk_src *clk_src,
+ struct dc_context *ctx,
+ struct dc_bios *bios,
+ enum clock_source_id id,
+ const struct dce110_clk_src_regs *regs,
+ const struct dce110_clk_src_shift *cs_shift,
+ const struct dce110_clk_src_mask *cs_mask);
#endif
/* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 2ecd7bbfa0d4..3c5efa61dff9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -2177,7 +2177,7 @@ static struct clock_source *dcn30_clock_source_create(
if (!clk_src)
return NULL;
- if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+ if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
regs, &cs_shift, &cs_mask)) {
clk_src->base.dp_clk_src = dp_clk_src;
return &clk_src->base;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
index 72d581c6092f..2e378d9cd00d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn316/dcn316_resource.c
@@ -1759,7 +1759,7 @@ static struct clock_source *dcn31_clock_source_create(
if (!clk_src)
return NULL;
- if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
+ if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
regs, &cs_shift, &cs_mask)) {
clk_src->base.dp_clk_src = dp_clk_src;
return &clk_src->base;
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-03-07 14:25 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-07 20:59 [PATCH 00/21] DC Patches Mar 7, 2022 Alan Liu
2022-03-07 14:25 ` Wheeler, Daniel
2022-03-07 20:59 ` [PATCH 01/21] drm/amd/display: fix deep color ratio Alan Liu
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