* [PATCH] imx: imx8m: drop uneeded check
@ 2022-04-29 8:18 Peng Fan (OSS)
2022-05-16 7:21 ` ZHIZHIKIN Andrey
2022-05-20 13:44 ` sbabic
0 siblings, 2 replies; 5+ messages in thread
From: Peng Fan (OSS) @ 2022-04-29 8:18 UTC (permalink / raw)
To: sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
waste cpu cycles.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 8e23e6da326..5240dc11363 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -72,15 +72,13 @@ void enable_tzc380(void)
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
- if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
- setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
* imx8mn and imx8mp implements the lock bit for
* TZASC_ID_SWAP_BYPASS, enable it to lock settings
*/
- if (is_imx8mn() || is_imx8mp())
- setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+ setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
/*
* set Region 0 attribute to allow secure and non-secure
--
2.36.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] imx: imx8m: drop uneeded check
2022-04-29 8:18 [PATCH] imx: imx8m: drop uneeded check Peng Fan (OSS)
@ 2022-05-16 7:21 ` ZHIZHIKIN Andrey
2022-05-16 7:24 ` Peng Fan
2022-05-20 13:44 ` sbabic
1 sibling, 1 reply; 5+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-05-16 7:21 UTC (permalink / raw)
To: Peng Fan (OSS), sbabic, festevam, NXP i.MX U-Boot Team; +Cc: u-boot, Peng Fan
Hello Peng,
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan (OSS)
> Sent: Friday, April 29, 2022 10:19 AM
> To: sbabic@denx.de; festevam@gmail.com; NXP i.MX U-Boot Team <uboot-imx@nxp.com>
> Cc: u-boot@lists.denx.de; Peng Fan <peng.fan@nxp.com>
> Subject: [PATCH] imx: imx8m: drop uneeded check
>
> From: Peng Fan <peng.fan@nxp.com>
>
> All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
> waste cpu cycles.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/mach-imx/imx8m/soc.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
> index 8e23e6da326..5240dc11363 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -72,15 +72,13 @@ void enable_tzc380(void)
> * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
> * order to avoid AXI Bus errors when GPU is in use
> */
> - if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
> - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
> + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
Since you've dropped the SoC-specific check, perhaps you can combine
bits set that are done by setbits_le32 together with one below?
>
> /*
> * imx8mn and imx8mp implements the lock bit for
> * TZASC_ID_SWAP_BYPASS, enable it to lock settings
> */
> - if (is_imx8mn() || is_imx8mp())
> - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
> + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
BYPASS_LOCK is not present in i.MX8MM TRM, but I guess you've checked
that it is implemented already, right?
>
> /*
> * set Region 0 attribute to allow secure and non-secure
> --
> 2.36.0
-- andrey
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] imx: imx8m: drop uneeded check
2022-05-16 7:21 ` ZHIZHIKIN Andrey
@ 2022-05-16 7:24 ` Peng Fan
2022-05-16 7:30 ` ZHIZHIKIN Andrey
0 siblings, 1 reply; 5+ messages in thread
From: Peng Fan @ 2022-05-16 7:24 UTC (permalink / raw)
To: ZHIZHIKIN Andrey, Peng Fan (OSS), sbabic, festevam, dl-uboot-imx; +Cc: u-boot
> Subject: RE: [PATCH] imx: imx8m: drop uneeded check
>
> Hello Peng,
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan
> > (OSS)
> > Sent: Friday, April 29, 2022 10:19 AM
> > To: sbabic@denx.de; festevam@gmail.com; NXP i.MX U-Boot Team
> > <uboot-imx@nxp.com>
> > Cc: u-boot@lists.denx.de; Peng Fan <peng.fan@nxp.com>
> > Subject: [PATCH] imx: imx8m: drop uneeded check
> >
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
> > waste cpu cycles.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> > arch/arm/mach-imx/imx8m/soc.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/imx8m/soc.c
> > b/arch/arm/mach-imx/imx8m/soc.c index 8e23e6da326..5240dc11363
> 100644
> > --- a/arch/arm/mach-imx/imx8m/soc.c
> > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > @@ -72,15 +72,13 @@ void enable_tzc380(void)
> > * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
> > * order to avoid AXI Bus errors when GPU is in use
> > */
> > - if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
> > - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
> > + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
>
> Since you've dropped the SoC-specific check, perhaps you can combine bits set
> that are done by setbits_le32 together with one below?
Let’s separate them, first set, then lock.
>
> >
> > /*
> > * imx8mn and imx8mp implements the lock bit for
> > * TZASC_ID_SWAP_BYPASS, enable it to lock settings
> > */
> > - if (is_imx8mn() || is_imx8mp())
> > - setbits_le32(&gpr->gpr[10],
> GPR_TZASC_ID_SWAP_BYPASS_LOCK);
> > + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
>
> BYPASS_LOCK is not present in i.MX8MM TRM, but I guess you've checked that it
> is implemented already, right?
Yes. It is implemented. RM needs update.
Regards,
Peng.
>
> >
> > /*
> > * set Region 0 attribute to allow secure and non-secure
> > --
> > 2.36.0
>
> -- andrey
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] imx: imx8m: drop uneeded check
2022-05-16 7:24 ` Peng Fan
@ 2022-05-16 7:30 ` ZHIZHIKIN Andrey
0 siblings, 0 replies; 5+ messages in thread
From: ZHIZHIKIN Andrey @ 2022-05-16 7:30 UTC (permalink / raw)
To: Peng Fan, Peng Fan (OSS), sbabic, festevam, dl-uboot-imx; +Cc: u-boot
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan
> Sent: Monday, May 16, 2022 9:25 AM
> To: ZHIZHIKIN Andrey <andrey.zhizhikin@leica-geosystems.com>; Peng Fan (OSS)
> <peng.fan@oss.nxp.com>; sbabic@denx.de; festevam@gmail.com; dl-uboot-imx <uboot-
> imx@nxp.com>
> Cc: u-boot@lists.denx.de
> Subject: RE: [PATCH] imx: imx8m: drop uneeded check
>
> > Subject: RE: [PATCH] imx: imx8m: drop uneeded check
> >
> > Hello Peng,
> >
> > > -----Original Message-----
> > > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Peng Fan
> > > (OSS)
> > > Sent: Friday, April 29, 2022 10:19 AM
> > > To: sbabic@denx.de; festevam@gmail.com; NXP i.MX U-Boot Team
> > > <uboot-imx@nxp.com>
> > > Cc: u-boot@lists.denx.de; Peng Fan <peng.fan@nxp.com>
> > > Subject: [PATCH] imx: imx8m: drop uneeded check
> > >
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
> > > waste cpu cycles.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > > arch/arm/mach-imx/imx8m/soc.c | 6 ++----
> > > 1 file changed, 2 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-imx/imx8m/soc.c
> > > b/arch/arm/mach-imx/imx8m/soc.c index 8e23e6da326..5240dc11363
> > 100644
> > > --- a/arch/arm/mach-imx/imx8m/soc.c
> > > +++ b/arch/arm/mach-imx/imx8m/soc.c
> > > @@ -72,15 +72,13 @@ void enable_tzc380(void)
> > > * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
> > > * order to avoid AXI Bus errors when GPU is in use
> > > */
> > > - if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
> > > - setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
> > > + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
> >
> > Since you've dropped the SoC-specific check, perhaps you can combine bits set
> > that are done by setbits_le32 together with one below?
>
> Let’s separate them, first set, then lock.
OK, sounds logical.
> >
> > >
> > > /*
> > > * imx8mn and imx8mp implements the lock bit for
> > > * TZASC_ID_SWAP_BYPASS, enable it to lock settings
> > > */
> > > - if (is_imx8mn() || is_imx8mp())
> > > - setbits_le32(&gpr->gpr[10],
> > GPR_TZASC_ID_SWAP_BYPASS_LOCK);
> > > + setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
> >
> > BYPASS_LOCK is not present in i.MX8MM TRM, but I guess you've checked that it
> > is implemented already, right?
>
> Yes. It is implemented. RM needs update.
Understood, thanks for clarifications!
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
>
> Regards,
> Peng.
>
> >
> > >
> > > /*
> > > * set Region 0 attribute to allow secure and non-secure
> > > --
> > > 2.36.0
> >
> > -- andrey
-- andrey
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] imx: imx8m: drop uneeded check
2022-04-29 8:18 [PATCH] imx: imx8m: drop uneeded check Peng Fan (OSS)
2022-05-16 7:21 ` ZHIZHIKIN Andrey
@ 2022-05-20 13:44 ` sbabic
1 sibling, 0 replies; 5+ messages in thread
From: sbabic @ 2022-05-20 13:44 UTC (permalink / raw)
To: Peng Fan (OSS), u-boot
> From: Peng Fan <peng.fan@nxp.com>
> All i.MX8M needs TZASC ID SWAP set and locked, no need the check to
> waste cpu cycles.
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-05-20 13:50 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-29 8:18 [PATCH] imx: imx8m: drop uneeded check Peng Fan (OSS)
2022-05-16 7:21 ` ZHIZHIKIN Andrey
2022-05-16 7:24 ` Peng Fan
2022-05-16 7:30 ` ZHIZHIKIN Andrey
2022-05-20 13:44 ` sbabic
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