From: Peng Fan <peng.fan@nxp.com> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, "Peng Fan (OSS)" <peng.fan@oss.nxp.com>, Abel Vesa <abelvesa@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com> Cc: "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, "imx@lists.linux.dev" <imx@lists.linux.dev>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org> Subject: RE: [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU CSR module Date: Mon, 18 Mar 2024 07:15:35 +0000 [thread overview] Message-ID: <DU0PR04MB9417BA412243B8E3FEC0A46D882D2@DU0PR04MB9417.eurprd04.prod.outlook.com> (raw) In-Reply-To: <99b72931-0007-4ab5-87fb-9b4c3021c1c2@linaro.org> > Subject: Re: [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU > CSR module > > On 14/03/2024 14:25, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The i.MX95 VPU_CSR contains control and status registers for VPU > > status, pending transaction status, and clock gating controls. > > > > This patch is to add clock features for VPU CSR. > > Fix the subject prefix. You mess with people's filters. Sorry, a typo error. Will fix it. > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 > ++++++++++++++++++++++ > > include/dt-bindings/clock/nxp,imx95-clock.h | 14 ++++++ > > 2 files changed, 64 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > new file mode 100644 > > index 000000000000..4a1c6dcfe3f8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > @@ -0,0 +1,50 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fschemas%2Fclock%2Fnxp%2Cimx95-vpu- > csr.yaml%23&data=05%7C > > > +02%7Cpeng.fan%40nxp.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7 > C686ea1d3 > > > +bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638461324818682648%7CUnk > nown%7CTWF > > > +pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > VCI6 > > > +Mn0%3D%7C0%7C%7C%7C&sdata=PtStE2Y%2BnS4HpesF9wE66t8bh0Qmg > 3s3y4aERwhSr > > +Mo%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=05%7C02%7Cpeng.fan%40nx > > > +p.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7C686ea1d3bc2b4c6fa > 92cd99c5c > > > +301635%7C0%7C0%7C638461324818692719%7CUnknown%7CTWFpbGZs > b3d8eyJWIjoiM > > > +C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7 > C%7C%7 > > > +C&sdata=zWKRFnTPTwLZvtOvOrFUo%2FNlqPKRqRIEYCrztlfhzAU%3D&reserv > ed=0 > > + > > +title: NXP i.MX95 VPUMIX Block Control > > + > > +maintainers: > > + - Peng Fan <peng.fan@nxp.com> > > + > > +properties: > > + compatible: > > + items: > > + - const: nxp,imx95-vpu-csr > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + description: > > + The clock consumer should specify the desired clock by having the > clock > > + ID in its "clocks" phandle cell. See > > + include/dt-bindings/clock/nxp,imx95-clock.h > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscon@4c410000 { > > + compatible = "nxp,imx95-vpu-csr", "syscon"; > > + reg = <0x4c410000 0x10000>; > > + #clock-cells = <1>; > > + clocks = <&scmi_clk 114>; > > + power-domains = <&scmi_devpd 21>; > > + }; > > +... > > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h > > b/include/dt-bindings/clock/nxp,imx95-clock.h > > new file mode 100644 > > index 000000000000..9d8f0a6d12d0 > > --- /dev/null > > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h > > If the header is only for clock IDs for this binding, then keep the same > filename as binding filename. No, this file will also include other IDs in following patches. Thanks, Peng. > > Best regards, > Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Peng Fan <peng.fan@nxp.com> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, "Peng Fan (OSS)" <peng.fan@oss.nxp.com>, Abel Vesa <abelvesa@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com> Cc: "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>, "imx@lists.linux.dev" <imx@lists.linux.dev>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org> Subject: RE: [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU CSR module Date: Mon, 18 Mar 2024 07:15:35 +0000 [thread overview] Message-ID: <DU0PR04MB9417BA412243B8E3FEC0A46D882D2@DU0PR04MB9417.eurprd04.prod.outlook.com> (raw) In-Reply-To: <99b72931-0007-4ab5-87fb-9b4c3021c1c2@linaro.org> > Subject: Re: [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU > CSR module > > On 14/03/2024 14:25, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The i.MX95 VPU_CSR contains control and status registers for VPU > > status, pending transaction status, and clock gating controls. > > > > This patch is to add clock features for VPU CSR. > > Fix the subject prefix. You mess with people's filters. Sorry, a typo error. Will fix it. > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 > ++++++++++++++++++++++ > > include/dt-bindings/clock/nxp,imx95-clock.h | 14 ++++++ > > 2 files changed, 64 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > new file mode 100644 > > index 000000000000..4a1c6dcfe3f8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > @@ -0,0 +1,50 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fschemas%2Fclock%2Fnxp%2Cimx95-vpu- > csr.yaml%23&data=05%7C > > > +02%7Cpeng.fan%40nxp.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7 > C686ea1d3 > > > +bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638461324818682648%7CUnk > nown%7CTWF > > > +pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > VCI6 > > > +Mn0%3D%7C0%7C%7C%7C&sdata=PtStE2Y%2BnS4HpesF9wE66t8bh0Qmg > 3s3y4aERwhSr > > +Mo%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=05%7C02%7Cpeng.fan%40nx > > > +p.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7C686ea1d3bc2b4c6fa > 92cd99c5c > > > +301635%7C0%7C0%7C638461324818692719%7CUnknown%7CTWFpbGZs > b3d8eyJWIjoiM > > > +C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7 > C%7C%7 > > > +C&sdata=zWKRFnTPTwLZvtOvOrFUo%2FNlqPKRqRIEYCrztlfhzAU%3D&reserv > ed=0 > > + > > +title: NXP i.MX95 VPUMIX Block Control > > + > > +maintainers: > > + - Peng Fan <peng.fan@nxp.com> > > + > > +properties: > > + compatible: > > + items: > > + - const: nxp,imx95-vpu-csr > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + description: > > + The clock consumer should specify the desired clock by having the > clock > > + ID in its "clocks" phandle cell. See > > + include/dt-bindings/clock/nxp,imx95-clock.h > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscon@4c410000 { > > + compatible = "nxp,imx95-vpu-csr", "syscon"; > > + reg = <0x4c410000 0x10000>; > > + #clock-cells = <1>; > > + clocks = <&scmi_clk 114>; > > + power-domains = <&scmi_devpd 21>; > > + }; > > +... > > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h > > b/include/dt-bindings/clock/nxp,imx95-clock.h > > new file mode 100644 > > index 000000000000..9d8f0a6d12d0 > > --- /dev/null > > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h > > If the header is only for clock IDs for this binding, then keep the same > filename as binding filename. No, this file will also include other IDs in following patches. Thanks, Peng. > > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-03-18 7:15 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-03-14 13:25 [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-14 13:25 ` [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU CSR module Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-15 16:54 ` Rob Herring 2024-03-15 16:54 ` Rob Herring 2024-03-15 20:47 ` Krzysztof Kozlowski 2024-03-15 20:47 ` Krzysztof Kozlowski 2024-03-18 7:15 ` Peng Fan [this message] 2024-03-18 7:15 ` Peng Fan 2024-03-14 13:25 ` [PATCH v4 2/6] dt-bindindgs: clock: nxp: support i.MX95 Camera " Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-15 17:24 ` Rob Herring 2024-03-15 17:24 ` Rob Herring 2024-03-14 13:25 ` [PATCH v4 3/6] dt-bindindgs: clock: nxp: support i.MX95 Display Master " Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-15 17:26 ` Rob Herring 2024-03-15 17:26 ` Rob Herring 2024-03-14 13:25 ` [PATCH v4 4/6] dt-bindindgs: clock: nxp: support i.MX95 LVDS " Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-15 17:27 ` Rob Herring 2024-03-15 17:27 ` Rob Herring 2024-03-14 13:25 ` [PATCH v4 5/6] dt-bindindgs: clock: nxp: support i.MX95 Display " Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-15 20:49 ` Krzysztof Kozlowski 2024-03-15 20:49 ` Krzysztof Kozlowski 2024-03-18 12:37 ` Peng Fan 2024-03-18 12:37 ` Peng Fan 2024-03-18 15:44 ` Krzysztof Kozlowski 2024-03-18 15:44 ` Krzysztof Kozlowski 2024-03-14 13:25 ` [PATCH v4 6/6] clk: imx: add i.MX95 BLK CTL clk driver Peng Fan (OSS) 2024-03-14 13:25 ` Peng Fan (OSS) 2024-03-17 15:59 ` [PATCH v4 0/6] Add support i.MX95 BLK CTL module clock features Marco Felsch 2024-03-17 15:59 ` Marco Felsch 2024-03-18 1:22 ` Peng Fan 2024-03-18 1:22 ` Peng Fan 2024-03-18 9:59 ` Marco Felsch 2024-03-18 9:59 ` Marco Felsch 2024-03-18 11:01 ` Peng Fan 2024-03-18 11:01 ` Peng Fan 2024-03-18 14:07 ` Marco Felsch 2024-03-18 14:07 ` Marco Felsch 2024-03-18 23:11 ` Peng Fan 2024-03-18 23:11 ` Peng Fan 2024-03-19 7:17 ` Marco Felsch 2024-03-19 7:17 ` Marco Felsch
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