[PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Russell King - ARM Linux]

Currently cpu_suspend is not like a normal C function - when it's called
it returns normally to a bunch of code which is not expected to return.
The return path is via code pointed to by 'r3'.

It also corrupts a bunch of registers in ways which make it non-compliant
with a C API.

If we do make this compliant as a normal C-like function, it eliminates
this register saving, and also allows us to make greater savings.  We
also swap 'lr' and 'r3', so cpu_suspend effectively only returns to
following code on resume - and r3 points to the suspend code.

So, this becomes:
static void soc_suspend(void)
{
        [soc specific preparation]

        cpu_suspend(0, PLAT_PHYS_OFFSET - PAGE_OFFSET,
                soc_suspend_arg, soc_finish_suspend);

        [soc specific cleanup ]
}

where soc_suspend_fn can be either assembly or C code - but must never
return.  (See separate patch posted on 13th June to allow it to return.)

This patch series also merges the call to cpu_init() into cpu_suspend(),
and makes cpu_init() call the per-CPU initialization function to ensure
that various registers are setup (eg, clock switching on StrongARM,
read-buffer enabled for userspace, etc.)  This allows some more custom
platform suspend code to be removed.

Lastly, I've made an attempt to (a) clean up OMAP3 suspend support a little
and (b) convert it to use cpu_suspend().  This works, but I've been unable
to test cpuidle as cpuidle doesn't want to enter any of the deeper sleep
states.

The only platform not converted to cpu_suspend() is the shmobile stuff,
which I've requested their assistance with.

This patch set also eliminates about 300 LOC from platform code.

Tested on Assabet (SA1100) and 3430LDP only.

 arch/arm/include/asm/system.h           |    2 +
 arch/arm/kernel/setup.c                 |   99 +++++++++++----------
 arch/arm/kernel/sleep.S                 |   71 ++++++---------
 arch/arm/mach-exynos4/pm.c              |    2 +-
 arch/arm/mach-exynos4/sleep.S           |   22 -----
 arch/arm/mach-omap2/pm34xx.c            |   39 ++-------
 arch/arm/mach-omap2/sleep34xx.S         |  147 ++----------------------------
 arch/arm/mach-pxa/include/mach/pm.h     |    4 +-
 arch/arm/mach-pxa/pm.c                  |    1 -
 arch/arm/mach-pxa/pxa25x.c              |    3 +-
 arch/arm/mach-pxa/pxa27x.c              |   11 ++-
 arch/arm/mach-pxa/pxa3xx.c              |   13 +++-
 arch/arm/mach-pxa/sleep.S               |   55 ++----------
 arch/arm/mach-pxa/zeus.c                |    3 +-
 arch/arm/mach-s3c2412/pm.c              |    4 +-
 arch/arm/mach-s3c2416/pm.c              |    4 +-
 arch/arm/mach-s3c64xx/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/sleep.S           |   23 -----
 arch/arm/mach-s5pv210/pm.c              |    2 +-
 arch/arm/mach-s5pv210/sleep.S           |   21 -----
 arch/arm/mach-sa1100/pm.c               |    6 +-
 arch/arm/mach-sa1100/sleep.S            |   19 +----
 arch/arm/mm/proc-v7.S                   |   10 ++-
 arch/arm/plat-s3c24xx/sleep.S           |   25 -----
 arch/arm/plat-samsung/include/plat/pm.h |    5 +-
 arch/arm/plat-samsung/pm.c              |   10 +--
 26 files changed, 152 insertions(+), 451 deletions(-)

[PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Russell King - ARM Linux]

Currently cpu_suspend is not like a normal C function - when it's called
it returns normally to a bunch of code which is not expected to return.
The return path is via code pointed to by 'r3'.

It also corrupts a bunch of registers in ways which make it non-compliant
with a C API.

If we do make this compliant as a normal C-like function, it eliminates
this register saving, and also allows us to make greater savings.  We
also swap 'lr' and 'r3', so cpu_suspend effectively only returns to
following code on resume - and r3 points to the suspend code.

So, this becomes:
static void soc_suspend(void)
{
        [soc specific preparation]

        cpu_suspend(0, PLAT_PHYS_OFFSET - PAGE_OFFSET,
                soc_suspend_arg, soc_finish_suspend);

        [soc specific cleanup ]
}

where soc_suspend_fn can be either assembly or C code - but must never
return.  (See separate patch posted on 13th June to allow it to return.)

This patch series also merges the call to cpu_init() into cpu_suspend(),
and makes cpu_init() call the per-CPU initialization function to ensure
that various registers are setup (eg, clock switching on StrongARM,
read-buffer enabled for userspace, etc.)  This allows some more custom
platform suspend code to be removed.

Lastly, I've made an attempt to (a) clean up OMAP3 suspend support a little
and (b) convert it to use cpu_suspend().  This works, but I've been unable
to test cpuidle as cpuidle doesn't want to enter any of the deeper sleep
states.

The only platform not converted to cpu_suspend() is the shmobile stuff,
which I've requested their assistance with.

This patch set also eliminates about 300 LOC from platform code.

Tested on Assabet (SA1100) and 3430LDP only.

 arch/arm/include/asm/system.h           |    2 +
 arch/arm/kernel/setup.c                 |   99 +++++++++++----------
 arch/arm/kernel/sleep.S                 |   71 ++++++---------
 arch/arm/mach-exynos4/pm.c              |    2 +-
 arch/arm/mach-exynos4/sleep.S           |   22 -----
 arch/arm/mach-omap2/pm34xx.c            |   39 ++-------
 arch/arm/mach-omap2/sleep34xx.S         |  147 ++----------------------------
 arch/arm/mach-pxa/include/mach/pm.h     |    4 +-
 arch/arm/mach-pxa/pm.c                  |    1 -
 arch/arm/mach-pxa/pxa25x.c              |    3 +-
 arch/arm/mach-pxa/pxa27x.c              |   11 ++-
 arch/arm/mach-pxa/pxa3xx.c              |   13 +++-
 arch/arm/mach-pxa/sleep.S               |   55 ++----------
 arch/arm/mach-pxa/zeus.c                |    3 +-
 arch/arm/mach-s3c2412/pm.c              |    4 +-
 arch/arm/mach-s3c2416/pm.c              |    4 +-
 arch/arm/mach-s3c64xx/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/sleep.S           |   23 -----
 arch/arm/mach-s5pv210/pm.c              |    2 +-
 arch/arm/mach-s5pv210/sleep.S           |   21 -----
 arch/arm/mach-sa1100/pm.c               |    6 +-
 arch/arm/mach-sa1100/sleep.S            |   19 +----
 arch/arm/mm/proc-v7.S                   |   10 ++-
 arch/arm/plat-s3c24xx/sleep.S           |   25 -----
 arch/arm/plat-samsung/include/plat/pm.h |    5 +-
 arch/arm/plat-samsung/pm.c              |   10 +--
 26 files changed, 152 insertions(+), 451 deletions(-)

[PATCH 01/25] ARM: pm: make MULTI_CPU and !MULTI_CPU resume paths the same

[Russell King - ARM Linux]

Eliminate the differences between MULTI_CPU and non-MULTI_CPU resume
paths, making the saved structure identical irrespective of the way
the kernel was configured.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 6398ead..97a6577 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -40,9 +40,11 @@ ENTRY(cpu_suspend)
 #else
 	mov	r2, sp			@ current virtual SP
 	ldr	r0, =cpu_suspend_size
+	ldr	ip, =cpu_do_resume
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
-	stmfd	sp!, {r1, r2, r3}	@ save v:p, virt SP, return fn
+	add	ip, ip, r1		@ convert resume fn to phys
+	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -120,20 +122,12 @@ ENTRY(cpu_resume)
 	ldr	r0, sleep_save_sp	@ stack phys addr
 #endif
 	setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
-#ifdef MULTI_CPU
 	@ load v:p, stack, return fn, resume fn
   ARM(	ldmia	r0!, {r1, sp, lr, pc}	)
 THUMB(	ldmia	r0!, {r1, r2, r3, r4}	)
 THUMB(	mov	sp, r2			)
 THUMB(	mov	lr, r3			)
 THUMB(	bx	r4			)
-#else
-	@ load v:p, stack, return fn
-  ARM(	ldmia	r0!, {r1, sp, lr}	)
-THUMB(	ldmia	r0!, {r1, r2, lr}	)
-THUMB(	mov	sp, r2			)
-	b	cpu_do_resume
-#endif
 ENDPROC(cpu_resume)
 
 sleep_save_sp:
-- 
1.7.4.4

[PATCH 01/25] ARM: pm: make MULTI_CPU and !MULTI_CPU resume paths the same

[Russell King - ARM Linux]

Eliminate the differences between MULTI_CPU and non-MULTI_CPU resume
paths, making the saved structure identical irrespective of the way
the kernel was configured.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 6398ead..97a6577 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -40,9 +40,11 @@ ENTRY(cpu_suspend)
 #else
 	mov	r2, sp			@ current virtual SP
 	ldr	r0, =cpu_suspend_size
+	ldr	ip, =cpu_do_resume
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
-	stmfd	sp!, {r1, r2, r3}	@ save v:p, virt SP, return fn
+	add	ip, ip, r1		@ convert resume fn to phys
+	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -120,20 +122,12 @@ ENTRY(cpu_resume)
 	ldr	r0, sleep_save_sp	@ stack phys addr
 #endif
 	setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
-#ifdef MULTI_CPU
 	@ load v:p, stack, return fn, resume fn
   ARM(	ldmia	r0!, {r1, sp, lr, pc}	)
 THUMB(	ldmia	r0!, {r1, r2, r3, r4}	)
 THUMB(	mov	sp, r2			)
 THUMB(	mov	lr, r3			)
 THUMB(	bx	r4			)
-#else
-	@ load v:p, stack, return fn
-  ARM(	ldmia	r0!, {r1, sp, lr}	)
-THUMB(	ldmia	r0!, {r1, r2, lr}	)
-THUMB(	mov	sp, r2			)
-	b	cpu_do_resume
-#endif
 ENDPROC(cpu_resume)
 
 sleep_save_sp:
-- 
1.7.4.4

[PATCH 02/25] ARM: pm: move return address (for cpu_resume) to top of stack

[Russell King - ARM Linux]

Move the return address for cpu_resume to the top of stack so that
cpu_resume looks more like a normal function.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 97a6577..f8e9251 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -15,6 +15,7 @@
  * r0-r3,r9,r10,lr corrupted
  */
 ENTRY(cpu_suspend)
+	stmfd	sp!, {r3}
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
@@ -24,7 +25,7 @@ ENTRY(cpu_suspend)
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
+	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -44,7 +45,7 @@ ENTRY(cpu_suspend)
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
+	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -99,7 +100,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
-	mov	pc, lr
+	ldmfd	sp!, {pc}
 ENDPROC(cpu_resume_after_mmu)
 
 /*
@@ -122,12 +123,11 @@ ENTRY(cpu_resume)
 	ldr	r0, sleep_save_sp	@ stack phys addr
 #endif
 	setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
-	@ load v:p, stack, return fn, resume fn
-  ARM(	ldmia	r0!, {r1, sp, lr, pc}	)
-THUMB(	ldmia	r0!, {r1, r2, r3, r4}	)
+	@ load v:p, stack, resume fn
+  ARM(	ldmia	r0!, {r1, sp, pc}	)
+THUMB(	ldmia	r0!, {r1, r2, r3}	)
 THUMB(	mov	sp, r2			)
-THUMB(	mov	lr, r3			)
-THUMB(	bx	r4			)
+THUMB(	bx	r3			)
 ENDPROC(cpu_resume)
 
 sleep_save_sp:
-- 
1.7.4.4

[PATCH 02/25] ARM: pm: move return address (for cpu_resume) to top of stack

[Russell King - ARM Linux]

Move the return address for cpu_resume to the top of stack so that
cpu_resume looks more like a normal function.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 97a6577..f8e9251 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -15,6 +15,7 @@
  * r0-r3,r9,r10,lr corrupted
  */
 ENTRY(cpu_suspend)
+	stmfd	sp!, {r3}
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
@@ -24,7 +25,7 @@ ENTRY(cpu_suspend)
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
+	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -44,7 +45,7 @@ ENTRY(cpu_suspend)
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, r3, ip}	@ save v:p, virt SP, retfn, phys resume fn
+	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r3, =sleep_save_sp
 	add	r2, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
@@ -99,7 +100,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
-	mov	pc, lr
+	ldmfd	sp!, {pc}
 ENDPROC(cpu_resume_after_mmu)
 
 /*
@@ -122,12 +123,11 @@ ENTRY(cpu_resume)
 	ldr	r0, sleep_save_sp	@ stack phys addr
 #endif
 	setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
-	@ load v:p, stack, return fn, resume fn
-  ARM(	ldmia	r0!, {r1, sp, lr, pc}	)
-THUMB(	ldmia	r0!, {r1, r2, r3, r4}	)
+	@ load v:p, stack, resume fn
+  ARM(	ldmia	r0!, {r1, sp, pc}	)
+THUMB(	ldmia	r0!, {r1, r2, r3}	)
 THUMB(	mov	sp, r2			)
-THUMB(	mov	lr, r3			)
-THUMB(	bx	r4			)
+THUMB(	bx	r3			)
 ENDPROC(cpu_resume)
 
 sleep_save_sp:
-- 
1.7.4.4

[PATCH 03/25] ARM: pm: extract common code from MULTI_CPU/!MULTI_CPU paths

[Russell King - ARM Linux]

Very little code is different between these two paths now, so extract
the common code.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   24 ++++++------------------
 1 files changed, 6 insertions(+), 18 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index f8e9251..0a778c3 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -19,29 +19,13 @@ ENTRY(cpu_suspend)
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
-	mov	r2, sp			@ current virtual SP
 	ldr	r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
 	ldr	ip, [r10, #CPU_DO_RESUME] @ virtual resume function
-	sub	sp, sp, r0		@ allocate CPU state on stack
-	mov	r0, sp			@ save pointer
-	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
-	ldr	r3, =sleep_save_sp
-	add	r2, sp, r1		@ convert SP to phys
-#ifdef CONFIG_SMP
-	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-	ALT_UP(mov lr, #0)
-	and	lr, lr, #15
-	str	r2, [r3, lr, lsl #2]	@ save phys SP
 #else
-	str	r2, [r3]		@ save phys SP
-#endif
-	mov	lr, pc
-	ldr	pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
-#else
-	mov	r2, sp			@ current virtual SP
 	ldr	r0, =cpu_suspend_size
 	ldr	ip, =cpu_do_resume
+#endif
+	mov	r2, sp			@ current virtual SP
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
@@ -56,6 +40,10 @@ ENTRY(cpu_suspend)
 #else
 	str	r2, [r3]		@ save phys SP
 #endif
+#ifdef MULTI_CPU
+	mov	lr, pc
+	ldr	pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
+#else
 	bl	cpu_do_suspend
 #endif
 
-- 
1.7.4.4

[PATCH 03/25] ARM: pm: extract common code from MULTI_CPU/!MULTI_CPU paths

[Russell King - ARM Linux]

Very little code is different between these two paths now, so extract
the common code.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   24 ++++++------------------
 1 files changed, 6 insertions(+), 18 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index f8e9251..0a778c3 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -19,29 +19,13 @@ ENTRY(cpu_suspend)
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
-	mov	r2, sp			@ current virtual SP
 	ldr	r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
 	ldr	ip, [r10, #CPU_DO_RESUME] @ virtual resume function
-	sub	sp, sp, r0		@ allocate CPU state on stack
-	mov	r0, sp			@ save pointer
-	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
-	ldr	r3, =sleep_save_sp
-	add	r2, sp, r1		@ convert SP to phys
-#ifdef CONFIG_SMP
-	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-	ALT_UP(mov lr, #0)
-	and	lr, lr, #15
-	str	r2, [r3, lr, lsl #2]	@ save phys SP
 #else
-	str	r2, [r3]		@ save phys SP
-#endif
-	mov	lr, pc
-	ldr	pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
-#else
-	mov	r2, sp			@ current virtual SP
 	ldr	r0, =cpu_suspend_size
 	ldr	ip, =cpu_do_resume
+#endif
+	mov	r2, sp			@ current virtual SP
 	sub	sp, sp, r0		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
@@ -56,6 +40,10 @@ ENTRY(cpu_suspend)
 #else
 	str	r2, [r3]		@ save phys SP
 #endif
+#ifdef MULTI_CPU
+	mov	lr, pc
+	ldr	pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
+#else
 	bl	cpu_do_suspend
 #endif
 
-- 
1.7.4.4

[PATCH 04/25] ARM: pm: preserve r4 - r11 across a suspend

[Russell King - ARM Linux]

Make cpu_suspend()..return function preserve r4 to r11 across a suspend
cycle.  This is in preparation of relieving platform support code from
this task.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 0a778c3..8dbca93 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -12,10 +12,11 @@
  *  r1 = v:p offset
  *  r3 = virtual return function
  * Note: sp is decremented to allocate space for CPU state on stack
- * r0-r3,r9,r10,lr corrupted
+ * r0-r3,ip,lr corrupted
  */
 ENTRY(cpu_suspend)
 	stmfd	sp!, {r3}
+	stmfd	sp!, {r4 - r11}
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
@@ -88,7 +89,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
-	ldmfd	sp!, {pc}
+	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_resume_after_mmu)
 
 /*
-- 
1.7.4.4

[PATCH 04/25] ARM: pm: preserve r4 - r11 across a suspend

[Russell King - ARM Linux]

Make cpu_suspend()..return function preserve r4 to r11 across a suspend
cycle.  This is in preparation of relieving platform support code from
this task.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 0a778c3..8dbca93 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -12,10 +12,11 @@
  *  r1 = v:p offset
  *  r3 = virtual return function
  * Note: sp is decremented to allocate space for CPU state on stack
- * r0-r3,r9,r10,lr corrupted
+ * r0-r3,ip,lr corrupted
  */
 ENTRY(cpu_suspend)
 	stmfd	sp!, {r3}
+	stmfd	sp!, {r4 - r11}
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
@@ -88,7 +89,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
-	ldmfd	sp!, {pc}
+	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_resume_after_mmu)
 
 /*
-- 
1.7.4.4

[PATCH 05/25] ARM: pm: reallocate registers to avoid r2, r3

[Russell King - ARM Linux]

Avoid using r2 and r3 in the suspend code, allowing these to be
passed further into the function as arguments.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 8dbca93..358be13 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -20,26 +20,26 @@ ENTRY(cpu_suspend)
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
-	ldr	r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
+	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
 	ldr	ip, [r10, #CPU_DO_RESUME] @ virtual resume function
 #else
-	ldr	r0, =cpu_suspend_size
+	ldr	r5, =cpu_suspend_size
 	ldr	ip, =cpu_do_resume
 #endif
-	mov	r2, sp			@ current virtual SP
-	sub	sp, sp, r0		@ allocate CPU state on stack
+	mov	r6, sp			@ current virtual SP
+	sub	sp, sp, r5		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
-	ldr	r3, =sleep_save_sp
-	add	r2, sp, r1		@ convert SP to phys
+	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
+	ldr	r5, =sleep_save_sp
+	add	r6, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
 	and	lr, lr, #15
-	str	r2, [r3, lr, lsl #2]	@ save phys SP
+	str	r6, [r5, lr, lsl #2]	@ save phys SP
 #else
-	str	r2, [r3]		@ save phys SP
+	str	r6, [r5]		@ save phys SP
 #endif
 #ifdef MULTI_CPU
 	mov	lr, pc
-- 
1.7.4.4

[PATCH 05/25] ARM: pm: reallocate registers to avoid r2, r3

[Russell King - ARM Linux]

Avoid using r2 and r3 in the suspend code, allowing these to be
passed further into the function as arguments.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 8dbca93..358be13 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -20,26 +20,26 @@ ENTRY(cpu_suspend)
 	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
-	ldr	r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
+	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
 	ldr	ip, [r10, #CPU_DO_RESUME] @ virtual resume function
 #else
-	ldr	r0, =cpu_suspend_size
+	ldr	r5, =cpu_suspend_size
 	ldr	ip, =cpu_do_resume
 #endif
-	mov	r2, sp			@ current virtual SP
-	sub	sp, sp, r0		@ allocate CPU state on stack
+	mov	r6, sp			@ current virtual SP
+	sub	sp, sp, r5		@ allocate CPU state on stack
 	mov	r0, sp			@ save pointer
 	add	ip, ip, r1		@ convert resume fn to phys
-	stmfd	sp!, {r1, r2, ip}	@ save v:p, virt SP, phys resume fn
-	ldr	r3, =sleep_save_sp
-	add	r2, sp, r1		@ convert SP to phys
+	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
+	ldr	r5, =sleep_save_sp
+	add	r6, sp, r1		@ convert SP to phys
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
 	and	lr, lr, #15
-	str	r2, [r3, lr, lsl #2]	@ save phys SP
+	str	r6, [r5, lr, lsl #2]	@ save phys SP
 #else
-	str	r2, [r3]		@ save phys SP
+	str	r6, [r5]		@ save phys SP
 #endif
 #ifdef MULTI_CPU
 	mov	lr, pc
-- 
1.7.4.4

[PATCH 06/25] ARM: pm: rejig suspend follow-on function calling convention

[Russell King - ARM Linux]

Save the suspend function pointer onto the stack for use when returning.
Allocate r2 to pass an argument to the suspend function.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 358be13..b924bcc 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -10,6 +10,7 @@
 /*
  * Save CPU state for a suspend
  *  r1 = v:p offset
+ *  r2 = suspend function arg0
  *  r3 = virtual return function
  * Note: sp is decremented to allocate space for CPU state on stack
  * r0-r3,ip,lr corrupted
@@ -17,7 +18,6 @@
 ENTRY(cpu_suspend)
 	stmfd	sp!, {r3}
 	stmfd	sp!, {r4 - r11}
-	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
 	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
@@ -33,6 +33,7 @@ ENTRY(cpu_suspend)
 	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r5, =sleep_save_sp
 	add	r6, sp, r1		@ convert SP to phys
+	stmfd	sp!, {r2, lr}		@ save suspend func arg and pointer
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
@@ -51,12 +52,12 @@ ENTRY(cpu_suspend)
 	@ flush data cache
 #ifdef MULTI_CACHE
 	ldr	r10, =cpu_cache
-	mov	lr, r9
+	mov	lr, pc
 	ldr	pc, [r10, #CACHE_FLUSH_KERN_ALL]
 #else
-	mov	lr, r9
-	b	__cpuc_flush_kern_all
+	bl	__cpuc_flush_kern_all
 #endif
+	ldmfd	sp!, {r0, pc}		@ call suspend fn
 ENDPROC(cpu_suspend)
 	.ltorg
 
-- 
1.7.4.4

[PATCH 06/25] ARM: pm: rejig suspend follow-on function calling convention

[Russell King - ARM Linux]

Save the suspend function pointer onto the stack for use when returning.
Allocate r2 to pass an argument to the suspend function.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 358be13..b924bcc 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -10,6 +10,7 @@
 /*
  * Save CPU state for a suspend
  *  r1 = v:p offset
+ *  r2 = suspend function arg0
  *  r3 = virtual return function
  * Note: sp is decremented to allocate space for CPU state on stack
  * r0-r3,ip,lr corrupted
@@ -17,7 +18,6 @@
 ENTRY(cpu_suspend)
 	stmfd	sp!, {r3}
 	stmfd	sp!, {r4 - r11}
-	mov	r9, lr
 #ifdef MULTI_CPU
 	ldr	r10, =processor
 	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
@@ -33,6 +33,7 @@ ENTRY(cpu_suspend)
 	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r5, =sleep_save_sp
 	add	r6, sp, r1		@ convert SP to phys
+	stmfd	sp!, {r2, lr}		@ save suspend func arg and pointer
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
@@ -51,12 +52,12 @@ ENTRY(cpu_suspend)
 	@ flush data cache
 #ifdef MULTI_CACHE
 	ldr	r10, =cpu_cache
-	mov	lr, r9
+	mov	lr, pc
 	ldr	pc, [r10, #CACHE_FLUSH_KERN_ALL]
 #else
-	mov	lr, r9
-	b	__cpuc_flush_kern_all
+	bl	__cpuc_flush_kern_all
 #endif
+	ldmfd	sp!, {r0, pc}		@ call suspend fn
 ENDPROC(cpu_suspend)
 	.ltorg
 
-- 
1.7.4.4

[PATCH 07/25] ARM: pm: move sa1100 to use proper suspend func arg0

[Russell King - ARM Linux]

In the previous commit, we introduced an official way to supply an
argument to the suspend function.  Convert the sa1100 suspend code
to use this method.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/sleep.S |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 6f53688..613ddfa 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -59,7 +59,7 @@ ENTRY(pxa27x_cpu_suspend)
 	mra	r2, r3, acc0
 #endif
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
-	mov	r4, r0				@ save sleep mode
+	mov	r2, r0				@ save sleep mode
 	ldr	r3, =pxa_cpu_resume		@ resume function
 	bl	cpu_suspend
 
@@ -67,7 +67,7 @@ ENTRY(pxa27x_cpu_suspend)
 	@ (also workaround for sighting 28071)
 
 	@ prepare value for sleep mode
-	mov	r1, r4				@ sleep mode
+	mov	r1, r0				@ sleep mode
 
 	@ prepare pointer to physical address 0 (virtual mapping in generic.c)
 	mov	r2, #UNCACHED_PHYS_0
@@ -109,11 +109,11 @@ ENTRY(pxa27x_cpu_suspend)
 
 ENTRY(pxa25x_cpu_suspend)
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
-	mov	r4, r0				@ save sleep mode
+	mov	r2, r0				@ save sleep mode
 	ldr	r3, =pxa_cpu_resume		@ resume function
 	bl	cpu_suspend
 	@ prepare value for sleep mode
-	mov	r1, r4				@ sleep mode
+	mov	r1, r0				@ sleep mode
 
 	@ prepare pointer to physical address 0 (virtual mapping in generic.c)
 	mov	r2, #UNCACHED_PHYS_0
-- 
1.7.4.4

[PATCH 07/25] ARM: pm: move sa1100 to use proper suspend func arg0

[Russell King - ARM Linux]

In the previous commit, we introduced an official way to supply an
argument to the suspend function.  Convert the sa1100 suspend code
to use this method.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/sleep.S |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 6f53688..613ddfa 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -59,7 +59,7 @@ ENTRY(pxa27x_cpu_suspend)
 	mra	r2, r3, acc0
 #endif
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
-	mov	r4, r0				@ save sleep mode
+	mov	r2, r0				@ save sleep mode
 	ldr	r3, =pxa_cpu_resume		@ resume function
 	bl	cpu_suspend
 
@@ -67,7 +67,7 @@ ENTRY(pxa27x_cpu_suspend)
 	@ (also workaround for sighting 28071)
 
 	@ prepare value for sleep mode
-	mov	r1, r4				@ sleep mode
+	mov	r1, r0				@ sleep mode
 
 	@ prepare pointer to physical address 0 (virtual mapping in generic.c)
 	mov	r2, #UNCACHED_PHYS_0
@@ -109,11 +109,11 @@ ENTRY(pxa27x_cpu_suspend)
 
 ENTRY(pxa25x_cpu_suspend)
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
-	mov	r4, r0				@ save sleep mode
+	mov	r2, r0				@ save sleep mode
 	ldr	r3, =pxa_cpu_resume		@ resume function
 	bl	cpu_suspend
 	@ prepare value for sleep mode
-	mov	r1, r4				@ sleep mode
+	mov	r1, r0				@ sleep mode
 
 	@ prepare pointer to physical address 0 (virtual mapping in generic.c)
 	mov	r2, #UNCACHED_PHYS_0
-- 
1.7.4.4

[PATCH 08/25] ARM: pm: convert cpu_suspend() to a normal function

[Russell King - ARM Linux]

cpu_suspend() has a weird calling method which makes it only possible to
call from assembly code: it returns with a modified stack pointer to
finish the suspend, but on resume, it 'returns' via a provided pointer.

We can make cpu_suspend() appear to be a normal function merely by
swapping the resume pointer argument and the link register.

Do so, and update all callers to take account of this more traditional
behaviour.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/include/asm/system.h |    2 ++
 arch/arm/kernel/sleep.S       |   10 ++++------
 arch/arm/mach-exynos4/sleep.S |    7 +++----
 arch/arm/mach-pxa/sleep.S     |   13 ++++++++++---
 arch/arm/mach-s3c64xx/sleep.S |    9 +++------
 arch/arm/mach-s5pv210/sleep.S |    7 +++----
 arch/arm/mach-sa1100/sleep.S  |   15 ++++-----------
 arch/arm/plat-s3c24xx/sleep.S |   10 +++-------
 8 files changed, 32 insertions(+), 41 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832888d..50be605 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -106,6 +106,8 @@ extern void __show_regs(struct pt_regs *);
 
 extern int cpu_architecture(void);
 extern void cpu_init(void);
+extern void cpu_suspend(int, long, unsigned long, void (*)(unsigned long));
+extern void cpu_resume(void);
 
 void arm_machine_restart(char mode, const char *cmd);
 extern void (*arm_pm_restart)(char str, const char *cmd);
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index b924bcc..e062677 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -11,13 +11,11 @@
  * Save CPU state for a suspend
  *  r1 = v:p offset
  *  r2 = suspend function arg0
- *  r3 = virtual return function
- * Note: sp is decremented to allocate space for CPU state on stack
- * r0-r3,ip,lr corrupted
+ *  r3 = suspend function
+ * Note: does not return until system resumes
  */
 ENTRY(cpu_suspend)
-	stmfd	sp!, {r3}
-	stmfd	sp!, {r4 - r11}
+	stmfd	sp!, {r4 - r11, lr}
 #ifdef MULTI_CPU
 	ldr	r10, =processor
 	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
@@ -33,7 +31,7 @@ ENTRY(cpu_suspend)
 	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r5, =sleep_save_sp
 	add	r6, sp, r1		@ convert SP to phys
-	stmfd	sp!, {r2, lr}		@ save suspend func arg and pointer
+	stmfd	sp!, {r2, r3}		@ save suspend func arg and pointer
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index 6b62425..d9a2287 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -42,16 +42,15 @@
 ENTRY(s3c_cpu_save)
 
 	stmfd	sp!, { r3 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(exynos4_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r3 - r12, pc }
 
+exynos4_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 
-resume_with_mmu:
-	ldmfd	sp!, { r3 - r12, pc }
-
 	.ltorg
 
 	/*
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 613ddfa..3a67887 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -35,9 +35,11 @@ ENTRY(pxa3xx_cpu_suspend)
 #endif
 	stmfd	sp!, {r2 - r12, lr}	@ save registers on stack
 	mov	r1, r0
-	ldr	r3, =pxa_cpu_resume	@ resume function
+	adr	r3, BSYM(pxa3xx_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
 
+pxa3xx_finish_suspend:
 	mov	r0, #0x06		@ S2D3C4 mode
 	mcr	p14, 0, r0, c7, c0, 0	@ enter sleep
 
@@ -60,9 +62,11 @@ ENTRY(pxa27x_cpu_suspend)
 #endif
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
-	ldr	r3, =pxa_cpu_resume		@ resume function
+	adr	r3, BSYM(pxa27x_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
 
+pxa27x_finish_suspend:
 	@ Put the processor to sleep
 	@ (also workaround for sighting 28071)
 
@@ -110,8 +114,11 @@ ENTRY(pxa27x_cpu_suspend)
 ENTRY(pxa25x_cpu_suspend)
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
-	ldr	r3, =pxa_cpu_resume		@ resume function
+	adr	r3, BSYM(pxa25x_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
+
+pxa25x_finish_suspend:
 	@ prepare value for sleep mode
 	mov	r1, r0				@ sleep mode
 
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index 1f87732..dc4f582 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -36,18 +36,15 @@
 
 ENTRY(s3c_cpu_save)
 	stmfd	sp!, { r4 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s3c64xx_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r4 - r12, pc }
 
+s3c64xx_finish_suspend:
 	@@ call final suspend code
 	ldr	r0, =pm_cpu_sleep
 	ldr	pc, [r0]
 	
-	@@ return to the caller, after the MMU is turned on.
-	@@ restore the last bits of the stack and return.
-resume_with_mmu:
-	ldmfd	sp!, { r4 - r12, pc }	@ return, from sp from s3c_cpu_save
-
 	/* Sleep magic, the word before the resume entry point so that the
 	 * bootloader can check for a resumeable image. */
 
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index a3d6494..1182fc8 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -41,16 +41,15 @@
 ENTRY(s3c_cpu_save)
 
 	stmfd	sp!, { r3 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s5pv210_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r3 - r12, pc }
 
+s5pv210_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 
-resume_with_mmu:
-	ldmfd	sp!, { r3 - r12, pc }
-
 	.ltorg
 
 	/* sleep magic, to allow the bootloader to check for an valid
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 04f2a61..214f4e2 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -31,9 +31,12 @@
 ENTRY(sa1100_cpu_suspend)
 	stmfd	sp!, {r4 - r12, lr}		@ save registers on stack
 	mov	r1, r0
-	ldr	r3, =sa1100_cpu_resume		@ return function
+	adr	r3, BSYM(sa1100_finish_suspend)
 	bl	cpu_suspend
+	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
+	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
 
+sa1100_finish_suspend:
 	@ disable clock switching
 	mcr	p15, 0, r1, c15, c2, 2
 
@@ -139,13 +142,3 @@ sa1110_sdram_controller_fix:
 	str	r13, [r12]
 
 20:	b	20b			@ loop waiting for sleep
-
-/*
- * cpu_sa1100_resume()
- *
- * entry point from bootloader into kernel during resume
- */
-	.align 5
-sa1100_cpu_resume:
-	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index fd7032f..f822e62 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -49,21 +49,17 @@
 
 ENTRY(s3c_cpu_save)
 	stmfd	sp!, { r4 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s3c24xx_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r4 - r12, pc }
 
+s3c24xx_finish_suspend:
 	@@ jump to final code to send system to sleep
 	ldr	r0, =pm_cpu_sleep
 	@@ldr	pc, [ r0 ]
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 	
-	@@ return to the caller, after having the MMU
-	@@ turned on, this restores the last bits from the
-	@@ stack
-resume_with_mmu:
-	ldmfd	sp!, { r4 - r12, pc }
-
 	.ltorg
 
 	/* sleep magic, to allow the bootloader to check for an valid
-- 
1.7.4.4

[PATCH 08/25] ARM: pm: convert cpu_suspend() to a normal function

[Russell King - ARM Linux]

cpu_suspend() has a weird calling method which makes it only possible to
call from assembly code: it returns with a modified stack pointer to
finish the suspend, but on resume, it 'returns' via a provided pointer.

We can make cpu_suspend() appear to be a normal function merely by
swapping the resume pointer argument and the link register.

Do so, and update all callers to take account of this more traditional
behaviour.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/include/asm/system.h |    2 ++
 arch/arm/kernel/sleep.S       |   10 ++++------
 arch/arm/mach-exynos4/sleep.S |    7 +++----
 arch/arm/mach-pxa/sleep.S     |   13 ++++++++++---
 arch/arm/mach-s3c64xx/sleep.S |    9 +++------
 arch/arm/mach-s5pv210/sleep.S |    7 +++----
 arch/arm/mach-sa1100/sleep.S  |   15 ++++-----------
 arch/arm/plat-s3c24xx/sleep.S |   10 +++-------
 8 files changed, 32 insertions(+), 41 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 832888d..50be605 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -106,6 +106,8 @@ extern void __show_regs(struct pt_regs *);
 
 extern int cpu_architecture(void);
 extern void cpu_init(void);
+extern void cpu_suspend(int, long, unsigned long, void (*)(unsigned long));
+extern void cpu_resume(void);
 
 void arm_machine_restart(char mode, const char *cmd);
 extern void (*arm_pm_restart)(char str, const char *cmd);
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index b924bcc..e062677 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -11,13 +11,11 @@
  * Save CPU state for a suspend
  *  r1 = v:p offset
  *  r2 = suspend function arg0
- *  r3 = virtual return function
- * Note: sp is decremented to allocate space for CPU state on stack
- * r0-r3,ip,lr corrupted
+ *  r3 = suspend function
+ * Note: does not return until system resumes
  */
 ENTRY(cpu_suspend)
-	stmfd	sp!, {r3}
-	stmfd	sp!, {r4 - r11}
+	stmfd	sp!, {r4 - r11, lr}
 #ifdef MULTI_CPU
 	ldr	r10, =processor
 	ldr	r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
@@ -33,7 +31,7 @@ ENTRY(cpu_suspend)
 	stmfd	sp!, {r1, r6, ip}	@ save v:p, virt SP, phys resume fn
 	ldr	r5, =sleep_save_sp
 	add	r6, sp, r1		@ convert SP to phys
-	stmfd	sp!, {r2, lr}		@ save suspend func arg and pointer
+	stmfd	sp!, {r2, r3}		@ save suspend func arg and pointer
 #ifdef CONFIG_SMP
 	ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
 	ALT_UP(mov lr, #0)
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index 6b62425..d9a2287 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -42,16 +42,15 @@
 ENTRY(s3c_cpu_save)
 
 	stmfd	sp!, { r3 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(exynos4_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r3 - r12, pc }
 
+exynos4_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 
-resume_with_mmu:
-	ldmfd	sp!, { r3 - r12, pc }
-
 	.ltorg
 
 	/*
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 613ddfa..3a67887 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -35,9 +35,11 @@ ENTRY(pxa3xx_cpu_suspend)
 #endif
 	stmfd	sp!, {r2 - r12, lr}	@ save registers on stack
 	mov	r1, r0
-	ldr	r3, =pxa_cpu_resume	@ resume function
+	adr	r3, BSYM(pxa3xx_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
 
+pxa3xx_finish_suspend:
 	mov	r0, #0x06		@ S2D3C4 mode
 	mcr	p14, 0, r0, c7, c0, 0	@ enter sleep
 
@@ -60,9 +62,11 @@ ENTRY(pxa27x_cpu_suspend)
 #endif
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
-	ldr	r3, =pxa_cpu_resume		@ resume function
+	adr	r3, BSYM(pxa27x_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
 
+pxa27x_finish_suspend:
 	@ Put the processor to sleep
 	@ (also workaround for sighting 28071)
 
@@ -110,8 +114,11 @@ ENTRY(pxa27x_cpu_suspend)
 ENTRY(pxa25x_cpu_suspend)
 	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
-	ldr	r3, =pxa_cpu_resume		@ resume function
+	adr	r3, BSYM(pxa25x_finish_suspend)
 	bl	cpu_suspend
+	b	pxa_cpu_resume
+
+pxa25x_finish_suspend:
 	@ prepare value for sleep mode
 	mov	r1, r0				@ sleep mode
 
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index 1f87732..dc4f582 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -36,18 +36,15 @@
 
 ENTRY(s3c_cpu_save)
 	stmfd	sp!, { r4 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s3c64xx_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r4 - r12, pc }
 
+s3c64xx_finish_suspend:
 	@@ call final suspend code
 	ldr	r0, =pm_cpu_sleep
 	ldr	pc, [r0]
 	
-	@@ return to the caller, after the MMU is turned on.
-	@@ restore the last bits of the stack and return.
-resume_with_mmu:
-	ldmfd	sp!, { r4 - r12, pc }	@ return, from sp from s3c_cpu_save
-
 	/* Sleep magic, the word before the resume entry point so that the
 	 * bootloader can check for a resumeable image. */
 
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index a3d6494..1182fc8 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -41,16 +41,15 @@
 ENTRY(s3c_cpu_save)
 
 	stmfd	sp!, { r3 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s5pv210_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r3 - r12, pc }
 
+s5pv210_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 
-resume_with_mmu:
-	ldmfd	sp!, { r3 - r12, pc }
-
 	.ltorg
 
 	/* sleep magic, to allow the bootloader to check for an valid
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 04f2a61..214f4e2 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -31,9 +31,12 @@
 ENTRY(sa1100_cpu_suspend)
 	stmfd	sp!, {r4 - r12, lr}		@ save registers on stack
 	mov	r1, r0
-	ldr	r3, =sa1100_cpu_resume		@ return function
+	adr	r3, BSYM(sa1100_finish_suspend)
 	bl	cpu_suspend
+	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
+	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
 
+sa1100_finish_suspend:
 	@ disable clock switching
 	mcr	p15, 0, r1, c15, c2, 2
 
@@ -139,13 +142,3 @@ sa1110_sdram_controller_fix:
 	str	r13, [r12]
 
 20:	b	20b			@ loop waiting for sleep
-
-/*
- * cpu_sa1100_resume()
- *
- * entry point from bootloader into kernel during resume
- */
-	.align 5
-sa1100_cpu_resume:
-	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index fd7032f..f822e62 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -49,21 +49,17 @@
 
 ENTRY(s3c_cpu_save)
 	stmfd	sp!, { r4 - r12, lr }
-	ldr	r3, =resume_with_mmu
+	adr	r3, BSYM(s3c24xx_finish_suspend)
 	bl	cpu_suspend
+	ldmfd	sp!, { r4 - r12, pc }
 
+s3c24xx_finish_suspend:
 	@@ jump to final code to send system to sleep
 	ldr	r0, =pm_cpu_sleep
 	@@ldr	pc, [ r0 ]
 	ldr	r0, [ r0 ]
 	mov	pc, r0
 	
-	@@ return to the caller, after having the MMU
-	@@ turned on, this restores the last bits from the
-	@@ stack
-resume_with_mmu:
-	ldmfd	sp!, { r4 - r12, pc }
-
 	.ltorg
 
 	/* sleep magic, to allow the bootloader to check for an valid
-- 
1.7.4.4

[PATCH 09/25] ARM: pm: plat-s3c24xx: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/plat-s3c24xx/sleep.S |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index f822e62..6ada459 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -48,10 +48,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-	stmfd	sp!, { r4 - r12, lr }
 	adr	r3, BSYM(s3c24xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r4 - r12, pc }
+	b	cpu_suspend
 
 s3c24xx_finish_suspend:
 	@@ jump to final code to send system to sleep
-- 
1.7.4.4

[PATCH 09/25] ARM: pm: plat-s3c24xx: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/plat-s3c24xx/sleep.S |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index f822e62..6ada459 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -48,10 +48,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-	stmfd	sp!, { r4 - r12, lr }
 	adr	r3, BSYM(s3c24xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r4 - r12, pc }
+	b	cpu_suspend
 
 s3c24xx_finish_suspend:
 	@@ jump to final code to send system to sleep
-- 
1.7.4.4

[PATCH 10/25] ARM: pm: sa1100: cleanup sa1100_cpu_suspend

[Russell King - ARM Linux]

sa1100_cpu_suspend does not need to save any registers to the stack
with the new cpu_suspend calling convention.  Remove these redundant
instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/sleep.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 214f4e2..e814b60 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -29,12 +29,12 @@
  */
 
 ENTRY(sa1100_cpu_suspend)
-	stmfd	sp!, {r4 - r12, lr}		@ save registers on stack
+	mov	r9, lr
 	mov	r1, r0
 	adr	r3, BSYM(sa1100_finish_suspend)
 	bl	cpu_suspend
 	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
+	mov	pc, r9				@ return to caller
 
 sa1100_finish_suspend:
 	@ disable clock switching
-- 
1.7.4.4

[PATCH 10/25] ARM: pm: sa1100: cleanup sa1100_cpu_suspend

[Russell King - ARM Linux]

sa1100_cpu_suspend does not need to save any registers to the stack
with the new cpu_suspend calling convention.  Remove these redundant
instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/sleep.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 214f4e2..e814b60 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -29,12 +29,12 @@
  */
 
 ENTRY(sa1100_cpu_suspend)
-	stmfd	sp!, {r4 - r12, lr}		@ save registers on stack
+	mov	r9, lr
 	mov	r1, r0
 	adr	r3, BSYM(sa1100_finish_suspend)
 	bl	cpu_suspend
 	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
+	mov	pc, r9				@ return to caller
 
 sa1100_finish_suspend:
 	@ disable clock switching
-- 
1.7.4.4

[PATCH 11/25] ARM: pm: mach-s5pv210: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s5pv210/sleep.S |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 1182fc8..28dfeff 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -39,11 +39,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-
-	stmfd	sp!, { r3 - r12, lr }
 	adr	r3, BSYM(s5pv210_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r3 - r12, pc }
+	b	cpu_suspend
 
 s5pv210_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
-- 
1.7.4.4

[PATCH 11/25] ARM: pm: mach-s5pv210: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s5pv210/sleep.S |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 1182fc8..28dfeff 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -39,11 +39,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-
-	stmfd	sp!, { r3 - r12, lr }
 	adr	r3, BSYM(s5pv210_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r3 - r12, pc }
+	b	cpu_suspend
 
 s5pv210_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
-- 
1.7.4.4

[PATCH 12/25] ARM: pm: mach-exynos4: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-exynos4/sleep.S |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index d9a2287..b56a491 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -40,11 +40,8 @@
 	 */
 
 ENTRY(s3c_cpu_save)
-
-	stmfd	sp!, { r3 - r12, lr }
 	adr	r3, BSYM(exynos4_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r3 - r12, pc }
+	b	cpu_suspend
 
 exynos4_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
-- 
1.7.4.4

[PATCH 12/25] ARM: pm: mach-exynos4: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-exynos4/sleep.S |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index d9a2287..b56a491 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -40,11 +40,8 @@
 	 */
 
 ENTRY(s3c_cpu_save)
-
-	stmfd	sp!, { r3 - r12, lr }
 	adr	r3, BSYM(exynos4_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r3 - r12, pc }
+	b	cpu_suspend
 
 exynos4_finish_suspend:
 	ldr	r0, =pm_cpu_sleep
-- 
1.7.4.4

[PATCH 13/25] ARM: pm: mach-s3c64xx: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s3c64xx/sleep.S |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index dc4f582..2fd3433 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -35,10 +35,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-	stmfd	sp!, { r4 - r12, lr }
 	adr	r3, BSYM(s3c64xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r4 - r12, pc }
+	b	cpu_suspend
 
 s3c64xx_finish_suspend:
 	@@ call final suspend code
-- 
1.7.4.4

[PATCH 13/25] ARM: pm: mach-s3c64xx: cleanup s3c_cpu_save

[Russell King - ARM Linux]

s3c_cpu_save does not need to save any registers with the new
cpu_suspend calling convention.  Remove these redundant instructions.

Acked-by: Frank Hofmann <frank.hofmann@tomtom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s3c64xx/sleep.S |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index dc4f582..2fd3433 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -35,10 +35,8 @@
 	*/
 
 ENTRY(s3c_cpu_save)
-	stmfd	sp!, { r4 - r12, lr }
 	adr	r3, BSYM(s3c64xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, { r4 - r12, pc }
+	b	cpu_suspend
 
 s3c64xx_finish_suspend:
 	@@ call final suspend code
-- 
1.7.4.4

[PATCH 14/25] ARM: pm: pxa: cleanup PXA suspend code

[Russell King - ARM Linux]

Remove now redundant stacking of registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/sleep.S |   33 +++++++++++++--------------------
 1 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 3a67887..cd39293 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -33,11 +33,15 @@ ENTRY(pxa3xx_cpu_suspend)
 #ifndef CONFIG_IWMMXT
 	mra	r2, r3, acc0
 #endif
-	stmfd	sp!, {r2 - r12, lr}	@ save registers on stack
+	stmfd	sp!, {r2, r3, lr}	@ save registers on stack
 	mov	r1, r0
 	adr	r3, BSYM(pxa3xx_finish_suspend)
 	bl	cpu_suspend
-	b	pxa_cpu_resume
+	ldmfd	sp!, {r2, r3, lr}
+#ifndef CONFIG_IWMMXT
+	mar	acc0, r2, r3
+#endif
+	mov	pc, lr
 
 pxa3xx_finish_suspend:
 	mov	r0, #0x06		@ S2D3C4 mode
@@ -60,11 +64,15 @@ ENTRY(pxa27x_cpu_suspend)
 #ifndef CONFIG_IWMMXT
 	mra	r2, r3, acc0
 #endif
-	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
+	stmfd	sp!, {r2, r3, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
 	adr	r3, BSYM(pxa27x_finish_suspend)
 	bl	cpu_suspend
-	b	pxa_cpu_resume
+	ldmfd	sp!, {r2, r3, lr}
+#ifndef CONFIG_IWMMXT
+	mar	acc0, r2, r3
+#endif
+	mov	pc, lr
 
 pxa27x_finish_suspend:
 	@ Put the processor to sleep
@@ -112,11 +120,9 @@ pxa27x_finish_suspend:
  */
 
 ENTRY(pxa25x_cpu_suspend)
-	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
 	adr	r3, BSYM(pxa25x_finish_suspend)
-	bl	cpu_suspend
-	b	pxa_cpu_resume
+	b	cpu_suspend
 
 pxa25x_finish_suspend:
 	@ prepare value for sleep mode
@@ -202,16 +208,3 @@ pxa_cpu_do_suspend:
 	mcr	p14, 0, r1, c7, c0, 0		@ PWRMODE
 
 20:	b	20b				@ loop waiting for sleep
-
-/*
- * pxa_cpu_resume()
- *
- * entry point from bootloader into kernel during resume
- */
-	.align 5
-pxa_cpu_resume:
-	ldmfd	sp!, {r2, r3}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
-- 
1.7.4.4

[PATCH 14/25] ARM: pm: pxa: cleanup PXA suspend code

[Russell King - ARM Linux]

Remove now redundant stacking of registers.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/sleep.S |   33 +++++++++++++--------------------
 1 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 3a67887..cd39293 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -33,11 +33,15 @@ ENTRY(pxa3xx_cpu_suspend)
 #ifndef CONFIG_IWMMXT
 	mra	r2, r3, acc0
 #endif
-	stmfd	sp!, {r2 - r12, lr}	@ save registers on stack
+	stmfd	sp!, {r2, r3, lr}	@ save registers on stack
 	mov	r1, r0
 	adr	r3, BSYM(pxa3xx_finish_suspend)
 	bl	cpu_suspend
-	b	pxa_cpu_resume
+	ldmfd	sp!, {r2, r3, lr}
+#ifndef CONFIG_IWMMXT
+	mar	acc0, r2, r3
+#endif
+	mov	pc, lr
 
 pxa3xx_finish_suspend:
 	mov	r0, #0x06		@ S2D3C4 mode
@@ -60,11 +64,15 @@ ENTRY(pxa27x_cpu_suspend)
 #ifndef CONFIG_IWMMXT
 	mra	r2, r3, acc0
 #endif
-	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
+	stmfd	sp!, {r2, r3, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
 	adr	r3, BSYM(pxa27x_finish_suspend)
 	bl	cpu_suspend
-	b	pxa_cpu_resume
+	ldmfd	sp!, {r2, r3, lr}
+#ifndef CONFIG_IWMMXT
+	mar	acc0, r2, r3
+#endif
+	mov	pc, lr
 
 pxa27x_finish_suspend:
 	@ Put the processor to sleep
@@ -112,11 +120,9 @@ pxa27x_finish_suspend:
  */
 
 ENTRY(pxa25x_cpu_suspend)
-	stmfd	sp!, {r2 - r12, lr}		@ save registers on stack
 	mov	r2, r0				@ save sleep mode
 	adr	r3, BSYM(pxa25x_finish_suspend)
-	bl	cpu_suspend
-	b	pxa_cpu_resume
+	b	cpu_suspend
 
 pxa25x_finish_suspend:
 	@ prepare value for sleep mode
@@ -202,16 +208,3 @@ pxa_cpu_do_suspend:
 	mcr	p14, 0, r1, c7, c0, 0		@ PWRMODE
 
 20:	b	20b				@ loop waiting for sleep
-
-/*
- * pxa_cpu_resume()
- *
- * entry point from bootloader into kernel during resume
- */
-	.align 5
-pxa_cpu_resume:
-	ldmfd	sp!, {r2, r3}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	ldmfd	sp!, {r4 - r12, pc}		@ return to caller
-- 
1.7.4.4

[PATCH 15/25] ARM: pm: sa1100: move cpu_suspend into C code

[Russell King - ARM Linux]

We don't need a veneer for cpu_suspend, it can be called directly from
C code now.  Move it into sa11x0_pm_enter() along with the re-enabling
of clock switching.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/pm.c    |    7 +++++--
 arch/arm/mach-sa1100/sleep.S |   12 ++----------
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index c4661aa..7d8f80e 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -32,7 +32,7 @@
 #include <asm/system.h>
 #include <asm/mach/time.h>
 
-extern void sa1100_cpu_suspend(long);
+extern void sa1100_finish_suspend(unsigned long);
 
 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
@@ -75,7 +75,10 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	PSPR = virt_to_phys(cpu_resume);
 
 	/* go zzz */
-	sa1100_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, sa1100_finish_suspend);
+
+	/* Re-enable clock switching */
+	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
 
 	cpu_init();
 
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index e814b60..e822331 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -22,21 +22,13 @@
 
 		.text
 /*
- * sa1100_cpu_suspend()
+ * sa1100_finish_suspend()
  *
  * Causes sa11x0 to enter sleep state
  *
  */
 
-ENTRY(sa1100_cpu_suspend)
-	mov	r9, lr
-	mov	r1, r0
-	adr	r3, BSYM(sa1100_finish_suspend)
-	bl	cpu_suspend
-	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	mov	pc, r9				@ return to caller
-
-sa1100_finish_suspend:
+ENTRY(sa1100_finish_suspend)
 	@ disable clock switching
 	mcr	p15, 0, r1, c15, c2, 2
 
-- 
1.7.4.4

[PATCH 15/25] ARM: pm: sa1100: move cpu_suspend into C code

[Russell King - ARM Linux]

We don't need a veneer for cpu_suspend, it can be called directly from
C code now.  Move it into sa11x0_pm_enter() along with the re-enabling
of clock switching.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/pm.c    |    7 +++++--
 arch/arm/mach-sa1100/sleep.S |   12 ++----------
 2 files changed, 7 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index c4661aa..7d8f80e 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -32,7 +32,7 @@
 #include <asm/system.h>
 #include <asm/mach/time.h>
 
-extern void sa1100_cpu_suspend(long);
+extern void sa1100_finish_suspend(unsigned long);
 
 #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
 #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
@@ -75,7 +75,10 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	PSPR = virt_to_phys(cpu_resume);
 
 	/* go zzz */
-	sa1100_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, sa1100_finish_suspend);
+
+	/* Re-enable clock switching */
+	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
 
 	cpu_init();
 
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index e814b60..e822331 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -22,21 +22,13 @@
 
 		.text
 /*
- * sa1100_cpu_suspend()
+ * sa1100_finish_suspend()
  *
  * Causes sa11x0 to enter sleep state
  *
  */
 
-ENTRY(sa1100_cpu_suspend)
-	mov	r9, lr
-	mov	r1, r0
-	adr	r3, BSYM(sa1100_finish_suspend)
-	bl	cpu_suspend
-	mcr	p15, 0, r1, c15, c1, 2		@ enable clock switching
-	mov	pc, r9				@ return to caller
-
-sa1100_finish_suspend:
+ENTRY(sa1100_finish_suspend)
 	@ disable clock switching
 	mcr	p15, 0, r1, c15, c2, 2
 
-- 
1.7.4.4

[PATCH 16/25] ARM: pm: pxa: move cpu_suspend into C code

[Russell King - ARM Linux]

We don't need a veneer for cpu_suspend, it can be called directly from
C code now.  Move it into the PXA CPU suspend functions, along with
the accumulator register saving/restoring.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/include/mach/pm.h |    4 +-
 arch/arm/mach-pxa/pxa25x.c          |    3 +-
 arch/arm/mach-pxa/pxa27x.c          |   11 +++++++-
 arch/arm/mach-pxa/pxa3xx.c          |   13 +++++++-
 arch/arm/mach-pxa/sleep.S           |   51 ++++------------------------------
 arch/arm/mach-pxa/zeus.c            |    3 +-
 6 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index f15afe0..a566720 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -22,8 +22,8 @@ struct pxa_cpu_pm_fns {
 extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
 
 /* sleep.S */
-extern void pxa25x_cpu_suspend(unsigned int, long);
-extern void pxa27x_cpu_suspend(unsigned int, long);
+extern void pxa25x_finish_suspend(unsigned long);
+extern void pxa27x_finish_suspend(unsigned long);
 
 extern int pxa_pm_enter(suspend_state_t state);
 extern int pxa_pm_prepare(void);
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index fed363c..fd7725c 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -244,7 +244,8 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
 
 	switch (state) {
 	case PM_SUSPEND_MEM:
-		pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, PWRMODE_SLEEP,
+			    pxa25x_finish_suspend);
 		break;
 	}
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 2fecbec..824379d 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -284,6 +284,11 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 void pxa27x_cpu_pm_enter(suspend_state_t state)
 {
 	extern void pxa_cpu_standby(void);
+#ifndef CONFIG_IWMMXT
+	u64 acc0;
+
+	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
+#endif
 
 	/* ensure voltage-change sequencer not initiated, which hangs */
 	PCFR &= ~PCFR_FVC;
@@ -299,7 +304,11 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
 		pxa_cpu_standby();
 		break;
 	case PM_SUSPEND_MEM:
-		pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, pwrmode,
+			    pxa27x_finish_suspend);
+#ifndef CONFIG_IWMMXT
+		asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
+#endif
 		break;
 	}
 }
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 8521d7d..220fd8c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -141,8 +141,13 @@ static void pxa3xx_cpu_pm_suspend(void)
 {
 	volatile unsigned long *p = (volatile void *)0xc0000000;
 	unsigned long saved_data = *p;
+#ifndef CONFIG_IWMMXT
+	u64 acc0;
 
-	extern void pxa3xx_cpu_suspend(long);
+	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
+#endif
+
+	extern void pxa3xx_finish_suspend(unsigned long);
 
 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
@@ -162,11 +167,15 @@ static void pxa3xx_cpu_pm_suspend(void)
 	/* overwrite with the resume address */
 	*p = virt_to_phys(cpu_resume);
 
-	pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, pxa3xx_finish_suspend);
 
 	*p = saved_data;
 
 	AD3ER = 0;
+
+#ifndef CONFIG_IWMMXT
+	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
+#endif
 }
 
 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index cd39293..1e544be 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -24,26 +24,9 @@
 
 #ifdef CONFIG_PXA3xx
 /*
- * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
- *
- * r0 = v:p offset
+ * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
  */
-ENTRY(pxa3xx_cpu_suspend)
-
-#ifndef CONFIG_IWMMXT
-	mra	r2, r3, acc0
-#endif
-	stmfd	sp!, {r2, r3, lr}	@ save registers on stack
-	mov	r1, r0
-	adr	r3, BSYM(pxa3xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, {r2, r3, lr}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	mov	pc, lr
-
-pxa3xx_finish_suspend:
+ENTRY(pxa3xx_finish_suspend)
 	mov	r0, #0x06		@ S2D3C4 mode
 	mcr	p14, 0, r0, c7, c0, 0	@ enter sleep
 
@@ -52,29 +35,13 @@ pxa3xx_finish_suspend:
 
 #ifdef CONFIG_PXA27x
 /*
- * pxa27x_cpu_suspend()
+ * pxa27x_finish_suspend()
  *
  * Forces CPU into sleep state.
  *
  * r0 = value for PWRMODE M field for desired sleep state
- * r1 = v:p offset
  */
-ENTRY(pxa27x_cpu_suspend)
-
-#ifndef CONFIG_IWMMXT
-	mra	r2, r3, acc0
-#endif
-	stmfd	sp!, {r2, r3, lr}		@ save registers on stack
-	mov	r2, r0				@ save sleep mode
-	adr	r3, BSYM(pxa27x_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, {r2, r3, lr}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	mov	pc, lr
-
-pxa27x_finish_suspend:
+ENTRY(pxa27x_finish_suspend)
 	@ Put the processor to sleep
 	@ (also workaround for sighting 28071)
 
@@ -111,20 +78,14 @@ pxa27x_finish_suspend:
 
 #ifdef CONFIG_PXA25x
 /*
- * pxa25x_cpu_suspend()
+ * pxa25x_finish_suspend()
  *
  * Forces CPU into sleep state.
  *
  * r0 = value for PWRMODE M field for desired sleep state
- * r1 = v:p offset
  */
 
-ENTRY(pxa25x_cpu_suspend)
-	mov	r2, r0				@ save sleep mode
-	adr	r3, BSYM(pxa25x_finish_suspend)
-	b	cpu_suspend
-
-pxa25x_finish_suspend:
+ENTRY(pxa25x_finish_suspend)
 	@ prepare value for sleep mode
 	mov	r1, r0				@ sleep mode
 
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 00363c7..28eb410 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -676,7 +676,8 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = {
 static void zeus_power_off(void)
 {
 	local_irq_disable();
-	pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, PWRMODE_DEEPSLEEP,
+		    pxa27x_finish_suspend);
 }
 #else
 #define zeus_power_off   NULL
-- 
1.7.4.4

[PATCH 16/25] ARM: pm: pxa: move cpu_suspend into C code

[Russell King - ARM Linux]

We don't need a veneer for cpu_suspend, it can be called directly from
C code now.  Move it into the PXA CPU suspend functions, along with
the accumulator register saving/restoring.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-pxa/include/mach/pm.h |    4 +-
 arch/arm/mach-pxa/pxa25x.c          |    3 +-
 arch/arm/mach-pxa/pxa27x.c          |   11 +++++++-
 arch/arm/mach-pxa/pxa3xx.c          |   13 +++++++-
 arch/arm/mach-pxa/sleep.S           |   51 ++++------------------------------
 arch/arm/mach-pxa/zeus.c            |    3 +-
 6 files changed, 33 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h
index f15afe0..a566720 100644
--- a/arch/arm/mach-pxa/include/mach/pm.h
+++ b/arch/arm/mach-pxa/include/mach/pm.h
@@ -22,8 +22,8 @@ struct pxa_cpu_pm_fns {
 extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
 
 /* sleep.S */
-extern void pxa25x_cpu_suspend(unsigned int, long);
-extern void pxa27x_cpu_suspend(unsigned int, long);
+extern void pxa25x_finish_suspend(unsigned long);
+extern void pxa27x_finish_suspend(unsigned long);
 
 extern int pxa_pm_enter(suspend_state_t state);
 extern int pxa_pm_prepare(void);
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index fed363c..fd7725c 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -244,7 +244,8 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
 
 	switch (state) {
 	case PM_SUSPEND_MEM:
-		pxa25x_cpu_suspend(PWRMODE_SLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, PWRMODE_SLEEP,
+			    pxa25x_finish_suspend);
 		break;
 	}
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 2fecbec..824379d 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -284,6 +284,11 @@ void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 void pxa27x_cpu_pm_enter(suspend_state_t state)
 {
 	extern void pxa_cpu_standby(void);
+#ifndef CONFIG_IWMMXT
+	u64 acc0;
+
+	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
+#endif
 
 	/* ensure voltage-change sequencer not initiated, which hangs */
 	PCFR &= ~PCFR_FVC;
@@ -299,7 +304,11 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
 		pxa_cpu_standby();
 		break;
 	case PM_SUSPEND_MEM:
-		pxa27x_cpu_suspend(pwrmode, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, pwrmode,
+			    pxa27x_finish_suspend);
+#ifndef CONFIG_IWMMXT
+		asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
+#endif
 		break;
 	}
 }
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 8521d7d..220fd8c 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -141,8 +141,13 @@ static void pxa3xx_cpu_pm_suspend(void)
 {
 	volatile unsigned long *p = (volatile void *)0xc0000000;
 	unsigned long saved_data = *p;
+#ifndef CONFIG_IWMMXT
+	u64 acc0;
 
-	extern void pxa3xx_cpu_suspend(long);
+	asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
+#endif
+
+	extern void pxa3xx_finish_suspend(unsigned long);
 
 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
@@ -162,11 +167,15 @@ static void pxa3xx_cpu_pm_suspend(void)
 	/* overwrite with the resume address */
 	*p = virt_to_phys(cpu_resume);
 
-	pxa3xx_cpu_suspend(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, pxa3xx_finish_suspend);
 
 	*p = saved_data;
 
 	AD3ER = 0;
+
+#ifndef CONFIG_IWMMXT
+	asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
+#endif
 }
 
 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index cd39293..1e544be 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -24,26 +24,9 @@
 
 #ifdef CONFIG_PXA3xx
 /*
- * pxa3xx_cpu_suspend() - forces CPU into sleep state (S2D3C4)
- *
- * r0 = v:p offset
+ * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
  */
-ENTRY(pxa3xx_cpu_suspend)
-
-#ifndef CONFIG_IWMMXT
-	mra	r2, r3, acc0
-#endif
-	stmfd	sp!, {r2, r3, lr}	@ save registers on stack
-	mov	r1, r0
-	adr	r3, BSYM(pxa3xx_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, {r2, r3, lr}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	mov	pc, lr
-
-pxa3xx_finish_suspend:
+ENTRY(pxa3xx_finish_suspend)
 	mov	r0, #0x06		@ S2D3C4 mode
 	mcr	p14, 0, r0, c7, c0, 0	@ enter sleep
 
@@ -52,29 +35,13 @@ pxa3xx_finish_suspend:
 
 #ifdef CONFIG_PXA27x
 /*
- * pxa27x_cpu_suspend()
+ * pxa27x_finish_suspend()
  *
  * Forces CPU into sleep state.
  *
  * r0 = value for PWRMODE M field for desired sleep state
- * r1 = v:p offset
  */
-ENTRY(pxa27x_cpu_suspend)
-
-#ifndef CONFIG_IWMMXT
-	mra	r2, r3, acc0
-#endif
-	stmfd	sp!, {r2, r3, lr}		@ save registers on stack
-	mov	r2, r0				@ save sleep mode
-	adr	r3, BSYM(pxa27x_finish_suspend)
-	bl	cpu_suspend
-	ldmfd	sp!, {r2, r3, lr}
-#ifndef CONFIG_IWMMXT
-	mar	acc0, r2, r3
-#endif
-	mov	pc, lr
-
-pxa27x_finish_suspend:
+ENTRY(pxa27x_finish_suspend)
 	@ Put the processor to sleep
 	@ (also workaround for sighting 28071)
 
@@ -111,20 +78,14 @@ pxa27x_finish_suspend:
 
 #ifdef CONFIG_PXA25x
 /*
- * pxa25x_cpu_suspend()
+ * pxa25x_finish_suspend()
  *
  * Forces CPU into sleep state.
  *
  * r0 = value for PWRMODE M field for desired sleep state
- * r1 = v:p offset
  */
 
-ENTRY(pxa25x_cpu_suspend)
-	mov	r2, r0				@ save sleep mode
-	adr	r3, BSYM(pxa25x_finish_suspend)
-	b	cpu_suspend
-
-pxa25x_finish_suspend:
+ENTRY(pxa25x_finish_suspend)
 	@ prepare value for sleep mode
 	mov	r1, r0				@ sleep mode
 
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 00363c7..28eb410 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -676,7 +676,8 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = {
 static void zeus_power_off(void)
 {
 	local_irq_disable();
-	pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, PWRMODE_DEEPSLEEP,
+		    pxa27x_finish_suspend);
 }
 #else
 #define zeus_power_off   NULL
-- 
1.7.4.4

[PATCH 17/25] ARM: pm: move cpu_init() call into core code

[Russell King - ARM Linux]

As we have core code dealing with CPU suspend/resume, we can
re-initialize the CPUs exception banked registers via that code rather
than having platforms deal with that level of detail.  So, move the
call to cpu_init() out of platform code into core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S    |    1 +
 arch/arm/mach-pxa/pm.c     |    1 -
 arch/arm/mach-sa1100/pm.c  |    2 --
 arch/arm/plat-samsung/pm.c |    4 ----
 4 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index e062677..5392274 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -88,6 +88,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
+	bl	cpu_init		@ restore the und/abt/irq banked regs
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_resume_after_mmu)
 
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 51e1583..37178a8 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -42,7 +42,6 @@ int pxa_pm_enter(suspend_state_t state)
 
 	/* *** go zzz *** */
 	pxa_cpu_pm_fns->enter(state);
-	cpu_init();
 
 	if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->restore) {
 		/* after sleeping, validate the checksum */
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 7d8f80e..d49eaf2 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -80,8 +80,6 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	/* Re-enable clock switching */
 	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
 
-	cpu_init();
-
 	/*
 	 * Ensure not to come back here if it wasn't intended
 	 */
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5c0a440..3828191 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -300,10 +300,6 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
 
-	/* restore the cpu state using the kernel's cpu init code. */
-
-	cpu_init();
-
 	/* restore the system state */
 
 	s3c_pm_restore_core();
-- 
1.7.4.4

[PATCH 17/25] ARM: pm: move cpu_init() call into core code

[Russell King - ARM Linux]

As we have core code dealing with CPU suspend/resume, we can
re-initialize the CPUs exception banked registers via that code rather
than having platforms deal with that level of detail.  So, move the
call to cpu_init() out of platform code into core code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/sleep.S    |    1 +
 arch/arm/mach-pxa/pm.c     |    1 -
 arch/arm/mach-sa1100/pm.c  |    2 --
 arch/arm/plat-samsung/pm.c |    4 ----
 4 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index e062677..5392274 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -88,6 +88,7 @@ ENDPROC(cpu_resume_turn_mmu_on)
 cpu_resume_after_mmu:
 	str	r5, [r2, r4, lsl #2]	@ restore old mapping
 	mcr	p15, 0, r0, c1, c0, 0	@ turn on D-cache
+	bl	cpu_init		@ restore the und/abt/irq banked regs
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_resume_after_mmu)
 
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 51e1583..37178a8 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -42,7 +42,6 @@ int pxa_pm_enter(suspend_state_t state)
 
 	/* *** go zzz *** */
 	pxa_cpu_pm_fns->enter(state);
-	cpu_init();
 
 	if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->restore) {
 		/* after sleeping, validate the checksum */
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 7d8f80e..d49eaf2 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -80,8 +80,6 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	/* Re-enable clock switching */
 	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
 
-	cpu_init();
-
 	/*
 	 * Ensure not to come back here if it wasn't intended
 	 */
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5c0a440..3828191 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -300,10 +300,6 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
 
-	/* restore the cpu state using the kernel's cpu init code. */
-
-	cpu_init();
-
 	/* restore the system state */
 
 	s3c_pm_restore_core();
-- 
1.7.4.4

[PATCH 18/25] ARM: pm: arrange for cpu_proc_init() to be called on resume

[Russell King - ARM Linux]

cpu_proc_init() does processor specific initialization, which we do
at boot time.  We have been omitting to do this on resume, which
causes some of this initialization to be skipped.  We've also been
skipping this on SMP initialization too.

Ensure that cpu_proc_init() is always called appropriately by
moving it into cpu_init(), and move cpu_init() to a more appropriate
point in the boot initialization.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/setup.c |   99 ++++++++++++++++++++++++-----------------------
 1 files changed, 50 insertions(+), 49 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ed11fb0..edcab02 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -342,54 +342,6 @@ static void __init feat_v6_fixup(void)
 		elf_hwcap &= ~HWCAP_TLS;
 }
 
-static void __init setup_processor(void)
-{
-	struct proc_info_list *list;
-
-	/*
-	 * locate processor in the list of supported processor
-	 * types.  The linker builds this table for us from the
-	 * entries in arch/arm/mm/proc-*.S
-	 */
-	list = lookup_processor_type(read_cpuid_id());
-	if (!list) {
-		printk("CPU configuration botched (ID %08x), unable "
-		       "to continue.\n", read_cpuid_id());
-		while (1);
-	}
-
-	cpu_name = list->cpu_name;
-
-#ifdef MULTI_CPU
-	processor = *list->proc;
-#endif
-#ifdef MULTI_TLB
-	cpu_tlb = *list->tlb;
-#endif
-#ifdef MULTI_USER
-	cpu_user = *list->user;
-#endif
-#ifdef MULTI_CACHE
-	cpu_cache = *list->cache;
-#endif
-
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
-
-	sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
-	sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
-	elf_hwcap = list->elf_hwcap;
-#ifndef CONFIG_ARM_THUMB
-	elf_hwcap &= ~HWCAP_THUMB;
-#endif
-
-	feat_v6_fixup();
-
-	cacheid_init();
-	cpu_proc_init();
-}
-
 /*
  * cpu_init - initialise one CPU.
  *
@@ -405,6 +357,8 @@ void cpu_init(void)
 		BUG();
 	}
 
+	cpu_proc_init();
+
 	/*
 	 * Define the placement constraint for the inline asm directive below.
 	 * In Thumb-2, msr with an immediate value is not allowed.
@@ -441,6 +395,54 @@ void cpu_init(void)
 	    : "r14");
 }
 
+static void __init setup_processor(void)
+{
+	struct proc_info_list *list;
+
+	/*
+	 * locate processor in the list of supported processor
+	 * types.  The linker builds this table for us from the
+	 * entries in arch/arm/mm/proc-*.S
+	 */
+	list = lookup_processor_type(read_cpuid_id());
+	if (!list) {
+		printk("CPU configuration botched (ID %08x), unable "
+		       "to continue.\n", read_cpuid_id());
+		while (1);
+	}
+
+	cpu_name = list->cpu_name;
+
+#ifdef MULTI_CPU
+	processor = *list->proc;
+#endif
+#ifdef MULTI_TLB
+	cpu_tlb = *list->tlb;
+#endif
+#ifdef MULTI_USER
+	cpu_user = *list->user;
+#endif
+#ifdef MULTI_CACHE
+	cpu_cache = *list->cache;
+#endif
+
+	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
+	       proc_arch[cpu_architecture()], cr_alignment);
+
+	sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
+	sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
+	elf_hwcap = list->elf_hwcap;
+#ifndef CONFIG_ARM_THUMB
+	elf_hwcap &= ~HWCAP_THUMB;
+#endif
+
+	feat_v6_fixup();
+
+	cacheid_init();
+	cpu_init();
+}
+
 void __init dump_machine_table(void)
 {
 	struct machine_desc *p;
@@ -913,7 +915,6 @@ void __init setup_arch(char **cmdline_p)
 #endif
 	reserve_crashkernel();
 
-	cpu_init();
 	tcm_init();
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
-- 
1.7.4.4

[PATCH 18/25] ARM: pm: arrange for cpu_proc_init() to be called on resume

[Russell King - ARM Linux]

cpu_proc_init() does processor specific initialization, which we do
at boot time.  We have been omitting to do this on resume, which
causes some of this initialization to be skipped.  We've also been
skipping this on SMP initialization too.

Ensure that cpu_proc_init() is always called appropriately by
moving it into cpu_init(), and move cpu_init() to a more appropriate
point in the boot initialization.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/kernel/setup.c |   99 ++++++++++++++++++++++++-----------------------
 1 files changed, 50 insertions(+), 49 deletions(-)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index ed11fb0..edcab02 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -342,54 +342,6 @@ static void __init feat_v6_fixup(void)
 		elf_hwcap &= ~HWCAP_TLS;
 }
 
-static void __init setup_processor(void)
-{
-	struct proc_info_list *list;
-
-	/*
-	 * locate processor in the list of supported processor
-	 * types.  The linker builds this table for us from the
-	 * entries in arch/arm/mm/proc-*.S
-	 */
-	list = lookup_processor_type(read_cpuid_id());
-	if (!list) {
-		printk("CPU configuration botched (ID %08x), unable "
-		       "to continue.\n", read_cpuid_id());
-		while (1);
-	}
-
-	cpu_name = list->cpu_name;
-
-#ifdef MULTI_CPU
-	processor = *list->proc;
-#endif
-#ifdef MULTI_TLB
-	cpu_tlb = *list->tlb;
-#endif
-#ifdef MULTI_USER
-	cpu_user = *list->user;
-#endif
-#ifdef MULTI_CACHE
-	cpu_cache = *list->cache;
-#endif
-
-	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-	       proc_arch[cpu_architecture()], cr_alignment);
-
-	sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
-	sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
-	elf_hwcap = list->elf_hwcap;
-#ifndef CONFIG_ARM_THUMB
-	elf_hwcap &= ~HWCAP_THUMB;
-#endif
-
-	feat_v6_fixup();
-
-	cacheid_init();
-	cpu_proc_init();
-}
-
 /*
  * cpu_init - initialise one CPU.
  *
@@ -405,6 +357,8 @@ void cpu_init(void)
 		BUG();
 	}
 
+	cpu_proc_init();
+
 	/*
 	 * Define the placement constraint for the inline asm directive below.
 	 * In Thumb-2, msr with an immediate value is not allowed.
@@ -441,6 +395,54 @@ void cpu_init(void)
 	    : "r14");
 }
 
+static void __init setup_processor(void)
+{
+	struct proc_info_list *list;
+
+	/*
+	 * locate processor in the list of supported processor
+	 * types.  The linker builds this table for us from the
+	 * entries in arch/arm/mm/proc-*.S
+	 */
+	list = lookup_processor_type(read_cpuid_id());
+	if (!list) {
+		printk("CPU configuration botched (ID %08x), unable "
+		       "to continue.\n", read_cpuid_id());
+		while (1);
+	}
+
+	cpu_name = list->cpu_name;
+
+#ifdef MULTI_CPU
+	processor = *list->proc;
+#endif
+#ifdef MULTI_TLB
+	cpu_tlb = *list->tlb;
+#endif
+#ifdef MULTI_USER
+	cpu_user = *list->user;
+#endif
+#ifdef MULTI_CACHE
+	cpu_cache = *list->cache;
+#endif
+
+	printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
+	       cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
+	       proc_arch[cpu_architecture()], cr_alignment);
+
+	sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
+	sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
+	elf_hwcap = list->elf_hwcap;
+#ifndef CONFIG_ARM_THUMB
+	elf_hwcap &= ~HWCAP_THUMB;
+#endif
+
+	feat_v6_fixup();
+
+	cacheid_init();
+	cpu_init();
+}
+
 void __init dump_machine_table(void)
 {
 	struct machine_desc *p;
@@ -913,7 +915,6 @@ void __init setup_arch(char **cmdline_p)
 #endif
 	reserve_crashkernel();
 
-	cpu_init();
 	tcm_init();
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
-- 
1.7.4.4

[PATCH 19/25] ARM: pm: sa1100: no need to re-enable clock switching

[Russell King - ARM Linux]

This is now taken care of by calling cpu_proc_init() in the resume
path, so eliminate this unnecessary call.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/pm.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index d49eaf2..259ed3b 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -77,9 +77,6 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	/* go zzz */
 	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, sa1100_finish_suspend);
 
-	/* Re-enable clock switching */
-	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
-
 	/*
 	 * Ensure not to come back here if it wasn't intended
 	 */
-- 
1.7.4.4

[PATCH 19/25] ARM: pm: sa1100: no need to re-enable clock switching

[Russell King - ARM Linux]

This is now taken care of by calling cpu_proc_init() in the resume
path, so eliminate this unnecessary call.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-sa1100/pm.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index d49eaf2..259ed3b 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -77,9 +77,6 @@ static int sa11x0_pm_enter(suspend_state_t state)
 	/* go zzz */
 	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, sa1100_finish_suspend);
 
-	/* Re-enable clock switching */
-	asm volatile("mcr p15, 0, %0, c15, c1, 2" : : "r" (0));
-
 	/*
 	 * Ensure not to come back here if it wasn't intended
 	 */
-- 
1.7.4.4

[PATCH 20/25] ARM: pm: samsung: move cpu_suspend into C code

[Russell King - ARM Linux]

Move the call to cpu_suspend into C code, and noticing that all the
s3c_cpu_save implementations are now identical, we can move this
into the common samsung code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-exynos4/pm.c              |    2 +-
 arch/arm/mach-exynos4/sleep.S           |   18 ------------------
 arch/arm/mach-s3c2412/pm.c              |    2 +-
 arch/arm/mach-s3c2416/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/sleep.S           |   18 ------------------
 arch/arm/mach-s5pv210/pm.c              |    2 +-
 arch/arm/mach-s5pv210/sleep.S           |   17 -----------------
 arch/arm/plat-s3c24xx/sleep.S           |   19 -------------------
 arch/arm/plat-samsung/include/plat/pm.h |    5 ++---
 arch/arm/plat-samsung/pm.c              |    6 +++---
 11 files changed, 10 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 8755ca8..5c01c60 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -280,7 +280,7 @@ static struct sleep_save exynos4_l2cc_save[] = {
 	SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
 };
 
-void exynos4_cpu_suspend(void)
+void exynos4_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 	unsigned long mask = 0xFFFFFFFF;
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index b56a491..0984078 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -33,24 +33,6 @@
 	.text
 
 	/*
-	 * s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	 */
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(exynos4_finish_suspend)
-	b	cpu_suspend
-
-exynos4_finish_suspend:
-	ldr	r0, =pm_cpu_sleep
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-
-	.ltorg
-
-	/*
 	 * sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 752b13a..fecd854 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -37,7 +37,7 @@
 
 extern void s3c2412_sleep_enter(void);
 
-static void s3c2412_cpu_suspend(void)
+static void s3c2412_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 41db2b2..268fda7 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -24,7 +24,7 @@
 
 extern void s3c2412_sleep_enter(void);
 
-static void s3c2416_cpu_suspend(void)
+static void s3c2416_cpu_suspend(unsigned long arg)
 {
 	flush_cache_all();
 
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index bc1c470..7cc1879 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -112,7 +112,7 @@ void s3c_pm_save_core(void)
  * this.
  */
 
-static void s3c64xx_cpu_suspend(void)
+static void s3c64xx_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index 2fd3433..34313f9 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -25,24 +25,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * Save enough processor state to allow the restart of the pm.c
-	 * code after resume.
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s3c64xx_finish_suspend)
-	b	cpu_suspend
-
-s3c64xx_finish_suspend:
-	@@ call final suspend code
-	ldr	r0, =pm_cpu_sleep
-	ldr	pc, [r0]
-	
 	/* Sleep magic, the word before the resume entry point so that the
 	 * bootloader can check for a resumeable image. */
 
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 24febae..309e388 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
 	SAVE_ITEM(S3C2410_TCNTO(0)),
 };
 
-void s5pv210_cpu_suspend(void)
+void s5pv210_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 28dfeff..e3452cc 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -32,23 +32,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s5pv210_finish_suspend)
-	b	cpu_suspend
-
-s5pv210_finish_suspend:
-	ldr	r0, =pm_cpu_sleep
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-
-	.ltorg
-
 	/* sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 6ada459..c566125 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,25 +41,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s3c24xx_finish_suspend)
-	b	cpu_suspend
-
-s3c24xx_finish_suspend:
-	@@ jump to final code to send system to sleep
-	ldr	r0, =pm_cpu_sleep
-	@@ldr	pc, [ r0 ]
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-	
-	.ltorg
-
 	/* sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 7fb6f6b..0a5b7fa 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -42,7 +42,7 @@ extern unsigned long s3c_irqwake_eintallow;
 /* per-cpu sleep functions */
 
 extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
+extern void (*pm_cpu_sleep)(unsigned long);
 
 /* Flags for PM Control */
 
@@ -52,10 +52,9 @@ extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 
 /* from sleep.S */
 
-extern int  s3c_cpu_save(unsigned long *saveblk, long);
 extern void s3c_cpu_resume(void);
 
-extern void s3c2410_cpu_suspend(void);
+extern void s3c2410_cpu_suspend(unsigned long);
 
 /* sleep save info */
 
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 3828191..3a6d076 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -231,7 +231,7 @@ static void __maybe_unused s3c_pm_show_resume_irqs(int start,
 
 
 void (*pm_cpu_prep)(void);
-void (*pm_cpu_sleep)(void);
+void (*pm_cpu_sleep)(unsigned long);
 
 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
 
@@ -294,11 +294,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_pm_arch_stop_clocks();
 
-	/* s3c_cpu_save will also act as our return point from when
+	/* this will also act as our return point from when
 	 * we resume as it saves its own register state and restores it
 	 * during the resume.  */
 
-	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, pm_cpu_sleep);
 
 	/* restore the system state */
 
-- 
1.7.4.4

[PATCH 20/25] ARM: pm: samsung: move cpu_suspend into C code

[Russell King - ARM Linux]

Move the call to cpu_suspend into C code, and noticing that all the
s3c_cpu_save implementations are now identical, we can move this
into the common samsung code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-exynos4/pm.c              |    2 +-
 arch/arm/mach-exynos4/sleep.S           |   18 ------------------
 arch/arm/mach-s3c2412/pm.c              |    2 +-
 arch/arm/mach-s3c2416/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/pm.c              |    2 +-
 arch/arm/mach-s3c64xx/sleep.S           |   18 ------------------
 arch/arm/mach-s5pv210/pm.c              |    2 +-
 arch/arm/mach-s5pv210/sleep.S           |   17 -----------------
 arch/arm/plat-s3c24xx/sleep.S           |   19 -------------------
 arch/arm/plat-samsung/include/plat/pm.h |    5 ++---
 arch/arm/plat-samsung/pm.c              |    6 +++---
 11 files changed, 10 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 8755ca8..5c01c60 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -280,7 +280,7 @@ static struct sleep_save exynos4_l2cc_save[] = {
 	SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
 };
 
-void exynos4_cpu_suspend(void)
+void exynos4_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 	unsigned long mask = 0xFFFFFFFF;
diff --git a/arch/arm/mach-exynos4/sleep.S b/arch/arm/mach-exynos4/sleep.S
index b56a491..0984078 100644
--- a/arch/arm/mach-exynos4/sleep.S
+++ b/arch/arm/mach-exynos4/sleep.S
@@ -33,24 +33,6 @@
 	.text
 
 	/*
-	 * s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	 */
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(exynos4_finish_suspend)
-	b	cpu_suspend
-
-exynos4_finish_suspend:
-	ldr	r0, =pm_cpu_sleep
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-
-	.ltorg
-
-	/*
 	 * sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index 752b13a..fecd854 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -37,7 +37,7 @@
 
 extern void s3c2412_sleep_enter(void);
 
-static void s3c2412_cpu_suspend(void)
+static void s3c2412_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 41db2b2..268fda7 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -24,7 +24,7 @@
 
 extern void s3c2412_sleep_enter(void);
 
-static void s3c2416_cpu_suspend(void)
+static void s3c2416_cpu_suspend(unsigned long arg)
 {
 	flush_cache_all();
 
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index bc1c470..7cc1879 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -112,7 +112,7 @@ void s3c_pm_save_core(void)
  * this.
  */
 
-static void s3c64xx_cpu_suspend(void)
+static void s3c64xx_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index 2fd3433..34313f9 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -25,24 +25,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * Save enough processor state to allow the restart of the pm.c
-	 * code after resume.
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s3c64xx_finish_suspend)
-	b	cpu_suspend
-
-s3c64xx_finish_suspend:
-	@@ call final suspend code
-	ldr	r0, =pm_cpu_sleep
-	ldr	pc, [r0]
-	
 	/* Sleep magic, the word before the resume entry point so that the
 	 * bootloader can check for a resumeable image. */
 
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 24febae..309e388 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -88,7 +88,7 @@ static struct sleep_save s5pv210_core_save[] = {
 	SAVE_ITEM(S3C2410_TCNTO(0)),
 };
 
-void s5pv210_cpu_suspend(void)
+void s5pv210_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
index 28dfeff..e3452cc 100644
--- a/arch/arm/mach-s5pv210/sleep.S
+++ b/arch/arm/mach-s5pv210/sleep.S
@@ -32,23 +32,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s5pv210_finish_suspend)
-	b	cpu_suspend
-
-s5pv210_finish_suspend:
-	ldr	r0, =pm_cpu_sleep
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-
-	.ltorg
-
 	/* sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 6ada459..c566125 100644
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -41,25 +41,6 @@
 
 	.text
 
-	/* s3c_cpu_save
-	 *
-	 * entry:
-	 *	r1 = v:p offset
-	*/
-
-ENTRY(s3c_cpu_save)
-	adr	r3, BSYM(s3c24xx_finish_suspend)
-	b	cpu_suspend
-
-s3c24xx_finish_suspend:
-	@@ jump to final code to send system to sleep
-	ldr	r0, =pm_cpu_sleep
-	@@ldr	pc, [ r0 ]
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-	
-	.ltorg
-
 	/* sleep magic, to allow the bootloader to check for an valid
 	 * image to resume to. Must be the first word before the
 	 * s3c_cpu_resume entry.
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 7fb6f6b..0a5b7fa 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -42,7 +42,7 @@ extern unsigned long s3c_irqwake_eintallow;
 /* per-cpu sleep functions */
 
 extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
+extern void (*pm_cpu_sleep)(unsigned long);
 
 /* Flags for PM Control */
 
@@ -52,10 +52,9 @@ extern unsigned char pm_uart_udivslot;  /* true to save UART UDIVSLOT */
 
 /* from sleep.S */
 
-extern int  s3c_cpu_save(unsigned long *saveblk, long);
 extern void s3c_cpu_resume(void);
 
-extern void s3c2410_cpu_suspend(void);
+extern void s3c2410_cpu_suspend(unsigned long);
 
 /* sleep save info */
 
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 3828191..3a6d076 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -231,7 +231,7 @@ static void __maybe_unused s3c_pm_show_resume_irqs(int start,
 
 
 void (*pm_cpu_prep)(void);
-void (*pm_cpu_sleep)(void);
+void (*pm_cpu_sleep)(unsigned long);
 
 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
 
@@ -294,11 +294,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_pm_arch_stop_clocks();
 
-	/* s3c_cpu_save will also act as our return point from when
+	/* this will also act as our return point from when
 	 * we resume as it saves its own register state and restores it
 	 * during the resume.  */
 
-	s3c_cpu_save(0, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, 0, pm_cpu_sleep);
 
 	/* restore the system state */
 
-- 
1.7.4.4

[PATCH 21/25] ARM: pm: samsung: no need to call flush_cache_all()

[Russell King - ARM Linux]

The core suspend code calls flush_cache_all() immediately prior to
calling the suspend finisher function, so remove these needless calls
from the finisher functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s3c2412/pm.c |    2 --
 arch/arm/mach-s3c2416/pm.c |    2 --
 2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index fecd854..9a1fb89 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -41,8 +41,6 @@ static void s3c2412_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
-	flush_cache_all();
-
 	/* set our standby method to sleep */
 
 	tmp = __raw_readl(S3C2412_PWRCFG);
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 268fda7..9e67a2a 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -26,8 +26,6 @@ extern void s3c2412_sleep_enter(void);
 
 static void s3c2416_cpu_suspend(unsigned long arg)
 {
-	flush_cache_all();
-
 	/* enable wakeup sources regardless of battery state */
 	__raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
 
-- 
1.7.4.4

[PATCH 21/25] ARM: pm: samsung: no need to call flush_cache_all()

[Russell King - ARM Linux]

The core suspend code calls flush_cache_all() immediately prior to
calling the suspend finisher function, so remove these needless calls
from the finisher functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-s3c2412/pm.c |    2 --
 arch/arm/mach-s3c2416/pm.c |    2 --
 2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index fecd854..9a1fb89 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -41,8 +41,6 @@ static void s3c2412_cpu_suspend(unsigned long arg)
 {
 	unsigned long tmp;
 
-	flush_cache_all();
-
 	/* set our standby method to sleep */
 
 	tmp = __raw_readl(S3C2412_PWRCFG);
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 268fda7..9e67a2a 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -26,8 +26,6 @@ extern void s3c2412_sleep_enter(void);
 
 static void s3c2416_cpu_suspend(unsigned long arg)
 {
-	flush_cache_all();
-
 	/* enable wakeup sources regardless of battery state */
 	__raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG);
 
-- 
1.7.4.4

[PATCH 22/25] ARM: pm: omap: no need to save all registers in sleep34xx.S

[Russell King - ARM Linux]

The ABI allows called functions to corrupt r0-r3 and ip (r12).  So
its pointless saving these registers in the suspend code - the
calling function will expect them to be corrupted and so won't rely
on their contents after resume.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/sleep34xx.S |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 63f1066..9551c7d 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -133,7 +133,7 @@ ENDPROC(enable_omap3630_toggle_l2_on_restore)
 /* Function to call rom code to save secure ram context */
 	.align	3
 ENTRY(save_secure_ram_context)
-	stmfd	sp!, {r1-r12, lr}	@ save registers on stack
+	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
 	adr	r3, api_params		@ r3 points to parameters
 	str	r0, [r3,#0x4]		@ r0 has sdram address
 	ldr	r12, high_mask
@@ -152,7 +152,7 @@ ENTRY(save_secure_ram_context)
 	nop
 	nop
 	nop
-	ldmfd	sp!, {r1-r12, pc}
+	ldmfd	sp!, {r4 - r11, pc}
 	.align
 sram_phy_addr_mask:
 	.word	SRAM_BASE_P
@@ -187,7 +187,7 @@ ENTRY(save_secure_ram_context_sz)
  */
 	.align	3
 ENTRY(omap34xx_cpu_suspend)
-	stmfd	sp!, {r0-r12, lr}	@ save registers on stack
+	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
 
 	/*
 	 * r0 contains CPU context save/restore pointer in sdram
@@ -329,7 +329,7 @@ omap3_do_wfi:
  * == Exit point from non-OFF modes ==
  * ===================================
  */
-	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
+	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
 
 
 /*
@@ -572,7 +572,7 @@ usettbr0:
  * ==============================
  */
 restoremmu_on:
-	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
+	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
 
 
 /*
-- 
1.7.4.4

[PATCH 22/25] ARM: pm: omap: no need to save all registers in sleep34xx.S

[Russell King - ARM Linux]

The ABI allows called functions to corrupt r0-r3 and ip (r12).  So
its pointless saving these registers in the suspend code - the
calling function will expect them to be corrupted and so won't rely
on their contents after resume.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/sleep34xx.S |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 63f1066..9551c7d 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -133,7 +133,7 @@ ENDPROC(enable_omap3630_toggle_l2_on_restore)
 /* Function to call rom code to save secure ram context */
 	.align	3
 ENTRY(save_secure_ram_context)
-	stmfd	sp!, {r1-r12, lr}	@ save registers on stack
+	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
 	adr	r3, api_params		@ r3 points to parameters
 	str	r0, [r3,#0x4]		@ r0 has sdram address
 	ldr	r12, high_mask
@@ -152,7 +152,7 @@ ENTRY(save_secure_ram_context)
 	nop
 	nop
 	nop
-	ldmfd	sp!, {r1-r12, pc}
+	ldmfd	sp!, {r4 - r11, pc}
 	.align
 sram_phy_addr_mask:
 	.word	SRAM_BASE_P
@@ -187,7 +187,7 @@ ENTRY(save_secure_ram_context_sz)
  */
 	.align	3
 ENTRY(omap34xx_cpu_suspend)
-	stmfd	sp!, {r0-r12, lr}	@ save registers on stack
+	stmfd	sp!, {r4 - r11, lr}	@ save registers on stack
 
 	/*
 	 * r0 contains CPU context save/restore pointer in sdram
@@ -329,7 +329,7 @@ omap3_do_wfi:
  * == Exit point from non-OFF modes ==
  * ===================================
  */
-	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
+	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
 
 
 /*
@@ -572,7 +572,7 @@ usettbr0:
  * ==============================
  */
 restoremmu_on:
-	ldmfd	sp!, {r0-r12, pc}	@ restore regs and return
+	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
 
 
 /*
-- 
1.7.4.4

[PATCH 23/25] ARM: pm: omap34xx: remove misleading comment and use of r9

[Russell King - ARM Linux]

The code alludes to r9 being used to indicate what was lost over the
suspend/resume transition.  However, although r9 is set, it is never
actually used.

Also, the comments before the code (which refer to the value of r9)
and the comments against the assignment of r9 contradict each other,
so just remove them to avoid confusion.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/sleep34xx.S |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 9551c7d..12e9da2 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -381,18 +381,13 @@ restore_3630:
 
 restore:
 	/*
-	 * Check what was the reason for mpu reset and store the reason in r9:
-	 *  0 - No context lost
-	 *  1 - Only L1 and logic lost
-	 *  2 - Only L2 lost - In this case, we wont be here
-	 *  3 - Both L1 and L2 lost
+	 * Read the pwstctrl register to check the reason for mpu reset.
+	 * This tells us what was lost.
 	 */
 	ldr	r1, pm_pwstctrl_mpu
 	ldr	r2, [r1]
 	and	r2, r2, #0x3
 	cmp	r2, #0x0	@ Check if target power state was OFF or RET
-	moveq	r9, #0x3	@ MPU OFF => L1 and L2 lost
-	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
 	bne	logic_l1_restore
 
 	ldr	r0, l2dis_3630
-- 
1.7.4.4

[PATCH 23/25] ARM: pm: omap34xx: remove misleading comment and use of r9

[Russell King - ARM Linux]

The code alludes to r9 being used to indicate what was lost over the
suspend/resume transition.  However, although r9 is set, it is never
actually used.

Also, the comments before the code (which refer to the value of r9)
and the comments against the assignment of r9 contradict each other,
so just remove them to avoid confusion.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/sleep34xx.S |    9 ++-------
 1 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 9551c7d..12e9da2 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -381,18 +381,13 @@ restore_3630:
 
 restore:
 	/*
-	 * Check what was the reason for mpu reset and store the reason in r9:
-	 *  0 - No context lost
-	 *  1 - Only L1 and logic lost
-	 *  2 - Only L2 lost - In this case, we wont be here
-	 *  3 - Both L1 and L2 lost
+	 * Read the pwstctrl register to check the reason for mpu reset.
+	 * This tells us what was lost.
 	 */
 	ldr	r1, pm_pwstctrl_mpu
 	ldr	r2, [r1]
 	and	r2, r2, #0x3
 	cmp	r2, #0x0	@ Check if target power state was OFF or RET
-	moveq	r9, #0x3	@ MPU OFF => L1 and L2 lost
-	movne	r9, #0x1	@ Only L1 and L2 lost => avoid L2 invalidation
 	bne	logic_l1_restore
 
 	ldr	r0, l2dis_3630
-- 
1.7.4.4

[PATCH 24/25] ARM: pm: ensure ARMv7 CPUs save and restore the TLS register

[Russell King - ARM Linux]

Ensure that the TLS register is saved and restored over a suspend
cycle, so that userspace programs don't see a corrupted TLS value.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mm/proc-v7.S |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566e..426c946 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -208,19 +208,21 @@ cpu_v7_name:
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl	cpu_v7_suspend_size
-.equ	cpu_v7_suspend_size, 4 * 8
+.equ	cpu_v7_suspend_size, 4 * 9
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v7_do_suspend)
 	stmfd	sp!, {r4 - r11, lr}
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
+	mrc	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
+	stmia	r0!, {r4 - r6}
 	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
 	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
 	mrc	p15, 0, r9, c1, c0, 0	@ Control register
 	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
 	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
-	stmia	r0, {r4 - r11}
+	stmia	r0, {r6 - r11}
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_v7_do_suspend)
 
@@ -228,9 +230,11 @@ ENTRY(cpu_v7_do_resume)
 	mov	ip, #0
 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
-	ldmia	r0, {r4 - r11}
+	ldmia	r0!, {r4 - r6}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
+	mcr	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
+	ldmia	r0, {r6 - r11}
 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mcr	p15, 0, r7, c2, c0, 0	@ TTB 0
 	mcr	p15, 0, r8, c2, c0, 1	@ TTB 1
-- 
1.7.4.4

[PATCH 24/25] ARM: pm: ensure ARMv7 CPUs save and restore the TLS register

[Russell King - ARM Linux]

Ensure that the TLS register is saved and restored over a suspend
cycle, so that userspace programs don't see a corrupted TLS value.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mm/proc-v7.S |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566e..426c946 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -208,19 +208,21 @@ cpu_v7_name:
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl	cpu_v7_suspend_size
-.equ	cpu_v7_suspend_size, 4 * 8
+.equ	cpu_v7_suspend_size, 4 * 9
 #ifdef CONFIG_PM_SLEEP
 ENTRY(cpu_v7_do_suspend)
 	stmfd	sp!, {r4 - r11, lr}
 	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
+	mrc	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
+	stmia	r0!, {r4 - r6}
 	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
 	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
 	mrc	p15, 0, r9, c1, c0, 0	@ Control register
 	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
 	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
-	stmia	r0, {r4 - r11}
+	stmia	r0, {r6 - r11}
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_v7_do_suspend)
 
@@ -228,9 +230,11 @@ ENTRY(cpu_v7_do_resume)
 	mov	ip, #0
 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
-	ldmia	r0, {r4 - r11}
+	ldmia	r0!, {r4 - r6}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
+	mcr	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
+	ldmia	r0, {r6 - r11}
 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
 	mcr	p15, 0, r7, c2, c0, 0	@ TTB 0
 	mcr	p15, 0, r8, c2, c0, 1	@ TTB 1
-- 
1.7.4.4

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

Convert sa11x0 to use the generic CPU suspend/resume support, rather
than implementing its own version.  Tested on 3430 LDP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/pm34xx.c    |   39 ++----------
 arch/arm/mach-omap2/sleep34xx.S |  130 +-------------------------------------
 2 files changed, 11 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d..09e14cb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -64,11 +64,6 @@ static inline bool is_suspending(void)
 }
 #endif
 
-/* Scratchpad offsets */
-#define OMAP343X_TABLE_ADDRESS_OFFSET	   0xc4
-#define OMAP343X_TABLE_VALUE_OFFSET	   0xc0
-#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
-
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
 
@@ -312,28 +307,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-/* Function to restore the table entry that was modified for enabling MMU */
-static void restore_table_entry(void)
+static void omap34xx_do_sram_idle(unsigned long save_state)
 {
-	void __iomem *scratchpad_address;
-	u32 previous_value, control_reg_value;
-	u32 *address;
-
-	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
-
-	/* Get address of entry that was modified */
-	address = (u32 *)__raw_readl(scratchpad_address +
-				     OMAP343X_TABLE_ADDRESS_OFFSET);
-	/* Get the previous value which needs to be restored */
-	previous_value = __raw_readl(scratchpad_address +
-				     OMAP343X_TABLE_VALUE_OFFSET);
-	address = __va(address);
-	*address = previous_value;
-	flush_tlb_all();
-	control_reg_value = __raw_readl(scratchpad_address
-					+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
-	/* This will enable caches and prediction */
-	set_cr(control_reg_value);
+	_omap_sram_idle(omap3_arm_context, save_state);
 }
 
 void omap_sram_idle(void)
@@ -436,8 +412,11 @@ void omap_sram_idle(void)
 	 * get saved. The restore path then reads from this
 	 * location and restores them back.
 	 */
-	_omap_sram_idle(omap3_arm_context, save_state);
-	cpu_init();
+	if (save_state == 1 || save_state == 3)
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state,
+			    omap34xx_do_sram_idle);
+	else
+		omap34xx_do_sram_idle(save_state);
 
 	/* Restore normal SDRC POWER settings */
 	if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -445,10 +424,6 @@ void omap_sram_idle(void)
 	    core_next_state == PWRDM_POWER_OFF)
 		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 
-	/* Restore table entry modified during MMU restoration */
-	if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
-		restore_table_entry();
-
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
 		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 12e9da2..6d1d083 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -211,37 +211,6 @@ save_context_wfi:
 	mrc	p15, 1, r5, c9, c0, 2	@ Read L2 AUX ctrl register
 	stmia	r8!, {r4-r5}		@ Push parameters for restore call
 
-        /* Check what that target sleep state is from r1 */
-	cmp	r1, #0x2		@ Only L2 lost, no need to save context
-	beq	clean_caches
-
-l1_logic_lost:
-	mov	r4, sp			@ Store sp
-	mrs	r5, spsr		@ Store spsr
-	mov	r6, lr			@ Store lr
-	stmia	r8!, {r4-r6}
-
-	mrc	p15, 0, r4, c1, c0, 2	@ Coprocessor access control register
-	mrc	p15, 0, r5, c2, c0, 0	@ TTBR0
-	mrc	p15, 0, r6, c2, c0, 1	@ TTBR1
-	mrc	p15, 0, r7, c2, c0, 2	@ TTBCR
-	stmia	r8!, {r4-r7}
-
-	mrc	p15, 0, r4, c3, c0, 0	@ Domain access Control Register
-	mrc	p15, 0, r5, c10, c2, 0	@ PRRR
-	mrc	p15, 0, r6, c10, c2, 1	@ NMRR
-	stmia	r8!,{r4-r6}
-
-	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
-	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
-	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
-	mrs	r7, cpsr		@ Store current cpsr
-	stmia	r8!, {r4-r7}
-
-	mrc	p15, 0, r4, c1, c0, 0	@ save control register
-	stmia	r8!, {r4}
-
-clean_caches:
 	/*
 	 * jump out to kernel flush routine
 	 *  - reuse that code is better
@@ -473,102 +442,11 @@ skipl2reen:
 	 */
 	mcr	p15, 0, r1, c7, c5, 0
 
-	ldr	r4, scratchpad_base
-	ldr	r3, [r4,#0xBC]
-	adds	r3, r3, #16
-
-	ldmia	r3!, {r4-r6}
-	mov	sp, r4			@ Restore sp
-	msr	spsr_cxsf, r5		@ Restore spsr
-	mov	lr, r6			@ Restore lr
-
-	ldmia	r3!, {r4-r7}
-	mcr	p15, 0, r4, c1, c0, 2	@ Coprocessor access Control Register
-	mcr	p15, 0, r5, c2, c0, 0	@ TTBR0
-	mcr	p15, 0, r6, c2, c0, 1	@ TTBR1
-	mcr	p15, 0, r7, c2, c0, 2	@ TTBCR
-
-	ldmia	r3!,{r4-r6}
-	mcr	p15, 0, r4, c3, c0, 0	@ Domain access Control Register
-	mcr	p15, 0, r5, c10, c2, 0	@ PRRR
-	mcr	p15, 0, r6, c10, c2, 1	@ NMRR
-
-
-	ldmia	r3!,{r4-r7}
-	mcr	p15, 0, r4, c13, c0, 1	@ Context ID
-	mcr	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
-	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
-	msr	cpsr, r7		@ store cpsr
-
-	/* Enabling MMU here */
-	mrc	p15, 0, r7, c2, c0, 2 	@ Read TTBRControl
-	/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
-	and	r7, #0x7
-	cmp	r7, #0x0
-	beq	usettbr0
-ttbr_error:
-	/*
-	 * More work needs to be done to support N[0:2] value other than 0
-	 * So looping here so that the error can be detected
-	 */
-	b	ttbr_error
-usettbr0:
-	mrc	p15, 0, r2, c2, c0, 0
-	ldr	r5, ttbrbit_mask
-	and	r2, r5
-	mov	r4, pc
-	ldr	r5, table_index_mask
-	and	r4, r5			@ r4 = 31 to 20 bits of pc
-	/* Extract the value to be written to table entry */
-	ldr	r1, table_entry
-	/* r1 has the value to be written to table entry*/
-	add	r1, r1, r4
-	/* Getting the address of table entry to modify */
-	lsr	r4, #18
-	/* r2 has the location which needs to be modified */
-	add	r2, r4
-	/* Storing previous entry of location being modified */
-	ldr	r5, scratchpad_base
-	ldr	r4, [r2]
-	str	r4, [r5, #0xC0]
-	/* Modify the table entry */
-	str	r1, [r2]
-	/*
-	 * Storing address of entry being modified
-	 * - will be restored after enabling MMU
-	 */
-	ldr	r5, scratchpad_base
-	str	r2, [r5, #0xC4]
-
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 4	@ Flush prefetch buffer
-	mcr	p15, 0, r0, c7, c5, 6	@ Invalidate branch predictor array
-	mcr	p15, 0, r0, c8, c5, 0	@ Invalidate instruction TLB
-	mcr	p15, 0, r0, c8, c6, 0	@ Invalidate data TLB
-	/*
-	 * Restore control register. This enables the MMU.
-	 * The caches and prediction are not enabled here, they
-	 * will be enabled after restoring the MMU table entry.
-	 */
-	ldmia	r3!, {r4}
-	/* Store previous value of control register in scratchpad */
-	str	r4, [r5, #0xC8]
-	ldr	r2, cache_pred_disable_mask
-	and	r4, r2
-	mcr	p15, 0, r4, c1, c0, 0
-	dsb
-	isb
-	ldr     r0, =restoremmu_on
-	bx      r0
-
-/*
- * ==============================
- * == Exit point from OFF mode ==
- * ==============================
- */
-restoremmu_on:
-	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
+	/* Now branch to the common CPU resume function */
+	ldr	r0, =cpu_resume
+	bx	r0
 
+	.ltorg
 
 /*
  * Internal functions
-- 
1.7.4.4

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

Convert sa11x0 to use the generic CPU suspend/resume support, rather
than implementing its own version.  Tested on 3430 LDP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
 arch/arm/mach-omap2/pm34xx.c    |   39 ++----------
 arch/arm/mach-omap2/sleep34xx.S |  130 +-------------------------------------
 2 files changed, 11 insertions(+), 158 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c155c9d..09e14cb 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -64,11 +64,6 @@ static inline bool is_suspending(void)
 }
 #endif
 
-/* Scratchpad offsets */
-#define OMAP343X_TABLE_ADDRESS_OFFSET	   0xc4
-#define OMAP343X_TABLE_VALUE_OFFSET	   0xc0
-#define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
-
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
 
@@ -312,28 +307,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-/* Function to restore the table entry that was modified for enabling MMU */
-static void restore_table_entry(void)
+static void omap34xx_do_sram_idle(unsigned long save_state)
 {
-	void __iomem *scratchpad_address;
-	u32 previous_value, control_reg_value;
-	u32 *address;
-
-	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
-
-	/* Get address of entry that was modified */
-	address = (u32 *)__raw_readl(scratchpad_address +
-				     OMAP343X_TABLE_ADDRESS_OFFSET);
-	/* Get the previous value which needs to be restored */
-	previous_value = __raw_readl(scratchpad_address +
-				     OMAP343X_TABLE_VALUE_OFFSET);
-	address = __va(address);
-	*address = previous_value;
-	flush_tlb_all();
-	control_reg_value = __raw_readl(scratchpad_address
-					+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
-	/* This will enable caches and prediction */
-	set_cr(control_reg_value);
+	_omap_sram_idle(omap3_arm_context, save_state);
 }
 
 void omap_sram_idle(void)
@@ -436,8 +412,11 @@ void omap_sram_idle(void)
 	 * get saved. The restore path then reads from this
 	 * location and restores them back.
 	 */
-	_omap_sram_idle(omap3_arm_context, save_state);
-	cpu_init();
+	if (save_state == 1 || save_state == 3)
+		cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state,
+			    omap34xx_do_sram_idle);
+	else
+		omap34xx_do_sram_idle(save_state);
 
 	/* Restore normal SDRC POWER settings */
 	if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@@ -445,10 +424,6 @@ void omap_sram_idle(void)
 	    core_next_state == PWRDM_POWER_OFF)
 		sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 
-	/* Restore table entry modified during MMU restoration */
-	if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
-		restore_table_entry();
-
 	/* CORE */
 	if (core_next_state < PWRDM_POWER_ON) {
 		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 12e9da2..6d1d083 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -211,37 +211,6 @@ save_context_wfi:
 	mrc	p15, 1, r5, c9, c0, 2	@ Read L2 AUX ctrl register
 	stmia	r8!, {r4-r5}		@ Push parameters for restore call
 
-        /* Check what that target sleep state is from r1 */
-	cmp	r1, #0x2		@ Only L2 lost, no need to save context
-	beq	clean_caches
-
-l1_logic_lost:
-	mov	r4, sp			@ Store sp
-	mrs	r5, spsr		@ Store spsr
-	mov	r6, lr			@ Store lr
-	stmia	r8!, {r4-r6}
-
-	mrc	p15, 0, r4, c1, c0, 2	@ Coprocessor access control register
-	mrc	p15, 0, r5, c2, c0, 0	@ TTBR0
-	mrc	p15, 0, r6, c2, c0, 1	@ TTBR1
-	mrc	p15, 0, r7, c2, c0, 2	@ TTBCR
-	stmia	r8!, {r4-r7}
-
-	mrc	p15, 0, r4, c3, c0, 0	@ Domain access Control Register
-	mrc	p15, 0, r5, c10, c2, 0	@ PRRR
-	mrc	p15, 0, r6, c10, c2, 1	@ NMRR
-	stmia	r8!,{r4-r6}
-
-	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
-	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
-	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
-	mrs	r7, cpsr		@ Store current cpsr
-	stmia	r8!, {r4-r7}
-
-	mrc	p15, 0, r4, c1, c0, 0	@ save control register
-	stmia	r8!, {r4}
-
-clean_caches:
 	/*
 	 * jump out to kernel flush routine
 	 *  - reuse that code is better
@@ -473,102 +442,11 @@ skipl2reen:
 	 */
 	mcr	p15, 0, r1, c7, c5, 0
 
-	ldr	r4, scratchpad_base
-	ldr	r3, [r4,#0xBC]
-	adds	r3, r3, #16
-
-	ldmia	r3!, {r4-r6}
-	mov	sp, r4			@ Restore sp
-	msr	spsr_cxsf, r5		@ Restore spsr
-	mov	lr, r6			@ Restore lr
-
-	ldmia	r3!, {r4-r7}
-	mcr	p15, 0, r4, c1, c0, 2	@ Coprocessor access Control Register
-	mcr	p15, 0, r5, c2, c0, 0	@ TTBR0
-	mcr	p15, 0, r6, c2, c0, 1	@ TTBR1
-	mcr	p15, 0, r7, c2, c0, 2	@ TTBCR
-
-	ldmia	r3!,{r4-r6}
-	mcr	p15, 0, r4, c3, c0, 0	@ Domain access Control Register
-	mcr	p15, 0, r5, c10, c2, 0	@ PRRR
-	mcr	p15, 0, r6, c10, c2, 1	@ NMRR
-
-
-	ldmia	r3!,{r4-r7}
-	mcr	p15, 0, r4, c13, c0, 1	@ Context ID
-	mcr	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
-	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
-	msr	cpsr, r7		@ store cpsr
-
-	/* Enabling MMU here */
-	mrc	p15, 0, r7, c2, c0, 2 	@ Read TTBRControl
-	/* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
-	and	r7, #0x7
-	cmp	r7, #0x0
-	beq	usettbr0
-ttbr_error:
-	/*
-	 * More work needs to be done to support N[0:2] value other than 0
-	 * So looping here so that the error can be detected
-	 */
-	b	ttbr_error
-usettbr0:
-	mrc	p15, 0, r2, c2, c0, 0
-	ldr	r5, ttbrbit_mask
-	and	r2, r5
-	mov	r4, pc
-	ldr	r5, table_index_mask
-	and	r4, r5			@ r4 = 31 to 20 bits of pc
-	/* Extract the value to be written to table entry */
-	ldr	r1, table_entry
-	/* r1 has the value to be written to table entry*/
-	add	r1, r1, r4
-	/* Getting the address of table entry to modify */
-	lsr	r4, #18
-	/* r2 has the location which needs to be modified */
-	add	r2, r4
-	/* Storing previous entry of location being modified */
-	ldr	r5, scratchpad_base
-	ldr	r4, [r2]
-	str	r4, [r5, #0xC0]
-	/* Modify the table entry */
-	str	r1, [r2]
-	/*
-	 * Storing address of entry being modified
-	 * - will be restored after enabling MMU
-	 */
-	ldr	r5, scratchpad_base
-	str	r2, [r5, #0xC4]
-
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c5, 4	@ Flush prefetch buffer
-	mcr	p15, 0, r0, c7, c5, 6	@ Invalidate branch predictor array
-	mcr	p15, 0, r0, c8, c5, 0	@ Invalidate instruction TLB
-	mcr	p15, 0, r0, c8, c6, 0	@ Invalidate data TLB
-	/*
-	 * Restore control register. This enables the MMU.
-	 * The caches and prediction are not enabled here, they
-	 * will be enabled after restoring the MMU table entry.
-	 */
-	ldmia	r3!, {r4}
-	/* Store previous value of control register in scratchpad */
-	str	r4, [r5, #0xC8]
-	ldr	r2, cache_pred_disable_mask
-	and	r4, r2
-	mcr	p15, 0, r4, c1, c0, 0
-	dsb
-	isb
-	ldr     r0, =restoremmu_on
-	bx      r0
-
-/*
- * ==============================
- * == Exit point from OFF mode ==
- * ==============================
- */
-restoremmu_on:
-	ldmfd	sp!, {r4 - r11, pc}	@ restore regs and return
+	/* Now branch to the common CPU resume function */
+	ldr	r0, =cpu_resume
+	bx	r0
 
+	.ltorg
 
 /*
  * Internal functions
-- 
1.7.4.4

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

A couple of things to point out here:

On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
> -	mrs	r7, cpsr		@ Store current cpsr
> -	stmia	r8!, {r4-r7}

1. The User r/w thread and process ID is not saved/restored by Linux over
context switches, so it doesn't serve any useful purpose to save and
restore over resume.

2. Compare the instruction saving and restoring the vector base address
(see below for the restore code.)

> -	ldmia	r3!,{r4-r7}
> -	mcr	p15, 0, r4, c13, c0, 1	@ Context ID
> -	mcr	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
> -	msr	cpsr, r7		@ store cpsr

Which means it's pointless saving and restoring that register, because
we already aren't restoring it (plus there's the possibility that if we
were to write to it, we'd get an abort.)

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

A couple of things to point out here:

On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
> -	mrs	r7, cpsr		@ Store current cpsr
> -	stmia	r8!, {r4-r7}

1. The User r/w thread and process ID is not saved/restored by Linux over
context switches, so it doesn't serve any useful purpose to save and
restore over resume.

2. Compare the instruction saving and restoring the vector base address
(see below for the restore code.)

> -	ldmia	r3!,{r4-r7}
> -	mcr	p15, 0, r4, c13, c0, 1	@ Context ID
> -	mcr	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
> -	msr	cpsr, r7		@ store cpsr

Which means it's pointless saving and restoring that register, because
we already aren't restoring it (plus there's the possibility that if we
were to write to it, we'd get an abort.)

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Santosh Shilimkar]

On 6/22/2011 9:40 PM, Russell King - ARM Linux wrote:
> A couple of things to point out here:
>
> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
>> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
>> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
>> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
>> -	mrs	r7, cpsr		@ Store current cpsr
>> -	stmia	r8!, {r4-r7}
>
> 1. The User r/w thread and process ID is not saved/restored by Linux over
> context switches, so it doesn't serve any useful purpose to save and
> restore over resume.
>
It will be needed for CPUIDLE I guess.

> 2. Compare the instruction saving and restoring the vector base address
> (see below for the restore code.)
>
That's typo. It should have been mcr. Actually VBAR isn't used on GP
devices but might be used on secure devices. I know that common suspend
code doesn't consider this register. It's fine to keep it that way
and if OMAP needs it, it can save/restored outside common code.

Regards
Santosh

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Santosh Shilimkar]

On 6/22/2011 9:40 PM, Russell King - ARM Linux wrote:
> A couple of things to point out here:
>
> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
>> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
>> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
>> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
>> -	mrs	r7, cpsr		@ Store current cpsr
>> -	stmia	r8!, {r4-r7}
>
> 1. The User r/w thread and process ID is not saved/restored by Linux over
> context switches, so it doesn't serve any useful purpose to save and
> restore over resume.
>
It will be needed for CPUIDLE I guess.

> 2. Compare the instruction saving and restoring the vector base address
> (see below for the restore code.)
>
That's typo. It should have been mcr. Actually VBAR isn't used on GP
devices but might be used on secure devices. I know that common suspend
code doesn't consider this register. It's fine to keep it that way
and if OMAP needs it, it can save/restored outside common code.

Regards
Santosh

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 05:03:39AM +0530, Santosh Shilimkar wrote:
> On 6/22/2011 9:40 PM, Russell King - ARM Linux wrote:
>> A couple of things to point out here:
>>
>> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
>>> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
>>> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
>>> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
>>> -	mrs	r7, cpsr		@ Store current cpsr
>>> -	stmia	r8!, {r4-r7}
>>
>> 1. The User r/w thread and process ID is not saved/restored by Linux over
>> context switches, so it doesn't serve any useful purpose to save and
>> restore over resume.
>>
> It will be needed for CPUIDLE I guess.

No it isn't.  It is not used by Linux at all - the only thread register
which is used is the User r/o thread register, and I've patched the
proc-v7 code to preserve that register.

>> 2. Compare the instruction saving and restoring the vector base address
>> (see below for the restore code.)
>>
> That's typo. It should have been mcr. Actually VBAR isn't used on GP
> devices but might be used on secure devices. I know that common suspend
> code doesn't consider this register. It's fine to keep it that way
> and if OMAP needs it, it can save/restored outside common code.

The kernel doesn't use or initialize the register, so its not something
which the kernel should be concerned about.  Presumably secure devices
need to restore the secure-mode version of that register.

However, there's an extra twist here:
| On an implementation that does not include the Security Extensions all
| CP15 c12 encodings are UNDEFINED.

And a further twist is this:
| B3.12.40 c12, Vector Base Address Register (VBAR)
| When the Security Extensions are implemented and high exception vectors are
| not selected, the Vector Base Address Register, VBAR, provides the exception
| base address for exceptions that are not handled in Monitor mode, see
| Exception vectors and the exception base address on page B1-30. The high
| exception vectors always have the base address 0xFFFF0000 and are not
| affected by the value of VBAR.

Since we always select high exception vectors, VBAR is not used, so we have
no requirement to save and restore this register on any ARMv7 MMU platform.
Given that it would be dangerous to do so (due to not knowing whether
security stuff is implemented or not) ignoring the presence of this register
is for the best.

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 05:03:39AM +0530, Santosh Shilimkar wrote:
> On 6/22/2011 9:40 PM, Russell King - ARM Linux wrote:
>> A couple of things to point out here:
>>
>> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
>>> -	mrc	p15, 0, r4, c13, c0, 1	@ Context ID
>>> -	mrc	p15, 0, r5, c13, c0, 2	@ User r/w thread and process ID
>>> -	mrc	p15, 0, r6, c12, c0, 0	@ Secure or NS vector base address
>>> -	mrs	r7, cpsr		@ Store current cpsr
>>> -	stmia	r8!, {r4-r7}
>>
>> 1. The User r/w thread and process ID is not saved/restored by Linux over
>> context switches, so it doesn't serve any useful purpose to save and
>> restore over resume.
>>
> It will be needed for CPUIDLE I guess.

No it isn't.  It is not used by Linux at all - the only thread register
which is used is the User r/o thread register, and I've patched the
proc-v7 code to preserve that register.

>> 2. Compare the instruction saving and restoring the vector base address
>> (see below for the restore code.)
>>
> That's typo. It should have been mcr. Actually VBAR isn't used on GP
> devices but might be used on secure devices. I know that common suspend
> code doesn't consider this register. It's fine to keep it that way
> and if OMAP needs it, it can save/restored outside common code.

The kernel doesn't use or initialize the register, so its not something
which the kernel should be concerned about.  Presumably secure devices
need to restore the secure-mode version of that register.

However, there's an extra twist here:
| On an implementation that does not include the Security Extensions all
| CP15 c12 encodings are UNDEFINED.

And a further twist is this:
| B3.12.40 c12, Vector Base Address Register (VBAR)
| When the Security Extensions are implemented and high exception vectors are
| not selected, the Vector Base Address Register, VBAR, provides the exception
| base address for exceptions that are not handled in Monitor mode, see
| Exception vectors and the exception base address on page B1-30. The high
| exception vectors always have the base address 0xFFFF0000 and are not
| affected by the value of VBAR.

Since we always select high exception vectors, VBAR is not used, so we have
no requirement to save and restore this register on any ARMv7 MMU platform.
Given that it would be dangerous to do so (due to not knowing whether
security stuff is implemented or not) ignoring the presence of this register
is for the best.

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [110622 08:24]:
> Convert sa11x0 to use the generic CPU suspend/resume support, rather
          ^^^^^^
Should be omap34xx above.

> than implementing its own version.  Tested on 3430 LDP.

Nice job with this series Russell!

Tony

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [110622 08:24]:
> Convert sa11x0 to use the generic CPU suspend/resume support, rather
          ^^^^^^
Should be omap34xx above.

> than implementing its own version.  Tested on 3430 LDP.

Nice job with this series Russell!

Tony

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> +	/* Now branch to the common CPU resume function */
> +	ldr	r0, =cpu_resume
> +	bx	r0
>  
> +	.ltorg

A slight correction - firstly this code does not run from SRAM.
Secondly, this will try to branch to the virtual address of cpu_resume
which is not a good idea.

Replace this with:
	b	cpu_resume

and comment out the auxillary control register write in proc-v7.S, and
it should work on OMAP3.

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> +	/* Now branch to the common CPU resume function */
> +	ldr	r0, =cpu_resume
> +	bx	r0
>  
> +	.ltorg

A slight correction - firstly this code does not run from SRAM.
Secondly, this will try to branch to the virtual address of cpu_resume
which is not a good idea.

Replace this with:
	b	cpu_resume

and comment out the auxillary control register write in proc-v7.S, and
it should work on OMAP3.

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 11:06:10AM +0100, Russell King - ARM Linux wrote:
> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> > +	/* Now branch to the common CPU resume function */
> > +	ldr	r0, =cpu_resume
> > +	bx	r0
> >  
> > +	.ltorg
> 
> A slight correction - firstly this code does not run from SRAM.
> Secondly, this will try to branch to the virtual address of cpu_resume
> which is not a good idea.
> 
> Replace this with:
> 	b	cpu_resume
> 
> and comment out the auxillary control register write in proc-v7.S, and
> it should work on OMAP3.

Actually... writing to the ACR seems fine on OMAP3.

Santosh,

I thought you pointed out a problem with the code in proc-v7.S which meant
there was a problem executing it in non-secure mode?  I can't seem to find
any problem there.  Could you re-state your concern please?

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Russell King - ARM Linux]

On Thu, Jun 23, 2011 at 11:06:10AM +0100, Russell King - ARM Linux wrote:
> On Wed, Jun 22, 2011 at 04:16:58PM +0100, Russell King - ARM Linux wrote:
> > +	/* Now branch to the common CPU resume function */
> > +	ldr	r0, =cpu_resume
> > +	bx	r0
> >  
> > +	.ltorg
> 
> A slight correction - firstly this code does not run from SRAM.
> Secondly, this will try to branch to the virtual address of cpu_resume
> which is not a good idea.
> 
> Replace this with:
> 	b	cpu_resume
> 
> and comment out the auxillary control register write in proc-v7.S, and
> it should work on OMAP3.

Actually... writing to the ACR seems fine on OMAP3.

Santosh,

I thought you pointed out a problem with the code in proc-v7.S which meant
there was a problem executing it in non-secure mode?  I can't seem to find
any problem there.  Could you re-state your concern please?

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Hi Russell,

Russell King - ARM Linux <linux@arm.linux.org.uk> writes:

> Convert sa11x0 to use the generic CPU suspend/resume support, rather
> than implementing its own version.  Tested on 3430 LDP.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

I tested this on 3430/n900 and 3530/Overo and it worked fine for
retention, but not for off.

Testing with off-mode, I found the MULTI_CPU path to be broken in
cpu_suspend (jumping to zero.)  Rebuilding for only OMAP3, it worked
fine for full-chip retention in suspend and idle as well as full-chip
off in suspend and idle.

I'm digging into the MULTI_CPU path now.

Kevin

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Hi Russell,

Russell King - ARM Linux <linux@arm.linux.org.uk> writes:

> Convert sa11x0 to use the generic CPU suspend/resume support, rather
> than implementing its own version.  Tested on 3430 LDP.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

I tested this on 3430/n900 and 3530/Overo and it worked fine for
retention, but not for off.

Testing with off-mode, I found the MULTI_CPU path to be broken in
cpu_suspend (jumping to zero.)  Rebuilding for only OMAP3, it worked
fine for full-chip retention in suspend and idle as well as full-chip
off in suspend and idle.

I'm digging into the MULTI_CPU path now.

Kevin

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Kevin Hilman <khilman@ti.com> writes:

> Hi Russell,
>
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>
>> Convert sa11x0 to use the generic CPU suspend/resume support, rather
>> than implementing its own version.  Tested on 3430 LDP.
>>
>> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> I tested this on 3430/n900 and 3530/Overo and it worked fine for
> retention, but not for off.
>
> Testing with off-mode, I found the MULTI_CPU path to be broken in
> cpu_suspend (jumping to zero.)  Rebuilding for only OMAP3, it worked
> fine for full-chip retention in suspend and idle as well as full-chip
> off in suspend and idle.
>
> I'm digging into the MULTI_CPU path now.

Here's a dump of the printk __log_buf using Lauterbach:

Looks like cpu_suspend is jumping to 0x0, which triggers the fault
handler which then triggers the BUG in might_sleep().

Now looking into why cpu_suspend is jumping to 0x0...

Kevin


<5>[    0.000000] Linux version 3.0.0-rc4-pm+initramfs+debug+cmdline-14038-g9ec291c (khilman@paris) (gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu3) ) #19 SMP Thu Jun 23 13:21:58 PDT 2011
<4>[    0.000000] CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c53c7f
<4>[    0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
<4>[    0.000000] Machine: Nokia RX-51 board
<4>[    0.000000] Ignoring unrecognised tag 0x414f4d50
<6>[    0.000000] bootconsole [earlycon0] enabled
<6>[    0.000000] Reserving 16777216 bytes SDRAM for VRAM
<4>[    0.000000] Memory policy: ECC disabled, Data cache writeback
<6>[    0.000000] OMAP3430/3530 ES3.1 (l2cache iva sgx neon isp )
<6>[    0.000000] SRAM: Mapped pa 0x40208000 to va 0xfe408000 size: 0x7000
<7>[    0.000000] On node 0 totalpages: 61440
<7>[    0.000000] free_area_init_node: node 0, pgdat c086de40, node_mem_map c0dc5000
<7>[    0.000000]   Normal zone: 512 pages used for memmap
<7>[    0.000000]   Normal zone: 0 pages reserved
<7>[    0.000000]   Normal zone: 60928 pages, LIFO batch:15
<6>[    0.000000] Clocking rate (Crystal/Core/MPU): 19.2/332/500 MHz
<6>[    0.000000] Reprogramming SDRC clock to 332000000 Hz
<6>[    0.000000] PERCPU: Embedded 7 pages/cpu @c0fca000 s7264 r8192 d13216 u32768
<7>[    0.000000] pcpu-alloc: s7264 r8192 d13216 u32768 alloc=8*4096
<7>[    0.000000] pcpu-alloc: [0] 0 
<4>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 60928
<5>[    0.000000] Kernel command line: console=ttyO2,115200n8 debug earlyprintk
<6>[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
<6>[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
<6>[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
<6>[    0.000000] Memory: 240MB = 240MB total
<5>[    0.000000] Memory: 229364k/229364k available, 32780k reserved, 0K highmem
<5>[    0.000000] Virtual kernel memory layout:
<5>[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
<5>[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
<5>[    0.000000]     DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
<5>[    0.000000]     vmalloc : 0xd0800000 - 0xf8000000   ( 632 MB)
<5>[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
<5>[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
<5>[    0.000000]       .init : 0xc0008000 - 0xc024f000   (2332 kB)
<5>[    0.000000]       .text : 0xc024f000 - 0xc07edf0c   (5756 kB)
<5>[    0.000000]       .data : 0xc07ee000 - 0xc086f260   ( 517 kB)
<5>[    0.000000]        .bss : 0xc086f284 - 0xc0dc4328   (5461 kB)
<6>[    0.000000] Hierarchical RCU implementation.
<6>[    0.000000] NR_IRQS:410
<6>[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
<6>[    0.000000] Total of 96 interrupts on 1 active controller
<6>[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
<6>[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
<6>[    0.000000] Console: colour dummy device 80x30
<4>[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
<4>[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
<4>[    0.000000] ... MAX_LOCK_DEPTH:          48
<4>[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
<4>[    0.000000] ... CLASSHASH_SIZE:          4096
<4>[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
<4>[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
<4>[    0.000000] ... CHAINHASH_SIZE:          16384
<4>[    0.000000]  memory used by lock dependency info: 3695 kB
<4>[    0.000000]  per task-struct memory footprint: 1152 bytes
<6>[    0.057434] Calibrating delay loop... 497.82 BogoMIPS (lpj=1941504)
<6>[    0.096252] pid_max: default: 32768 minimum: 301
<6>[    0.102050] Security Framework initialized
<6>[    0.106811] Mount-cache hash table entries: 512
<6>[    0.117370] CPU: Testing write buffer coherency: ok
<6>[    0.126129] Brought up 1 CPUs
<6>[    0.129302] SMP: Total of 1 processors activated (497.82 BogoMIPS).
<4>[    0.154693] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_core
<4>[    0.162261] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_per
<4>[    0.169677] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_wkup
<4>[    0.177642] omap_hwmod: gpt12_fck: missing clockdomain for gpt12_fck.
<4>[    0.200012] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
<4>[    0.220520] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
<4>[    0.240936] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
<4>[    0.248260] omap_hwmod: am35x_otg_hs: cannot be enabled (3)
<6>[    0.260345] print_constraints: dummy: 
<6>[    0.266113] NET: Registered protocol family 16
<6>[    0.272277] GPMC revision 5.0
<4>[    0.286712] omap_device: omap_gpio.0: new worst case activate latency 0: 91552
<6>[    0.297882] OMAP GPIO hardware version 2.5
<6>[    0.321319] omap_mux_init: Add partition: #1: core, flags: 0
<4>[    0.331848] omap_device: omap_uart.0: new worst case activate latency 0: 30517
<4>[    0.343688] omap_device: omap_uart.2: new worst case deactivate latency 0: 30517
<6>[    0.469421] hw-breakpoint: debug architecture 0x4 unsupported.
<6>[    0.496551] Reserving DMA channels 0 and 1 for HS ROM code
<6>[    0.502716] OMAP DMA hardware revision 4.0
<6>[    0.593872] bio: create slab <bio-0> at 0
<5>[    0.609985] SCSI subsystem initialized
<4>[    0.614715] omap_device: omap2_mcspi.1: new worst case activate latency 0: 61035
<4>[    0.628173] omap_device: omap2_mcspi.1: new worst case deactivate latency 0: 30517
<6>[    0.645477] usbcore: registered new interface driver usbfs
<6>[    0.652923] usbcore: registered new interface driver hub
<6>[    0.659942] usbcore: registered new device driver usb
<4>[    0.667724] omap_device: omap_i2c.1: new worst case activate latency 0: 30517
<6>[    0.675598] omap_i2c omap_i2c.1: bus 1 rev1.3.12 at 2200 kHz
<6>[    0.730743] twl4030: PIH (irq 7) chaining IRQs 368..375
<6>[    0.736480] twl4030: power (irq 373) chaining IRQs 376..383
<6>[    0.744873] twl4030: gpio (irq 368) chaining IRQs 384..401
<6>[    0.763610] print_constraints: VPLL: 1800 mV normal standby
<6>[    0.774322] print_constraints: VIO: 1800 mV normal standby
<6>[    0.783447] print_constraints: VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
<6>[    0.794433] print_constraints: VDAC: 1800 mV normal standby
<6>[    0.803253] print_constraints: VCSI: 1800 mV normal standby
<6>[    0.812744] print_constraints: VINTANA1: 1500 mV normal standby
<6>[    0.822753] print_constraints: VINTANA2: 2750 mV normal standby
<6>[    0.832489] print_constraints: VINTDIG: 1500 mV normal standby
<6>[    0.842102] print_constraints: VSDI_CSI: 1800 mV normal standby
<6>[    0.852020] print_constraints: V28_A: 2800 <--> 3000 mV at 2600 mV normal standby
<6>[    0.863037] print_constraints: VMMC2_IO_18: 1800 mV normal standby
<6>[    0.872772] print_constraints: V28: 2800 mV normal standby
<6>[    0.881744] print_constraints: VMMC2_30: 2800 <--> 3000 mV at 2800 mV normal standby
<6>[    0.892974] print_constraints: VCAM_ANA_28: 2800 mV normal standby
<4>[    0.900421] omap_device: omap_i2c.1: new worst case deactivate latency 0: 30517
<6>[    0.908538] omap_i2c omap_i2c.2: bus 2 rev1.3.12 at 100 kHz
<6>[    0.918792] omap_i2c omap_i2c.3: bus 3 rev1.3.12 at 400 kHz
<6>[    0.936279] Switching to clocksource 32k_counter
<6>[    0.945373] Switched to NOHz mode on CPU #0
<6>[    1.081390] NET: Registered protocol family 2
<6>[    1.087432] IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
<6>[    1.097198] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
<6>[    1.105194] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
<6>[    1.117156] TCP: Hash tables configured (established 8192 bind 8192)
<6>[    1.123962] TCP reno registered
<6>[    1.127319] UDP hash table entries: 128 (order: 1, 10240 bytes)
<6>[    1.133941] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes)
<6>[    1.141845] NET: Registered protocol family 1
<6>[    1.148284] RPC: Registered named UNIX socket transport module.
<6>[    1.154876] RPC: Registered udp transport module.
<6>[    1.159820] RPC: Registered tcp transport module.
<6>[    1.164825] RPC: Registered tcp NFSv4.1 backchannel transport module.
<4>[    1.272949] NetWinder Floating Point Emulator V0.97 (double precision)
<5>[    1.475921] VFS: Disk quotas dquot_6.5.2
<4>[    1.480499] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
<6>[    1.491271] JFFS2 version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
<6>[    1.500152] msgmni has been set to 447
<6>[    1.528320] io scheduler noop registered
<6>[    1.532470] io scheduler deadline registered
<6>[    1.537353] io scheduler cfq registered (default)
<6>[    1.548095] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
<6>[    1.564727] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 72) is a OMAP UART0
<6>[    1.575347] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 73) is a OMAP UART1
<6>[    1.584350] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 74) is a OMAP UART2
<6>[    1.592285] console [ttyO2] enabled, bootconsole disabled
<6>[    1.649993] brd: module loaded
<6>[    1.675323] loop: module loaded
<4>[    1.680358] omap_device: omap_i2c.1: new worst case activate latency 0: 122070
<3>[    1.697875] mtdoops: mtd device (mtddev=name/number) must be supplied
<6>[    1.705078] omap2-nand driver initializing
<6>[    1.710662] OneNAND driver initializing
<6>[    1.716064] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base d0880000, freq 83 MHz
<7>[    1.727447] OneNAND Manufacturer: Numonyx (0x20)
<6>[    1.732391] Muxed OneNAND 256MB 1.8V 16-bit (0x40)
<6>[    1.737426] OneNAND version = 0x0031
<7>[    1.741271] Chip support all block unlock
<7>[    1.745483] Chip has 2 plane
<6>[    1.750671] Scanning device for bad blocks
<7>[    1.813232] onenand_bbt_wait: ecc 0x2222 ctrl 0x2400 intr 0x8080 addr1 0x22a addr8 0x0
<6>[    1.821655] OneNAND eraseblock 554 is an initial bad block
<5>[    1.981475] Creating 6 MTD partitions on "omap2-onenand":
<5>[    1.987182] 0x000000000000-0x000000020000 : "bootloader"
<5>[    2.002593] 0x000000020000-0x000000080000 : "config"
<5>[    2.014892] 0x000000080000-0x0000000c0000 : "log"
<5>[    2.026123] 0x0000000c0000-0x0000002c0000 : "kernel"
<5>[    2.037902] 0x0000002c0000-0x0000004c0000 : "initfs"
<5>[    2.049499] 0x0000004c0000-0x000010000000 : "rootfs"
<4>[    2.086059] smc91x: not found (-19).
<6>[    2.093109] usbcore: registered new interface driver asix
<6>[    2.099792] usbcore: registered new interface driver cdc_ether
<6>[    2.106903] usbcore: registered new interface driver net1080
<6>[    2.113586] usbcore: registered new interface driver cdc_subset
<6>[    2.120666] usbcore: registered new interface driver zaurus
<6>[    2.126770] cdc_ncm: 01-June-2011
<6>[    2.131042] usbcore: registered new interface driver cdc_ncm
<6>[    2.140289] usbcore: registered new interface driver cdc_wdm
<6>[    2.146423] Initializing USB Mass Storage driver...
<6>[    2.152404] usbcore: registered new interface driver usb-storage
<6>[    2.158935] USB Mass Storage support registered.
<6>[    2.165527] usbcore: registered new interface driver libusual
<6>[    2.172576] usbcore: registered new interface driver usbtest
<6>[    2.182830] mousedev: PS/2 mouse device common for all mice
<6>[    2.194427] input: gpio-keys as /devices/platform/gpio-keys/input/input0
<6>[    2.208007] input: TWL4030 Keypad as /devices/platform/omap/omap_i2c.1/i2c-1/1-004a/twl4030_keypad/input/input1
<6>[    2.230712] input: twl4030_pwrbutton as /devices/platform/omap/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input2
<6>[    2.249114] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
<4>[    2.256164] twl_rtc twl_rtc: Power up reset detected.
<6>[    2.262542] twl_rtc twl_rtc: Enabling TWL-RTC.
<6>[    2.268890] i2c /dev entries driver
<6>[    2.279052] Driver for 1-wire Dallas network protocol.
<4>[    2.287200] omap_device: omap_wdt.-1: new worst case activate latency 0: 30517
<6>[    2.297027] OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
<4>[    2.303619] omap_device: omap_wdt.-1: new worst case deactivate latency 0: 30517
<3>[    2.312927] twl4030_wdt twl4030_wdt: Failed to register misc device
<4>[    2.319763] twl4030_wdt: probe of twl4030_wdt failed with error -16
<6>[    2.327423] cpuidle: using governor ladder
<6>[    2.331756] cpuidle: using governor menu
<6>[    2.354064] usbcore: registered new interface driver usbhid
<6>[    2.360107] usbhid: USB HID core driver
<6>[    2.364227] oprofile: hardware counters not available
<6>[    2.369567] oprofile: using timer interrupt.
<6>[    2.374969] TCP cubic registered
<6>[    2.378387] Initializing XFRM netlink socket
<6>[    2.383178] NET: Registered protocol family 17
<6>[    2.388092] NET: Registered protocol family 15
<5>[    2.393157] Registering the dns_resolver key type
<6>[    2.398986] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
<6>[    2.407165] ThumbEE CPU extension supported.
<4>[    2.440399] sr_init: No PMIC hook to init smartreflex
<6>[    2.446624] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
<6>[    2.455810] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
<6>[    2.465698] SmartReflex Class3 initialized
<6>[    2.515441] clock: disabling unused clocks to save power
<6>[    2.528503] regulator_init_complete: VCSI: disabling
<6>[    2.536132] twl_rtc twl_rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
<6>[    2.550109] Freeing init memory: 2332K
<6>[    2.888244] mmc1: new high speed MMC card at address 0001
<6>[    2.897979] mmcblk0: mmc1:0001 MMC32G 29.8 GiB 
<6>[    2.903869] mmcblk0boot0: mmc1:0001 MMC32G partition 1 512 KiB
<6>[    2.910705] mmcblk0boot1: mmc1:0001 MMC32G partition 2 512 KiB
<6>[    2.925170]  mmcblk0: p1
<6>[    2.935729]  mmcblk0boot1: unknown partition table
<6>[    2.946075]  mmcblk0boot0: unknown partition table
<6>[   49.616638] PM: Syncing filesystems ... done.
<7>[   49.624084] PM: Preparing system for mem sleep
<4>[   49.635040] Freezing user space processes ... (elapsed 0.02 seconds) done.
<4>[   49.663970] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
<7>[   49.695281] PM: Entering mem sleep
<4>[   49.700592] Suspending console(s) (use no_console_suspend to debug)
<6>[   49.897003] PM: suspend of devices complete after 181.963 msecs
<6>[   49.900787] PM: late suspend of devices complete after 3.740 msecs
<4>[   49.900909] Disabling non-boot CPUs ...
<4>[   49.901641] omap_device: omap_uart.2: new worst case deactivate latency 0: 122070
<3>[   49.901916] BUG: sleeping function called from invalid context at /work/kernel/omap/pm/arch/arm/mm/fault.c:310
<3>[   49.901947] in_atomic(): 0, irqs_disabled(): 128, pid: 583, name: sh
<4>[   49.901947] 4 locks held by sh/583:
<4>[   49.901977]  #0:  (&buffer->mutex){+.+.+.}, at: [<c039135c>] sysfs_write_file+0x28/0x184
<4>[   49.902038]  #1:  (s_active#3){.+.+.+}, at: [<c0391410>] sysfs_write_file+0xdc/0x184
<4>[   49.902069]  #2:  (pm_mutex){+.+.+.}, at: [<c02dab44>] enter_state+0x28/0x128
<4>[   49.902130]  #3:  (&mm->mmap_sem){++++++}, at: [<c064e57c>] do_page_fault+0xb8/0x258
<4>[   49.902160] irq event stamp: 24205
<4>[   49.902191] hardirqs last  enabled at (24204): [<c064a9a0>] __mutex_unlock_slowpath+0xec/0x168
<4>[   49.902221] hardirqs last disabled at (24205): [<c02da93c>] suspend_enter+0xc4/0x15c
<4>[   49.902221] softirqs last  enabled at (21791): [<c029e290>] irq_exit+0x94/0xb0
<4>[   49.902282] softirqs last disabled at (21778): [<c029e290>] irq_exit+0x94/0xb0
<4>[   49.902343] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c064e66c>] (do_page_fault+0x1a8/0x258)
<4>[   49.902374] [<c064e66c>] (do_page_fault+0x1a8/0x258) from [<c024f45c>] (do_PrefetchAbort+0x34/0x9c)
<4>[   49.902404] [<c024f45c>] (do_PrefetchAbort+0x34/0x9c) from [<c064c278>] (__pabt_svc+0x58/0xa0)
<4>[   49.902435] Exception stack(0xce2cde28 to 0xce2cde70)
<4>[   49.902435] de20:                   ce2cde84 c0000000 00000003 c026e1b0 c086fd10 c0808358
<4>[   49.902465] de40: 8e2cde78 c086f5d4 00000009 000003e9 c0803870 00000002 c0000000 ce2cde70
<4>[   49.902496] de60: c025ef04 00000000 60000093 ffffffff
<4>[   49.902526] [<c064c278>] (__pabt_svc+0x58/0xa0) from [<c025ef04>] (cpu_suspend+0x44/0x60)
<4>[   49.902557] [<c025ef04>] (cpu_suspend+0x44/0x60) from [<ce2cde84>] (0xce2cde84)
<1>[   49.902587] Unable to handle kernel NULL pointer dereference at virtual address 00000000
<1>[   49.902618] pgd = ce310000
<1>[   49.902618] [00000000] *pgd=8e2f1831, *pte=00000000, *ppte=00000000
<0>[   49.902648] Internal error: Oops: 80000007 [#1] SMP
<4>[   49.902679] Modules linked in:
<4>[   49.902709] CPU: 0    Not tainted  (3.0.0-rc4-pm+initramfs+debug+cmdline-14038-g9ec291c #19)
<4>[   49.902709] PC is at 0x0
<4>[   49.902740] LR is at cpu_suspend+0x44/0x60
<4>[   49.902740] pc : [<00000000>]    lr : [<c025ef04>]    psr: 60000093
<4>[   49.902770] sp : ce2cde70  ip : c0000000  fp : 00000002
<4>[   49.902770] r10: c0803870  r9 : 000003e9  r8 : 00000009
<4>[   49.902801] r7 : c086f5d4  r6 : 8e2cde78  r5 : c0808358  r4 : c086fd10
<4>[   49.902801] r3 : c026e1b0  r2 : 00000003  r1 : c0000000  r0 : ce2cde84
<4>[   49.902832] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user
<4>[   49.902832] Control: 10c5387d  Table: 8e310019  DAC: 00000015
<0>[   49.902862] Process sh (pid: 583, stack limit = 0xce2cc2f8)
<0>[   49.902893] Stack: (0xce2cde70 to 0xce2ce000)
<0>[   49.902893] de60:                                     00000003 c026e1b0 c0000000 ce2cde84
<0>[   49.902923] de80: c0000000 c086fd10 00000000 00000000 c086f5d4 00000009 000003e9 00000003
<0>[   49.902954] dea0: 00000002 c026e534 c080a394 c080a3a0 00000003 00000000 00000000 ce8017e0
<0>[   49.902984] dec0: c07540c0 c026e91c c0d8227c 00000000 00000003 c02da9a8 00000000 00000003
<0>[   49.902984] dee0: 00000003 c0d8227c c086eacc c02daa94 00000003 c07540c0 00000000 00000003
<0>[   49.903015] df00: 00000004 c02dac08 ce2e5000 00000003 c06580f0 c02da15c 00000004 ce26e0c0
<0>[   49.903045] df20: ce26e0d8 ce2cdf80 ce818588 00000004 c066d8c8 c0464dc8 00000004 c0391434
<0>[   49.903076] df40: ce82a680 00000004 40080000 ce2cdf80 00000004 ce2cc000 00000000 c0339794
<0>[   49.903106] df60: 00000001 c025a108 ce82a680 40080000 00000000 00000000 00000004 c0339a1c
<0>[   49.903137] df80: 00000000 00000000 00000004 00000000 00000004 001fbac8 00000004 00000004
<0>[   49.903137] dfa0: c025a108 c0259f40 00000004 001fbac8 00000001 40080000 00000004 00000000
<0>[   49.903167] dfc0: 00000004 001fbac8 00000004 00000004 40080000 00000000 00201000 00000002
<0>[   49.903198] dfe0: 00000000 be87b5f8 00101ffc 00008e8c 60000010 00000001 00000000 00000000
<4>[   49.903228] [<c025ef04>] (cpu_suspend+0x44/0x60) from [<ce2cde84>] (0xce2cde84)
<0>[   49.903259] Code: bad PC value
<4>[   49.903289] ---[ end trace cba5fa1741250aad ]---
<4>[   49.903991] ------------[ cut here ]------------
<4>[   49.904052] WARNING: at /work/kernel/omap/pm/kernel/time/timekeeping.c:245 ktime_get+0x134/0x164()
<4>[   49.904052] Modules linked in:
<4>[   49.904113] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c0296f20>] (warn_slowpath_common+0x4c/0x64)
<4>[   49.904144] [<c0296f20>] (warn_slowpath_common+0x4c/0x64) from [<c0296f54>] (warn_slowpath_null+0x1c/0x24)
<4>[   49.904174] [<c0296f54>] (warn_slowpath_null+0x1c/0x24) from [<c02c07f8>] (ktime_get+0x134/0x164)
<4>[   49.904205] [<c02c07f8>] (ktime_get+0x134/0x164) from [<c02c7198>] (tick_nohz_stop_sched_tick+0x70/0x46c)
<4>[   49.904235] [<c02c7198>] (tick_nohz_stop_sched_tick+0x70/0x46c) from [<c025b1e0>] (cpu_idle+0x2c/0x104)
<4>[   49.904266] [<c025b1e0>] (cpu_idle+0x2c/0x104) from [<c0008a70>] (start_kernel+0x2a8/0x300)
<4>[   49.904296] [<c0008a70>] (start_kernel+0x2a8/0x300) from [<80008040>] (0x80008040)
<4>[   49.904327] ---[ end trace cba5fa1741250aae ]---
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[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Kevin Hilman <khilman@ti.com> writes:

> Hi Russell,
>
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>
>> Convert sa11x0 to use the generic CPU suspend/resume support, rather
>> than implementing its own version.  Tested on 3430 LDP.
>>
>> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> I tested this on 3430/n900 and 3530/Overo and it worked fine for
> retention, but not for off.
>
> Testing with off-mode, I found the MULTI_CPU path to be broken in
> cpu_suspend (jumping to zero.)  Rebuilding for only OMAP3, it worked
> fine for full-chip retention in suspend and idle as well as full-chip
> off in suspend and idle.
>
> I'm digging into the MULTI_CPU path now.

Here's a dump of the printk __log_buf using Lauterbach:

Looks like cpu_suspend is jumping to 0x0, which triggers the fault
handler which then triggers the BUG in might_sleep().

Now looking into why cpu_suspend is jumping to 0x0...

Kevin


<5>[    0.000000] Linux version 3.0.0-rc4-pm+initramfs+debug+cmdline-14038-g9ec291c (khilman at paris) (gcc version 4.5.2 (Ubuntu/Linaro 4.5.2-8ubuntu3) ) #19 SMP Thu Jun 23 13:21:58 PDT 2011
<4>[    0.000000] CPU: ARMv7 Processor [411fc083] revision 3 (ARMv7), cr=10c53c7f
<4>[    0.000000] CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
<4>[    0.000000] Machine: Nokia RX-51 board
<4>[    0.000000] Ignoring unrecognised tag 0x414f4d50
<6>[    0.000000] bootconsole [earlycon0] enabled
<6>[    0.000000] Reserving 16777216 bytes SDRAM for VRAM
<4>[    0.000000] Memory policy: ECC disabled, Data cache writeback
<6>[    0.000000] OMAP3430/3530 ES3.1 (l2cache iva sgx neon isp )
<6>[    0.000000] SRAM: Mapped pa 0x40208000 to va 0xfe408000 size: 0x7000
<7>[    0.000000] On node 0 totalpages: 61440
<7>[    0.000000] free_area_init_node: node 0, pgdat c086de40, node_mem_map c0dc5000
<7>[    0.000000]   Normal zone: 512 pages used for memmap
<7>[    0.000000]   Normal zone: 0 pages reserved
<7>[    0.000000]   Normal zone: 60928 pages, LIFO batch:15
<6>[    0.000000] Clocking rate (Crystal/Core/MPU): 19.2/332/500 MHz
<6>[    0.000000] Reprogramming SDRC clock to 332000000 Hz
<6>[    0.000000] PERCPU: Embedded 7 pages/cpu @c0fca000 s7264 r8192 d13216 u32768
<7>[    0.000000] pcpu-alloc: s7264 r8192 d13216 u32768 alloc=8*4096
<7>[    0.000000] pcpu-alloc: [0] 0 
<4>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 60928
<5>[    0.000000] Kernel command line: console=ttyO2,115200n8 debug earlyprintk
<6>[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
<6>[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
<6>[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
<6>[    0.000000] Memory: 240MB = 240MB total
<5>[    0.000000] Memory: 229364k/229364k available, 32780k reserved, 0K highmem
<5>[    0.000000] Virtual kernel memory layout:
<5>[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
<5>[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
<5>[    0.000000]     DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
<5>[    0.000000]     vmalloc : 0xd0800000 - 0xf8000000   ( 632 MB)
<5>[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
<5>[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
<5>[    0.000000]       .init : 0xc0008000 - 0xc024f000   (2332 kB)
<5>[    0.000000]       .text : 0xc024f000 - 0xc07edf0c   (5756 kB)
<5>[    0.000000]       .data : 0xc07ee000 - 0xc086f260   ( 517 kB)
<5>[    0.000000]        .bss : 0xc086f284 - 0xc0dc4328   (5461 kB)
<6>[    0.000000] Hierarchical RCU implementation.
<6>[    0.000000] NR_IRQS:410
<6>[    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 4.0) with 96 interrupts
<6>[    0.000000] Total of 96 interrupts on 1 active controller
<6>[    0.000000] OMAP clockevent source: GPTIMER1 at 32768 Hz
<6>[    0.000000] sched_clock: 32 bits at 32kHz, resolution 30517ns, wraps every 131071999ms
<6>[    0.000000] Console: colour dummy device 80x30
<4>[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
<4>[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
<4>[    0.000000] ... MAX_LOCK_DEPTH:          48
<4>[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
<4>[    0.000000] ... CLASSHASH_SIZE:          4096
<4>[    0.000000] ... MAX_LOCKDEP_ENTRIES:     16384
<4>[    0.000000] ... MAX_LOCKDEP_CHAINS:      32768
<4>[    0.000000] ... CHAINHASH_SIZE:          16384
<4>[    0.000000]  memory used by lock dependency info: 3695 kB
<4>[    0.000000]  per task-struct memory footprint: 1152 bytes
<6>[    0.057434] Calibrating delay loop... 497.82 BogoMIPS (lpj=1941504)
<6>[    0.096252] pid_max: default: 32768 minimum: 301
<6>[    0.102050] Security Framework initialized
<6>[    0.106811] Mount-cache hash table entries: 512
<6>[    0.117370] CPU: Testing write buffer coherency: ok
<6>[    0.126129] Brought up 1 CPUs
<6>[    0.129302] SMP: Total of 1 processors activated (497.82 BogoMIPS).
<4>[    0.154693] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_core
<4>[    0.162261] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_per
<4>[    0.169677] omap_hwmod: _populate_mpu_rt_base found no _mpu_rt_va for l4_wkup
<4>[    0.177642] omap_hwmod: gpt12_fck: missing clockdomain for gpt12_fck.
<4>[    0.200012] omap_hwmod: i2c1: softreset failed (waited 10000 usec)
<4>[    0.220520] omap_hwmod: i2c2: softreset failed (waited 10000 usec)
<4>[    0.240936] omap_hwmod: i2c3: softreset failed (waited 10000 usec)
<4>[    0.248260] omap_hwmod: am35x_otg_hs: cannot be enabled (3)
<6>[    0.260345] print_constraints: dummy: 
<6>[    0.266113] NET: Registered protocol family 16
<6>[    0.272277] GPMC revision 5.0
<4>[    0.286712] omap_device: omap_gpio.0: new worst case activate latency 0: 91552
<6>[    0.297882] OMAP GPIO hardware version 2.5
<6>[    0.321319] omap_mux_init: Add partition: #1: core, flags: 0
<4>[    0.331848] omap_device: omap_uart.0: new worst case activate latency 0: 30517
<4>[    0.343688] omap_device: omap_uart.2: new worst case deactivate latency 0: 30517
<6>[    0.469421] hw-breakpoint: debug architecture 0x4 unsupported.
<6>[    0.496551] Reserving DMA channels 0 and 1 for HS ROM code
<6>[    0.502716] OMAP DMA hardware revision 4.0
<6>[    0.593872] bio: create slab <bio-0> at 0
<5>[    0.609985] SCSI subsystem initialized
<4>[    0.614715] omap_device: omap2_mcspi.1: new worst case activate latency 0: 61035
<4>[    0.628173] omap_device: omap2_mcspi.1: new worst case deactivate latency 0: 30517
<6>[    0.645477] usbcore: registered new interface driver usbfs
<6>[    0.652923] usbcore: registered new interface driver hub
<6>[    0.659942] usbcore: registered new device driver usb
<4>[    0.667724] omap_device: omap_i2c.1: new worst case activate latency 0: 30517
<6>[    0.675598] omap_i2c omap_i2c.1: bus 1 rev1.3.12 at 2200 kHz
<6>[    0.730743] twl4030: PIH (irq 7) chaining IRQs 368..375
<6>[    0.736480] twl4030: power (irq 373) chaining IRQs 376..383
<6>[    0.744873] twl4030: gpio (irq 368) chaining IRQs 384..401
<6>[    0.763610] print_constraints: VPLL: 1800 mV normal standby
<6>[    0.774322] print_constraints: VIO: 1800 mV normal standby
<6>[    0.783447] print_constraints: VMMC1: 1850 <--> 3150 mV at 3000 mV normal standby
<6>[    0.794433] print_constraints: VDAC: 1800 mV normal standby
<6>[    0.803253] print_constraints: VCSI: 1800 mV normal standby
<6>[    0.812744] print_constraints: VINTANA1: 1500 mV normal standby
<6>[    0.822753] print_constraints: VINTANA2: 2750 mV normal standby
<6>[    0.832489] print_constraints: VINTDIG: 1500 mV normal standby
<6>[    0.842102] print_constraints: VSDI_CSI: 1800 mV normal standby
<6>[    0.852020] print_constraints: V28_A: 2800 <--> 3000 mV at 2600 mV normal standby
<6>[    0.863037] print_constraints: VMMC2_IO_18: 1800 mV normal standby
<6>[    0.872772] print_constraints: V28: 2800 mV normal standby
<6>[    0.881744] print_constraints: VMMC2_30: 2800 <--> 3000 mV at 2800 mV normal standby
<6>[    0.892974] print_constraints: VCAM_ANA_28: 2800 mV normal standby
<4>[    0.900421] omap_device: omap_i2c.1: new worst case deactivate latency 0: 30517
<6>[    0.908538] omap_i2c omap_i2c.2: bus 2 rev1.3.12 at 100 kHz
<6>[    0.918792] omap_i2c omap_i2c.3: bus 3 rev1.3.12 at 400 kHz
<6>[    0.936279] Switching to clocksource 32k_counter
<6>[    0.945373] Switched to NOHz mode on CPU #0
<6>[    1.081390] NET: Registered protocol family 2
<6>[    1.087432] IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
<6>[    1.097198] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
<6>[    1.105194] TCP bind hash table entries: 8192 (order: 6, 294912 bytes)
<6>[    1.117156] TCP: Hash tables configured (established 8192 bind 8192)
<6>[    1.123962] TCP reno registered
<6>[    1.127319] UDP hash table entries: 128 (order: 1, 10240 bytes)
<6>[    1.133941] UDP-Lite hash table entries: 128 (order: 1, 10240 bytes)
<6>[    1.141845] NET: Registered protocol family 1
<6>[    1.148284] RPC: Registered named UNIX socket transport module.
<6>[    1.154876] RPC: Registered udp transport module.
<6>[    1.159820] RPC: Registered tcp transport module.
<6>[    1.164825] RPC: Registered tcp NFSv4.1 backchannel transport module.
<4>[    1.272949] NetWinder Floating Point Emulator V0.97 (double precision)
<5>[    1.475921] VFS: Disk quotas dquot_6.5.2
<4>[    1.480499] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes)
<6>[    1.491271] JFFS2 version 2.2. (NAND) (SUMMARY)  ? 2001-2006 Red Hat, Inc.
<6>[    1.500152] msgmni has been set to 447
<6>[    1.528320] io scheduler noop registered
<6>[    1.532470] io scheduler deadline registered
<6>[    1.537353] io scheduler cfq registered (default)
<6>[    1.548095] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
<6>[    1.564727] omap_uart.0: ttyO0 at MMIO 0x4806a000 (irq = 72) is a OMAP UART0
<6>[    1.575347] omap_uart.1: ttyO1 at MMIO 0x4806c000 (irq = 73) is a OMAP UART1
<6>[    1.584350] omap_uart.2: ttyO2 at MMIO 0x49020000 (irq = 74) is a OMAP UART2
<6>[    1.592285] console [ttyO2] enabled, bootconsole disabled
<6>[    1.649993] brd: module loaded
<6>[    1.675323] loop: module loaded
<4>[    1.680358] omap_device: omap_i2c.1: new worst case activate latency 0: 122070
<3>[    1.697875] mtdoops: mtd device (mtddev=name/number) must be supplied
<6>[    1.705078] omap2-nand driver initializing
<6>[    1.710662] OneNAND driver initializing
<6>[    1.716064] omap2-onenand omap2-onenand: initializing on CS0, phys base 0x04000000, virtual base d0880000, freq 83 MHz
<7>[    1.727447] OneNAND Manufacturer: Numonyx (0x20)
<6>[    1.732391] Muxed OneNAND 256MB 1.8V 16-bit (0x40)
<6>[    1.737426] OneNAND version = 0x0031
<7>[    1.741271] Chip support all block unlock
<7>[    1.745483] Chip has 2 plane
<6>[    1.750671] Scanning device for bad blocks
<7>[    1.813232] onenand_bbt_wait: ecc 0x2222 ctrl 0x2400 intr 0x8080 addr1 0x22a addr8 0x0
<6>[    1.821655] OneNAND eraseblock 554 is an initial bad block
<5>[    1.981475] Creating 6 MTD partitions on "omap2-onenand":
<5>[    1.987182] 0x000000000000-0x000000020000 : "bootloader"
<5>[    2.002593] 0x000000020000-0x000000080000 : "config"
<5>[    2.014892] 0x000000080000-0x0000000c0000 : "log"
<5>[    2.026123] 0x0000000c0000-0x0000002c0000 : "kernel"
<5>[    2.037902] 0x0000002c0000-0x0000004c0000 : "initfs"
<5>[    2.049499] 0x0000004c0000-0x000010000000 : "rootfs"
<4>[    2.086059] smc91x: not found (-19).
<6>[    2.093109] usbcore: registered new interface driver asix
<6>[    2.099792] usbcore: registered new interface driver cdc_ether
<6>[    2.106903] usbcore: registered new interface driver net1080
<6>[    2.113586] usbcore: registered new interface driver cdc_subset
<6>[    2.120666] usbcore: registered new interface driver zaurus
<6>[    2.126770] cdc_ncm: 01-June-2011
<6>[    2.131042] usbcore: registered new interface driver cdc_ncm
<6>[    2.140289] usbcore: registered new interface driver cdc_wdm
<6>[    2.146423] Initializing USB Mass Storage driver...
<6>[    2.152404] usbcore: registered new interface driver usb-storage
<6>[    2.158935] USB Mass Storage support registered.
<6>[    2.165527] usbcore: registered new interface driver libusual
<6>[    2.172576] usbcore: registered new interface driver usbtest
<6>[    2.182830] mousedev: PS/2 mouse device common for all mice
<6>[    2.194427] input: gpio-keys as /devices/platform/gpio-keys/input/input0
<6>[    2.208007] input: TWL4030 Keypad as /devices/platform/omap/omap_i2c.1/i2c-1/1-004a/twl4030_keypad/input/input1
<6>[    2.230712] input: twl4030_pwrbutton as /devices/platform/omap/omap_i2c.1/i2c-1/1-0049/twl4030_pwrbutton/input/input2
<6>[    2.249114] twl_rtc twl_rtc: rtc core: registered twl_rtc as rtc0
<4>[    2.256164] twl_rtc twl_rtc: Power up reset detected.
<6>[    2.262542] twl_rtc twl_rtc: Enabling TWL-RTC.
<6>[    2.268890] i2c /dev entries driver
<6>[    2.279052] Driver for 1-wire Dallas network protocol.
<4>[    2.287200] omap_device: omap_wdt.-1: new worst case activate latency 0: 30517
<6>[    2.297027] OMAP Watchdog Timer Rev 0x31: initial timeout 60 sec
<4>[    2.303619] omap_device: omap_wdt.-1: new worst case deactivate latency 0: 30517
<3>[    2.312927] twl4030_wdt twl4030_wdt: Failed to register misc device
<4>[    2.319763] twl4030_wdt: probe of twl4030_wdt failed with error -16
<6>[    2.327423] cpuidle: using governor ladder
<6>[    2.331756] cpuidle: using governor menu
<6>[    2.354064] usbcore: registered new interface driver usbhid
<6>[    2.360107] usbhid: USB HID core driver
<6>[    2.364227] oprofile: hardware counters not available
<6>[    2.369567] oprofile: using timer interrupt.
<6>[    2.374969] TCP cubic registered
<6>[    2.378387] Initializing XFRM netlink socket
<6>[    2.383178] NET: Registered protocol family 17
<6>[    2.388092] NET: Registered protocol family 15
<5>[    2.393157] Registering the dns_resolver key type
<6>[    2.398986] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 1
<6>[    2.407165] ThumbEE CPU extension supported.
<4>[    2.440399] sr_init: No PMIC hook to init smartreflex
<6>[    2.446624] smartreflex smartreflex.0: omap_sr_probe: SmartReflex driver initialized
<6>[    2.455810] smartreflex smartreflex.1: omap_sr_probe: SmartReflex driver initialized
<6>[    2.465698] SmartReflex Class3 initialized
<6>[    2.515441] clock: disabling unused clocks to save power
<6>[    2.528503] regulator_init_complete: VCSI: disabling
<6>[    2.536132] twl_rtc twl_rtc: setting system clock to 2000-01-01 00:00:00 UTC (946684800)
<6>[    2.550109] Freeing init memory: 2332K
<6>[    2.888244] mmc1: new high speed MMC card at address 0001
<6>[    2.897979] mmcblk0: mmc1:0001 MMC32G 29.8 GiB 
<6>[    2.903869] mmcblk0boot0: mmc1:0001 MMC32G partition 1 512 KiB
<6>[    2.910705] mmcblk0boot1: mmc1:0001 MMC32G partition 2 512 KiB
<6>[    2.925170]  mmcblk0: p1
<6>[    2.935729]  mmcblk0boot1: unknown partition table
<6>[    2.946075]  mmcblk0boot0: unknown partition table
<6>[   49.616638] PM: Syncing filesystems ... done.
<7>[   49.624084] PM: Preparing system for mem sleep
<4>[   49.635040] Freezing user space processes ... (elapsed 0.02 seconds) done.
<4>[   49.663970] Freezing remaining freezable tasks ... (elapsed 0.02 seconds) done.
<7>[   49.695281] PM: Entering mem sleep
<4>[   49.700592] Suspending console(s) (use no_console_suspend to debug)
<6>[   49.897003] PM: suspend of devices complete after 181.963 msecs
<6>[   49.900787] PM: late suspend of devices complete after 3.740 msecs
<4>[   49.900909] Disabling non-boot CPUs ...
<4>[   49.901641] omap_device: omap_uart.2: new worst case deactivate latency 0: 122070
<3>[   49.901916] BUG: sleeping function called from invalid context at /work/kernel/omap/pm/arch/arm/mm/fault.c:310
<3>[   49.901947] in_atomic(): 0, irqs_disabled(): 128, pid: 583, name: sh
<4>[   49.901947] 4 locks held by sh/583:
<4>[   49.901977]  #0:  (&buffer->mutex){+.+.+.}, at: [<c039135c>] sysfs_write_file+0x28/0x184
<4>[   49.902038]  #1:  (s_active#3){.+.+.+}, at: [<c0391410>] sysfs_write_file+0xdc/0x184
<4>[   49.902069]  #2:  (pm_mutex){+.+.+.}, at: [<c02dab44>] enter_state+0x28/0x128
<4>[   49.902130]  #3:  (&mm->mmap_sem){++++++}, at: [<c064e57c>] do_page_fault+0xb8/0x258
<4>[   49.902160] irq event stamp: 24205
<4>[   49.902191] hardirqs last  enabled at (24204): [<c064a9a0>] __mutex_unlock_slowpath+0xec/0x168
<4>[   49.902221] hardirqs last disabled at (24205): [<c02da93c>] suspend_enter+0xc4/0x15c
<4>[   49.902221] softirqs last  enabled at (21791): [<c029e290>] irq_exit+0x94/0xb0
<4>[   49.902282] softirqs last disabled at (21778): [<c029e290>] irq_exit+0x94/0xb0
<4>[   49.902343] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c064e66c>] (do_page_fault+0x1a8/0x258)
<4>[   49.902374] [<c064e66c>] (do_page_fault+0x1a8/0x258) from [<c024f45c>] (do_PrefetchAbort+0x34/0x9c)
<4>[   49.902404] [<c024f45c>] (do_PrefetchAbort+0x34/0x9c) from [<c064c278>] (__pabt_svc+0x58/0xa0)
<4>[   49.902435] Exception stack(0xce2cde28 to 0xce2cde70)
<4>[   49.902435] de20:                   ce2cde84 c0000000 00000003 c026e1b0 c086fd10 c0808358
<4>[   49.902465] de40: 8e2cde78 c086f5d4 00000009 000003e9 c0803870 00000002 c0000000 ce2cde70
<4>[   49.902496] de60: c025ef04 00000000 60000093 ffffffff
<4>[   49.902526] [<c064c278>] (__pabt_svc+0x58/0xa0) from [<c025ef04>] (cpu_suspend+0x44/0x60)
<4>[   49.902557] [<c025ef04>] (cpu_suspend+0x44/0x60) from [<ce2cde84>] (0xce2cde84)
<1>[   49.902587] Unable to handle kernel NULL pointer dereference at virtual address 00000000
<1>[   49.902618] pgd = ce310000
<1>[   49.902618] [00000000] *pgd=8e2f1831, *pte=00000000, *ppte=00000000
<0>[   49.902648] Internal error: Oops: 80000007 [#1] SMP
<4>[   49.902679] Modules linked in:
<4>[   49.902709] CPU: 0    Not tainted  (3.0.0-rc4-pm+initramfs+debug+cmdline-14038-g9ec291c #19)
<4>[   49.902709] PC is at 0x0
<4>[   49.902740] LR is at cpu_suspend+0x44/0x60
<4>[   49.902740] pc : [<00000000>]    lr : [<c025ef04>]    psr: 60000093
<4>[   49.902770] sp : ce2cde70  ip : c0000000  fp : 00000002
<4>[   49.902770] r10: c0803870  r9 : 000003e9  r8 : 00000009
<4>[   49.902801] r7 : c086f5d4  r6 : 8e2cde78  r5 : c0808358  r4 : c086fd10
<4>[   49.902801] r3 : c026e1b0  r2 : 00000003  r1 : c0000000  r0 : ce2cde84
<4>[   49.902832] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment user
<4>[   49.902832] Control: 10c5387d  Table: 8e310019  DAC: 00000015
<0>[   49.902862] Process sh (pid: 583, stack limit = 0xce2cc2f8)
<0>[   49.902893] Stack: (0xce2cde70 to 0xce2ce000)
<0>[   49.902893] de60:                                     00000003 c026e1b0 c0000000 ce2cde84
<0>[   49.902923] de80: c0000000 c086fd10 00000000 00000000 c086f5d4 00000009 000003e9 00000003
<0>[   49.902954] dea0: 00000002 c026e534 c080a394 c080a3a0 00000003 00000000 00000000 ce8017e0
<0>[   49.902984] dec0: c07540c0 c026e91c c0d8227c 00000000 00000003 c02da9a8 00000000 00000003
<0>[   49.902984] dee0: 00000003 c0d8227c c086eacc c02daa94 00000003 c07540c0 00000000 00000003
<0>[   49.903015] df00: 00000004 c02dac08 ce2e5000 00000003 c06580f0 c02da15c 00000004 ce26e0c0
<0>[   49.903045] df20: ce26e0d8 ce2cdf80 ce818588 00000004 c066d8c8 c0464dc8 00000004 c0391434
<0>[   49.903076] df40: ce82a680 00000004 40080000 ce2cdf80 00000004 ce2cc000 00000000 c0339794
<0>[   49.903106] df60: 00000001 c025a108 ce82a680 40080000 00000000 00000000 00000004 c0339a1c
<0>[   49.903137] df80: 00000000 00000000 00000004 00000000 00000004 001fbac8 00000004 00000004
<0>[   49.903137] dfa0: c025a108 c0259f40 00000004 001fbac8 00000001 40080000 00000004 00000000
<0>[   49.903167] dfc0: 00000004 001fbac8 00000004 00000004 40080000 00000000 00201000 00000002
<0>[   49.903198] dfe0: 00000000 be87b5f8 00101ffc 00008e8c 60000010 00000001 00000000 00000000
<4>[   49.903228] [<c025ef04>] (cpu_suspend+0x44/0x60) from [<ce2cde84>] (0xce2cde84)
<0>[   49.903259] Code: bad PC value
<4>[   49.903289] ---[ end trace cba5fa1741250aad ]---
<4>[   49.903991] ------------[ cut here ]------------
<4>[   49.904052] WARNING: at /work/kernel/omap/pm/kernel/time/timekeeping.c:245 ktime_get+0x134/0x164()
<4>[   49.904052] Modules linked in:
<4>[   49.904113] [<c0261218>] (unwind_backtrace+0x0/0xf0) from [<c0296f20>] (warn_slowpath_common+0x4c/0x64)
<4>[   49.904144] [<c0296f20>] (warn_slowpath_common+0x4c/0x64) from [<c0296f54>] (warn_slowpath_null+0x1c/0x24)
<4>[   49.904174] [<c0296f54>] (warn_slowpath_null+0x1c/0x24) from [<c02c07f8>] (ktime_get+0x134/0x164)
<4>[   49.904205] [<c02c07f8>] (ktime_get+0x134/0x164) from [<c02c7198>] (tick_nohz_stop_sched_tick+0x70/0x46c)
<4>[   49.904235] [<c02c7198>] (tick_nohz_stop_sched_tick+0x70/0x46c) from [<c025b1e0>] (cpu_idle+0x2c/0x104)
<4>[   49.904266] [<c025b1e0>] (cpu_idle+0x2c/0x104) from [<c0008a70>] (start_kernel+0x2a8/0x300)
<4>[   49.904296] [<c0008a70>] (start_kernel+0x2a8/0x300) from [<80008040>] (0x80008040)
<4>[   49.904327] ---[ end trace cba5fa1741250aae ]---

Re: [PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Kevin Hilman <khilman@ti.com> writes:

> Hi Russell,
>
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>
>> Convert sa11x0 to use the generic CPU suspend/resume support, rather
>> than implementing its own version.  Tested on 3430 LDP.
>>
>> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> I tested this on 3430/n900 and 3530/Overo and it worked fine for
> retention, but not for off.
>
> Testing with off-mode, I found the MULTI_CPU path to be broken in
> cpu_suspend (jumping to zero.)  

Problem found, and patch sent to list:

[PATCH] ARM: pm: add v7 suspend/resume functions to v7_processor functions

With that patch, off-mode in both suspend and idle is working on
3430/n900 and 3530/Overo when built in MULTI_CPU mode also.

Kevin

[PATCH 25/25] ARM: pm: omap34xx: convert to generic suspend/resume support

[Kevin Hilman]

Kevin Hilman <khilman@ti.com> writes:

> Hi Russell,
>
> Russell King - ARM Linux <linux@arm.linux.org.uk> writes:
>
>> Convert sa11x0 to use the generic CPU suspend/resume support, rather
>> than implementing its own version.  Tested on 3430 LDP.
>>
>> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
>
> I tested this on 3430/n900 and 3530/Overo and it worked fine for
> retention, but not for off.
>
> Testing with off-mode, I found the MULTI_CPU path to be broken in
> cpu_suspend (jumping to zero.)  

Problem found, and patch sent to list:

[PATCH] ARM: pm: add v7 suspend/resume functions to v7_processor functions

With that patch, off-mode in both suspend and idle is working on
3430/n900 and 3530/Overo when built in MULTI_CPU mode also.

Kevin

Re: [PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 04:08:16PM +0100, Russell King - ARM Linux wrote:
> Tested on Assabet (SA1100) and 3430LDP only.

Correction - because suspend only goes into retention mode, these
changes have not been tested on the 3430.  Someone who knows what
they're doing with the mega-complicated OMAPs (and so knows how to
trigger the required modes to test these code paths) needs to test
this.

It will currently fail when trying to call cpu_resume() because we're
trying the virtual address for that function, whereas it needs to be
the physical address.  That's left as an exercise to solve (easiest
way is probably to pass virt_to_phys(cpu_resume) into _omap_sram_idle
and get it to save that away in SRAM.)

[PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Russell King - ARM Linux]

On Wed, Jun 22, 2011 at 04:08:16PM +0100, Russell King - ARM Linux wrote:
> Tested on Assabet (SA1100) and 3430LDP only.

Correction - because suspend only goes into retention mode, these
changes have not been tested on the 3430.  Someone who knows what
they're doing with the mega-complicated OMAPs (and so knows how to
trigger the required modes to test these code paths) needs to test
this.

It will currently fail when trying to call cpu_resume() because we're
trying the virtual address for that function, whereas it needs to be
the physical address.  That's left as an exercise to solve (easiest
way is probably to pass virt_to_phys(cpu_resume) into _omap_sram_idle
and get it to save that away in SRAM.)

Re: [PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Santosh Shilimkar]

On 6/23/2011 2:31 AM, Russell King - ARM Linux wrote:
> On Wed, Jun 22, 2011 at 04:08:16PM +0100, Russell King - ARM Linux wrote:
>> Tested on Assabet (SA1100) and 3430LDP only.
>
> Correction - because suspend only goes into retention mode, these
> changes have not been tested on the 3430.  Someone who knows what
> they're doing with the mega-complicated OMAPs (and so knows how to
> trigger the required modes to test these code paths) needs to test
> this.
>
> It will currently fail when trying to call cpu_resume() because we're
> trying the virtual address for that function, whereas it needs to be
> the physical address.  That's left as an exercise to solve (easiest
> way is probably to pass virt_to_phys(cpu_resume) into _omap_sram_idle
> and get it to save that away in SRAM.)
>
Firstly thanks for taking time to include OMAP this time. Even if the
changes are not tested, we can get them working with necessary fixes.

Have looked at your series briefly and have some comments for the same.
Am planning to test these patches, but it might take bit more time.

Will update the results as soon as I have them.

Regards
Santosh

[PATCH 00/25 v2] Re-jig cpu_suspend for a saner calling convention

[Santosh Shilimkar]

On 6/23/2011 2:31 AM, Russell King - ARM Linux wrote:
> On Wed, Jun 22, 2011 at 04:08:16PM +0100, Russell King - ARM Linux wrote:
>> Tested on Assabet (SA1100) and 3430LDP only.
>
> Correction - because suspend only goes into retention mode, these
> changes have not been tested on the 3430.  Someone who knows what
> they're doing with the mega-complicated OMAPs (and so knows how to
> trigger the required modes to test these code paths) needs to test
> this.
>
> It will currently fail when trying to call cpu_resume() because we're
> trying the virtual address for that function, whereas it needs to be
> the physical address.  That's left as an exercise to solve (easiest
> way is probably to pass virt_to_phys(cpu_resume) into _omap_sram_idle
> and get it to save that away in SRAM.)
>
Firstly thanks for taking time to include OMAP this time. Even if the
changes are not tested, we can get them working with necessary fixes.

Have looked at your series briefly and have some comments for the same.
Am planning to test these patches, but it might take bit more time.

Will update the results as soon as I have them.

Regards
Santosh