* [PATCH 00/23] entry assembly cleanups
@ 2011-06-29 9:18 Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro Russell King - ARM Linux
` (24 more replies)
0 siblings, 25 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:18 UTC (permalink / raw)
To: linux-arm-kernel
This patch series cleans up the entry assembly and CPU abort helpers.
Notable things about this patch series:
1. We now call the data and prefetch abort handlers with interrupts
disabled. This makes us more like x86 in this regard, and means
we can move the PMU abort special case out of the assembly.
As a result of this, we now always tell the irqs tracing code that
irqs are turned off whenever we enter an exception handler from SVC
mode.
2. The CPU abort helpers are no longer functions in their own right -
they tail-call through to the main C abort handlers now, resulting
in less entry code.
3. IRQs off tracing is implemented more accurately for user aborts.
4. Avoid reloading PSR into r5 on return in SVC exception handlers as
we now preserve the value across the code. There is no reason for
PSR to be changed while processing an SVC mode interrupt, prefetch
or data abort.
I did notice this though in abort-lv4t.S:
tst r8, #1 << 20 @ L = 1 -> write?
where the comment is wrong. L means load. Set for load, so it's a
read. The ARM610/ARM710 (proc-arm6_7.S) got this right, so I'm not
sure why abort-lv4t.S (which is basically a copy plus thumb handling)
decided to change this to be incorrect. I haven't fixed this in this
series.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
@ 2011-06-29 9:19 ` Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 02/23] ARM: entry: shark: don't directly reference registers in macros Russell King - ARM Linux
` (23 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:19 UTC (permalink / raw)
To: linux-arm-kernel
Platforms provide an empty irq_prio_table macro, and as nothing uses
this macro, it can simply be removed.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mach-bcmring/include/mach/entry-macro.S | 4 ----
arch/arm/mach-davinci/include/mach/entry-macro.S | 3 ---
arch/arm/mach-h720x/include/mach/entry-macro.S | 3 ---
arch/arm/mach-lpc32xx/include/mach/entry-macro.S | 4 ----
arch/arm/mach-omap2/include/mach/entry-macro.S | 3 ---
arch/arm/mach-pnx4008/include/mach/entry-macro.S | 5 -----
arch/arm/plat-mxc/include/mach/entry-macro.S | 4 ----
7 files changed, 0 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
index 7d393ca..94c950d 100644
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -80,7 +80,3 @@
.macro arch_ret_to_user, tmp1, tmp2
.endm
-
- .macro irq_prio_table
- .endm
-
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index fbdebc7..e14c0dc 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -46,6 +46,3 @@
#endif
1002:
.endm
-
- .macro irq_prio_table
- .endm
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
index 6d3b917..c3948e5 100644
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ b/arch/arm/mach-h720x/include/mach/entry-macro.S
@@ -57,9 +57,6 @@
tst \irqstat, #1 @ bit 0 should be set
.endm
- .macro irq_prio_table
- .endm
-
#else
#error hynix processor selection missmatch
#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index 870227c..b725f6c 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -41,7 +41,3 @@
rsb \irqnr, \irqnr, #31
teq \irqstat, #0
.endm
-
- .macro irq_prio_table
- .endm
-
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index a48690b..ceb8b7e 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -165,6 +165,3 @@
#endif
#endif /* MULTI_OMAP2 */
-
- .macro irq_prio_table
- .endm
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
index 8003037..db7eeeb 100644
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
@@ -120,8 +120,3 @@
1003:
.endm
-
- .macro irq_prio_table
- .endm
-
-
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 2e49e71..066d464 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -78,7 +78,3 @@
movs \irqnr, \irqnr
#endif
.endm
-
- @ irq priority table (not used)
- .macro irq_prio_table
- .endm
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 02/23] ARM: entry: shark: don't directly reference registers in macros
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro Russell King - ARM Linux
@ 2011-06-29 9:19 ` Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 03/23] ARM: entry: prefetch/data abort helpers: convert to macros Russell King - ARM Linux
` (22 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:19 UTC (permalink / raw)
To: linux-arm-kernel
Directly referencing registers in macros makes assembly code harder
to change, because the macros have side effects which are non-obvious.
Use the provided 'base' register rather than directly referencing r4.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mach-shark/include/mach/entry-macro.S | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index e2853c0..0bb6cc6 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -11,17 +11,17 @@
.endm
.macro get_irqnr_preamble, base, tmp
+ mov \base, #0xe0000000
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- mov r4, #0xe0000000
mov \irqstat, #0x0C
- strb \irqstat, [r4, #0x20] @outb(0x0C, 0x20) /* Poll command */
- ldrb \irqnr, [r4, #0x20] @irq = inb(0x20) & 7
+ strb \irqstat, [\base, #0x20] @outb(0x0C, 0x20) /* Poll command */
+ ldrb \irqnr, [\base, #0x20] @irq = inb(0x20) & 7
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 43f
@@ -29,8 +29,8 @@
teq \irqnr, #2
bne 44f
43: mov \irqstat, #0x0C
- strb \irqstat, [r4, #0xa0] @outb(0x0C, 0xA0) /* Poll command */
- ldrb \irqnr, [r4, #0xa0] @irq = (inb(0xA0) & 7) + 8
+ strb \irqstat, [\base, #0xa0] @outb(0x0C, 0xA0) /* Poll command */
+ ldrb \irqnr, [\base, #0xa0] @irq = (inb(0xA0) & 7) + 8
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 44f
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 03/23] ARM: entry: prefetch/data abort helpers: convert to macros
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 02/23] ARM: entry: shark: don't directly reference registers in macros Russell King - ARM Linux
@ 2011-06-29 9:19 ` Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (21 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:19 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 85 +++++++++++++++++------------------------
1 files changed, 35 insertions(+), 50 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 90c62cd..dbe9eb8 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -44,6 +44,37 @@
9997:
.endm
+ .macro pabt_helper
+ mov r0, r2 @ pass address of aborted instruction.
+#ifdef MULTI_PABORT
+ ldr r4, .LCprocfns
+ mov lr, pc
+ ldr pc, [r4, #PROCESSOR_PABT_FUNC]
+#else
+ bl CPU_PABORT_HANDLER
+#endif
+ .endm
+
+ .macro dabt_helper
+
+ @
+ @ Call the processor-specific abort handler:
+ @
+ @ r2 - aborted context pc
+ @ r3 - aborted context cpsr
+ @
+ @ The abort handler must return the aborted address in r0, and
+ @ the fault status register in r1. r9 must be preserved.
+ @
+#ifdef MULTI_DABORT
+ ldr r4, .LCprocfns
+ mov lr, pc
+ ldr pc, [r4, #PROCESSOR_DABT_FUNC]
+#else
+ bl CPU_DABORT_HANDLER
+#endif
+ .endm
+
#ifdef CONFIG_KPROBES
.section .kprobes.text,"ax",%progbits
#else
@@ -159,22 +190,7 @@ __dabt_svc:
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
- @
- @ Call the processor-specific abort handler:
- @
- @ r2 - aborted context pc
- @ r3 - aborted context cpsr
- @
- @ The abort handler must return the aborted address in r0, and
- @ the fault status register in r1. r9 must be preserved.
- @
-#ifdef MULTI_DABORT
- ldr r4, .LCprocfns
- mov lr, pc
- ldr pc, [r4, #PROCESSOR_DABT_FUNC]
-#else
- bl CPU_DABORT_HANDLER
-#endif
+ dabt_helper
@
@ set desired IRQ state, then call main handler
@@ -298,14 +314,7 @@ __pabt_svc:
tst r3, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
- mov r0, r2 @ pass address of aborted instruction.
-#ifdef MULTI_PABORT
- ldr r4, .LCprocfns
- mov lr, pc
- ldr pc, [r4, #PROCESSOR_PABT_FUNC]
-#else
- bl CPU_PABORT_HANDLER
-#endif
+ pabt_helper
debug_entry r1
msr cpsr_c, r9 @ Maybe enable interrupts
mov r2, sp @ regs
@@ -401,23 +410,7 @@ ENDPROC(__pabt_svc)
__dabt_usr:
usr_entry
kuser_cmpxchg_check
-
- @
- @ Call the processor-specific abort handler:
- @
- @ r2 - aborted context pc
- @ r3 - aborted context cpsr
- @
- @ The abort handler must return the aborted address in r0, and
- @ the fault status register in r1.
- @
-#ifdef MULTI_DABORT
- ldr r4, .LCprocfns
- mov lr, pc
- ldr pc, [r4, #PROCESSOR_DABT_FUNC]
-#else
- bl CPU_DABORT_HANDLER
-#endif
+ dabt_helper
@
@ IRQs on, then call the main handler
@@ -682,15 +675,7 @@ ENDPROC(__und_usr_unknown)
.align 5
__pabt_usr:
usr_entry
-
- mov r0, r2 @ pass address of aborted instruction.
-#ifdef MULTI_PABORT
- ldr r4, .LCprocfns
- mov lr, pc
- ldr pc, [r4, #PROCESSOR_PABT_FUNC]
-#else
- bl CPU_PABORT_HANDLER
-#endif
+ pabt_helper
debug_entry r1
enable_irq @ Enable interrupts
mov r2, sp @ regs
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 00/23] entry assembly cleanups
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (2 preceding siblings ...)
2011-06-29 9:19 ` [PATCH 03/23] ARM: entry: prefetch/data abort helpers: convert to macros Russell King - ARM Linux
@ 2011-06-29 9:20 ` Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 04/23] ARM: entry: prefetch/data abort helpers: avoid corrupting r4 Russell King - ARM Linux
` (20 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Oops, here's the overall diffstat:
arch/arm/include/asm/entry-macro-multi.S | 14 +-
arch/arm/kernel/entry-armv.S | 271 +++++++++-------------
arch/arm/kernel/entry-header.S | 19 --
arch/arm/kernel/hw_breakpoint.c | 6 +-
arch/arm/mach-bcmring/include/mach/entry-macro.S | 4 -
arch/arm/mach-davinci/include/mach/entry-macro.S | 3 -
arch/arm/mach-h720x/include/mach/entry-macro.S | 3 -
arch/arm/mach-lpc32xx/include/mach/entry-macro.S | 4 -
arch/arm/mach-omap2/include/mach/entry-macro.S | 3 -
arch/arm/mach-pnx4008/include/mach/entry-macro.S | 5 -
arch/arm/mach-shark/include/mach/entry-macro.S | 10 +-
arch/arm/mm/abort-ev4.S | 17 +-
arch/arm/mm/abort-ev4t.S | 17 +-
arch/arm/mm/abort-ev5t.S | 19 +-
arch/arm/mm/abort-ev5tj.S | 25 +--
arch/arm/mm/abort-ev6.S | 25 +--
arch/arm/mm/abort-ev7.S | 25 +--
arch/arm/mm/abort-lv4t.S | 141 ++++++------
arch/arm/mm/abort-macro.S | 34 ++--
arch/arm/mm/abort-nommu.S | 10 +-
arch/arm/mm/alignment.c | 3 +
arch/arm/mm/fault.c | 4 +
arch/arm/mm/pabort-legacy.S | 10 +-
arch/arm/mm/pabort-v6.S | 10 +-
arch/arm/mm/pabort-v7.S | 11 +-
arch/arm/mm/proc-arm6_7.S | 90 ++++----
arch/arm/plat-mxc/include/mach/entry-macro.S | 4 -
27 files changed, 333 insertions(+), 454 deletions(-)
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 04/23] ARM: entry: prefetch/data abort helpers: avoid corrupting r4
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (3 preceding siblings ...)
2011-06-29 9:20 ` [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
@ 2011-06-29 9:20 ` Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 05/23] ARM: entry: abort-macro: specify registers to be used for macros Russell King - ARM Linux
` (19 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Replace r4 with ip for calling abort helpers - ip is allowed to be
corrupted by called functions in the ABI, so it makes more sense to
use such a register.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index dbe9eb8..6855f6d 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -47,9 +47,9 @@
.macro pabt_helper
mov r0, r2 @ pass address of aborted instruction.
#ifdef MULTI_PABORT
- ldr r4, .LCprocfns
+ ldr ip, .LCprocfns
mov lr, pc
- ldr pc, [r4, #PROCESSOR_PABT_FUNC]
+ ldr pc, [ip, #PROCESSOR_PABT_FUNC]
#else
bl CPU_PABORT_HANDLER
#endif
@@ -67,9 +67,9 @@
@ the fault status register in r1. r9 must be preserved.
@
#ifdef MULTI_DABORT
- ldr r4, .LCprocfns
+ ldr ip, .LCprocfns
mov lr, pc
- ldr pc, [r4, #PROCESSOR_DABT_FUNC]
+ ldr pc, [ip, #PROCESSOR_DABT_FUNC]
#else
bl CPU_DABORT_HANDLER
#endif
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 05/23] ARM: entry: abort-macro: specify registers to be used for macros
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (4 preceding siblings ...)
2011-06-29 9:20 ` [PATCH 04/23] ARM: entry: prefetch/data abort helpers: avoid corrupting r4 Russell King - ARM Linux
@ 2011-06-29 9:20 ` Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 06/23] ARM: entry: abort-macro: simplify do_ldrd_abort Russell King - ARM Linux
` (18 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:20 UTC (permalink / raw)
To: linux-arm-kernel
Require all callers of abort macros to specify the registers to be
used. This improves the documentation at the callsites as to which
registers are being used by this assembly code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-ev4t.S | 2 +-
arch/arm/mm/abort-ev5t.S | 4 ++--
arch/arm/mm/abort-ev5tj.S | 4 ++--
arch/arm/mm/abort-ev6.S | 4 ++--
arch/arm/mm/abort-macro.S | 30 +++++++++++++++---------------
5 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index b628254..9910123 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -22,7 +22,7 @@
ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ check write
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 02251b5..800e8d4 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -22,10 +22,10 @@
ENTRY(v5t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
mov pc, lr
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d6..bcb58d2 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort)
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 1478aa5..ef526e7 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -35,12 +35,12 @@ ENTRY(v6_early_abort)
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
tst r3, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort
+ do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
ldreq r3, [r2] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
reveq r3, r3
#endif
- do_ldrd_abort
+ do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index d7cb1bf..8d3b9f9 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -9,33 +9,33 @@
*
*/
- .macro do_thumb_abort
- tst r3, #PSR_T_BIT
+ .macro do_thumb_abort, fsr, pc, psr, tmp
+ tst \psr, #PSR_T_BIT
beq not_thumb
- ldrh r3, [r2] @ Read aborted Thumb instruction
- and r3, r3, # 0xfe00 @ Mask opcode field
- cmp r3, # 0x5600 @ Is it ldrsb?
- orreq r3, r3, #1 << 11 @ Set L-bit if yes
- tst r3, #1 << 11 @ L = 0 -> write
- orreq r1, r1, #1 << 11 @ yes.
+ ldrh \tmp, [\pc] @ Read aborted Thumb instruction
+ and \tmp, \tmp, # 0xfe00 @ Mask opcode field
+ cmp \tmp, # 0x5600 @ Is it ldrsb?
+ orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
+ tst \tmp, #1 << 11 @ L = 0 -> write
+ orreq \psr, \psr, #1 << 11 @ yes.
mov pc, lr
not_thumb:
.endm
/*
- * We check for the following insturction encoding for LDRD.
+ * We check for the following instruction encoding for LDRD.
*
- * [27:25] == 0
+ * [27:25] == 000
* [7:4] == 1101
* [20] == 0
*/
- .macro do_ldrd_abort
- tst r3, #0x0e000000 @ [27:25] == 0
+ .macro do_ldrd_abort, tmp, insn
+ tst \insn, #0x0e000000 @ [27:25] == 0
bne not_ldrd
- and r2, r3, #0x000000f0 @ [7:4] == 1101
- cmp r2, #0x000000d0
+ and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
+ cmp \tmp, #0x000000d0
bne not_ldrd
- tst r3, #1 << 20 @ [20] == 0
+ tst \insn, #1 << 20 @ [20] == 0
moveq pc, lr
not_ldrd:
.endm
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 06/23] ARM: entry: abort-macro: simplify do_ldrd_abort
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (5 preceding siblings ...)
2011-06-29 9:20 ` [PATCH 05/23] ARM: entry: abort-macro: specify registers to be used for macros Russell King - ARM Linux
@ 2011-06-29 9:20 ` Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 07/23] ARM: entry: no need to increase preempt count for IRQ handlers Russell King - ARM Linux
` (17 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:20 UTC (permalink / raw)
To: linux-arm-kernel
We can test bits 27:25 and 20 of the instruction at the same time;
there's no need to separate out the check of bit 20.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-macro.S | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index 8d3b9f9..af97a10 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -30,12 +30,10 @@ not_thumb:
* [20] == 0
*/
.macro do_ldrd_abort, tmp, insn
- tst \insn, #0x0e000000 @ [27:25] == 0
+ tst \insn, #0x0e100000 @ [27:25,20] == 0
bne not_ldrd
and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
cmp \tmp, #0x000000d0
- bne not_ldrd
- tst \insn, #1 << 20 @ [20] == 0
moveq pc, lr
not_ldrd:
.endm
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 07/23] ARM: entry: no need to increase preempt count for IRQ handlers
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (6 preceding siblings ...)
2011-06-29 9:20 ` [PATCH 06/23] ARM: entry: abort-macro: simplify do_ldrd_abort Russell King - ARM Linux
@ 2011-06-29 9:21 ` Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 08/23] ARM: entry: no need to check parent IRQ mask in IRQ handler return Russell King - ARM Linux
` (16 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:21 UTC (permalink / raw)
To: linux-arm-kernel
irq_enter() and irq_exit() already take care of the preempt_count
handling for interrupts, which increment and decrement the hardirq
bits of the preempt count. So we can remove the preempt count handing
in our IRQ entry/exit assembly, like x86 did some 9 years ago.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 27 ++++-----------------------
1 files changed, 4 insertions(+), 23 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 6855f6d..1e5f387 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -220,16 +220,12 @@ __irq_svc:
#ifdef CONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_off
#endif
-#ifdef CONFIG_PREEMPT
- get_thread_info tsk
- ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
- add r7, r8, #1 @ increment it
- str r7, [tsk, #TI_PREEMPT]
-#endif
irq_handler
+
#ifdef CONFIG_PREEMPT
- str r8, [tsk, #TI_PREEMPT] @ restore preempt count
+ get_thread_info tsk
+ ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
ldr r0, [tsk, #TI_FLAGS] @ get flags
teq r8, #0 @ if preempt count != 0
movne r0, #0 @ force flags to 0
@@ -432,23 +428,8 @@ __irq_usr:
bl trace_hardirqs_off
#endif
- get_thread_info tsk
-#ifdef CONFIG_PREEMPT
- ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
- add r7, r8, #1 @ increment it
- str r7, [tsk, #TI_PREEMPT]
-#endif
-
irq_handler
-#ifdef CONFIG_PREEMPT
- ldr r0, [tsk, #TI_PREEMPT]
- str r8, [tsk, #TI_PREEMPT]
- teq r0, r7
- ARM( strne r0, [r0, -r0] )
- THUMB( movne r0, #0 )
- THUMB( strne r0, [r0] )
-#endif
-
+ get_thread_info tsk
mov why, #0
b ret_to_user_from_irq
UNWIND(.fnend )
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 08/23] ARM: entry: no need to check parent IRQ mask in IRQ handler return
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (7 preceding siblings ...)
2011-06-29 9:21 ` [PATCH 07/23] ARM: entry: no need to increase preempt count for IRQ handlers Russell King - ARM Linux
@ 2011-06-29 9:21 ` Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 09/23] ARM: entry: rejig register allocation in exception entry handlers Russell King - ARM Linux
` (15 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:21 UTC (permalink / raw)
To: linux-arm-kernel
There's no point checking to see whether IRQs were masked in the parent
context when returning from IRQ handling - the fact that we're handling
an IRQ means that the parent context must have had IRQs unmasked.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 1e5f387..fd42e66 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -234,8 +234,9 @@ __irq_svc:
#endif
ldr r4, [sp, #S_PSR] @ irqs are already disabled
#ifdef CONFIG_TRACE_IRQFLAGS
- tst r4, #PSR_I_BIT
- bleq trace_hardirqs_on
+ @ The parent context IRQs must have been enabled to get here in
+ @ the first place, so there's no point checking the PSR I bit.
+ bl trace_hardirqs_on
#endif
svc_exit r4 @ return from exception
UNWIND(.fnend )
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 09/23] ARM: entry: rejig register allocation in exception entry handlers
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (8 preceding siblings ...)
2011-06-29 9:21 ` [PATCH 08/23] ARM: entry: no need to check parent IRQ mask in IRQ handler return Russell King - ARM Linux
@ 2011-06-29 9:21 ` Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 10/23] ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0 Russell King - ARM Linux
` (14 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:21 UTC (permalink / raw)
To: linux-arm-kernel
This allows us to avoid moving registers twice to work around the
clobbered registers when we add calls to trace_hardirqs_{on,off}.
Ensure that all SVC handlers return with SPSR in r5 for consistency.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 75 ++++++++++++++++++++++-------------------
1 files changed, 40 insertions(+), 35 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index fd42e66..353b639 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -45,7 +45,7 @@
.endm
.macro pabt_helper
- mov r0, r2 @ pass address of aborted instruction.
+ mov r0, r4 @ pass address of aborted instruction.
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc
@@ -56,6 +56,8 @@
.endm
.macro dabt_helper
+ mov r2, r4
+ mov r3, r5
@
@ Call the processor-specific abort handler:
@@ -157,26 +159,26 @@ ENDPROC(__und_invalid)
SPFIX( subeq sp, sp, #4 )
stmia sp, {r1 - r12}
- ldmia r0, {r1 - r3}
- add r5, sp, #S_SP - 4 @ here for interlock avoidance
- mov r4, #-1 @ "" "" "" ""
- add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
- SPFIX( addeq r0, r0, #4 )
- str r1, [sp, #-4]! @ save the "real" r0 copied
+ ldmia r0, {r3 - r5}
+ add r7, sp, #S_SP - 4 @ here for interlock avoidance
+ mov r6, #-1 @ "" "" "" ""
+ add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+ SPFIX( addeq r2, r2, #4 )
+ str r3, [sp, #-4]! @ save the "real" r0 copied
@ from the exception stack
- mov r1, lr
+ mov r3, lr
@
@ We are now ready to fill in the remaining blanks on the stack:
@
- @ r0 - sp_svc
- @ r1 - lr_svc
- @ r2 - lr_<exception>, already fixed up for correct return/restart
- @ r3 - spsr_<exception>
- @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
+ @ r2 - sp_svc
+ @ r3 - lr_svc
+ @ r4 - lr_<exception>, already fixed up for correct return/restart
+ @ r5 - spsr_<exception>
+ @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
@
- stmia r5, {r0 - r4}
+ stmia r7, {r2 - r6}
.endm
.align 5
@@ -187,7 +189,7 @@ __dabt_svc:
@ get ready to re-enable interrupts if appropriate
@
mrs r9, cpsr
- tst r3, #PSR_I_BIT
+ tst r5, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
dabt_helper
@@ -208,8 +210,8 @@ __dabt_svc:
@
@ restore SPSR and restart the instruction
@
- ldr r2, [sp, #S_PSR]
- svc_exit r2 @ return from exception
+ ldr r5, [sp, #S_PSR]
+ svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__dabt_svc)
@@ -232,13 +234,13 @@ __irq_svc:
tst r0, #_TIF_NEED_RESCHED
blne svc_preempt
#endif
- ldr r4, [sp, #S_PSR] @ irqs are already disabled
+ ldr r5, [sp, #S_PSR]
#ifdef CONFIG_TRACE_IRQFLAGS
@ The parent context IRQs must have been enabled to get here in
@ the first place, so there's no point checking the PSR I bit.
bl trace_hardirqs_on
#endif
- svc_exit r4 @ return from exception
+ svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__irq_svc)
@@ -273,15 +275,16 @@ __und_svc:
@ r0 - instruction
@
#ifndef CONFIG_THUMB2_KERNEL
- ldr r0, [r2, #-4]
+ ldr r0, [r4, #-4]
#else
- ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
+ ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
and r9, r0, #0xf800
cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
- ldrhhs r9, [r2] @ bottom 16 bits
+ ldrhhs r9, [r4] @ bottom 16 bits
orrhs r0, r9, r0, lsl #16
#endif
adr r9, BSYM(1f)
+ mov r2, r4
bl call_fpe
mov r0, sp @ struct pt_regs *regs
@@ -295,8 +298,8 @@ __und_svc:
@
@ restore SPSR and restart the instruction
@
- ldr r2, [sp, #S_PSR] @ Get SVC cpsr
- svc_exit r2 @ return from exception
+ ldr r5, [sp, #S_PSR] @ Get SVC cpsr
+ svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__und_svc)
@@ -308,7 +311,7 @@ __pabt_svc:
@ re-enable interrupts if appropriate
@
mrs r9, cpsr
- tst r3, #PSR_I_BIT
+ tst r5, #PSR_I_BIT
biceq r9, r9, #PSR_I_BIT
pabt_helper
@@ -325,8 +328,8 @@ __pabt_svc:
@
@ restore SPSR and restart the instruction
@
- ldr r2, [sp, #S_PSR]
- svc_exit r2 @ return from exception
+ ldr r5, [sp, #S_PSR]
+ svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__pabt_svc)
@@ -357,23 +360,23 @@ ENDPROC(__pabt_svc)
ARM( stmib sp, {r1 - r12} )
THUMB( stmia sp, {r0 - r12} )
- ldmia r0, {r1 - r3}
+ ldmia r0, {r3 - r5}
add r0, sp, #S_PC @ here for interlock avoidance
- mov r4, #-1 @ "" "" "" ""
+ mov r6, #-1 @ "" "" "" ""
- str r1, [sp] @ save the "real" r0 copied
+ str r3, [sp] @ save the "real" r0 copied
@ from the exception stack
@
@ We are now ready to fill in the remaining blanks on the stack:
@
- @ r2 - lr_<exception>, already fixed up for correct return/restart
- @ r3 - spsr_<exception>
- @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
+ @ r4 - lr_<exception>, already fixed up for correct return/restart
+ @ r5 - spsr_<exception>
+ @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
@
@ Also, separately save sp_usr and lr_usr
@
- stmia r0, {r2 - r4}
+ stmia r0, {r4 - r6}
ARM( stmdb r0, {sp, lr}^ )
THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
@@ -397,7 +400,7 @@ ENDPROC(__pabt_svc)
@ if it was interrupted in a critical region. Here we
@ perform a quick test inline since it should be false
@ 99.9999% of the time. The rest is done out of line.
- cmp r2, #TASK_SIZE
+ cmp r4, #TASK_SIZE
blhs kuser_cmpxchg_fixup
#endif
#endif
@@ -441,6 +444,8 @@ ENDPROC(__irq_usr)
.align 5
__und_usr:
usr_entry
+ mov r2, r4
+ mov r3, r5
@
@ fall through to the emulation code, which returns using r9 if
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 10/23] ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (9 preceding siblings ...)
2011-06-29 9:21 ` [PATCH 09/23] ARM: entry: rejig register allocation in exception entry handlers Russell King - ARM Linux
@ 2011-06-29 9:22 ` Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers Russell King - ARM Linux
` (13 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:22 UTC (permalink / raw)
To: linux-arm-kernel
This avoids unnecessary instructions for CPUs which implement the IFAR
(instruction fault address register).
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 2 +-
arch/arm/mm/pabort-legacy.S | 3 ++-
arch/arm/mm/pabort-v6.S | 3 ++-
arch/arm/mm/pabort-v7.S | 2 +-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 353b639..ee425f7 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -45,7 +45,7 @@
.endm
.macro pabt_helper
- mov r0, r4 @ pass address of aborted instruction.
+ @ PABORT handler takes fault address in r4
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc
diff --git a/arch/arm/mm/pabort-legacy.S b/arch/arm/mm/pabort-legacy.S
index 87970eb..8a5d8aa 100644
--- a/arch/arm/mm/pabort-legacy.S
+++ b/arch/arm/mm/pabort-legacy.S
@@ -4,7 +4,7 @@
/*
* Function: legacy_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = Simulated IFSR with section translation fault status
@@ -14,6 +14,7 @@
.align 5
ENTRY(legacy_pabort)
+ mov r0, r4
mov r1, #5
mov pc, lr
ENDPROC(legacy_pabort)
diff --git a/arch/arm/mm/pabort-v6.S b/arch/arm/mm/pabort-v6.S
index 06e3d1e..eaac1cb 100644
--- a/arch/arm/mm/pabort-v6.S
+++ b/arch/arm/mm/pabort-v6.S
@@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR
@@ -14,6 +14,7 @@
.align 5
ENTRY(v6_pabort)
+ mov r0, r4
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
mov pc, lr
ENDPROC(v6_pabort)
diff --git a/arch/arm/mm/pabort-v7.S b/arch/arm/mm/pabort-v7.S
index a8b3b30..b515e0b 100644
--- a/arch/arm/mm/pabort-v7.S
+++ b/arch/arm/mm/pabort-v7.S
@@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (10 preceding siblings ...)
2011-06-29 9:22 ` [PATCH 10/23] ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0 Russell King - ARM Linux
@ 2011-06-29 9:22 ` Russell King - ARM Linux
2011-06-29 20:05 ` Will Deacon
2011-06-29 9:22 ` [PATCH 12/23] ARM: entry: instrument svc undefined exception handler with irqtrace Russell King - ARM Linux
` (12 subsequent siblings)
24 siblings, 1 reply; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:22 UTC (permalink / raw)
To: linux-arm-kernel
Avoid enabling interrupts if the parent context had interrupts enabled
in the abort handler assembly code, and move this into the breakpoint/
page/alignment fault handlers instead.
This gets rid of some special-casing for the breakpoint fault handlers
from the low level abort handler path.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 43 +++++++++++++++++---------------------
| 19 -----------------
arch/arm/kernel/hw_breakpoint.c | 6 +++-
arch/arm/mm/alignment.c | 3 ++
arch/arm/mm/fault.c | 4 +++
5 files changed, 30 insertions(+), 45 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index ee425f7..8048056 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -185,20 +185,15 @@ ENDPROC(__und_invalid)
__dabt_svc:
svc_entry
- @
- @ get ready to re-enable interrupts if appropriate
- @
- mrs r9, cpsr
- tst r5, #PSR_I_BIT
- biceq r9, r9, #PSR_I_BIT
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
dabt_helper
@
- @ set desired IRQ state, then call main handler
+ @ call main handler
@
- debug_entry r1
- msr cpsr_c, r9
mov r2, sp
bl do_DataAbort
@@ -211,6 +206,12 @@ __dabt_svc:
@ restore SPSR and restart the instruction
@
ldr r5, [sp, #S_PSR]
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__dabt_svc)
@@ -307,16 +308,11 @@ ENDPROC(__und_svc)
__pabt_svc:
svc_entry
- @
- @ re-enable interrupts if appropriate
- @
- mrs r9, cpsr
- tst r5, #PSR_I_BIT
- biceq r9, r9, #PSR_I_BIT
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
pabt_helper
- debug_entry r1
- msr cpsr_c, r9 @ Maybe enable interrupts
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
@@ -329,6 +325,12 @@ __pabt_svc:
@ restore SPSR and restart the instruction
@
ldr r5, [sp, #S_PSR]
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__pabt_svc)
@@ -412,11 +414,6 @@ __dabt_usr:
kuser_cmpxchg_check
dabt_helper
- @
- @ IRQs on, then call the main handler
- @
- debug_entry r1
- enable_irq
mov r2, sp
adr lr, BSYM(ret_from_exception)
b do_DataAbort
@@ -663,8 +660,6 @@ ENDPROC(__und_usr_unknown)
__pabt_usr:
usr_entry
pabt_helper
- debug_entry r1
- enable_irq @ Enable interrupts
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
UNWIND(.fnend )
--git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 051166c..4d6ad83 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -165,25 +165,6 @@
.endm
#endif /* !CONFIG_THUMB2_KERNEL */
- @
- @ Debug exceptions are taken as prefetch or data aborts.
- @ We must disable preemption during the handler so that
- @ we can access the debug registers safely.
- @
- .macro debug_entry, fsr
-#if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT)
- ldr r4, =0x40f @ mask out fsr.fs
- and r5, r4, \fsr
- cmp r5, #2 @ debug exception
- bne 1f
- get_thread_info r10
- ldr r6, [r10, #TI_PREEMPT] @ get preempt count
- add r11, r6, #1 @ increment it
- str r11, [r10, #TI_PREEMPT]
-1:
-#endif
- .endm
-
/*
* These are the registers used in the syscall handler, and allow us to
* have in theory up to 7 arguments to a function - r0 to r6.
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 87acc25..b813e1e 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -804,8 +804,10 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
int ret = 0;
u32 dscr;
- /* We must be called with preemption disabled. */
- WARN_ON(preemptible());
+ preempt_disable();
+
+ if (interrupts_enabled(regs))
+ local_irq_enable();
/* We only handle watchpoints and hardware breakpoints. */
ARM_DBG_READ(c1, 0, dscr);
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 724ba3b..be7c638 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -727,6 +727,9 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
int isize = 4;
int thumb2_32b = 0;
+ if (interrupts_enabled(regs))
+ local_irq_enable();
+
instrptr = instruction_pointer(regs);
fs = get_fs();
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index bc0e1d8..20e5d51 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -285,6 +285,10 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
tsk = current;
mm = tsk->mm;
+ /* Enable interrupts if they were enabled in the parent context. */
+ if (interrupts_enabled(regs))
+ local_irq_enable();
+
/*
* If we're in an interrupt or have no user
* context, we must not take the fault..
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 12/23] ARM: entry: instrument svc undefined exception handler with irqtrace
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (11 preceding siblings ...)
2011-06-29 9:22 ` [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers Russell King - ARM Linux
@ 2011-06-29 9:22 ` Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 13/23] ARM: entry: instrument usr exception handlers with irqsoff tracing Russell King - ARM Linux
` (11 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:22 UTC (permalink / raw)
To: linux-arm-kernel
Add irqtrace function calls to the undefined exception handler, so
that we get sane lockdep traces from locking problems in undefined
exception handlers.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 8048056..474934c 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -268,6 +268,10 @@ __und_svc:
svc_entry
#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
+
@
@ call emulation code, which returns using r9 if it has emulated
@ the instruction, or the more conventional lr if we are to treat
@@ -300,6 +304,12 @@ __und_svc:
@ restore SPSR and restart the instruction
@
ldr r5, [sp, #S_PSR] @ Get SVC cpsr
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__und_svc)
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 13/23] ARM: entry: instrument usr exception handlers with irqsoff tracing
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (12 preceding siblings ...)
2011-06-29 9:22 ` [PATCH 12/23] ARM: entry: instrument svc undefined exception handler with irqtrace Russell King - ARM Linux
@ 2011-06-29 9:23 ` Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 14/23] ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros Russell King - ARM Linux
` (10 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:23 UTC (permalink / raw)
To: linux-arm-kernel
As we no longer re-enable interrupts in these exception handlers, add
the irqsoff tracing calls to them so that the kernel tracks the state
more accurately.
Note that these calls are conditional on IRQSOFF_TRACER:
kernel ----------> user ---------> kernel
^ irqs enabled ^ irqs disabled
No kernel code can run on the local CPU until we've re-entered the
kernel through one of the exception handlers - and userspace can not
take any locks etc. So, the kernel doesn't care about the IRQ mask
state while userspace is running unless we're doing IRQ off latency
tracing. So, we can (and do) avoid the overhead of updating the IRQ
mask state on every kernel->user and user->kernel transition.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 17 ++++++++++++++++-
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 474934c..c01cdb1 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -421,6 +421,11 @@ ENDPROC(__pabt_svc)
.align 5
__dabt_usr:
usr_entry
+
+#ifdef CONFIG_IRQSOFF_TRACER
+ bl trace_hardirqs_off
+#endif
+
kuser_cmpxchg_check
dabt_helper
@@ -433,12 +438,12 @@ ENDPROC(__dabt_usr)
.align 5
__irq_usr:
usr_entry
- kuser_cmpxchg_check
#ifdef CONFIG_IRQSOFF_TRACER
bl trace_hardirqs_off
#endif
+ kuser_cmpxchg_check
irq_handler
get_thread_info tsk
mov why, #0
@@ -451,6 +456,11 @@ ENDPROC(__irq_usr)
.align 5
__und_usr:
usr_entry
+
+#ifdef CONFIG_IRQSOFF_TRACER
+ bl trace_hardirqs_off
+#endif
+
mov r2, r4
mov r3, r5
@@ -669,6 +679,11 @@ ENDPROC(__und_usr_unknown)
.align 5
__pabt_usr:
usr_entry
+
+#ifdef CONFIG_IRQSOFF_TRACER
+ bl trace_hardirqs_off
+#endif
+
pabt_helper
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 14/23] ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (13 preceding siblings ...)
2011-06-29 9:23 ` [PATCH 13/23] ARM: entry: instrument usr exception handlers with irqsoff tracing Russell King - ARM Linux
@ 2011-06-29 9:23 ` Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 15/23] ARM: entry: re-allocate registers in irq entry assembly macros Russell King - ARM Linux
` (9 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:23 UTC (permalink / raw)
To: linux-arm-kernel
All handlers now call trace_hardirqs_off, so move this common code into
the (svc|usr)_entry assembler macros.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 47 +++++++----------------------------------
1 files changed, 8 insertions(+), 39 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index c01cdb1..1da985f 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -179,16 +179,15 @@ ENDPROC(__und_invalid)
@ r6 - orig_r0 (see pt_regs definition in ptrace.h)
@
stmia r7, {r2 - r6}
- .endm
-
- .align 5
-__dabt_svc:
- svc_entry
#ifdef CONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_off
#endif
+ .endm
+ .align 5
+__dabt_svc:
+ svc_entry
dabt_helper
@
@@ -219,11 +218,6 @@ ENDPROC(__dabt_svc)
.align 5
__irq_svc:
svc_entry
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- bl trace_hardirqs_off
-#endif
-
irq_handler
#ifdef CONFIG_PREEMPT
@@ -267,11 +261,6 @@ __und_svc:
#else
svc_entry
#endif
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- bl trace_hardirqs_off
-#endif
-
@
@ call emulation code, which returns using r9 if it has emulated
@ the instruction, or the more conventional lr if we are to treat
@@ -317,11 +306,6 @@ ENDPROC(__und_svc)
.align 5
__pabt_svc:
svc_entry
-
-#ifdef CONFIG_TRACE_IRQFLAGS
- bl trace_hardirqs_off
-#endif
-
pabt_helper
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
@@ -401,6 +385,10 @@ ENDPROC(__pabt_svc)
@ Clear FP to mark the first stack frame
@
zero_fp
+
+#ifdef CONFIG_IRQSOFF_TRACER
+ bl trace_hardirqs_off
+#endif
.endm
.macro kuser_cmpxchg_check
@@ -421,11 +409,6 @@ ENDPROC(__pabt_svc)
.align 5
__dabt_usr:
usr_entry
-
-#ifdef CONFIG_IRQSOFF_TRACER
- bl trace_hardirqs_off
-#endif
-
kuser_cmpxchg_check
dabt_helper
@@ -438,11 +421,6 @@ ENDPROC(__dabt_usr)
.align 5
__irq_usr:
usr_entry
-
-#ifdef CONFIG_IRQSOFF_TRACER
- bl trace_hardirqs_off
-#endif
-
kuser_cmpxchg_check
irq_handler
get_thread_info tsk
@@ -457,10 +435,6 @@ ENDPROC(__irq_usr)
__und_usr:
usr_entry
-#ifdef CONFIG_IRQSOFF_TRACER
- bl trace_hardirqs_off
-#endif
-
mov r2, r4
mov r3, r5
@@ -679,11 +653,6 @@ ENDPROC(__und_usr_unknown)
.align 5
__pabt_usr:
usr_entry
-
-#ifdef CONFIG_IRQSOFF_TRACER
- bl trace_hardirqs_off
-#endif
-
pabt_helper
mov r2, sp @ regs
bl do_PrefetchAbort @ call abort handler
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 15/23] ARM: entry: re-allocate registers in irq entry assembly macros
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (14 preceding siblings ...)
2011-06-29 9:23 ` [PATCH 14/23] ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros Russell King - ARM Linux
@ 2011-06-29 9:23 ` Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 16/23] ARM: entry: prefetch abort: tail-call the main prefetch abort handler Russell King - ARM Linux
` (8 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:23 UTC (permalink / raw)
To: linux-arm-kernel
This avoids the irq entry assembly corrupting r5, thereby allowing it
to be preserved through to the svc exit code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/include/asm/entry-macro-multi.S | 14 +++++++-------
arch/arm/kernel/entry-armv.S | 10 +++++-----
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index 2da8547..2f1e209 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -4,8 +4,8 @@
* Interrupt handling. Preserves r7, r8, r9
*/
.macro arch_irq_handler_default
- get_irqnr_preamble r5, lr
-1: get_irqnr_and_base r0, r6, r5, lr
+ get_irqnr_preamble r6, lr
+1: get_irqnr_and_base r0, r2, r6, lr
movne r1, sp
@
@ routine called with r0 = irq number, r1 = struct pt_regs *
@@ -17,17 +17,17 @@
/*
* XXX
*
- * this macro assumes that irqstat (r6) and base (r5) are
+ * this macro assumes that irqstat (r2) and base (r6) are
* preserved from get_irqnr_and_base above
*/
- ALT_SMP(test_for_ipi r0, r6, r5, lr)
+ ALT_SMP(test_for_ipi r0, r2, r6, lr)
ALT_UP_B(9997f)
movne r1, sp
adrne lr, BSYM(1b)
bne do_IPI
#ifdef CONFIG_LOCAL_TIMERS
- test_for_ltirq r0, r6, r5, lr
+ test_for_ltirq r0, r2, r6, lr
movne r0, sp
adrne lr, BSYM(1b)
bne do_local_timer
@@ -40,7 +40,7 @@
.align 5
.global \symbol_name
\symbol_name:
- mov r4, lr
+ mov r8, lr
arch_irq_handler_default
- mov pc, r4
+ mov pc, r8
.endm
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 1da985f..b7c4792 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -29,16 +29,16 @@
#include <asm/entry-macro-multi.S>
/*
- * Interrupt handling. Preserves r7, r8, r9
+ * Interrupt handling.
*/
.macro irq_handler
#ifdef CONFIG_MULTI_IRQ_HANDLER
- ldr r5, =handle_arch_irq
+ ldr r1, =handle_arch_irq
mov r0, sp
- ldr r5, [r5]
+ ldr r1, [r1]
adr lr, BSYM(9997f)
- teq r5, #0
- movne pc, r5
+ teq r1, #0
+ movne pc, r1
#endif
arch_irq_handler_default
9997:
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 16/23] ARM: entry: prefetch abort: tail-call the main prefetch abort handler
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (15 preceding siblings ...)
2011-06-29 9:23 ` [PATCH 15/23] ARM: entry: re-allocate registers in irq entry assembly macros Russell King - ARM Linux
@ 2011-06-29 9:24 ` Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 17/23] ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 Russell King - ARM Linux
` (7 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:24 UTC (permalink / raw)
To: linux-arm-kernel
Tail-call the main C prefetch abort handler code from the per-CPU
helper code. Also note that the helper function becomes ABI
compliant in terms of the registers preserved.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 8 +++-----
arch/arm/mm/pabort-legacy.S | 9 +++++----
arch/arm/mm/pabort-v6.S | 9 +++++----
arch/arm/mm/pabort-v7.S | 11 ++++++-----
4 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index b7c4792..54c07a8 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -45,7 +45,7 @@
.endm
.macro pabt_helper
- @ PABORT handler takes fault address in r4
+ @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc
@@ -306,9 +306,8 @@ ENDPROC(__und_svc)
.align 5
__pabt_svc:
svc_entry
- pabt_helper
mov r2, sp @ regs
- bl do_PrefetchAbort @ call abort handler
+ pabt_helper
@
@ IRQs off again before pulling preserved data off the stack
@@ -653,9 +652,8 @@ ENDPROC(__und_usr_unknown)
.align 5
__pabt_usr:
usr_entry
- pabt_helper
mov r2, sp @ regs
- bl do_PrefetchAbort @ call abort handler
+ pabt_helper
UNWIND(.fnend )
/* fall through */
/*
diff --git a/arch/arm/mm/pabort-legacy.S b/arch/arm/mm/pabort-legacy.S
index 8a5d8aa..8bbff02 100644
--- a/arch/arm/mm/pabort-legacy.S
+++ b/arch/arm/mm/pabort-legacy.S
@@ -4,10 +4,11 @@
/*
* Function: legacy_pabort
*
- * Params : r4 = address of aborted instruction
+ * Params : r2 = pt_regs
+ * : r4 = address of aborted instruction
+ * : r5 = psr for parent context
*
- * Returns : r0 = address of abort
- * : r1 = Simulated IFSR with section translation fault status
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current prefetch abort.
*/
@@ -16,5 +17,5 @@
ENTRY(legacy_pabort)
mov r0, r4
mov r1, #5
- mov pc, lr
+ b do_PrefetchAbort
ENDPROC(legacy_pabort)
diff --git a/arch/arm/mm/pabort-v6.S b/arch/arm/mm/pabort-v6.S
index eaac1cb..9627646 100644
--- a/arch/arm/mm/pabort-v6.S
+++ b/arch/arm/mm/pabort-v6.S
@@ -4,10 +4,11 @@
/*
* Function: v6_pabort
*
- * Params : r4 = address of aborted instruction
+ * Params : r2 = pt_regs
+ * : r4 = address of aborted instruction
+ * : r5 = psr for parent context
*
- * Returns : r0 = address of abort
- * : r1 = IFSR
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current prefetch abort.
*/
@@ -16,5 +17,5 @@
ENTRY(v6_pabort)
mov r0, r4
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
- mov pc, lr
+ b do_PrefetchAbort
ENDPROC(v6_pabort)
diff --git a/arch/arm/mm/pabort-v7.S b/arch/arm/mm/pabort-v7.S
index b515e0b..875761f 100644
--- a/arch/arm/mm/pabort-v7.S
+++ b/arch/arm/mm/pabort-v7.S
@@ -2,12 +2,13 @@
#include <asm/assembler.h>
/*
- * Function: v6_pabort
+ * Function: v7_pabort
*
- * Params : r4 = address of aborted instruction
+ * Params : r2 = pt_regs
+ * : r4 = address of aborted instruction
+ * : r5 = psr for parent context
*
- * Returns : r0 = address of abort
- * : r1 = IFSR
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current prefetch abort.
*/
@@ -16,5 +17,5 @@
ENTRY(v7_pabort)
mrc p15, 0, r0, c6, c0, 2 @ get IFAR
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
- mov pc, lr
+ b do_PrefetchAbort
ENDPROC(v7_pabort)
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 17/23] ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (16 preceding siblings ...)
2011-06-29 9:24 ` [PATCH 16/23] ARM: entry: prefetch abort: tail-call the main prefetch abort handler Russell King - ARM Linux
@ 2011-06-29 9:24 ` Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 18/23] ARM: entry: data abort: avoid using r2 in abort helpers Russell King - ARM Linux
` (6 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:24 UTC (permalink / raw)
To: linux-arm-kernel
Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather
than r2/r3.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 6 ++----
arch/arm/mm/abort-ev4.S | 8 +++-----
arch/arm/mm/abort-ev4t.S | 8 ++++----
arch/arm/mm/abort-ev5t.S | 8 ++++----
arch/arm/mm/abort-ev5tj.S | 12 +++++-------
arch/arm/mm/abort-ev6.S | 12 +++++-------
arch/arm/mm/abort-ev7.S | 4 ++--
arch/arm/mm/abort-lv4t.S | 12 ++++++------
arch/arm/mm/abort-nommu.S | 4 ++--
arch/arm/mm/proc-arm6_7.S | 10 +++++-----
10 files changed, 38 insertions(+), 46 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 54c07a8..36c9409 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -56,14 +56,12 @@
.endm
.macro dabt_helper
- mov r2, r4
- mov r3, r5
@
@ Call the processor-specific abort handler:
@
- @ r2 - aborted context pc
- @ r3 - aborted context cpsr
+ @ r4 - aborted context pc
+ @ r5 - aborted context psr
@
@ The abort handler must return the aborted address in r0, and
@ the fault status register in r1. r9 must be preserved.
diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
index 4f18f9e..beb112b 100644
--- a/arch/arm/mm/abort-ev4.S
+++ b/arch/arm/mm/abort-ev4.S
@@ -3,8 +3,8 @@
/*
* Function: v4_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -21,10 +21,8 @@
ENTRY(v4_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r3, [r2] @ read aborted ARM instruction
+ ldr r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ L = 1 -> write?
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
-
-
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index 9910123..eaa4ac0 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,8 +4,8 @@
/*
* Function: v4t_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@
ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
- ldreq r3, [r2] @ read aborted ARM instruction
+ do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+ ldreq r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 800e8d4..97eee7c 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -4,8 +4,8 @@
/*
* Function: v5t_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -22,8 +22,8 @@
ENTRY(v5t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
- ldreq r3, [r2] @ read aborted ARM instruction
+ do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+ ldreq r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR
do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ check write
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bcb58d2..9a365cf 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,8 +4,8 @@
/*
* Function: v5tj_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -23,13 +23,11 @@ ENTRY(v5tj_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
- tst r3, #PSR_J_BIT @ Java?
+ tst r5, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
- ldreq r3, [r2] @ read aborted ARM instruction
+ do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+ ldreq r3, [r4] @ read aborted ARM instruction
do_ldrd_abort tmp=r2, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
-
-
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ef526e7..52db4a3 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,8 +4,8 @@
/*
* Function: v6_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -33,10 +33,10 @@ ENTRY(v6_early_abort)
* The test below covers all the write situations, including Java bytecodes
*/
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
- tst r3, #PSR_J_BIT @ Java?
+ tst r5, #PSR_J_BIT @ Java?
movne pc, lr
- do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
- ldreq r3, [r2] @ read aborted ARM instruction
+ do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+ ldreq r3, [r4] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
reveq r3, r3
#endif
@@ -44,5 +44,3 @@ ENTRY(v6_early_abort)
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
-
-
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index ec88b15..6cb5143 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -3,8 +3,8 @@
/*
* Function: v7_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 9fb7b0e..fea7514 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -3,8 +3,8 @@
/*
* Function: v4t_late_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = address of abort
* : r1 = FSR, bit 11 = write
@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
ENTRY(v4t_late_abort)
- tst r3, #PSR_T_BIT @ check for thumb mode
+ tst r5, #PSR_T_BIT @ check for thumb mode
#ifdef CONFIG_CPU_CP15_MMU
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
@@ -28,7 +28,7 @@ ENTRY(v4t_late_abort)
mov r1, #0
#endif
bne .data_thumb_abort
- ldr r8, [r2] @ read arm instruction
+ ldr r8, [r4] @ read arm instruction
tst r8, #1 << 20 @ L = 1 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24
@@ -52,7 +52,7 @@ ENTRY(v4t_late_abort)
/* e */ b .data_unknown
/* f */
.data_unknown: @ Part of jumptable
- mov r0, r2
+ mov r0, r4
mov r1, r8
mov r2, sp
bl baddataabort
@@ -159,7 +159,7 @@ ENTRY(v4t_late_abort)
b .data_unknown @ F: MUL?
.data_thumb_abort:
- ldrh r8, [r2] @ read instruction
+ ldrh r8, [r4] @ read instruction
tst r8, #1 << 11 @ L = 1 -> write?
orreq r1, r1, #1 << 8 @ yes
and r7, r8, #15 << 12
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index 625e580..9eaef6f 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -3,8 +3,8 @@
/*
* Function: nommu_early_abort
*
- * Params : r2 = address of aborted instruction
- * : r3 = saved SPSR
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Returns : r0 = 0 (abort address)
* : r1 = 0 (FSR)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 5f79dc4..e7be700 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,8 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
/*
* Function: arm6_7_data_abort ()
*
- * Params : r2 = address of aborted instruction
- * : sp = pointer to registers
+ * Params : r4 = aborted context pc
+ * : r5 = aborted context psr
*
* Purpose : obtain information about current aborted instruction
*
@@ -41,7 +41,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
ENTRY(cpu_arm7_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r2] @ read arm instruction
+ ldr r8, [r4] @ read arm instruction
tst r8, #1 << 20 @ L = 0 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #15 << 24
@@ -65,7 +65,7 @@ ENTRY(cpu_arm7_data_abort)
/* e */ b .data_unknown
/* f */
.data_unknown: @ Part of jumptable
- mov r0, r2
+ mov r0, r4
mov r1, r8
mov r2, sp
bl baddataabort
@@ -74,7 +74,7 @@ ENTRY(cpu_arm7_data_abort)
ENTRY(cpu_arm6_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r2] @ read arm instruction
+ ldr r8, [r4] @ read arm instruction
tst r8, #1 << 20 @ L = 0 -> write?
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #14 << 24
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 18/23] ARM: entry: data abort: avoid using r2 in abort helpers
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (17 preceding siblings ...)
2011-06-29 9:24 ` [PATCH 17/23] ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 Russell King - ARM Linux
@ 2011-06-29 9:24 ` Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 19/23] ARM: entry: data abort: tail-call the main data abort handler Russell King - ARM Linux
` (5 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:24 UTC (permalink / raw)
To: linux-arm-kernel
This allows us to pass the pt_regs pointer in to these functions
ready for tail-calling the abort handler.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-ev5t.S | 2 +-
arch/arm/mm/abort-ev5tj.S | 2 +-
arch/arm/mm/abort-ev6.S | 2 +-
arch/arm/mm/abort-ev7.S | 8 ++++----
arch/arm/mm/abort-lv4t.S | 34 +++++++++++++++++-----------------
arch/arm/mm/proc-arm6_7.S | 18 +++++++++---------
6 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 97eee7c..751391a 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -25,7 +25,7 @@ ENTRY(v5t_early_abort)
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction
bic r1, r1, #1 << 11 @ clear bits 11 of FSR
- do_ldrd_abort tmp=r2, insn=r3
+ do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
mov pc, lr
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index 9a365cf..ccfbc93 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -27,7 +27,7 @@ ENTRY(v5tj_early_abort)
movne pc, lr
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction
- do_ldrd_abort tmp=r2, insn=r3
+ do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 52db4a3..b64d886 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -40,7 +40,7 @@ ENTRY(v6_early_abort)
#ifdef CONFIG_CPU_ENDIAN_BE8
reveq r3, r3
#endif
- do_ldrd_abort tmp=r2, insn=r3
+ do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
mov pc, lr
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 6cb5143..6f98b3a 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -41,13 +41,13 @@ ENTRY(v7_early_abort)
mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
isb
- mrc p15, 0, r2, c7, c4, 0 @ Read the PAR
- and r3, r2, #0x7b @ On translation fault
+ mrc p15, 0, ip, c7, c4, 0 @ Read the PAR
+ and r3, ip, #0x7b @ On translation fault
cmp r3, #0x0b
movne pc, lr
bic r1, r1, #0xf @ Fix up FSR FS[5:0]
- and r2, r2, #0x7e
- orr r1, r1, r2, LSR #1
+ and ip, ip, #0x7e
+ orr r1, r1, ip, LSR #1
#endif
mov pc, lr
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index fea7514..d032b1f 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -64,12 +64,12 @@ ENTRY(v4t_late_abort)
mov r7, #0x11
orr r7, r7, #0x1100
and r6, r8, r7
- and r2, r8, r7, lsl #1
- add r6, r6, r2, lsr #1
- and r2, r8, r7, lsl #2
- add r6, r6, r2, lsr #2
- and r2, r8, r7, lsl #3
- add r6, r6, r2, lsr #3
+ and r9, r8, r7, lsl #1
+ add r6, r6, r9, lsr #1
+ and r9, r8, r7, lsl #2
+ add r6, r6, r9, lsr #2
+ and r9, r8, r7, lsl #3
+ add r6, r6, r9, lsr #3
add r6, r6, r6, lsr #8
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
@@ -103,13 +103,13 @@ ENTRY(v4t_late_abort)
tst r8, #1 << 21 @ check writeback bit
moveq pc, lr @ no writeback -> no fixup
.data_arm_lateldrpostconst:
- movs r2, r8, lsl #20 @ Get offset
+ movs r9, r8, lsl #20 @ Get offset
moveq pc, lr @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r2, lsr #20 @ Undo increment
- addeq r7, r7, r2, lsr #20 @ Undo decrement
+ subne r7, r7, r9, lsr #20 @ Undo increment
+ addeq r7, r7, r9, lsr #20 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
mov pc, lr
@@ -194,11 +194,11 @@ ENTRY(v4t_late_abort)
tst r8, #1 << 10
beq .data_unknown
and r6, r8, #0x55 @ hweight8(r8) + R bit
- and r2, r8, #0xaa
- add r6, r6, r2, lsr #1
- and r2, r6, #0xcc
+ and r9, r8, #0xaa
+ add r6, r6, r9, lsr #1
+ and r9, r6, #0xcc
and r6, r6, #0x33
- add r6, r6, r2, lsr #2
+ add r6, r6, r9, lsr #2
movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
and r6, r6, #15 @ number of regs to transfer
@@ -211,11 +211,11 @@ ENTRY(v4t_late_abort)
.data_thumb_ldmstm:
and r6, r8, #0x55 @ hweight8(r8)
- and r2, r8, #0xaa
- add r6, r6, r2, lsr #1
- and r2, r6, #0xcc
+ and r9, r8, #0xaa
+ add r6, r6, r9, lsr #1
+ and r9, r6, #0xcc
and r6, r6, #0x33
- add r6, r6, r2, lsr #2
+ add r6, r6, r9, lsr #2
add r6, r6, r6, lsr #4
and r5, r8, #7 << 8
ldr r7, [sp, r5, lsr #6]
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index e7be700..d4c328e 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -87,12 +87,12 @@ ENTRY(cpu_arm6_data_abort)
mov r7, #0x11
orr r7, r7, #0x1100
and r6, r8, r7
- and r2, r8, r7, lsl #1
- add r6, r6, r2, lsr #1
- and r2, r8, r7, lsl #2
- add r6, r6, r2, lsr #2
- and r2, r8, r7, lsl #3
- add r6, r6, r2, lsr #3
+ and r9, r8, r7, lsl #1
+ add r6, r6, r9, lsr #1
+ and r9, r8, r7, lsl #2
+ add r6, r6, r9, lsr #2
+ and r9, r8, r7, lsl #3
+ add r6, r6, r9, lsr #3
add r6, r6, r6, lsr #8
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
@@ -117,13 +117,13 @@ ENTRY(cpu_arm6_data_abort)
tst r8, #1 << 21 @ check writeback bit
moveq pc, lr @ no writeback -> no fixup
.data_arm_lateldrpostconst:
- movs r2, r8, lsl #20 @ Get offset
+ movs r9, r8, lsl #20 @ Get offset
moveq pc, lr @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r2, lsr #20 @ Undo increment
- addeq r7, r7, r2, lsr #20 @ Undo decrement
+ subne r7, r7, r9, lsr #20 @ Undo increment
+ addeq r7, r7, r9, lsr #20 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
mov pc, lr
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 19/23] ARM: entry: data abort: tail-call the main data abort handler
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (18 preceding siblings ...)
2011-06-29 9:24 ` [PATCH 18/23] ARM: entry: data abort: avoid using r2 in abort helpers Russell King - ARM Linux
@ 2011-06-29 9:25 ` Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 20/23] ARM: entry: data abort: use r2 as base of pt_regs rather than stack Russell King - ARM Linux
` (4 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Tail-call the main C data abort handler code from the per-CPU helper
code. Update the comments in the code wrt the new calling and return
register state.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 14 +++---------
arch/arm/mm/abort-ev4.S | 11 +++------
arch/arm/mm/abort-ev4t.S | 11 +++------
arch/arm/mm/abort-ev5t.S | 11 +++------
arch/arm/mm/abort-ev5tj.S | 13 ++++-------
arch/arm/mm/abort-ev6.S | 13 ++++-------
arch/arm/mm/abort-ev7.S | 15 +++++--------
arch/arm/mm/abort-lv4t.S | 43 ++++++++++++++++++++---------------------
arch/arm/mm/abort-macro.S | 4 +-
arch/arm/mm/abort-nommu.S | 8 +++---
arch/arm/mm/proc-arm6_7.S | 29 +++++++++++++--------------
11 files changed, 73 insertions(+), 99 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 36c9409..3fa90ae 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -60,6 +60,7 @@
@
@ Call the processor-specific abort handler:
@
+ @ r2 - pt_regs
@ r4 - aborted context pc
@ r5 - aborted context psr
@
@@ -186,13 +187,8 @@ ENDPROC(__und_invalid)
.align 5
__dabt_svc:
svc_entry
- dabt_helper
-
- @
- @ call main handler
- @
mov r2, sp
- bl do_DataAbort
+ dabt_helper
@
@ IRQs off again before pulling preserved data off the stack
@@ -407,11 +403,9 @@ ENDPROC(__pabt_svc)
__dabt_usr:
usr_entry
kuser_cmpxchg_check
- dabt_helper
-
mov r2, sp
- adr lr, BSYM(ret_from_exception)
- b do_DataAbort
+ dabt_helper
+ b ret_from_exception
UNWIND(.fnend )
ENDPROC(__dabt_usr)
diff --git a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
index beb112b..54473cd 100644
--- a/arch/arm/mm/abort-ev4.S
+++ b/arch/arm/mm/abort-ev4.S
@@ -3,14 +3,11 @@
/*
* Function: v4_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -25,4 +22,4 @@ ENTRY(v4_early_abort)
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ L = 1 -> write?
orreq r1, r1, #1 << 11 @ yes.
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index eaa4ac0..9da704e 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -4,14 +4,11 @@
/*
* Function: v4t_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -27,4 +24,4 @@ ENTRY(v4t_early_abort)
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 751391a..a0908d4 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -4,14 +4,11 @@
/*
* Function: v5t_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -28,4 +25,4 @@ ENTRY(v5t_early_abort)
do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ check write
orreq r1, r1, #1 << 11
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index ccfbc93..4006b7a 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
/*
* Function: v5tj_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -24,10 +21,10 @@ ENTRY(v5tj_early_abort)
mrc p15, 0, r0, c6, c0, 0 @ get FAR
bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
tst r5, #PSR_J_BIT @ Java?
- movne pc, lr
+ bne do_DataAbort
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction
do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index b64d886..ff1f7cc 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -4,14 +4,11 @@
/*
* Function: v6_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -34,7 +31,7 @@ ENTRY(v6_early_abort)
*/
bic r1, r1, #1 << 11 @ clear bit 11 of FSR
tst r5, #PSR_J_BIT @ Java?
- movne pc, lr
+ bne do_DataAbort
do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
ldreq r3, [r4] @ read aborted ARM instruction
#ifdef CONFIG_CPU_ENDIAN_BE8
@@ -43,4 +40,4 @@ ENTRY(v6_early_abort)
do_ldrd_abort tmp=ip, insn=r3
tst r3, #1 << 20 @ L = 0 -> write
orreq r1, r1, #1 << 11 @ yes.
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S
index 6f98b3a..7033752 100644
--- a/arch/arm/mm/abort-ev7.S
+++ b/arch/arm/mm/abort-ev7.S
@@ -3,14 +3,11 @@
/*
* Function: v7_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
*/
@@ -37,18 +34,18 @@ ENTRY(v7_early_abort)
ldr r3, =0x40d @ On permission fault
and r3, r1, r3
cmp r3, #0x0d
- movne pc, lr
+ bne do_DataAbort
mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
isb
mrc p15, 0, ip, c7, c4, 0 @ Read the PAR
and r3, ip, #0x7b @ On translation fault
cmp r3, #0x0b
- movne pc, lr
+ bne do_DataAbort
bic r1, r1, #0xf @ Fix up FSR FS[5:0]
and ip, ip, #0x7e
orr r1, r1, ip, LSR #1
#endif
- mov pc, lr
+ b do_DataAbort
ENDPROC(v7_early_abort)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index d032b1f..d432f31 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -3,7 +3,8 @@
/*
* Function: v4t_late_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
* Returns : r0 = address of abort
@@ -47,20 +48,18 @@ ENTRY(v4t_late_abort)
/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
/* a */ b .data_unknown
/* b */ b .data_unknown
-/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
-/* d */ mov pc, lr @ ldc rd, [rn, #m]
+/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
+/* d */ b do_DataAbort @ ldc rd, [rn, #m]
/* e */ b .data_unknown
/* f */
.data_unknown: @ Part of jumptable
mov r0, r4
mov r1, r8
- mov r2, sp
- bl baddataabort
- b ret_from_exception
+ b baddataabort
.data_arm_ldmstm:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
mov r7, #0x11
orr r7, r7, #0x1100
and r6, r8, r7
@@ -79,11 +78,11 @@ ENTRY(v4t_late_abort)
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_lateldrhpre:
tst r8, #1 << 21 @ Check writeback bit
- moveq pc, lr @ No writeback -> no fixup
+ beq do_DataAbort @ No writeback -> no fixup
.data_arm_lateldrhpost:
and r5, r8, #0x00f @ get Rm / low nibble of immediate value
tst r8, #1 << 22 @ if (immediate offset)
@@ -97,25 +96,25 @@ ENTRY(v4t_late_abort)
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_lateldrpreconst:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostconst:
movs r9, r8, lsl #20 @ Get offset
- moveq pc, lr @ zero -> no fixup
+ beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r9, lsr #20 @ Undo increment
addeq r7, r7, r9, lsr #20 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_lateldrprereg:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
@@ -172,10 +171,10 @@ ENTRY(v4t_late_abort)
/* 3 */ b .data_unknown
/* 4 */ b .data_unknown
/* 5 */ b .data_thumb_reg
-/* 6 */ mov pc, lr
-/* 7 */ mov pc, lr
-/* 8 */ mov pc, lr
-/* 9 */ mov pc, lr
+/* 6 */ b do_DataAbort
+/* 7 */ b do_DataAbort
+/* 8 */ b do_DataAbort
+/* 9 */ b do_DataAbort
/* A */ b .data_unknown
/* B */ b .data_thumb_pushpop
/* C */ b .data_thumb_ldmstm
@@ -185,10 +184,10 @@ ENTRY(v4t_late_abort)
.data_thumb_reg:
tst r8, #1 << 9
- moveq pc, lr
+ beq do_DataAbort
tst r8, #1 << 10 @ If 'S' (signed) bit is set
movne r1, #0 @ it must be a load instr
- mov pc, lr
+ b do_DataAbort
.data_thumb_pushpop:
tst r8, #1 << 10
@@ -207,7 +206,7 @@ ENTRY(v4t_late_abort)
addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
subne r7, r7, r6, lsl #2 @ decrement SP if POP
str r7, [sp, #13 << 2]
- mov pc, lr
+ b do_DataAbort
.data_thumb_ldmstm:
and r6, r8, #0x55 @ hweight8(r8)
@@ -222,4 +221,4 @@ ENTRY(v4t_late_abort)
and r6, r6, #15 @ number of regs to transfer
sub r7, r7, r6, lsl #2 @ always decrement
str r7, [sp, r5, lsr #6]
- mov pc, lr
+ b do_DataAbort
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index af97a10..52162d5 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -18,7 +18,7 @@
orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
tst \tmp, #1 << 11 @ L = 0 -> write
orreq \psr, \psr, #1 << 11 @ yes.
- mov pc, lr
+ b do_DataAbort
not_thumb:
.endm
@@ -34,7 +34,7 @@ not_thumb:
bne not_ldrd
and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
cmp \tmp, #0x000000d0
- moveq pc, lr
+ beq do_DataAbort
not_ldrd:
.endm
diff --git a/arch/arm/mm/abort-nommu.S b/arch/arm/mm/abort-nommu.S
index 9eaef6f..119cb47 100644
--- a/arch/arm/mm/abort-nommu.S
+++ b/arch/arm/mm/abort-nommu.S
@@ -3,11 +3,11 @@
/*
* Function: nommu_early_abort
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = 0 (abort address)
- * : r1 = 0 (FSR)
+ * Returns : r4 - r11, r13 preserved
*
* Note: There is no FSR/FAR on !CPU_CP15_MMU cores.
* Just fill zero into the registers.
@@ -16,5 +16,5 @@
ENTRY(nommu_early_abort)
mov r0, #0 @ clear r0, r1 (no FSR/FAR)
mov r1, #0
- mov pc, lr
+ b do_DataAbort
ENDPROC(nommu_early_abort)
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index d4c328e..d755d5b 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -29,7 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
/*
* Function: arm6_7_data_abort ()
*
- * Params : r4 = aborted context pc
+ * Params : r2 = pt_regs
+ * : r4 = aborted context pc
* : r5 = aborted context psr
*
* Purpose : obtain information about current aborted instruction
@@ -49,7 +50,7 @@ ENTRY(cpu_arm7_data_abort)
nop
/* 0 */ b .data_unknown
-/* 1 */ mov pc, lr @ swp
+/* 1 */ b do_DataAbort @ swp
/* 2 */ b .data_unknown
/* 3 */ b .data_unknown
/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
@@ -60,16 +61,14 @@ ENTRY(cpu_arm7_data_abort)
/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
/* a */ b .data_unknown
/* b */ b .data_unknown
-/* c */ mov pc, lr @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
-/* d */ mov pc, lr @ ldc rd, [rn, #m]
+/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
+/* d */ b do_DataAbort @ ldc rd, [rn, #m]
/* e */ b .data_unknown
/* f */
.data_unknown: @ Part of jumptable
mov r0, r4
mov r1, r8
- mov r2, sp
- bl baddataabort
- b ret_from_exception
+ b baddataabort
ENTRY(cpu_arm6_data_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
@@ -79,11 +78,11 @@ ENTRY(cpu_arm6_data_abort)
orreq r1, r1, #1 << 11 @ yes.
and r7, r8, #14 << 24
teq r7, #8 << 24 @ was it ldm/stm
- movne pc, lr
+ bne do_DataAbort
.data_arm_ldmstm:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
mov r7, #0x11
orr r7, r7, #0x1100
and r6, r8, r7
@@ -102,7 +101,7 @@ ENTRY(cpu_arm6_data_abort)
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_apply_r6_and_rn:
and r5, r8, #15 << 16 @ Extract 'n' from instruction
@@ -111,25 +110,25 @@ ENTRY(cpu_arm6_data_abort)
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_lateldrpreconst:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostconst:
movs r9, r8, lsl #20 @ Get offset
- moveq pc, lr @ zero -> no fixup
+ beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r9, lsr #20 @ Undo increment
addeq r7, r7, r9, lsr #20 @ Undo decrement
str r7, [sp, r5, lsr #14] @ Put register 'Rn'
- mov pc, lr
+ b do_DataAbort
.data_arm_lateldrprereg:
tst r8, #1 << 21 @ check writeback bit
- moveq pc, lr @ no writeback -> no fixup
+ beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 20/23] ARM: entry: data abort: use r2 as base of pt_regs rather than stack
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (19 preceding siblings ...)
2011-06-29 9:25 ` [PATCH 19/23] ARM: entry: data abort: tail-call the main data abort handler Russell King - ARM Linux
@ 2011-06-29 9:25 ` Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 21/23] ARM: entry: data abort: always use r6 for offset Russell King - ARM Linux
` (3 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Now that we pass r2 into these helper functions as the pointer to
pt_regs, use r2 as the base of the registers on the stack rather
than using the stack pointer directly.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-lv4t.S | 24 ++++++++++++------------
arch/arm/mm/proc-arm6_7.S | 14 +++++++-------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index d432f31..921aaab 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -73,11 +73,11 @@ ENTRY(v4t_late_abort)
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrhpre:
@@ -88,14 +88,14 @@ ENTRY(v4t_late_abort)
tst r8, #1 << 22 @ if (immediate offset)
andne r6, r8, #0xf00 @ { immediate high nibble
orrne r6, r5, r6, lsr #4 @ combine nibbles } else
- ldreq r6, [sp, r5, lsl #2] @ { load Rm value }
+ ldreq r6, [r2, r5, lsl #2] @ { load Rm value }
.data_arm_apply_r6_and_rn:
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrpreconst:
@@ -105,11 +105,11 @@ ENTRY(v4t_late_abort)
movs r9, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r9, lsr #20 @ Undo increment
addeq r7, r7, r9, lsr #20 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrprereg:
@@ -117,7 +117,7 @@ ENTRY(v4t_late_abort)
beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
- ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
+ ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
mov r5, r8, lsr #7 @ get shift count
ands r5, r5, #31
and r7, r8, #0x70 @ get shift type
@@ -201,11 +201,11 @@ ENTRY(v4t_late_abort)
movs r7, r8, lsr #9 @ C = r8 bit 8 (R bit)
adc r6, r6, r6, lsr #4 @ high + low nibble + R bit
and r6, r6, #15 @ number of regs to transfer
- ldr r7, [sp, #13 << 2]
+ ldr r7, [r2, #13 << 2]
tst r8, #1 << 11
addeq r7, r7, r6, lsl #2 @ increment SP if PUSH
subne r7, r7, r6, lsl #2 @ decrement SP if POP
- str r7, [sp, #13 << 2]
+ str r7, [r2, #13 << 2]
b do_DataAbort
.data_thumb_ldmstm:
@@ -217,8 +217,8 @@ ENTRY(v4t_late_abort)
add r6, r6, r9, lsr #2
add r6, r6, r6, lsr #4
and r5, r8, #7 << 8
- ldr r7, [sp, r5, lsr #6]
+ ldr r7, [r2, r5, lsr #6]
and r6, r6, #15 @ number of regs to transfer
sub r7, r7, r6, lsl #2 @ always decrement
- str r7, [sp, r5, lsr #6]
+ str r7, [r2, r5, lsr #6]
b do_DataAbort
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index d755d5b..141906e 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -96,20 +96,20 @@ ENTRY(cpu_arm6_data_abort)
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_apply_r6_and_rn:
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrpreconst:
@@ -119,11 +119,11 @@ ENTRY(cpu_arm6_data_abort)
movs r9, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [sp, r5, lsr #14] @ Get register 'Rn'
+ ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r9, lsr #20 @ Undo increment
addeq r7, r7, r9, lsr #20 @ Undo decrement
- str r7, [sp, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrprereg:
@@ -131,7 +131,7 @@ ENTRY(cpu_arm6_data_abort)
beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
- ldr r6, [sp, r7, lsl #2] @ Get register 'Rm'
+ ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
mov r5, r8, lsr #7 @ get shift count
ands r5, r5, #31
and r7, r8, #0x70 @ get shift type
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 21/23] ARM: entry: data abort: always use r6 for offset
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (20 preceding siblings ...)
2011-06-29 9:25 ` [PATCH 20/23] ARM: entry: data abort: use r2 as base of pt_regs rather than stack Russell King - ARM Linux
@ 2011-06-29 9:25 ` Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 22/23] ARM: entry: data abort: ensure r5 is preserved by abort functions Russell King - ARM Linux
` (2 subsequent siblings)
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-lv4t.S | 6 +++---
arch/arm/mm/proc-arm6_7.S | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 921aaab..54b6d27 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -102,13 +102,13 @@ ENTRY(v4t_late_abort)
tst r8, #1 << 21 @ check writeback bit
beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostconst:
- movs r9, r8, lsl #20 @ Get offset
+ movs r6, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r9, lsr #20 @ Undo increment
- addeq r7, r7, r9, lsr #20 @ Undo decrement
+ subne r7, r7, r6, lsr #20 @ Undo increment
+ addeq r7, r7, r6, lsr #20 @ Undo decrement
str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 141906e..4d96311 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -116,13 +116,13 @@ ENTRY(cpu_arm6_data_abort)
tst r8, #1 << 21 @ check writeback bit
beq do_DataAbort @ no writeback -> no fixup
.data_arm_lateldrpostconst:
- movs r9, r8, lsl #20 @ Get offset
+ movs r6, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
and r5, r8, #15 << 16 @ Extract 'n' from instruction
ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r9, lsr #20 @ Undo increment
- addeq r7, r7, r9, lsr #20 @ Undo decrement
+ subne r7, r7, r6, lsr #20 @ Undo increment
+ addeq r7, r7, r6, lsr #20 @ Undo decrement
str r7, [r2, r5, lsr #14] @ Put register 'Rn'
b do_DataAbort
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 22/23] ARM: entry: data abort: ensure r5 is preserved by abort functions
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (21 preceding siblings ...)
2011-06-29 9:25 ` [PATCH 21/23] ARM: entry: data abort: always use r6 for offset Russell King - ARM Linux
@ 2011-06-29 9:26 ` Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 23/23] ARM: entry: no need to reload the SPSR value from struct pt_regs Russell King - ARM Linux
2011-06-29 14:53 ` [PATCH 00/23] entry assembly cleanups Jean-Christophe PLAGNIOL-VILLARD
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:26 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/mm/abort-lv4t.S | 48 ++++++++++++++++++++------------------------
arch/arm/mm/proc-arm6_7.S | 33 +++++++++++++++---------------
2 files changed, 38 insertions(+), 43 deletions(-)
diff --git a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
index 54b6d27..f398258 100644
--- a/arch/arm/mm/abort-lv4t.S
+++ b/arch/arm/mm/abort-lv4t.S
@@ -7,11 +7,7 @@
* : r4 = aborted context pc
* : r5 = aborted context psr
*
- * Returns : r0 = address of abort
- * : r1 = FSR, bit 11 = write
- * : r2-r8 = corrupted
- * : r9 = preserved
- * : sp = pointer to registers
+ * Returns : r4-r5, r10-r11, r13 preserved
*
* Purpose : obtain information about current aborted instruction.
* Note: we read user space. This means we might cause a data
@@ -72,30 +68,30 @@ ENTRY(v4t_late_abort)
add r6, r6, r6, lsr #8
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrhpre:
tst r8, #1 << 21 @ Check writeback bit
beq do_DataAbort @ No writeback -> no fixup
.data_arm_lateldrhpost:
- and r5, r8, #0x00f @ get Rm / low nibble of immediate value
+ and r9, r8, #0x00f @ get Rm / low nibble of immediate value
tst r8, #1 << 22 @ if (immediate offset)
andne r6, r8, #0xf00 @ { immediate high nibble
- orrne r6, r5, r6, lsr #4 @ combine nibbles } else
- ldreq r6, [r2, r5, lsl #2] @ { load Rm value }
+ orrne r6, r9, r6, lsr #4 @ combine nibbles } else
+ ldreq r6, [r2, r9, lsl #2] @ { load Rm value }
.data_arm_apply_r6_and_rn:
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrpreconst:
@@ -104,12 +100,12 @@ ENTRY(v4t_late_abort)
.data_arm_lateldrpostconst:
movs r6, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsr #20 @ Undo increment
addeq r7, r7, r6, lsr #20 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrprereg:
@@ -118,14 +114,14 @@ ENTRY(v4t_late_abort)
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
- mov r5, r8, lsr #7 @ get shift count
- ands r5, r5, #31
+ mov r9, r8, lsr #7 @ get shift count
+ ands r9, r9, #31
and r7, r8, #0x70 @ get shift type
orreq r7, r7, #8 @ shift count = 0
add pc, pc, r7
nop
- mov r6, r6, lsl r5 @ 0: LSL #!0
+ mov r6, r6, lsl r9 @ 0: LSL #!0
b .data_arm_apply_r6_and_rn
b .data_arm_apply_r6_and_rn @ 1: LSL #0
nop
@@ -133,7 +129,7 @@ ENTRY(v4t_late_abort)
nop
b .data_unknown @ 3: MUL?
nop
- mov r6, r6, lsr r5 @ 4: LSR #!0
+ mov r6, r6, lsr r9 @ 4: LSR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, lsr #32 @ 5: LSR #32
b .data_arm_apply_r6_and_rn
@@ -141,7 +137,7 @@ ENTRY(v4t_late_abort)
nop
b .data_unknown @ 7: MUL?
nop
- mov r6, r6, asr r5 @ 8: ASR #!0
+ mov r6, r6, asr r9 @ 8: ASR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, asr #32 @ 9: ASR #32
b .data_arm_apply_r6_and_rn
@@ -149,7 +145,7 @@ ENTRY(v4t_late_abort)
nop
b .data_unknown @ B: MUL?
nop
- mov r6, r6, ror r5 @ C: ROR #!0
+ mov r6, r6, ror r9 @ C: ROR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, rrx @ D: RRX
b .data_arm_apply_r6_and_rn
@@ -216,9 +212,9 @@ ENTRY(v4t_late_abort)
and r6, r6, #0x33
add r6, r6, r9, lsr #2
add r6, r6, r6, lsr #4
- and r5, r8, #7 << 8
- ldr r7, [r2, r5, lsr #6]
+ and r9, r8, #7 << 8
+ ldr r7, [r2, r9, lsr #6]
and r6, r6, #15 @ number of regs to transfer
sub r7, r7, r6, lsl #2 @ always decrement
- str r7, [r2, r5, lsr #6]
+ str r7, [r2, r9, lsr #6]
b do_DataAbort
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 4d96311..50e3543 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -35,8 +35,7 @@ ENTRY(cpu_arm7_dcache_clean_area)
*
* Purpose : obtain information about current aborted instruction
*
- * Returns : r0 = address of abort
- * : r1 = FSR
+ * Returns : r4-r5, r10-r11, r13 preserved
*/
ENTRY(cpu_arm7_data_abort)
@@ -95,21 +94,21 @@ ENTRY(cpu_arm6_data_abort)
add r6, r6, r6, lsr #8
add r6, r6, r6, lsr #4
and r6, r6, #15 @ r6 = no. of registers to transfer.
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsl #2 @ Undo increment
addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_apply_r6_and_rn:
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6 @ Undo incrmenet
addeq r7, r7, r6 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrpreconst:
@@ -118,12 +117,12 @@ ENTRY(cpu_arm6_data_abort)
.data_arm_lateldrpostconst:
movs r6, r8, lsl #20 @ Get offset
beq do_DataAbort @ zero -> no fixup
- and r5, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r5, lsr #14] @ Get register 'Rn'
+ and r9, r8, #15 << 16 @ Extract 'n' from instruction
+ ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
tst r8, #1 << 23 @ Check U bit
subne r7, r7, r6, lsr #20 @ Undo increment
addeq r7, r7, r6, lsr #20 @ Undo decrement
- str r7, [r2, r5, lsr #14] @ Put register 'Rn'
+ str r7, [r2, r9, lsr #14] @ Put register 'Rn'
b do_DataAbort
.data_arm_lateldrprereg:
@@ -132,14 +131,14 @@ ENTRY(cpu_arm6_data_abort)
.data_arm_lateldrpostreg:
and r7, r8, #15 @ Extract 'm' from instruction
ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
- mov r5, r8, lsr #7 @ get shift count
- ands r5, r5, #31
+ mov r9, r8, lsr #7 @ get shift count
+ ands r9, r9, #31
and r7, r8, #0x70 @ get shift type
orreq r7, r7, #8 @ shift count = 0
add pc, pc, r7
nop
- mov r6, r6, lsl r5 @ 0: LSL #!0
+ mov r6, r6, lsl r9 @ 0: LSL #!0
b .data_arm_apply_r6_and_rn
b .data_arm_apply_r6_and_rn @ 1: LSL #0
nop
@@ -147,7 +146,7 @@ ENTRY(cpu_arm6_data_abort)
nop
b .data_unknown @ 3: MUL?
nop
- mov r6, r6, lsr r5 @ 4: LSR #!0
+ mov r6, r6, lsr r9 @ 4: LSR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, lsr #32 @ 5: LSR #32
b .data_arm_apply_r6_and_rn
@@ -155,7 +154,7 @@ ENTRY(cpu_arm6_data_abort)
nop
b .data_unknown @ 7: MUL?
nop
- mov r6, r6, asr r5 @ 8: ASR #!0
+ mov r6, r6, asr r9 @ 8: ASR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, asr #32 @ 9: ASR #32
b .data_arm_apply_r6_and_rn
@@ -163,7 +162,7 @@ ENTRY(cpu_arm6_data_abort)
nop
b .data_unknown @ B: MUL?
nop
- mov r6, r6, ror r5 @ C: ROR #!0
+ mov r6, r6, ror r9 @ C: ROR #!0
b .data_arm_apply_r6_and_rn
mov r6, r6, rrx @ D: RRX
b .data_arm_apply_r6_and_rn
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 23/23] ARM: entry: no need to reload the SPSR value from struct pt_regs
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (22 preceding siblings ...)
2011-06-29 9:26 ` [PATCH 22/23] ARM: entry: data abort: ensure r5 is preserved by abort functions Russell King - ARM Linux
@ 2011-06-29 9:26 ` Russell King - ARM Linux
2011-06-29 14:53 ` [PATCH 00/23] entry assembly cleanups Jean-Christophe PLAGNIOL-VILLARD
24 siblings, 0 replies; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-29 9:26 UTC (permalink / raw)
To: linux-arm-kernel
The SVC IRQ, prefetch and data abort handlers preserve the SPSR value
via r5 across the exception. Rather than re-loading it from pt_regs,
use the preserved value instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
---
arch/arm/kernel/entry-armv.S | 10 +---------
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3fa90ae..047ed5d 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -195,10 +195,6 @@ __dabt_svc:
@
disable_irq_notrace
- @
- @ restore SPSR and restart the instruction
- @
- ldr r5, [sp, #S_PSR]
#ifdef CONFIG_TRACE_IRQFLAGS
tst r5, #PSR_I_BIT
bleq trace_hardirqs_on
@@ -223,7 +219,7 @@ __irq_svc:
tst r0, #_TIF_NEED_RESCHED
blne svc_preempt
#endif
- ldr r5, [sp, #S_PSR]
+
#ifdef CONFIG_TRACE_IRQFLAGS
@ The parent context IRQs must have been enabled to get here in
@ the first place, so there's no point checking the PSR I bit.
@@ -308,10 +304,6 @@ __pabt_svc:
@
disable_irq_notrace
- @
- @ restore SPSR and restart the instruction
- @
- ldr r5, [sp, #S_PSR]
#ifdef CONFIG_TRACE_IRQFLAGS
tst r5, #PSR_I_BIT
bleq trace_hardirqs_on
--
1.7.4.4
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 00/23] entry assembly cleanups
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
` (23 preceding siblings ...)
2011-06-29 9:26 ` [PATCH 23/23] ARM: entry: no need to reload the SPSR value from struct pt_regs Russell King - ARM Linux
@ 2011-06-29 14:53 ` Jean-Christophe PLAGNIOL-VILLARD
24 siblings, 0 replies; 29+ messages in thread
From: Jean-Christophe PLAGNIOL-VILLARD @ 2011-06-29 14:53 UTC (permalink / raw)
To: linux-arm-kernel
On 10:18 Wed 29 Jun , Russell King - ARM Linux wrote:
> This patch series cleans up the entry assembly and CPU abort helpers.
> Notable things about this patch series:
>
do you have a git repos where we could pull it?
otherwise great job tks
Best Regards,
J.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers
2011-06-29 9:22 ` [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers Russell King - ARM Linux
@ 2011-06-29 20:05 ` Will Deacon
2011-06-30 9:27 ` Russell King - ARM Linux
0 siblings, 1 reply; 29+ messages in thread
From: Will Deacon @ 2011-06-29 20:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Russell,
This looks good, thanks. Minor comment inline.
On Wed, Jun 29, 2011 at 10:22:35AM +0100, Russell King - ARM Linux wrote:
> Avoid enabling interrupts if the parent context had interrupts enabled
> in the abort handler assembly code, and move this into the breakpoint/
> page/alignment fault handlers instead.
>
> This gets rid of some special-casing for the breakpoint fault handlers
> from the low level abort handler path.
>
> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
> arch/arm/kernel/entry-armv.S | 43 +++++++++++++++++---------------------
> arch/arm/kernel/entry-header.S | 19 -----------------
> arch/arm/kernel/hw_breakpoint.c | 6 +++-
> arch/arm/mm/alignment.c | 3 ++
> arch/arm/mm/fault.c | 4 +++
> 5 files changed, 30 insertions(+), 45 deletions(-)
[...]
> diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
> index 87acc25..b813e1e 100644
> --- a/arch/arm/kernel/hw_breakpoint.c
> +++ b/arch/arm/kernel/hw_breakpoint.c
> @@ -804,8 +804,10 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
> int ret = 0;
> u32 dscr;
>
> - /* We must be called with preemption disabled. */
> - WARN_ON(preemptible());
> + preempt_disable();
> +
> + if (interrupts_enabled(regs))
> + local_irq_enable();
>
> /* We only handle watchpoints and hardware breakpoints. */
> ARM_DBG_READ(c1, 0, dscr);
Could you also update the comments for this function too please? There's one
immediately before the function that states we are called with preemption
disabled and there's another one where we re-enable preemption stating that
it was disabled by the low-level exception handling code.
With those two extra changes:
Acked-by: Will Deacon <will.deacon@arm.com>
Cheers,
Will
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers
2011-06-29 20:05 ` Will Deacon
@ 2011-06-30 9:27 ` Russell King - ARM Linux
2011-06-30 21:51 ` Will Deacon
0 siblings, 1 reply; 29+ messages in thread
From: Russell King - ARM Linux @ 2011-06-30 9:27 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jun 29, 2011 at 09:05:23PM +0100, Will Deacon wrote:
> Hi Russell,
>
> This looks good, thanks. Minor comment inline.
>
> On Wed, Jun 29, 2011 at 10:22:35AM +0100, Russell King - ARM Linux wrote:
> > Avoid enabling interrupts if the parent context had interrupts enabled
> > in the abort handler assembly code, and move this into the breakpoint/
> > page/alignment fault handlers instead.
> >
> > This gets rid of some special-casing for the breakpoint fault handlers
> > from the low level abort handler path.
> >
> > Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
> > ---
> > arch/arm/kernel/entry-armv.S | 43 +++++++++++++++++---------------------
> > arch/arm/kernel/entry-header.S | 19 -----------------
> > arch/arm/kernel/hw_breakpoint.c | 6 +++-
> > arch/arm/mm/alignment.c | 3 ++
> > arch/arm/mm/fault.c | 4 +++
> > 5 files changed, 30 insertions(+), 45 deletions(-)
>
> [...]
>
> > diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
> > index 87acc25..b813e1e 100644
> > --- a/arch/arm/kernel/hw_breakpoint.c
> > +++ b/arch/arm/kernel/hw_breakpoint.c
> > @@ -804,8 +804,10 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
> > int ret = 0;
> > u32 dscr;
> >
> > - /* We must be called with preemption disabled. */
> > - WARN_ON(preemptible());
> > + preempt_disable();
> > +
> > + if (interrupts_enabled(regs))
> > + local_irq_enable();
> >
> > /* We only handle watchpoints and hardware breakpoints. */
> > ARM_DBG_READ(c1, 0, dscr);
>
> Could you also update the comments for this function too please? There's one
> immediately before the function that states we are called with preemption
> disabled and there's another one where we re-enable preemption stating that
> it was disabled by the low-level exception handling code.
I'll change the one before the function thusly s/preemption/interrupts/
and remove the other entirely because it no longer serves much purpose.
Ok?
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers
2011-06-30 9:27 ` Russell King - ARM Linux
@ 2011-06-30 21:51 ` Will Deacon
0 siblings, 0 replies; 29+ messages in thread
From: Will Deacon @ 2011-06-30 21:51 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jun 30, 2011 at 10:27:02AM +0100, Russell King - ARM Linux wrote:
> On Wed, Jun 29, 2011 at 09:05:23PM +0100, Will Deacon wrote:
> > Could you also update the comments for this function too please? There's one
> > immediately before the function that states we are called with preemption
> > disabled and there's another one where we re-enable preemption stating that
> > it was disabled by the low-level exception handling code.
>
> I'll change the one before the function thusly s/preemption/interrupts/
> and remove the other entirely because it no longer serves much purpose.
> Ok?
Sounds good to me, you add my ack with those changes.
Thanks,
Will
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2011-06-30 21:51 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-06-29 9:18 [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 01/23] ARM: entry: remove unused irq_prio_table macro Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 02/23] ARM: entry: shark: don't directly reference registers in macros Russell King - ARM Linux
2011-06-29 9:19 ` [PATCH 03/23] ARM: entry: prefetch/data abort helpers: convert to macros Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 00/23] entry assembly cleanups Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 04/23] ARM: entry: prefetch/data abort helpers: avoid corrupting r4 Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 05/23] ARM: entry: abort-macro: specify registers to be used for macros Russell King - ARM Linux
2011-06-29 9:20 ` [PATCH 06/23] ARM: entry: abort-macro: simplify do_ldrd_abort Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 07/23] ARM: entry: no need to increase preempt count for IRQ handlers Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 08/23] ARM: entry: no need to check parent IRQ mask in IRQ handler return Russell King - ARM Linux
2011-06-29 9:21 ` [PATCH 09/23] ARM: entry: rejig register allocation in exception entry handlers Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 10/23] ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0 Russell King - ARM Linux
2011-06-29 9:22 ` [PATCH 11/23] ARM: entry: avoid enabling interrupts in prefetch/data abort handlers Russell King - ARM Linux
2011-06-29 20:05 ` Will Deacon
2011-06-30 9:27 ` Russell King - ARM Linux
2011-06-30 21:51 ` Will Deacon
2011-06-29 9:22 ` [PATCH 12/23] ARM: entry: instrument svc undefined exception handler with irqtrace Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 13/23] ARM: entry: instrument usr exception handlers with irqsoff tracing Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 14/23] ARM: entry: consolidate trace_hardirqs_off into (svc|usr)_entry macros Russell King - ARM Linux
2011-06-29 9:23 ` [PATCH 15/23] ARM: entry: re-allocate registers in irq entry assembly macros Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 16/23] ARM: entry: prefetch abort: tail-call the main prefetch abort handler Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 17/23] ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5 Russell King - ARM Linux
2011-06-29 9:24 ` [PATCH 18/23] ARM: entry: data abort: avoid using r2 in abort helpers Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 19/23] ARM: entry: data abort: tail-call the main data abort handler Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 20/23] ARM: entry: data abort: use r2 as base of pt_regs rather than stack Russell King - ARM Linux
2011-06-29 9:25 ` [PATCH 21/23] ARM: entry: data abort: always use r6 for offset Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 22/23] ARM: entry: data abort: ensure r5 is preserved by abort functions Russell King - ARM Linux
2011-06-29 9:26 ` [PATCH 23/23] ARM: entry: no need to reload the SPSR value from struct pt_regs Russell King - ARM Linux
2011-06-29 14:53 ` [PATCH 00/23] entry assembly cleanups Jean-Christophe PLAGNIOL-VILLARD
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