[PATCH 0/7] ASoC: Intel: Skylake: Fix suspend issues

[PATCH 0/7] ASoC: Intel: Skylake: Fix suspend issues

[Vinod Koul]

While testing legacy Suspend on Skylake, we found few issues that require
driver changes. This was tested with usermode apps and aplay.

We need to add RESUME capability in driver to let ALSA resume us, then HDA
was not getting reconfigured upon resume so that is updated.  CLDMA needs to
be polled as that takes a little while like HDA DMA, also clear of
registers is required per spec upon setup

Last one fixes resource leak upon failures by movng free call up (not
related to suspend though but observed when we saw failures)

Jeeja KP (6):
  ASoC: Intel: Skylake: Add Resume capability in PCM info.
  ASoC: Intel: Skylake: Reconfigure HDA stream register in
    prepare/resume
  ASoC: Intel: Skylake: Fix to update bit depth for module params
  ASoC: Intel: Skylake: Add pcm capability to support 16/8k rates.
  ASoC: Intel: Skylake: Poll CLDMA RUN bit when set
  ASoC: Intel: Skylake: Clear stream registers before setting up stream

Vinod Koul (1):
  ASoC: Intel: Skylake: Move up pipe mem free

 sound/soc/intel/skylake/skl-pcm.c       | 22 +++++----
 sound/soc/intel/skylake/skl-sst-cldma.c | 82 +++++++++++++++++++++------------
 sound/soc/intel/skylake/skl-topology.c  | 22 +++++++--
 3 files changed, 86 insertions(+), 40 deletions(-)

-- 
1.9.1

[PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds pcm capability to support Resume.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index dae332beea3f..4378bf452582 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -35,6 +35,7 @@ static struct snd_pcm_hardware azx_pcm_hw = {
 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 				 SNDRV_PCM_INFO_MMAP_VALID |
 				 SNDRV_PCM_INFO_PAUSE |
+				 SNDRV_PCM_INFO_RESUME |
 				 SNDRV_PCM_INFO_SYNC_START |
 				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
-- 
1.9.1

[PATCH 2/7] ASoC: Intel: Skylake: Reconfigure HDA stream register in prepare/resume

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

PCM prepare callbacks can be called multiple times. During S3
the stream registers will be reset when Controller is reset.
When stream is resumed, these stream registers needs to reconfigured.

This patch removes the check in prepare callback() if stream already
prepared, which will allow reconfiguring of stream registers and also
decouple stream when stream is resumed to route audio via DSP.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 4378bf452582..43944aff8dcb 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -182,10 +182,6 @@ static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 	int err;
 
 	dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
-	if (hdac_stream(stream)->prepared) {
-		dev_dbg(dai->dev, "already stream is prepared - returning\n");
-		return 0;
-	}
 
 	format_val = skl_get_format(substream, dai);
 	dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
@@ -343,6 +339,8 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 	struct skl *skl = get_skl_ctx(dai->dev);
 	struct skl_sst *ctx = skl->skl_sst;
 	struct skl_module_cfg *mconfig;
+	struct hdac_ext_bus *ebus = get_bus_ctx(substream);
+	struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 	int ret;
 
 	mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
@@ -350,15 +348,17 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 		return -EIO;
 
 	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_RESUME:
+		skl_pcm_prepare(substream, dai);
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-	case SNDRV_PCM_TRIGGER_RESUME:
 		/*
 		 * Start HOST DMA and Start FE Pipe.This is to make sure that
 		 * there are no underrun/overrun in the case when the FE
 		 * pipeline is started but there is a delay in starting the
 		 * DMA channel on the host.
 		 */
+		snd_hdac_ext_stream_decouple(ebus, stream, true);
 		ret = skl_decoupled_trigger(substream, cmd);
 		if (ret < 0)
 			return ret;
@@ -378,6 +378,8 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 			return ret;
 
 		ret = skl_decoupled_trigger(substream, cmd);
+		if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
+			snd_hdac_ext_stream_decouple(ebus, stream, false);
 		break;
 
 	default:
-- 
1.9.1

[PATCH 3/7] ASoC: Intel: Skylake: Fix to update bit depth for module params

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

Module hw param fixup will change the valid bit depth based
on the fixup flag. If valid bit depth changes, need to set
the bit depth according to valid bit depth. This patch
fixes this issue of updating bit depth correctly.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-topology.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index 0937ea2129c1..698c4aa03933 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -147,8 +147,24 @@ static void skl_tplg_update_params(struct skl_module_fmt *fmt,
 		fmt->s_freq = params->s_freq;
 	if (fixup & SKL_CH_FIXUP_MASK)
 		fmt->channels = params->ch;
-	if (fixup & SKL_FMT_FIXUP_MASK)
-		fmt->valid_bit_depth = params->s_fmt;
+	if (fixup & SKL_FMT_FIXUP_MASK) {
+		fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
+
+		/*
+		 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
+		 * container so update bit depth accordingly
+		 */
+		switch (fmt->valid_bit_depth) {
+		case SKL_DEPTH_16BIT:
+			fmt->bit_depth = fmt->valid_bit_depth;
+			break;
+
+		default:
+			fmt->bit_depth = SKL_DEPTH_32BIT;
+			break;
+		}
+	}
+
 }
 
 /*
-- 
1.9.1

[PATCH 4/7] ASoC: Intel: Skylake: Update pcm capability

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds pcm capability to support 16/8k rates and 32 bit formats

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-pcm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 43944aff8dcb..787fd3c0cc4e 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -40,9 +40,12 @@ static struct snd_pcm_hardware azx_pcm_hw = {
 				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
 				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
-	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
-	.rates =		SNDRV_PCM_RATE_48000,
-	.rate_min =		48000,
+	.formats =		SNDRV_PCM_FMTBIT_S16_LE |
+				SNDRV_PCM_FMTBIT_S32_LE |
+				SNDRV_PCM_FMTBIT_S24_LE,
+	.rates =		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
+				SNDRV_PCM_RATE_8000,
+	.rate_min =		8000,
 	.rate_max =		48000,
 	.channels_min =		2,
 	.channels_max =		2,
-- 
1.9.1

[PATCH 5/7] ASoC: Intel: Skylake: Poll CLDMA RUN bit when set

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds polling of CLDMA stream run bit when set
to confirm the HW reports the same value.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-sst-cldma.c | 43 ++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 14 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-cldma.c b/sound/soc/intel/skylake/skl-sst-cldma.c
index b03d9db0acad..faaa852ed015 100644
--- a/sound/soc/intel/skylake/skl-sst-cldma.c
+++ b/sound/soc/intel/skylake/skl-sst-cldma.c
@@ -18,6 +18,7 @@
 #include <linux/device.h>
 #include <linux/mm.h>
 #include <linux/kthread.h>
+#include <linux/delay.h>
 #include "../common/sst-dsp.h"
 #include "../common/sst-dsp-priv.h"
 
@@ -33,6 +34,32 @@ void skl_cldma_int_disable(struct sst_dsp *ctx)
 			SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
 }
 
+static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
+{
+	unsigned char val;
+	int timeout;
+
+	sst_dsp_shim_update_bits_unlocked(ctx,
+			SKL_ADSP_REG_CL_SD_CTL,
+			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
+
+	udelay(3);
+	timeout = 300;
+	do {
+		/* waiting for hardware to report that the stream Run bit set */
+		val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
+			CL_SD_CTL_RUN_MASK;
+		if (enable && val)
+			break;
+		else if (!enable && !val)
+			break;
+		udelay(3);
+	} while (--timeout);
+
+	if (timeout == 0)
+		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
+}
+
 /* Code loader helper APIs */
 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 		struct snd_dma_buffer *dmab_data,
@@ -107,18 +134,6 @@ static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
 }
 
-static void skl_cldma_trigger(struct sst_dsp  *ctx, bool enable)
-{
-	if (enable)
-		sst_dsp_shim_update_bits_unlocked(ctx,
-			SKL_ADSP_REG_CL_SD_CTL,
-			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(1));
-	else
-		sst_dsp_shim_update_bits_unlocked(ctx,
-			SKL_ADSP_REG_CL_SD_CTL,
-			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(0));
-}
-
 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
 {
 	skl_cldma_cleanup_spb(ctx);
@@ -169,7 +184,7 @@ cleanup:
 
 static void skl_cldma_stop(struct sst_dsp *ctx)
 {
-	ctx->cl_dev.ops.cl_trigger(ctx, false);
+	skl_cldma_stream_run(ctx, false);
 }
 
 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
@@ -311,7 +326,7 @@ int skl_cldma_prepare(struct sst_dsp *ctx)
 	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
 	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
 	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
-	ctx->cl_dev.ops.cl_trigger = skl_cldma_trigger;
+	ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
 	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
 	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
 	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
-- 
1.9.1

[PATCH 6/7] ASoC: Intel: Skylake: Clear stream registers before setting up stream

[Vinod Koul]

From: Jeeja KP <jeeja.kp@intel.com>

This patch adds clean up routine to clear the stream registers and
calls this routine before setting up stream registers.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-sst-cldma.c | 39 ++++++++++++++++++++-------------
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-cldma.c b/sound/soc/intel/skylake/skl-sst-cldma.c
index faaa852ed015..b845c3acd3eb 100644
--- a/sound/soc/intel/skylake/skl-sst-cldma.c
+++ b/sound/soc/intel/skylake/skl-sst-cldma.c
@@ -60,6 +60,28 @@ static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
 		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
 }
 
+static void skl_cldma_stream_clear(struct sst_dsp  *ctx)
+{
+	/* make sure Run bit is cleared before setting stream register */
+	skl_cldma_stream_run(ctx, 0);
+
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
+	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
+				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
+
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
+
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
+	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
+}
+
+
 /* Code loader helper APIs */
 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 		struct snd_dma_buffer *dmab_data,
@@ -95,6 +117,7 @@ static void skl_cldma_setup_controller(struct sst_dsp  *ctx,
 		struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
 		u32 count)
 {
+	skl_cldma_stream_clear(ctx);
 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
 			CL_SD_BDLPLBA(dmab_bdl->addr));
 	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
@@ -137,21 +160,7 @@ static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
 {
 	skl_cldma_cleanup_spb(ctx);
-
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
-	sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
-				CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
-
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
-
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
-	sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
+	skl_cldma_stream_clear(ctx);
 
 	if (&ctx->cl_dev.dmab_data)
 		ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
-- 
1.9.1

[PATCH 7/7] ASoC: Intel: Skylake: Move up pipe mem free

[Vinod Koul]

The MCPS is freed first thing in pmd events but non memory. So if
we face error during teardown we leak this mem, so move the code
up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
 sound/soc/intel/skylake/skl-topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index 698c4aa03933..f221c758d601 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -652,6 +652,7 @@ static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
 	int ret = 0;
 
 	skl_tplg_free_pipe_mcps(skl, mconfig);
+	skl_tplg_free_pipe_mem(skl, mconfig);
 
 	list_for_each_entry(w_module, &s_pipe->w_list, node) {
 		dst_module = w_module->w->priv;
@@ -670,7 +671,6 @@ static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
 	}
 
 	ret = skl_delete_pipe(ctx, mconfig->pipe);
-	skl_tplg_free_pipe_mem(skl, mconfig);
 
 	return ret;
 }
-- 
1.9.1

Re: [PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Takashi Iwai]

On Mon, 23 Nov 2015 17:56:23 +0100,
Vinod Koul wrote:
> 
> From: Jeeja KP <jeeja.kp@intel.com>
> 
> This patch adds pcm capability to support Resume.

The flag indicates that the driver is capable of the full resume --
i.e. it must resume everything at the exactly same point to be
suspended.  Is it really the case?

If it's not and it's instead a kind of restart of streams, don't add
this flag.  The lack of the flag doesn't mean that the driver can't
resume at all.


Takashi

> 
> Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
> ---
>  sound/soc/intel/skylake/skl-pcm.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
> index dae332beea3f..4378bf452582 100644
> --- a/sound/soc/intel/skylake/skl-pcm.c
> +++ b/sound/soc/intel/skylake/skl-pcm.c
> @@ -35,6 +35,7 @@ static struct snd_pcm_hardware azx_pcm_hw = {
>  				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
>  				 SNDRV_PCM_INFO_MMAP_VALID |
>  				 SNDRV_PCM_INFO_PAUSE |
> +				 SNDRV_PCM_INFO_RESUME |
>  				 SNDRV_PCM_INFO_SYNC_START |
>  				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
>  				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
> -- 
> 1.9.1
> 
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel@alsa-project.org
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
> 

Re: [PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Vinod Koul]

On Mon, Nov 23, 2015 at 07:45:20PM +0100, Takashi Iwai wrote:
> On Mon, 23 Nov 2015 17:56:23 +0100,
> Vinod Koul wrote:
> > 
> > From: Jeeja KP <jeeja.kp@intel.com>
> > 
> > This patch adds pcm capability to support Resume.
> 
> The flag indicates that the driver is capable of the full resume --
> i.e. it must resume everything at the exactly same point to be
> suspended.  Is it really the case?
> 
> If it's not and it's instead a kind of restart of streams, don't add
> this flag.  The lack of the flag doesn't mean that the driver can't
> resume at all.

Yes, with this patch series we are able to resume from previous position.

Here is my test:

# aplay -Dhw:0,0 play.wav
Playing WAVE 'play.wav' : Signed 16 bit Little Endian, Rate 48000 Hz,
Stereo
Suspended. Trying resume. Done.

Thanks
-- 
~Vinod

Re: [PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Takashi Iwai]

On Tue, 24 Nov 2015 03:44:49 +0100,
Vinod Koul wrote:
> 
> On Mon, Nov 23, 2015 at 07:45:20PM +0100, Takashi Iwai wrote:
> > On Mon, 23 Nov 2015 17:56:23 +0100,
> > Vinod Koul wrote:
> > > 
> > > From: Jeeja KP <jeeja.kp@intel.com>
> > > 
> > > This patch adds pcm capability to support Resume.
> > 
> > The flag indicates that the driver is capable of the full resume --
> > i.e. it must resume everything at the exactly same point to be
> > suspended.  Is it really the case?
> > 
> > If it's not and it's instead a kind of restart of streams, don't add
> > this flag.  The lack of the flag doesn't mean that the driver can't
> > resume at all.
> 
> Yes, with this patch series we are able to resume from previous position.

I suppose you tested hibernation, too?
How does it assure that the in-flight data on FIFO are restored after
the link reset and re-prepare?

> Here is my test:
> 
> # aplay -Dhw:0,0 play.wav
> Playing WAVE 'play.wav' : Signed 16 bit Little Endian, Rate 48000 Hz,
> Stereo
> Suspended. Trying resume. Done.

As mentioned, the resume usually works (sort of), even without
SNDRV_PCM_INFO_RESUME bit.  It's because alsa-lib tries to re-prepare
the stuff by itself.

Did you try only the patch 2 without this patch?


Takashi

Applied "ASoC: Intel: Skylake: Move up pipe mem free" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Move up pipe mem free

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 65976878ca692566ed066f4fa977de517f697c59 Mon Sep 17 00:00:00 2001
From: Vinod Koul <vinod.koul@intel.com>
Date: Mon, 23 Nov 2015 22:26:29 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Move up pipe mem free

The MCPS is freed first thing in pmd events but non memory. So if
we face error during teardown we leak this mem, so move the code
up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index 698c4aa03933..f221c758d601 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -652,6 +652,7 @@ static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
 	int ret = 0;
 
 	skl_tplg_free_pipe_mcps(skl, mconfig);
+	skl_tplg_free_pipe_mem(skl, mconfig);
 
 	list_for_each_entry(w_module, &s_pipe->w_list, node) {
 		dst_module = w_module->w->priv;
@@ -670,7 +671,6 @@ static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
 	}
 
 	ret = skl_delete_pipe(ctx, mconfig->pipe);
-	skl_tplg_free_pipe_mem(skl, mconfig);
 
 	return ret;
 }
-- 
2.6.2

Applied "ASoC: Intel: Skylake: Poll CLDMA RUN bit when set" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Poll CLDMA RUN bit when set

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 2434caf098588856d1c332d2f60b8a2d8a198450 Mon Sep 17 00:00:00 2001
From: Jeeja KP <jeeja.kp@intel.com>
Date: Mon, 23 Nov 2015 22:26:27 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Poll CLDMA RUN bit when set

This patch adds polling of CLDMA stream run bit when set
to confirm the HW reports the same value.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-sst-cldma.c | 43 ++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 14 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-sst-cldma.c b/sound/soc/intel/skylake/skl-sst-cldma.c
index 947a08e42e86..8c7e8576cba3 100644
--- a/sound/soc/intel/skylake/skl-sst-cldma.c
+++ b/sound/soc/intel/skylake/skl-sst-cldma.c
@@ -18,6 +18,7 @@
 #include <linux/device.h>
 #include <linux/mm.h>
 #include <linux/kthread.h>
+#include <linux/delay.h>
 #include "../common/sst-dsp.h"
 #include "../common/sst-dsp-priv.h"
 
@@ -33,6 +34,32 @@ void skl_cldma_int_disable(struct sst_dsp *ctx)
 			SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
 }
 
+static void skl_cldma_stream_run(struct sst_dsp  *ctx, bool enable)
+{
+	unsigned char val;
+	int timeout;
+
+	sst_dsp_shim_update_bits_unlocked(ctx,
+			SKL_ADSP_REG_CL_SD_CTL,
+			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
+
+	udelay(3);
+	timeout = 300;
+	do {
+		/* waiting for hardware to report that the stream Run bit set */
+		val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
+			CL_SD_CTL_RUN_MASK;
+		if (enable && val)
+			break;
+		else if (!enable && !val)
+			break;
+		udelay(3);
+	} while (--timeout);
+
+	if (timeout == 0)
+		dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
+}
+
 /* Code loader helper APIs */
 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
 		struct snd_dma_buffer *dmab_data,
@@ -107,18 +134,6 @@ static void skl_cldma_cleanup_spb(struct sst_dsp  *ctx)
 	sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
 }
 
-static void skl_cldma_trigger(struct sst_dsp  *ctx, bool enable)
-{
-	if (enable)
-		sst_dsp_shim_update_bits_unlocked(ctx,
-			SKL_ADSP_REG_CL_SD_CTL,
-			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(1));
-	else
-		sst_dsp_shim_update_bits_unlocked(ctx,
-			SKL_ADSP_REG_CL_SD_CTL,
-			CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(0));
-}
-
 static void skl_cldma_cleanup(struct sst_dsp  *ctx)
 {
 	skl_cldma_cleanup_spb(ctx);
@@ -167,7 +182,7 @@ cleanup:
 
 static void skl_cldma_stop(struct sst_dsp *ctx)
 {
-	ctx->cl_dev.ops.cl_trigger(ctx, false);
+	skl_cldma_stream_run(ctx, false);
 }
 
 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
@@ -309,7 +324,7 @@ int skl_cldma_prepare(struct sst_dsp *ctx)
 	ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
 	ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
 	ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
-	ctx->cl_dev.ops.cl_trigger = skl_cldma_trigger;
+	ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
 	ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
 	ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
 	ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
-- 
2.6.2

Applied "ASoC: Intel: Skylake: Update pcm capability" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Update pcm capability

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 06b23d9379d4cd034b7a5edad323ea9419ab2016 Mon Sep 17 00:00:00 2001
From: Jeeja KP <jeeja.kp@intel.com>
Date: Mon, 23 Nov 2015 22:26:26 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Update pcm capability

This patch adds pcm capability to support 16/8k rates and 32 bit formats

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-pcm.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 3c891d78ba58..c79bbff00cb7 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -39,9 +39,12 @@ static struct snd_pcm_hardware azx_pcm_hw = {
 				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
 				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
-	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
-	.rates =		SNDRV_PCM_RATE_48000,
-	.rate_min =		48000,
+	.formats =		SNDRV_PCM_FMTBIT_S16_LE |
+				SNDRV_PCM_FMTBIT_S32_LE |
+				SNDRV_PCM_FMTBIT_S24_LE,
+	.rates =		SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
+				SNDRV_PCM_RATE_8000,
+	.rate_min =		8000,
 	.rate_max =		48000,
 	.channels_min =		2,
 	.channels_max =		2,
-- 
2.6.2

Applied "ASoC: Intel: Skylake: Fix to update bit depth for module params" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Fix to update bit depth for module params

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 98256f83d2895fda3e596824797762937ab79f6b Mon Sep 17 00:00:00 2001
From: Jeeja KP <jeeja.kp@intel.com>
Date: Mon, 23 Nov 2015 22:26:25 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Fix to update bit depth for module
 params

Module hw param fixup will change the valid bit depth based
on the fixup flag. If valid bit depth changes, need to set
the bit depth according to valid bit depth. This patch
fixes this issue of updating bit depth correctly.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-topology.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-topology.c b/sound/soc/intel/skylake/skl-topology.c
index 0937ea2129c1..698c4aa03933 100644
--- a/sound/soc/intel/skylake/skl-topology.c
+++ b/sound/soc/intel/skylake/skl-topology.c
@@ -147,8 +147,24 @@ static void skl_tplg_update_params(struct skl_module_fmt *fmt,
 		fmt->s_freq = params->s_freq;
 	if (fixup & SKL_CH_FIXUP_MASK)
 		fmt->channels = params->ch;
-	if (fixup & SKL_FMT_FIXUP_MASK)
-		fmt->valid_bit_depth = params->s_fmt;
+	if (fixup & SKL_FMT_FIXUP_MASK) {
+		fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
+
+		/*
+		 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
+		 * container so update bit depth accordingly
+		 */
+		switch (fmt->valid_bit_depth) {
+		case SKL_DEPTH_16BIT:
+			fmt->bit_depth = fmt->valid_bit_depth;
+			break;
+
+		default:
+			fmt->bit_depth = SKL_DEPTH_32BIT;
+			break;
+		}
+	}
+
 }
 
 /*
-- 
2.6.2

Applied "ASoC: Intel: Skylake: Reconfigure HDA stream register in prepare/resume" to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Reconfigure HDA stream register in prepare/resume

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 7e3a17d311ca89a74cfd39e02e96d29d92849d34 Mon Sep 17 00:00:00 2001
From: Jeeja KP <jeeja.kp@intel.com>
Date: Mon, 23 Nov 2015 22:26:24 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Reconfigure HDA stream register in
 prepare/resume

PCM prepare callbacks can be called multiple times. During S3
the stream registers will be reset when Controller is reset.
When stream is resumed, these stream registers needs to reconfigured.

This patch removes the check in prepare callback() if stream already
prepared, which will allow reconfiguring of stream registers and also
decouple stream when stream is resumed to route audio via DSP.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-pcm.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index dae332beea3f..3c891d78ba58 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -181,10 +181,6 @@ static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 	int err;
 
 	dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
-	if (hdac_stream(stream)->prepared) {
-		dev_dbg(dai->dev, "already stream is prepared - returning\n");
-		return 0;
-	}
 
 	format_val = skl_get_format(substream, dai);
 	dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
@@ -342,6 +338,8 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 	struct skl *skl = get_skl_ctx(dai->dev);
 	struct skl_sst *ctx = skl->skl_sst;
 	struct skl_module_cfg *mconfig;
+	struct hdac_ext_bus *ebus = get_bus_ctx(substream);
+	struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 	int ret;
 
 	mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
@@ -349,15 +347,17 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 		return -EIO;
 
 	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_RESUME:
+		skl_pcm_prepare(substream, dai);
 	case SNDRV_PCM_TRIGGER_START:
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-	case SNDRV_PCM_TRIGGER_RESUME:
 		/*
 		 * Start HOST DMA and Start FE Pipe.This is to make sure that
 		 * there are no underrun/overrun in the case when the FE
 		 * pipeline is started but there is a delay in starting the
 		 * DMA channel on the host.
 		 */
+		snd_hdac_ext_stream_decouple(ebus, stream, true);
 		ret = skl_decoupled_trigger(substream, cmd);
 		if (ret < 0)
 			return ret;
@@ -377,6 +377,8 @@ static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 			return ret;
 
 		ret = skl_decoupled_trigger(substream, cmd);
+		if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
+			snd_hdac_ext_stream_decouple(ebus, stream, false);
 		break;
 
 	default:
-- 
2.6.2

Re: [PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Vinod Koul]

On Tue, Nov 24, 2015 at 07:07:11AM +0100, Takashi Iwai wrote:
> On Tue, 24 Nov 2015 03:44:49 +0100,
> Vinod Koul wrote:
> > 
> > On Mon, Nov 23, 2015 at 07:45:20PM +0100, Takashi Iwai wrote:
> > > On Mon, 23 Nov 2015 17:56:23 +0100,
> > > Vinod Koul wrote:
> > > > 
> > > > From: Jeeja KP <jeeja.kp@intel.com>
> > > > 
> > > > This patch adds pcm capability to support Resume.
> > > 
> > > The flag indicates that the driver is capable of the full resume --
> > > i.e. it must resume everything at the exactly same point to be
> > > suspended.  Is it really the case?
> > > 
> > > If it's not and it's instead a kind of restart of streams, don't add
> > > this flag.  The lack of the flag doesn't mean that the driver can't
> > > resume at all.
> > 
> > Yes, with this patch series we are able to resume from previous position.
> 
> I suppose you tested hibernation, too?

No, only suspend and freeze

> How does it assure that the in-flight data on FIFO are restored after
> the link reset and re-prepare?

SKL has DMA resume capability, so we can restore the registers, Jeeja is
preparing those patches and we should be able to send those shortly :)

> > Here is my test:
> > 
> > # aplay -Dhw:0,0 play.wav
> > Playing WAVE 'play.wav' : Signed 16 bit Little Endian, Rate 48000 Hz,
> > Stereo
> > Suspended. Trying resume. Done.
> 
> As mentioned, the resume usually works (sort of), even without
> SNDRV_PCM_INFO_RESUME bit.  It's because alsa-lib tries to re-prepare
> the stuff by itself.
> 
> Did you try only the patch 2 without this patch?

Yes Jeeja did that and in that case it does prepare and resumes

-- 
~Vinod

Re: [PATCH 1/7] ASoC: Intel: Skylake: Add Resume capability in PCM info.

[Takashi Iwai]

On Thu, 26 Nov 2015 09:56:01 +0100,
Vinod Koul wrote:
> 
> On Tue, Nov 24, 2015 at 07:07:11AM +0100, Takashi Iwai wrote:
> > On Tue, 24 Nov 2015 03:44:49 +0100,
> > Vinod Koul wrote:
> > > 
> > > On Mon, Nov 23, 2015 at 07:45:20PM +0100, Takashi Iwai wrote:
> > > > On Mon, 23 Nov 2015 17:56:23 +0100,
> > > > Vinod Koul wrote:
> > > > > 
> > > > > From: Jeeja KP <jeeja.kp@intel.com>
> > > > > 
> > > > > This patch adds pcm capability to support Resume.
> > > > 
> > > > The flag indicates that the driver is capable of the full resume --
> > > > i.e. it must resume everything at the exactly same point to be
> > > > suspended.  Is it really the case?
> > > > 
> > > > If it's not and it's instead a kind of restart of streams, don't add
> > > > this flag.  The lack of the flag doesn't mean that the driver can't
> > > > resume at all.
> > > 
> > > Yes, with this patch series we are able to resume from previous position.
> > 
> > I suppose you tested hibernation, too?
> 
> No, only suspend and freeze
> 
> > How does it assure that the in-flight data on FIFO are restored after
> > the link reset and re-prepare?
> 
> SKL has DMA resume capability, so we can restore the registers, Jeeja is
> preparing those patches and we should be able to send those shortly :)

Well, the question is about hibernation.  Then the in-flight data on
the device is basically gone, and we can handle only the remaining CPU
data.  If your DMA can do that, it's fine, we can go in that way.

> > > Here is my test:
> > > 
> > > # aplay -Dhw:0,0 play.wav
> > > Playing WAVE 'play.wav' : Signed 16 bit Little Endian, Rate 48000 Hz,
> > > Stereo
> > > Suspended. Trying resume. Done.
> > 
> > As mentioned, the resume usually works (sort of), even without
> > SNDRV_PCM_INFO_RESUME bit.  It's because alsa-lib tries to re-prepare
> > the stuff by itself.
> > 
> > Did you try only the patch 2 without this patch?
> 
> Yes Jeeja did that and in that case it does prepare and resumes

That's the expected result.  As a fallback, user-space expects
prepares and restarts.


Takashi

Applied "ASoC: Intel: Skylake: Add Resume capability in PCM info." to the asoc tree

[Mark Brown]

The patch

   ASoC: Intel: Skylake: Add Resume capability in PCM info.

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 3637976b8975afb0a55a1fc88a2c320a2839a9da Mon Sep 17 00:00:00 2001
From: Jeeja KP <jeeja.kp@intel.com>
Date: Fri, 18 Dec 2015 15:12:09 +0530
Subject: [PATCH] ASoC: Intel: Skylake: Add Resume capability in PCM info.

This patch adds pcm capability to support Resume.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/intel/skylake/skl-pcm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/soc/intel/skylake/skl-pcm.c b/sound/soc/intel/skylake/skl-pcm.c
index 17a64362b283..f3553258091a 100644
--- a/sound/soc/intel/skylake/skl-pcm.c
+++ b/sound/soc/intel/skylake/skl-pcm.c
@@ -38,6 +38,7 @@ static struct snd_pcm_hardware azx_pcm_hw = {
 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
 				 SNDRV_PCM_INFO_MMAP_VALID |
 				 SNDRV_PCM_INFO_PAUSE |
+				 SNDRV_PCM_INFO_RESUME |
 				 SNDRV_PCM_INFO_SYNC_START |
 				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
 				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
-- 
2.7.0.rc3