* [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
@ 2018-09-13 21:55 Marty E. Plummer
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
` (4 more replies)
0 siblings, 5 replies; 19+ messages in thread
From: Marty E. Plummer @ 2018-09-13 21:55 UTC (permalink / raw)
To: u-boot
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
board/google/veyron/Kconfig | 16 ++
configs/chromebook_speedy_defconfig | 98 ++++++++++++
7 files changed, 302 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
create mode 100644 configs/chromebook_speedy_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 44ebc50bfa..eab90216f0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+ rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3368-lion.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
new file mode 100644
index 0000000000..22ba3490f2
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2015 Google, Inc
+ */
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x1>;
+ rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts
new file mode 100644
index 0000000000..20100bbdee
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron Speedy Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+#include "rk3288-veyron-speedy-u-boot.dtsi"
+
+/ {
+ model = "Google Speedy";
+ compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+ "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+ "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+ "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+ "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+ panel_regulator: panel-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+};
+
+&backlight {
+ power-supply = <&backlight_regulator>;
+};
+
+&cpu_alert0 {
+ temperature = <65000>;
+};
+
+&cpu_alert1 {
+ temperature = <70000>;
+};
+
+&edp {
+ /delete-property/pinctrl-names;
+ /delete-property/pinctrl-0;
+
+ force-hpd;
+};
+
+&panel {
+ power-supply= <&panel_regulator>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+};
+
+&sdmmc {
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ &sdmmc_bus4>;
+};
+
+&vcc_5v {
+ enable-active-high;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&drv_5v>;
+};
+
+&vcc50_hdmi {
+ enable-active-high;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc50_hdmi_en>;
+};
+
+&pinctrl {
+ backlight {
+ bl_pwr_en: bl_pwr_en {
+ rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buck-5v {
+ drv_5v: drv-5v {
+ rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ vcc50_hdmi_en: vcc50-hdmi-en {
+ rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_enable_h: lcd-en {
+ rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ avdd_1v8_disp_en: avdd-1v8-disp-en {
+ rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dvs_1: dvs-1 {
+ rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index abd62e520f..236cb932ba 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -71,7 +71,8 @@ u32 spl_boot_device(void)
fallback:
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
- defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
+ defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_MMC1;
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index b5447e5b65..bce8023881 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE
functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
internal MMC. The product name is ASUS Chromebook Flip.
+config TARGET_CHROMEBOOK_SPEEDY
+ bool "Google/Rockchip Veyron-Speedy Chromebook"
+ select BOARD_LATE_INIT
+ help
+ Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
+ micro HDMI, an 11.6 inch display, micro-SD card,
+ HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
+ EC (Cortex-M3) to provide access to the keyboard and battery
+ functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
+ The product name is Asus Chromebook C201PA.
+
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select BOARD_LATE_INIT
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
index 770e9aad28..7f55d78dac 100644
--- a/board/google/veyron/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
+
+if TARGET_CHROMEBOOK_SPEEDY
+
+config SYS_BOARD
+ default "veyron"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
new file mode 100644
index 0000000000..77b25eafab
--- /dev/null
+++ b/configs/chromebook_speedy_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SILENT_CONSOLE=y
+CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_ROCKCHIP_RK3288=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK8XX=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_SPL_OF_LIBFDT is not set
--
2.18.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
@ 2018-09-13 21:55 ` Marty E. Plummer
2018-09-14 10:55 ` Simon Glass
` (3 more replies)
2018-09-14 10:55 ` [U-Boot] [PATCH v2 1/2] " Simon Glass
` (3 subsequent siblings)
4 siblings, 4 replies; 19+ messages in thread
From: Marty E. Plummer @ 2018-09-13 21:55 UTC (permalink / raw)
To: u-boot
Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
Without this change, my u-boot build for the asus c201 chromebook (4GiB)
is incorrectly detected as 0 Bytes of ram.
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
arch/arm/mach-rockchip/sdram_common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
index 650d53e4d9..194dc74b9f 100644
--- a/arch/arm/mach-rockchip/sdram_common.c
+++ b/arch/arm/mach-rockchip/sdram_common.c
@@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
rank, col, bk, cs0_row, bw, row_3_4);
}
+ size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
+
return (size_t)size_mb << 20;
}
--
2.18.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
@ 2018-09-14 10:55 ` Simon Glass
2018-09-14 18:33 ` Marty E. Plummer
2018-11-13 19:58 ` [U-Boot] [U-Boot, v2, " Vagrant Cascadian
` (2 subsequent siblings)
4 siblings, 1 reply; 19+ messages in thread
From: Simon Glass @ 2018-09-14 10:55 UTC (permalink / raw)
To: u-boot
On 13 September 2018 at 23:55, Marty E. Plummer <hanetzer@startmail.com> wrote:
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 98 ++++++++++++
> 7 files changed, 302 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
Reviewed-by: Simon Glass <sjg@chromium.org>
But aren't you missing a changelog?
- Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
@ 2018-09-14 10:55 ` Simon Glass
2018-09-14 18:33 ` Marty E. Plummer
2018-11-14 23:37 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
` (2 subsequent siblings)
3 siblings, 1 reply; 19+ messages in thread
From: Simon Glass @ 2018-09-14 10:55 UTC (permalink / raw)
To: u-boot
Hi Marty,
On 13 September 2018 at 23:55, Marty E. Plummer <hanetzer@startmail.com> wrote:
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/mach-rockchip/sdram_common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> index 650d53e4d9..194dc74b9f 100644
> --- a/arch/arm/mach-rockchip/sdram_common.c
> +++ b/arch/arm/mach-rockchip/sdram_common.c
> @@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> rank, col, bk, cs0_row, bw, row_3_4);
> }
>
> + size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
> +
Is this because size_mb is only 32-bits?
> return (size_t)size_mb << 20;
> }
>
> --
> 2.18.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size
2018-09-14 10:55 ` Simon Glass
@ 2018-09-14 18:33 ` Marty E. Plummer
0 siblings, 0 replies; 19+ messages in thread
From: Marty E. Plummer @ 2018-09-14 18:33 UTC (permalink / raw)
To: u-boot
On Fri, Sep 14, 2018 at 12:55:19PM +0200, Simon Glass wrote:
> Hi Marty,
>
>
> On 13 September 2018 at 23:55, Marty E. Plummer <hanetzer@startmail.com> wrote:
> > Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
> >
> > Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> > is incorrectly detected as 0 Bytes of ram.
> >
> > Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> > ---
> > arch/arm/mach-rockchip/sdram_common.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> > index 650d53e4d9..194dc74b9f 100644
> > --- a/arch/arm/mach-rockchip/sdram_common.c
> > +++ b/arch/arm/mach-rockchip/sdram_common.c
> > @@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> > rank, col, bk, cs0_row, bw, row_3_4);
> > }
> >
> > + size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
> > +
>
> Is this because size_mb is only 32-bits?
>
Yeah. This has been discussed a bit before on the ml. 0x1_0000_0000 for
4GiB, and due to memory mapped peripherals it can only address
0xff00_0000 bytes anyways so clamp it down. Code is lifted from
coreboot's init code.
> > return (size_t)size_mb << 20;
> > }
> >
> > --
> > 2.18.0
> >
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-09-14 10:55 ` [U-Boot] [PATCH v2 1/2] " Simon Glass
@ 2018-09-14 18:33 ` Marty E. Plummer
0 siblings, 0 replies; 19+ messages in thread
From: Marty E. Plummer @ 2018-09-14 18:33 UTC (permalink / raw)
To: u-boot
On Fri, Sep 14, 2018 at 12:55:16PM +0200, Simon Glass wrote:
> On 13 September 2018 at 23:55, Marty E. Plummer <hanetzer@startmail.com> wrote:
> > This adds support for the ASUS C201, a RK3288-based clamshell
> > device. The device tree comes from linus's linux tree at
> > 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> > are for 4GB Samsung LPDDR3, decoded from coreboot's
> > src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> >
> > Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> > ---
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> > arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> > arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> > arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> > board/google/veyron/Kconfig | 16 ++
> > configs/chromebook_speedy_defconfig | 98 ++++++++++++
> > 7 files changed, 302 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> > create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> > create mode 100644 configs/chromebook_speedy_defconfig
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> But aren't you missing a changelog?
>
I don't follow.
> - Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
2018-09-14 10:55 ` [U-Boot] [PATCH v2 1/2] " Simon Glass
@ 2018-11-13 19:58 ` Vagrant Cascadian
2018-11-13 21:35 ` Simon Glass
2018-11-14 23:37 ` Philipp Tomsich
2018-11-30 21:05 ` Philipp Tomsich
4 siblings, 1 reply; 19+ messages in thread
From: Vagrant Cascadian @ 2018-11-13 19:58 UTC (permalink / raw)
To: u-boot
On 2018-09-13, Marty E. Plummer wrote:
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Any outstanding blockers on getting this patch series merged?
live well,
vagrant
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 98 ++++++++++++
> 7 files changed, 302 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 44ebc50bfa..eab90216f0 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
> rk3288-veyron-jerry.dtb \
> rk3288-veyron-mickey.dtb \
> rk3288-veyron-minnie.dtb \
> + rk3288-veyron-speedy.dtb \
> rk3288-vyasa.dtb \
> rk3328-evb.dtb \
> rk3368-lion.dtb \
> diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> new file mode 100644
> index 0000000000..22ba3490f2
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2015 Google, Inc
> + */
> +
> +&dmc {
> + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
> + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
> + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
> + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
> + 0x8 0x1f4>;
> + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
> + 0x0 0xc3 0x6 0x1>;
> + rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
> +};
> +
> +&sdmmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&emmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&uart2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&pinctrl {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts
> new file mode 100644
> index 0000000000..20100bbdee
> --- /dev/null
> +++ b/arch/arm/dts/rk3288-veyron-speedy.dts
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Google Veyron Speedy Rev 1+ board device tree source
> + *
> + * Copyright 2015 Google, Inc
> + */
> +
> +/dts-v1/;
> +#include "rk3288-veyron-chromebook.dtsi"
> +#include "cros-ec-sbs.dtsi"
> +#include "rk3288-veyron-speedy-u-boot.dtsi"
> +
> +/ {
> + model = "Google Speedy";
> + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
> + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
> + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
> + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
> + "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
> +
> + panel_regulator: panel-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&lcd_enable_h>;
> + regulator-name = "panel_regulator";
> + startup-delay-us = <100000>;
> + vin-supply = <&vcc33_sys>;
> + };
> +
> + vcc18_lcd: vcc18-lcd {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&avdd_1v8_disp_en>;
> + regulator-name = "vcc18_lcd";
> + regulator-always-on;
> + regulator-boot-on;
> + vin-supply = <&vcc18_wl>;
> + };
> +
> + backlight_regulator: backlight-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bl_pwr_en>;
> + regulator-name = "backlight_regulator";
> + vin-supply = <&vcc33_sys>;
> + startup-delay-us = <15000>;
> + };
> +};
> +
> +&backlight {
> + power-supply = <&backlight_regulator>;
> +};
> +
> +&cpu_alert0 {
> + temperature = <65000>;
> +};
> +
> +&cpu_alert1 {
> + temperature = <70000>;
> +};
> +
> +&edp {
> + /delete-property/pinctrl-names;
> + /delete-property/pinctrl-0;
> +
> + force-hpd;
> +};
> +
> +&panel {
> + power-supply= <&panel_regulator>;
> +};
> +
> +&rk808 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int_l>;
> +};
> +
> +&sdmmc {
> + disable-wp;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
> + &sdmmc_bus4>;
> +};
> +
> +&vcc_5v {
> + enable-active-high;
> + gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&drv_5v>;
> +};
> +
> +&vcc50_hdmi {
> + enable-active-high;
> + gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc50_hdmi_en>;
> +};
> +
> +&pinctrl {
> + backlight {
> + bl_pwr_en: bl_pwr_en {
> + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + buck-5v {
> + drv_5v: drv-5v {
> + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + hdmi {
> + vcc50_hdmi_en: vcc50-hdmi-en {
> + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + lcd {
> + lcd_enable_h: lcd-en {
> + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + avdd_1v8_disp_en: avdd-1v8-disp-en {
> + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pmic {
> + dvs_1: dvs-1 {
> + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> +
> + dvs_2: dvs-2 {
> + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> + };
> +};
> diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
> index abd62e520f..236cb932ba 100644
> --- a/arch/arm/mach-rockchip/rk3288-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
> @@ -71,7 +71,8 @@ u32 spl_boot_device(void)
> fallback:
> #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
> defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
> - defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
> + defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
> + defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
> return BOOT_DEVICE_SPI;
> #endif
> return BOOT_DEVICE_MMC1;
> diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
> index b5447e5b65..bce8023881 100644
> --- a/arch/arm/mach-rockchip/rk3288/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3288/Kconfig
> @@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE
> functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
> internal MMC. The product name is ASUS Chromebook Flip.
>
> +config TARGET_CHROMEBOOK_SPEEDY
> + bool "Google/Rockchip Veyron-Speedy Chromebook"
> + select BOARD_LATE_INIT
> + help
> + Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
> + micro HDMI, an 11.6 inch display, micro-SD card,
> + HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
> + EC (Cortex-M3) to provide access to the keyboard and battery
> + functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
> + The product name is Asus Chromebook C201PA.
> +
> config TARGET_EVB_RK3288
> bool "Evb-RK3288"
> select BOARD_LATE_INIT
> diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
> index 770e9aad28..7f55d78dac 100644
> --- a/board/google/veyron/Kconfig
> +++ b/board/google/veyron/Kconfig
> @@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> def_bool y
>
> endif
> +
> +if TARGET_CHROMEBOOK_SPEEDY
> +
> +config SYS_BOARD
> + default "veyron"
> +
> +config SYS_VENDOR
> + default "google"
> +
> +config SYS_CONFIG_NAME
> + default "veyron"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> + def_bool y
> +
> +endif
> diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
> new file mode 100644
> index 0000000000..77b25eafab
> --- /dev/null
> +++ b/configs/chromebook_speedy_defconfig
> @@ -0,0 +1,98 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00100000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_ROCKCHIP_RK3288=y
> +# CONFIG_SPL_MMC_SUPPORT is not set
> +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
> +CONFIG_DEBUG_UART_BASE=0xff690000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SPL_STACK_R_ADDR=0x80000
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
> +CONFIG_DEBUG_UART=y
> +CONFIG_NR_DRAM_BANKS=1
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_SILENT_CONSOLE=y
> +CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_BOARD_EARLY_INIT_F=y
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
> +CONFIG_SPL_SPI_LOAD=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SF_TEST=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_SPL_EFI_PARTITION is not set
> +CONFIG_SPL_PARTITION_UUIDS=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SPL_OF_PLATDATA=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +# CONFIG_SPL_SIMPLE_BUS is not set
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_FLASH=y
> +CONFIG_FASTBOOT_FLASH_MMC_DEV=0
> +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_I2C_CROS_EC_TUNNEL=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_I2C_MUX=y
> +CONFIG_DM_KEYBOARD=y
> +CONFIG_CROS_EC_KEYB=y
> +CONFIG_CROS_EC=y
> +CONFIG_CROS_EC_SPI=y
> +CONFIG_PWRSEQ=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +# CONFIG_SPL_PINCTRL_FULL is not set
> +CONFIG_PINCTRL_ROCKCHIP_RK3288=y
> +CONFIG_DM_PMIC=y
> +# CONFIG_SPL_PMIC_CHILDREN is not set
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_ROCKCHIP_SERIAL=y
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_ROCKCHIP_USB2_PHY=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
> +CONFIG_USB_GADGET_VENDOR_NUM=0x2207
> +CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_USB_FUNCTION_MASS_STORAGE=y
> +CONFIG_DM_VIDEO=y
> +CONFIG_DISPLAY=y
> +CONFIG_VIDEO_ROCKCHIP=y
> +CONFIG_DISPLAY_ROCKCHIP_EDP=y
> +CONFIG_DISPLAY_ROCKCHIP_HDMI=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_CMD_DHRYSTONE=y
> +CONFIG_ERRNO_STR=y
> +# CONFIG_SPL_OF_LIBFDT is not set
-------------- next part --------------
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-11-13 19:58 ` [U-Boot] [U-Boot, v2, " Vagrant Cascadian
@ 2018-11-13 21:35 ` Simon Glass
2018-11-24 15:01 ` Marty E. Plummer
0 siblings, 1 reply; 19+ messages in thread
From: Simon Glass @ 2018-11-13 21:35 UTC (permalink / raw)
To: u-boot
Hi,
On 13 November 2018 at 11:58, Vagrant Cascadian <vagrant@debian.org> wrote:
> On 2018-09-13, Marty E. Plummer wrote:
>> This adds support for the ASUS C201, a RK3288-based clamshell
>> device. The device tree comes from linus's linux tree at
>> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
>> are for 4GB Samsung LPDDR3, decoded from coreboot's
>> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Any outstanding blockers on getting this patch series merged?
Not that I know of.
The version history should be included with v2 patch so we know what
changes were made from v1.
Regards,
Simon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
` (2 preceding siblings ...)
2018-11-13 19:58 ` [U-Boot] [U-Boot, v2, " Vagrant Cascadian
@ 2018-11-14 23:37 ` Philipp Tomsich
2018-11-30 21:05 ` Philipp Tomsich
4 siblings, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-14 23:37 UTC (permalink / raw)
To: u-boot
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 98 ++++++++++++
> 7 files changed, 302 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 2/2] rockchip: fix incorrect detection of ram size
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
2018-09-14 10:55 ` Simon Glass
@ 2018-11-14 23:37 ` Philipp Tomsich
2018-11-15 14:05 ` [U-Boot] [PATCH v2 " Philipp Tomsich
2018-11-30 21:05 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
3 siblings, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-14 23:37 UTC (permalink / raw)
To: u-boot
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/mach-rockchip/sdram_common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
2018-09-14 10:55 ` Simon Glass
2018-11-14 23:37 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2018-11-15 14:05 ` Philipp Tomsich
2018-11-30 21:05 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
3 siblings, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-15 14:05 UTC (permalink / raw)
To: u-boot
Marty,
> On 13.09.2018, at 23:55, Marty E. Plummer <hanetzer@startmail.com> wrote:
>
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Please revise.
See below.
> ---
> arch/arm/mach-rockchip/sdram_common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c
> index 650d53e4d9..194dc74b9f 100644
> --- a/arch/arm/mach-rockchip/sdram_common.c
> +++ b/arch/arm/mach-rockchip/sdram_common.c
> @@ -48,6 +48,8 @@ size_t rockchip_sdram_size(phys_addr_t reg)
> rank, col, bk, cs0_row, bw, row_3_4);
> }
>
> + size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
> +
aarch64: + evb-rk3399 firefly-rk3399 geekbox evb-px5 sheep-rk3368 lion-rk3368 evb-rk3328 puma-rk3399
+In file included from include/linux/delay.h:6:0,
+ from include/common.h:26,
+ from arch/arm/mach-rockchip/sdram_common.c:6:
+arch/arm/mach-rockchip/sdram_common.c: In function 'rockchip_sdram_size':
+include/linux/kernel.h:161:17: error: comparison of distinct pointer types lacks a cast [-Werror]
+ (void) (&_min1 == &_min2); \
+ ^
+arch/arm/mach-rockchip/sdram_common.c:51:12: note: in expansion of macro 'min'
+ size_mb = min(size_mb, SDRAM_MAX_SIZE/SZ_1M);
+ ^~~
+cc1: all warnings being treated as errors
> return (size_t)size_mb << 20;
> }
>
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-11-13 21:35 ` Simon Glass
@ 2018-11-24 15:01 ` Marty E. Plummer
0 siblings, 0 replies; 19+ messages in thread
From: Marty E. Plummer @ 2018-11-24 15:01 UTC (permalink / raw)
To: u-boot
On Tue, Nov 13, 2018 at 01:35:48PM -0800, Simon Glass wrote:
> Hi,
>
> On 13 November 2018 at 11:58, Vagrant Cascadian <vagrant@debian.org> wrote:
> > On 2018-09-13, Marty E. Plummer wrote:
> >> This adds support for the ASUS C201, a RK3288-based clamshell
> >> device. The device tree comes from linus's linux tree at
> >> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> >> are for 4GB Samsung LPDDR3, decoded from coreboot's
> >> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
> >
> > Any outstanding blockers on getting this patch series merged?
>
> Not that I know of.
>
> The version history should be included with v2 patch so we know what
> changes were made from v1.
>
So, resend the series with changes from v1 to v2? As v2 again? Just
wanna be sure.
Regards,
Marty
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
` (3 preceding siblings ...)
2018-11-14 23:37 ` Philipp Tomsich
@ 2018-11-30 21:05 ` Philipp Tomsich
4 siblings, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-30 21:05 UTC (permalink / raw)
To: u-boot
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 98 ++++++++++++
> 7 files changed, 302 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 2/2] rockchip: fix incorrect detection of ram size
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
` (2 preceding siblings ...)
2018-11-15 14:05 ` [U-Boot] [PATCH v2 " Philipp Tomsich
@ 2018-11-30 21:05 ` Philipp Tomsich
2018-11-30 21:08 ` Philipp Tomsich
3 siblings, 1 reply; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-30 21:05 UTC (permalink / raw)
To: u-boot
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> arch/arm/mach-rockchip/sdram_common.c | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 2/2] rockchip: fix incorrect detection of ram size
2018-11-30 21:05 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
@ 2018-11-30 21:08 ` Philipp Tomsich
2019-01-06 0:55 ` Marty E. Plummer
2019-01-06 2:12 ` [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
0 siblings, 2 replies; 19+ messages in thread
From: Philipp Tomsich @ 2018-11-30 21:08 UTC (permalink / raw)
To: u-boot
Marty,
> On 30.11.2018, at 22:05, Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
>
>> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>>
>> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
>> is incorrectly detected as 0 Bytes of ram.
>>
>> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
>> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>> arch/arm/mach-rockchip/sdram_common.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>
> Applied to u-boot-rockchip, thanks!
Oops. I just had to pull this series out of the tree again...
Didn’t realise that it hadn’t been revised, so it triggered the same build error again.
When can you get an updated patch for me?
Thanks,
Philipp.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v2, 2/2] rockchip: fix incorrect detection of ram size
2018-11-30 21:08 ` Philipp Tomsich
@ 2019-01-06 0:55 ` Marty E. Plummer
2019-01-06 2:12 ` [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
1 sibling, 0 replies; 19+ messages in thread
From: Marty E. Plummer @ 2019-01-06 0:55 UTC (permalink / raw)
To: u-boot
On Fri, Nov 30, 2018 at 10:08:07PM +0100, Philipp Tomsich wrote:
> Marty,
>
> > On 30.11.2018, at 22:05, Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
> >
> >> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
> >>
> >> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> >> is incorrectly detected as 0 Bytes of ram.
> >>
> >> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> >> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> >> ---
> >> arch/arm/mach-rockchip/sdram_common.c | 2 ++
> >> 1 file changed, 2 insertions(+)
> >>
> >
> > Applied to u-boot-rockchip, thanks!
>
> Oops. I just had to pull this series out of the tree again...
> Didn’t realise that it hadn’t been revised, so it triggered the same build error again.
>
Sorry, I've been a bit busy (work and school; this is a hobby until I
can turn it/something similar into a real job). I've attempted to build
the defconfig but it fails out some fdt issue I can't quite solve atm.
I'd leave it alone for now, I'm going to try fixing the issue. I may
need some help.
> When can you get an updated patch for me?
>
As soon as I can figure out fixing 'normal' builds (without my patch)
for rk3399 I'll figure what I can do for the ram size clamp. I could
ifdef it around aarch64 or something, but that seems hacky(?), thoughts?
> Thanks,
> Philipp.
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2018-11-30 21:08 ` Philipp Tomsich
2019-01-06 0:55 ` Marty E. Plummer
@ 2019-01-06 2:12 ` Marty E. Plummer
2019-01-31 10:15 ` [U-Boot] [U-Boot, " Philipp Tomsich
2019-01-31 21:12 ` Philipp Tomsich
1 sibling, 2 replies; 19+ messages in thread
From: Marty E. Plummer @ 2019-01-06 2:12 UTC (permalink / raw)
To: u-boot
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
v2: drop sf: Add GigaDevice gd25q32b entry: subsumed by commit
b1f2b72e39465f2d4582bb4d8c426489ee94e2d9
split out rk3288-veyron-speedy-u-boot.dtsi
drop useless if (!size_mb)
apply changes from chromebook_jerry_defconfig
v3: drop rockchip: fix incorrect detection of ram size: subsumed by commit
3119ecc4accceb99cf931683567cc26148b7f99c
sort defconfig option to match changes in chromebook_jerry_defconfig
enable CONSOLE_TRUETYPE
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
board/google/veyron/Kconfig | 16 ++
configs/chromebook_speedy_defconfig | 100 ++++++++++++
7 files changed, 304 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
create mode 100644 configs/chromebook_speedy_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dda4e59491..5bddf824cd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-jerry.dtb \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
+ rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb \
rk3328-evb.dtb \
rk3399-ficus.dtb \
diff --git a/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
new file mode 100644
index 0000000000..22ba3490f2
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2015 Google, Inc
+ */
+
+&dmc {
+ rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
+ 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
+ 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
+ 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
+ 0x8 0x1f4>;
+ rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
+ 0x0 0xc3 0x6 0x1>;
+ rockchip,sdram-params = <0x20D266A4 0x5B6 6 533000000 6 13 0>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts b/arch/arm/dts/rk3288-veyron-speedy.dts
new file mode 100644
index 0000000000..58c1fe96ee
--- /dev/null
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Veyron Speedy Rev 1+ board device tree source
+ *
+ * Copyright 2015 Google, Inc
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+#include "rk3288-veyron-speedy-u-boot.dtsi"
+
+/ {
+ model = "Google Speedy";
+ compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+ "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+ "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+ "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+ "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+ panel_regulator: panel-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ startup-delay-us = <100000>;
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+};
+
+&backlight {
+ power-supply = <&backlight_regulator>;
+};
+
+&cpu_alert0 {
+ temperature = <65000>;
+};
+
+&cpu_alert1 {
+ temperature = <70000>;
+};
+
+&edp {
+ /delete-property/pinctrl-names;
+ /delete-property/pinctrl-0;
+
+ force-hpd;
+};
+
+&panel {
+ power-supply = <&panel_regulator>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+};
+
+&sdmmc {
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
+ &sdmmc_bus4>;
+};
+
+&vcc_5v {
+ enable-active-high;
+ gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&drv_5v>;
+};
+
+&vcc50_hdmi {
+ enable-active-high;
+ gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc50_hdmi_en>;
+};
+
+&pinctrl {
+ backlight {
+ bl_pwr_en: bl_pwr_en {
+ rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ buck-5v {
+ drv_5v: drv-5v {
+ rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ vcc50_hdmi_en: vcc50-hdmi-en {
+ rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ lcd {
+ lcd_enable_h: lcd-en {
+ rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ avdd_1v8_disp_en: avdd-1v8-disp-en {
+ rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ dvs_1: dvs-1 {
+ rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ dvs_2: dvs-2 {
+ rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index abd62e520f..236cb932ba 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -71,7 +71,8 @@ u32 spl_boot_device(void)
fallback:
#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
- defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
+ defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
+ defined(CONFIG_TARGET_CHROMEBOOK_SPEEDY)
return BOOT_DEVICE_SPI;
#endif
return BOOT_DEVICE_MMC1;
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index b5447e5b65..bce8023881 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -30,6 +30,17 @@ config TARGET_CHROMEBOOK_MINNIE
functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
internal MMC. The product name is ASUS Chromebook Flip.
+config TARGET_CHROMEBOOK_SPEEDY
+ bool "Google/Rockchip Veyron-Speedy Chromebook"
+ select BOARD_LATE_INIT
+ help
+ Speedy is a RK3288-based clamshell device with 2 USB 2.0 ports,
+ micro HDMI, an 11.6 inch display, micro-SD card,
+ HD camera, touchpad, wifi and Bluetooth. It includes a Chrome OS
+ EC (Cortex-M3) to provide access to the keyboard and battery
+ functions. It includes 2 or 4GB of SDRAM and 16GB of internal MMC.
+ The product name is Asus Chromebook C201PA.
+
config TARGET_EVB_RK3288
bool "Evb-RK3288"
select BOARD_LATE_INIT
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
index 770e9aad28..7f55d78dac 100644
--- a/board/google/veyron/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -45,3 +45,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
+
+if TARGET_CHROMEBOOK_SPEEDY
+
+config SYS_BOARD
+ default "veyron"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_CONFIG_NAME
+ default "veyron"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
new file mode 100644
index 0000000000..f1c5ed7293
--- /dev/null
+++ b/configs/chromebook_speedy_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00100000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3288=y
+# CONFIG_SPL_MMC_SUPPORT is not set
+CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
+CONFIG_DEBUG_UART_BASE=0xff690000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_NR_DRAM_BANKS=1
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_SILENT_CONSOLE=y
+CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_OF_PLATDATA=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SPL_SIMPLE_BUS is not set
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_CROS_EC_KEYB=y
+CONFIG_CROS_EC=y
+CONFIG_CROS_EC_SPI=y
+CONFIG_PWRSEQ=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_PINCTRL_ROCKCHIP_RK3288=y
+CONFIG_DM_PMIC=y
+# CONFIG_SPL_PMIC_CHILDREN is not set
+CONFIG_PMIC_RK8XX=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SERIAL=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_CONSOLE_TRUETYPE=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_EDP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+# CONFIG_USE_PRIVATE_LIBGCC is not set
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_DHRYSTONE=y
+CONFIG_ERRNO_STR=y
+# CONFIG_SPL_OF_LIBFDT is not set
--
2.20.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2019-01-06 2:12 ` [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
@ 2019-01-31 10:15 ` Philipp Tomsich
2019-01-31 21:12 ` Philipp Tomsich
1 sibling, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2019-01-31 10:15 UTC (permalink / raw)
To: u-boot
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> v2: drop sf: Add GigaDevice gd25q32b entry: subsumed by commit
> b1f2b72e39465f2d4582bb4d8c426489ee94e2d9
> split out rk3288-veyron-speedy-u-boot.dtsi
> drop useless if (!size_mb)
> apply changes from chromebook_jerry_defconfig
> v3: drop rockchip: fix incorrect detection of ram size: subsumed by commit
> 3119ecc4accceb99cf931683567cc26148b7f99c
> sort defconfig option to match changes in chromebook_jerry_defconfig
> enable CONSOLE_TRUETYPE
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 100 ++++++++++++
> 7 files changed, 304 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [U-Boot, v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201)
2019-01-06 2:12 ` [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
2019-01-31 10:15 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2019-01-31 21:12 ` Philipp Tomsich
1 sibling, 0 replies; 19+ messages in thread
From: Philipp Tomsich @ 2019-01-31 21:12 UTC (permalink / raw)
To: u-boot
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 3f16503b7d2274ac8cbab11163047ac0b4c66cfe. The SDRAM parameters
> are for 4GB Samsung LPDDR3, decoded from coreboot's
> src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB.inc
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> v2: drop sf: Add GigaDevice gd25q32b entry: subsumed by commit
> b1f2b72e39465f2d4582bb4d8c426489ee94e2d9
> split out rk3288-veyron-speedy-u-boot.dtsi
> drop useless if (!size_mb)
> apply changes from chromebook_jerry_defconfig
> v3: drop rockchip: fix incorrect detection of ram size: subsumed by commit
> 3119ecc4accceb99cf931683567cc26148b7f99c
> sort defconfig option to match changes in chromebook_jerry_defconfig
> enable CONSOLE_TRUETYPE
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi | 31 ++++
> arch/arm/dts/rk3288-veyron-speedy.dts | 143 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3288-board-spl.c | 3 +-
> arch/arm/mach-rockchip/rk3288/Kconfig | 11 ++
> board/google/veyron/Kconfig | 16 ++
> configs/chromebook_speedy_defconfig | 100 ++++++++++++
> 7 files changed, 304 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3288-veyron-speedy.dts
> create mode 100644 configs/chromebook_speedy_defconfig
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2019-01-31 21:12 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-13 21:55 [U-Boot] [PATCH v2 1/2] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
2018-09-13 21:55 ` [U-Boot] [PATCH v2 2/2] rockchip: fix incorrect detection of ram size Marty E. Plummer
2018-09-14 10:55 ` Simon Glass
2018-09-14 18:33 ` Marty E. Plummer
2018-11-14 23:37 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2018-11-15 14:05 ` [U-Boot] [PATCH v2 " Philipp Tomsich
2018-11-30 21:05 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2018-11-30 21:08 ` Philipp Tomsich
2019-01-06 0:55 ` Marty E. Plummer
2019-01-06 2:12 ` [U-Boot] [PATCH v3] rockchip: add support for veyron-speedy (ASUS Chromebook C201) Marty E. Plummer
2019-01-31 10:15 ` [U-Boot] [U-Boot, " Philipp Tomsich
2019-01-31 21:12 ` Philipp Tomsich
2018-09-14 10:55 ` [U-Boot] [PATCH v2 1/2] " Simon Glass
2018-09-14 18:33 ` Marty E. Plummer
2018-11-13 19:58 ` [U-Boot] [U-Boot, v2, " Vagrant Cascadian
2018-11-13 21:35 ` Simon Glass
2018-11-24 15:01 ` Marty E. Plummer
2018-11-14 23:37 ` Philipp Tomsich
2018-11-30 21:05 ` Philipp Tomsich
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