[PATCH 00/10] add support SATA for BMIPS_GENERIC

[PATCH 00/10] add support SATA for BMIPS_GENERIC

[Jaedon Shin]

Hi all,

This patch series adds support SATA for BMIPS_GENERIC.

Ralf,
I request you to drop already submitted patches for NAND device nodes.
It is merge conflicts with this patches.
http://patchwork.linux-mips.org/patch/10577/
http://patchwork.linux-mips.org/patch/10578/
http://patchwork.linux-mips.org/patch/10579/
http://patchwork.linux-mips.org/patch/10580/

Jaedon Shin (10):
  ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
  ata: ahch_brcmstb: add data for port offset
  ata: ahci_brcmstb: add support 40nm platforms
  phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC
  phy: phy_brcmstb_sata: remove unused definitions
  phy: phy_brcmstb_sata: add data for phy offset
  phy: phy_brcmstb_sata: add support 40nm platforms
  MIPS: BMIPS: brcmstb: add SATA nodes for bcm7346
  MIPS: BMIPS: brcmstb: add SATA nodes for bcm7360
  MIPS: BMIPS: brcmstb: add SATA nodes for bcm7362

 arch/mips/boot/dts/brcm/bcm7346.dtsi      | 40 +++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7360.dtsi      | 40 +++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm7362.dtsi      | 40 +++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97346dbsmb.dts |  8 +++++++
 arch/mips/boot/dts/brcm/bcm97360svmb.dts  |  8 +++++++
 arch/mips/boot/dts/brcm/bcm97362svmb.dts  |  8 +++++++
 drivers/ata/Kconfig                       |  2 +-
 drivers/ata/ahci_brcmstb.c                | 34 +++++++++++++++++++-------
 drivers/phy/Kconfig                       |  4 ++--
 drivers/phy/phy-brcmstb-sata.c            | 34 ++++++++++++++++++--------
 10 files changed, 196 insertions(+), 22 deletions(-)

-- 
2.6.2

[PATCH 01/10] ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC

[Jaedon Shin]

The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
SATA3.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/ata/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 15e40ee62a94..8f535a88a0c7 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM
 
 config AHCI_BRCMSTB
 	tristate "Broadcom STB AHCI SATA support"
-	depends on ARCH_BRCMSTB
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	help
 	  This option enables support for the AHCI SATA3 controller found on
 	  STB SoC's.
-- 
2.6.2

[PATCH 02/10] ata: ahch_brcmstb: add data for port offset

[Jaedon Shin]

Add data of device node for port offset.

Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/ata/ahci_brcmstb.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index 14b7305d2ba0..8cf6f7d4798f 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -72,6 +72,7 @@
 struct brcm_ahci_priv {
 	struct device *dev;
 	void __iomem *top_ctrl;
+	u32 port_offset;
 	u32 port_mask;
 };
 
@@ -110,7 +111,7 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 {
 	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
-				(port * SATA_TOP_CTRL_PHY_OFFS);
+				(port * priv->port_offset);
 	void __iomem *p;
 	u32 reg;
 
@@ -139,7 +140,7 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
 {
 	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
-				(port * SATA_TOP_CTRL_PHY_OFFS);
+				(port * priv->port_offset);
 	void __iomem *p;
 	u32 reg;
 
@@ -234,6 +235,13 @@ static int brcm_ahci_resume(struct device *dev)
 }
 #endif
 
+static const struct of_device_id ahci_of_match[] = {
+	{.compatible = "brcm,bcm7445-ahci",
+			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
+	{},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
 static struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
@@ -241,6 +249,7 @@ static struct scsi_host_template ahci_platform_sht = {
 static int brcm_ahci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	const struct of_device_id *of_id = NULL;
 	struct brcm_ahci_priv *priv;
 	struct ahci_host_priv *hpriv;
 	struct resource *res;
@@ -256,6 +265,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->top_ctrl))
 		return PTR_ERR(priv->top_ctrl);
 
+	of_id = of_match_node(ahci_of_match, dev->of_node);
+	if (!of_id)
+		return -EINVAL;
+
+	priv->port_offset = (u32)of_id->data;
+
 	brcm_sata_init(priv);
 
 	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
@@ -299,12 +314,6 @@ static int brcm_ahci_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id ahci_of_match[] = {
-	{.compatible = "brcm,bcm7445-ahci"},
-	{},
-};
-MODULE_DEVICE_TABLE(of, ahci_of_match);
-
 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
 
 static struct platform_driver brcm_ahci_driver = {
-- 
2.6.2

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[PATCH 02/10] ata: ahch_brcmstb: add data for port offset

[Jaedon Shin]

Add data of device node for port offset.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/ata/ahci_brcmstb.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index 14b7305d2ba0..8cf6f7d4798f 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -72,6 +72,7 @@
 struct brcm_ahci_priv {
 	struct device *dev;
 	void __iomem *top_ctrl;
+	u32 port_offset;
 	u32 port_mask;
 };
 
@@ -110,7 +111,7 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
 static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 {
 	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
-				(port * SATA_TOP_CTRL_PHY_OFFS);
+				(port * priv->port_offset);
 	void __iomem *p;
 	u32 reg;
 
@@ -139,7 +140,7 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
 static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
 {
 	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
-				(port * SATA_TOP_CTRL_PHY_OFFS);
+				(port * priv->port_offset);
 	void __iomem *p;
 	u32 reg;
 
@@ -234,6 +235,13 @@ static int brcm_ahci_resume(struct device *dev)
 }
 #endif
 
+static const struct of_device_id ahci_of_match[] = {
+	{.compatible = "brcm,bcm7445-ahci",
+			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
+	{},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
 static struct scsi_host_template ahci_platform_sht = {
 	AHCI_SHT(DRV_NAME),
 };
@@ -241,6 +249,7 @@ static struct scsi_host_template ahci_platform_sht = {
 static int brcm_ahci_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	const struct of_device_id *of_id = NULL;
 	struct brcm_ahci_priv *priv;
 	struct ahci_host_priv *hpriv;
 	struct resource *res;
@@ -256,6 +265,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->top_ctrl))
 		return PTR_ERR(priv->top_ctrl);
 
+	of_id = of_match_node(ahci_of_match, dev->of_node);
+	if (!of_id)
+		return -EINVAL;
+
+	priv->port_offset = (u32)of_id->data;
+
 	brcm_sata_init(priv);
 
 	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
@@ -299,12 +314,6 @@ static int brcm_ahci_remove(struct platform_device *pdev)
 	return 0;
 }
 
-static const struct of_device_id ahci_of_match[] = {
-	{.compatible = "brcm,bcm7445-ahci"},
-	{},
-};
-MODULE_DEVICE_TABLE(of, ahci_of_match);
-
 static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
 
 static struct platform_driver brcm_ahci_driver = {
-- 
2.6.2

[PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Jaedon Shin]

Add offsets for 40nm BMIPS based set-top box platforms.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/ata/ahci_brcmstb.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
index 8cf6f7d4798f..59eb526cf4f6 100644
--- a/drivers/ata/ahci_brcmstb.c
+++ b/drivers/ata/ahci_brcmstb.c
@@ -50,7 +50,8 @@
   #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
   #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
- #define SATA_TOP_CTRL_PHY_OFFS				0x8
+ #define SATA_TOP_CTRL_28NM_PHY_OFFS			0x8
+ #define SATA_TOP_CTRL_40NM_PHY_OFFS			0x4
  #define SATA_TOP_MAX_PHYS				2
 #define SATA_TOP_CTRL_SATA_TP_OUT			0x1c
 #define SATA_TOP_CTRL_CLIENT_INIT_CTRL			0x20
@@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
 
 static const struct of_device_id ahci_of_match[] = {
 	{.compatible = "brcm,bcm7445-ahci",
-			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
+			.data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
+	{.compatible = "brcm,bcm7346-ahci",
+			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
+	{.compatible = "brcm,bcm7360-ahci",
+			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
+	{.compatible = "brcm,bcm7362-ahci",
+			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
 	{},
 };
 MODULE_DEVICE_TABLE(of, ahci_of_match);
-- 
2.6.2

[PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Jaedon Shin]

The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
SATA3 PHY.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 47da573d0bab..c83e48661fd7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -364,11 +364,11 @@ config PHY_TUSB1210
 
 config PHY_BRCMSTB_SATA
 	tristate "Broadcom STB SATA PHY driver"
-	depends on ARCH_BRCMSTB
+	depends on ARCH_BRCMSTB || BMIPS_GENERIC
 	depends on OF
 	select GENERIC_PHY
 	help
-	  Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
+	  Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
 	  Likely useful only with CONFIG_SATA_BRCMSTB enabled.
 
 endmenu
-- 
2.6.2

[PATCH 05/10] phy: phy_brcmstb_sata: remove unused definitions

[Jaedon Shin]

Remove unused definitions.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/phy-brcmstb-sata.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 8a2cb16a1937..0be55dafe9ea 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -26,8 +26,6 @@
 
 #define SATA_MDIO_BANK_OFFSET				0x23c
 #define SATA_MDIO_REG_OFFSET(ofs)			((ofs) * 4)
-#define SATA_MDIO_REG_SPACE_SIZE			0x1000
-#define SATA_MDIO_REG_LENGTH				0x1f00
 
 #define MAX_PORTS					2
 
-- 
2.6.2

[PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset

[Jaedon Shin]

Add data of device node for phy offset.

Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/phy/phy-brcmstb-sata.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 0be55dafe9ea..41c7535d706b 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -42,6 +42,7 @@ struct brcm_sata_port {
 struct brcm_sata_phy {
 	struct device *dev;
 	void __iomem *phy_base;
+	u32 phy_offset;
 
 	struct brcm_sata_port phys[MAX_PORTS];
 };
@@ -65,7 +66,7 @@ static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
 
-	return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
+	return priv->phy_base + (port->portnum * priv->phy_offset);
 }
 
 static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
@@ -126,7 +127,8 @@ static const struct phy_ops phy_ops_28nm = {
 };
 
 static const struct of_device_id brcm_sata_phy_of_match[] = {
-	{ .compatible	= "brcm,bcm7445-sata-phy" },
+	{ .compatible	= "brcm,bcm7445-sata-phy",
+			.data = (void *)SATA_MDIO_REG_SPACE_SIZE },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
@@ -135,6 +137,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev->of_node, *child;
+	const struct of_device_id *of_id = NULL;
 	struct brcm_sata_phy *priv;
 	struct resource *res;
 	struct phy_provider *provider;
@@ -154,6 +157,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->phy_base))
 		return PTR_ERR(priv->phy_base);
 
+	of_id = of_match_node(brcm_sata_phy_of_match, dn);
+	if (!of_id)
+		return -EINVAL;
+
+	priv->phy_offset = (u32)of_id->data;
+
 	for_each_available_child_of_node(dn, child) {
 		unsigned int id;
 		struct brcm_sata_port *port;
-- 
2.6.2

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[PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset

[Jaedon Shin]

Add data of device node for phy offset.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/phy-brcmstb-sata.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 0be55dafe9ea..41c7535d706b 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -42,6 +42,7 @@ struct brcm_sata_port {
 struct brcm_sata_phy {
 	struct device *dev;
 	void __iomem *phy_base;
+	u32 phy_offset;
 
 	struct brcm_sata_port phys[MAX_PORTS];
 };
@@ -65,7 +66,7 @@ static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
 {
 	struct brcm_sata_phy *priv = port->phy_priv;
 
-	return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
+	return priv->phy_base + (port->portnum * priv->phy_offset);
 }
 
 static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
@@ -126,7 +127,8 @@ static const struct phy_ops phy_ops_28nm = {
 };
 
 static const struct of_device_id brcm_sata_phy_of_match[] = {
-	{ .compatible	= "brcm,bcm7445-sata-phy" },
+	{ .compatible	= "brcm,bcm7445-sata-phy",
+			.data = (void *)SATA_MDIO_REG_SPACE_SIZE },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
@@ -135,6 +137,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev->of_node, *child;
+	const struct of_device_id *of_id = NULL;
 	struct brcm_sata_phy *priv;
 	struct resource *res;
 	struct phy_provider *provider;
@@ -154,6 +157,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 	if (IS_ERR(priv->phy_base))
 		return PTR_ERR(priv->phy_base);
 
+	of_id = of_match_node(brcm_sata_phy_of_match, dn);
+	if (!of_id)
+		return -EINVAL;
+
+	priv->phy_offset = (u32)of_id->data;
+
 	for_each_available_child_of_node(dn, child) {
 		unsigned int id;
 		struct brcm_sata_port *port;
-- 
2.6.2

[PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms

[Jaedon Shin]

Add offsets for 40nm BMIPS based set-top box platforms.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 drivers/phy/phy-brcmstb-sata.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
index 41c7535d706b..1cc80743b1b6 100644
--- a/drivers/phy/phy-brcmstb-sata.c
+++ b/drivers/phy/phy-brcmstb-sata.c
@@ -30,7 +30,8 @@
 #define MAX_PORTS					2
 
 /* Register offset between PHYs in PCB space */
-#define SATA_MDIO_REG_SPACE_SIZE			0x1000
+#define SATA_MDIO_REG_28NM_SPACE_SIZE			0x1000
+#define SATA_MDIO_REG_40NM_SPACE_SIZE			0x10
 
 struct brcm_sata_port {
 	int portnum;
@@ -47,7 +48,7 @@ struct brcm_sata_phy {
 	struct brcm_sata_port phys[MAX_PORTS];
 };
 
-enum sata_mdio_phy_regs_28nm {
+enum sata_mdio_phy_regs {
 	PLL_REG_BANK_0				= 0x50,
 	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,
 
@@ -85,7 +86,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
 #define FMAX_VAL_DEFAULT	0x3df
 #define FMAX_VAL_SSC		0x83
 
-static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
+static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
 {
 	void __iomem *base = brcm_sata_phy_base(port);
 	struct brcm_sata_phy *priv = port->phy_priv;
@@ -116,19 +117,25 @@ static int brcm_sata_phy_init(struct phy *phy)
 {
 	struct brcm_sata_port *port = phy_get_drvdata(phy);
 
-	brcm_sata_cfg_ssc_28nm(port);
+	brcm_sata_cfg_ssc(port);
 
 	return 0;
 }
 
-static const struct phy_ops phy_ops_28nm = {
+static const struct phy_ops phy_ops = {
 	.init		= brcm_sata_phy_init,
 	.owner		= THIS_MODULE,
 };
 
 static const struct of_device_id brcm_sata_phy_of_match[] = {
 	{ .compatible	= "brcm,bcm7445-sata-phy",
-			.data = (void *)SATA_MDIO_REG_SPACE_SIZE },
+			.data = (void *)SATA_MDIO_REG_28NM_SPACE_SIZE },
+	{ .compatible   = "brcm,bcm7346-sata-phy",
+			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
+	{ .compatible   = "brcm,bcm7360-sata-phy",
+			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
+	{ .compatible   = "brcm,bcm7362-sata-phy",
+			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
 	{},
 };
 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
@@ -185,7 +192,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
 		port = &priv->phys[id];
 		port->portnum = id;
 		port->phy_priv = priv;
-		port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
+		port->phy = devm_phy_create(dev, child, &phy_ops);
 		port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
 		if (IS_ERR(port->phy)) {
 			dev_err(dev, "failed to create PHY\n");
-- 
2.6.2

[PATCH 08/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7346

[Jaedon Shin]

Add AHCI and PHY device nodes to BMIPS based BCM7346 platform.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7346.dtsi      | 40 +++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97346dbsmb.dts |  8 +++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index d817bb46b934..bf5b2d7a8b75 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -246,5 +246,45 @@
 			interrupts = <76>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7346-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x8>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <40>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7346-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
index 3fe0445b9d37..e147c61178cc 100644
--- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -64,3 +64,11 @@
 &ohci3 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
-- 
2.6.2

[PATCH 09/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7360

[Jaedon Shin]

Add AHCI and PHY device nodes to BMIPS based BCM7360 platform.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7360.dtsi     | 40 ++++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97360svmb.dts |  8 +++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 9e1e571ba346..1f5c99e9d0d1 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -183,5 +183,45 @@
 			interrupts = <66>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7360-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x8>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <86>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7360-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
index eee8b0e32681..0088925cc36a 100644
--- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -40,3 +40,11 @@
 &ohci0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
-- 
2.6.2

[PATCH 10/10] MIPS: BMIPS: brcmstb: add SATA nodes for bcm7362

[Jaedon Shin]

Add AHCI and PHY device nodes to BMIPS based BCM7362 platform.

Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
---
 arch/mips/boot/dts/brcm/bcm7362.dtsi     | 40 ++++++++++++++++++++++++++++++++
 arch/mips/boot/dts/brcm/bcm97362svmb.dts |  8 +++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index 6e65db86fc61..51c58a41d2b5 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -189,5 +189,45 @@
 			interrupts = <66>;
 			status = "disabled";
 		};
+
+		sata: sata@181000 {
+			compatible = "brcm,bcm7362-ahci", "brcm,sata3-ahci";
+			reg-names = "ahci", "top-ctrl";
+			reg = <0x181000 0xa9c>, <0x180020 0x8>;
+			interrupt-parent = <&periph_intc>;
+			interrupts = <86>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata0: sata-port@0 {
+				reg = <0>;
+				phys = <&sata_phy0>;
+			};
+
+			sata1: sata-port@1 {
+				reg = <1>;
+				phys = <&sata_phy1>;
+			};
+		};
+
+		sata_phy: sata-phy@1800000 {
+			compatible = "brcm,bcm7362-sata-phy", "brcm,phy-sata3";
+			reg = <0x180100 0x0eff>;
+			reg-names = "phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			sata_phy0: sata-phy@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+
+			sata_phy1: sata-phy@1 {
+				reg = <1>;
+				#phy-cells = <0>;
+			};
+		};
 	};
 };
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
index 739c2ef5663b..ef9a69b79bc4 100644
--- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -40,3 +40,11 @@
 &ohci0 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};
+
+&sata_phy {
+	status = "okay";
+};
-- 
2.6.2

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Tejun Heo]

On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote:
> Hi all,
> 
> This patch series adds support SATA for BMIPS_GENERIC.
> 
> Ralf,
> I request you to drop already submitted patches for NAND device nodes.
> It is merge conflicts with this patches.
> http://patchwork.linux-mips.org/patch/10577/
> http://patchwork.linux-mips.org/patch/10578/
> http://patchwork.linux-mips.org/patch/10579/
> http://patchwork.linux-mips.org/patch/10580/
> 
> Jaedon Shin (10):
>   ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
>   ata: ahch_brcmstb: add data for port offset
>   ata: ahci_brcmstb: add support 40nm platforms

ata part looks fine to me.  Let me know when the other parts get in.
I'll apply the ata ones to libata/for-4.4.

Thanks.

-- 
tejun

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Florian Fainelli]

2015-10-22 20:58 GMT-07:00 Tejun Heo <tj@kernel.org>:
> On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote:
>> Hi all,
>>
>> This patch series adds support SATA for BMIPS_GENERIC.
>>
>> Ralf,
>> I request you to drop already submitted patches for NAND device nodes.
>> It is merge conflicts with this patches.
>> http://patchwork.linux-mips.org/patch/10577/
>> http://patchwork.linux-mips.org/patch/10578/
>> http://patchwork.linux-mips.org/patch/10579/
>> http://patchwork.linux-mips.org/patch/10580/
>>
>> Jaedon Shin (10):
>>   ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
>>   ata: ahch_brcmstb: add data for port offset
>>   ata: ahci_brcmstb: add support 40nm platforms
>
> ata part looks fine to me.  Let me know when the other parts get in.
> I'll apply the ata ones to libata/for-4.4.

There are a few comments coming on the ATA and Device Tree part, and I
also would like Brian Norris (who submitted the patches) to take a
look at these. But overall, this looks great.

I think we have a bit too many compatible strings defined, I need to
lookup tomorrow when I am back in the office which BCM7xxx started
featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
sure

Thanks!
-- 
Florian

Re: [PATCH 01/10] ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  drivers/ata/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 15e40ee62a94..8f535a88a0c7 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -100,7 +100,7 @@ config SATA_AHCI_PLATFORM
>
>  config AHCI_BRCMSTB
>         tristate "Broadcom STB AHCI SATA support"
> -       depends on ARCH_BRCMSTB
> +       depends on ARCH_BRCMSTB || BMIPS_GENERIC
>         help
>           This option enables support for the AHCI SATA3 controller found on
>           STB SoC's.
> --
> 2.6.2
>



-- 
Florian

Re: [PATCH 02/10] ata: ahch_brcmstb: add data for port offset

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> Add data of device node for port offset.

Looks good to me, some minor nits below.

>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/ata/ahci_brcmstb.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 14b7305d2ba0..8cf6f7d4798f 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -72,6 +72,7 @@
>  struct brcm_ahci_priv {
>         struct device *dev;
>         void __iomem *top_ctrl;
> +       u32 port_offset;
>         u32 port_mask;
>  };
>
> @@ -110,7 +111,7 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
>  static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>  {
>         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> -                               (port * SATA_TOP_CTRL_PHY_OFFS);
> +                               (port * priv->port_offset);
>         void __iomem *p;
>         u32 reg;
>
> @@ -139,7 +140,7 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>  static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
>  {
>         void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> -                               (port * SATA_TOP_CTRL_PHY_OFFS);
> +                               (port * priv->port_offset);
>         void __iomem *p;
>         u32 reg;
>
> @@ -234,6 +235,13 @@ static int brcm_ahci_resume(struct device *dev)
>  }
>  #endif
>
> +static const struct of_device_id ahci_of_match[] = {
> +       {.compatible = "brcm,bcm7445-ahci",
> +                       .data = (void *)SATA_TOP_CTRL_PHY_OFFS},

We could omit having to specify explicitly the offset here.

> +       {},
> +};
> +MODULE_DEVICE_TABLE(of, ahci_of_match);
> +
>  static struct scsi_host_template ahci_platform_sht = {
>         AHCI_SHT(DRV_NAME),
>  };
> @@ -241,6 +249,7 @@ static struct scsi_host_template ahci_platform_sht = {
>  static int brcm_ahci_probe(struct platform_device *pdev)
>  {
>         struct device *dev = &pdev->dev;
> +       const struct of_device_id *of_id = NULL;
>         struct brcm_ahci_priv *priv;
>         struct ahci_host_priv *hpriv;
>         struct resource *res;
> @@ -256,6 +265,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>         if (IS_ERR(priv->top_ctrl))
>                 return PTR_ERR(priv->top_ctrl);
>
> +       of_id = of_match_node(ahci_of_match, dev->of_node);
> +       if (!of_id)
> +               return -EINVAL;
> +
> +       priv->port_offset = (u32)of_id->data;

And if of_id->data is NULL here, just default to
SATA_TOP_CTRL_PHY_OFFS. But I have no strong preference.

Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/ata/ahci_brcmstb.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 8cf6f7d4798f..59eb526cf4f6 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -50,7 +50,8 @@
>    #define SATA_TOP_CTRL_2_SW_RST_RX                    BIT(2)
>    #define SATA_TOP_CTRL_2_SW_RST_TX                    BIT(3)
>    #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET             BIT(14)
> - #define SATA_TOP_CTRL_PHY_OFFS                                0x8
> + #define SATA_TOP_CTRL_28NM_PHY_OFFS                   0x8
> + #define SATA_TOP_CTRL_40NM_PHY_OFFS                   0x4
>   #define SATA_TOP_MAX_PHYS                             2
>  #define SATA_TOP_CTRL_SATA_TP_OUT                      0x1c
>  #define SATA_TOP_CTRL_CLIENT_INIT_CTRL                 0x20
> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>
>  static const struct of_device_id ahci_of_match[] = {
>         {.compatible = "brcm,bcm7445-ahci",
> -                       .data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> +                       .data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
> +       {.compatible = "brcm,bcm7346-ahci",
> +                       .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> +       {.compatible = "brcm,bcm7360-ahci",
> +                       .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> +       {.compatible = "brcm,bcm7362-ahci",
> +                       .data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},

Since you are introducing new compatible strings, you also need to
update the binding document in Documentation/devicetree/bindings/ata/

We could just use the compatible string for the first 40nm chip that
started featuring such a SATA3 AHCI compliant core, which seems to be
7231. Apart from the existing known workarounds (disabling NCQ, tuning
the PHY) it seems to be largely identical across all 40nm chips.

This is fine either way, and more information cannot hurt, these are
all production chips, so we can actually look back at the history to
know everything about them.
-- 
Florian

Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3 PHY.
>
> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Acked-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

> ---
>  drivers/phy/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573d0bab..c83e48661fd7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -364,11 +364,11 @@ config PHY_TUSB1210
>
>  config PHY_BRCMSTB_SATA
>         tristate "Broadcom STB SATA PHY driver"
> -       depends on ARCH_BRCMSTB
> +       depends on ARCH_BRCMSTB || BMIPS_GENERIC
>         depends on OF
>         select GENERIC_PHY
>         help
> -         Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> +         Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
>           Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>
>  endmenu
> --
> 2.6.2
>



-- 
Florian
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Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3 PHY.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  drivers/phy/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573d0bab..c83e48661fd7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -364,11 +364,11 @@ config PHY_TUSB1210
>
>  config PHY_BRCMSTB_SATA
>         tristate "Broadcom STB SATA PHY driver"
> -       depends on ARCH_BRCMSTB
> +       depends on ARCH_BRCMSTB || BMIPS_GENERIC
>         depends on OF
>         select GENERIC_PHY
>         help
> -         Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> +         Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
>           Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>
>  endmenu
> --
> 2.6.2
>



-- 
Florian

Re: [PATCH 05/10] phy: phy_brcmstb_sata: remove unused definitions

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> Remove unused definitions.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Florian Fainelli <f.fainelli@gmail.com>

> ---
>  drivers/phy/phy-brcmstb-sata.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 8a2cb16a1937..0be55dafe9ea 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -26,8 +26,6 @@
>
>  #define SATA_MDIO_BANK_OFFSET                          0x23c
>  #define SATA_MDIO_REG_OFFSET(ofs)                      ((ofs) * 4)
> -#define SATA_MDIO_REG_SPACE_SIZE                       0x1000
> -#define SATA_MDIO_REG_LENGTH                           0x1f00
>
>  #define MAX_PORTS                                      2
>
> --
> 2.6.2
>



-- 
Florian

Re: [PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> Add data of device node for phy offset.

Similar comment to the AHCI portion, we could just omit specifying the
offset in the of_device_id.data member, and just assume the current
offset if not defined.

Acked-by: Florian Fainelli <f.fainelli@gmail.com>

>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 0be55dafe9ea..41c7535d706b 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -42,6 +42,7 @@ struct brcm_sata_port {
>  struct brcm_sata_phy {
>         struct device *dev;
>         void __iomem *phy_base;
> +       u32 phy_offset;
>
>         struct brcm_sata_port phys[MAX_PORTS];
>  };
> @@ -65,7 +66,7 @@ static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
>  {
>         struct brcm_sata_phy *priv = port->phy_priv;
>
> -       return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
> +       return priv->phy_base + (port->portnum * priv->phy_offset);
>  }
>
>  static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
> @@ -126,7 +127,8 @@ static const struct phy_ops phy_ops_28nm = {
>  };
>
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
> -       { .compatible   = "brcm,bcm7445-sata-phy" },
> +       { .compatible   = "brcm,bcm7445-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_SPACE_SIZE },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -135,6 +137,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>  {
>         struct device *dev = &pdev->dev;
>         struct device_node *dn = dev->of_node, *child;
> +       const struct of_device_id *of_id = NULL;
>         struct brcm_sata_phy *priv;
>         struct resource *res;
>         struct phy_provider *provider;
> @@ -154,6 +157,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>         if (IS_ERR(priv->phy_base))
>                 return PTR_ERR(priv->phy_base);
>
> +       of_id = of_match_node(brcm_sata_phy_of_match, dn);
> +       if (!of_id)
> +               return -EINVAL;
> +
> +       priv->phy_offset = (u32)of_id->data;
> +
>         for_each_available_child_of_node(dn, child) {
>                 unsigned int id;
>                 struct brcm_sata_port *port;
> --
> 2.6.2
>



-- 
Florian

Re: [PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 21 ++++++++++++++-------
>  1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 41c7535d706b..1cc80743b1b6 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -30,7 +30,8 @@
>  #define MAX_PORTS                                      2
>
>  /* Register offset between PHYs in PCB space */
> -#define SATA_MDIO_REG_SPACE_SIZE                       0x1000
> +#define SATA_MDIO_REG_28NM_SPACE_SIZE                  0x1000
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE                  0x10
>
>  struct brcm_sata_port {
>         int portnum;
> @@ -47,7 +48,7 @@ struct brcm_sata_phy {
>         struct brcm_sata_port phys[MAX_PORTS];
>  };
>
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
>         PLL_REG_BANK_0                          = 0x50,
>         PLL_REG_BANK_0_PLLCONTROL_0             = 0x81,
>
> @@ -85,7 +86,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
>  #define FMAX_VAL_DEFAULT       0x3df
>  #define FMAX_VAL_SSC           0x83
>
> -static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
> +static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
>  {
>         void __iomem *base = brcm_sata_phy_base(port);
>         struct brcm_sata_phy *priv = port->phy_priv;
> @@ -116,19 +117,25 @@ static int brcm_sata_phy_init(struct phy *phy)
>  {
>         struct brcm_sata_port *port = phy_get_drvdata(phy);
>
> -       brcm_sata_cfg_ssc_28nm(port);
> +       brcm_sata_cfg_ssc(port);
>
>         return 0;
>  }
>
> -static const struct phy_ops phy_ops_28nm = {
> +static const struct phy_ops phy_ops = {
>         .init           = brcm_sata_phy_init,
>         .owner          = THIS_MODULE,
>  };
>
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
>         { .compatible   = "brcm,bcm7445-sata-phy",
> -                       .data = (void *)SATA_MDIO_REG_SPACE_SIZE },
> +                       .data = (void *)SATA_MDIO_REG_28NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7346-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7360-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7362-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },

Same comment as the AHCI portion, we need to update the Device Tree
binding document to make these new compatible strings documented
there.

Thank you!

>         {},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -185,7 +192,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>                 port = &priv->phys[id];
>                 port->portnum = id;
>                 port->phy_priv = priv;
> -               port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
> +               port->phy = devm_phy_create(dev, child, &phy_ops);
>                 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
>                 if (IS_ERR(port->phy)) {
>                         dev_err(dev, "failed to create PHY\n");
> --
> 2.6.2
>



-- 
Florian
--
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Re: [PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms

[Florian Fainelli]

2015-10-22 18:44 GMT-07:00 Jaedon Shin <jaedon.shin@gmail.com>:
> Add offsets for 40nm BMIPS based set-top box platforms.
>
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 21 ++++++++++++++-------
>  1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 41c7535d706b..1cc80743b1b6 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -30,7 +30,8 @@
>  #define MAX_PORTS                                      2
>
>  /* Register offset between PHYs in PCB space */
> -#define SATA_MDIO_REG_SPACE_SIZE                       0x1000
> +#define SATA_MDIO_REG_28NM_SPACE_SIZE                  0x1000
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE                  0x10
>
>  struct brcm_sata_port {
>         int portnum;
> @@ -47,7 +48,7 @@ struct brcm_sata_phy {
>         struct brcm_sata_port phys[MAX_PORTS];
>  };
>
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
>         PLL_REG_BANK_0                          = 0x50,
>         PLL_REG_BANK_0_PLLCONTROL_0             = 0x81,
>
> @@ -85,7 +86,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
>  #define FMAX_VAL_DEFAULT       0x3df
>  #define FMAX_VAL_SSC           0x83
>
> -static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
> +static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
>  {
>         void __iomem *base = brcm_sata_phy_base(port);
>         struct brcm_sata_phy *priv = port->phy_priv;
> @@ -116,19 +117,25 @@ static int brcm_sata_phy_init(struct phy *phy)
>  {
>         struct brcm_sata_port *port = phy_get_drvdata(phy);
>
> -       brcm_sata_cfg_ssc_28nm(port);
> +       brcm_sata_cfg_ssc(port);
>
>         return 0;
>  }
>
> -static const struct phy_ops phy_ops_28nm = {
> +static const struct phy_ops phy_ops = {
>         .init           = brcm_sata_phy_init,
>         .owner          = THIS_MODULE,
>  };
>
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
>         { .compatible   = "brcm,bcm7445-sata-phy",
> -                       .data = (void *)SATA_MDIO_REG_SPACE_SIZE },
> +                       .data = (void *)SATA_MDIO_REG_28NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7346-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7360-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +       { .compatible   = "brcm,bcm7362-sata-phy",
> +                       .data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },

Same comment as the AHCI portion, we need to update the Device Tree
binding document to make these new compatible strings documented
there.

Thank you!

>         {},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -185,7 +192,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>                 port = &priv->phys[id];
>                 port->portnum = id;
>                 port->phy_priv = priv;
> -               port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
> +               port->phy = devm_phy_create(dev, child, &phy_ops);
>                 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
>                 if (IS_ERR(port->phy)) {
>                         dev_err(dev, "failed to create PHY\n");
> --
> 2.6.2
>



-- 
Florian

Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Kishon Vijay Abraham I]

+Brian Norris

Hi,

On Friday 23 October 2015 07:14 AM, Jaedon Shin wrote:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3 PHY.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573d0bab..c83e48661fd7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -364,11 +364,11 @@ config PHY_TUSB1210
>  
>  config PHY_BRCMSTB_SATA
>  	tristate "Broadcom STB SATA PHY driver"
> -	depends on ARCH_BRCMSTB
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC

Nice to see the same driver is been used across multiple platforms.
Cc'ed Brian who is the author of brcmstb-sata.c

Thanks
Kishon
>  	depends on OF
>  	select GENERIC_PHY
>  	help
> -	  Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> +	  Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
>  	  Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>  
>  endmenu
> 

Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Kishon Vijay Abraham I]

+Brian Norris

Hi,

On Friday 23 October 2015 07:14 AM, Jaedon Shin wrote:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3 PHY.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 47da573d0bab..c83e48661fd7 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -364,11 +364,11 @@ config PHY_TUSB1210
>  
>  config PHY_BRCMSTB_SATA
>  	tristate "Broadcom STB SATA PHY driver"
> -	depends on ARCH_BRCMSTB
> +	depends on ARCH_BRCMSTB || BMIPS_GENERIC

Nice to see the same driver is been used across multiple platforms.
Cc'ed Brian who is the author of brcmstb-sata.c

Thanks
Kishon
>  	depends on OF
>  	select GENERIC_PHY
>  	help
> -	  Enable this to support the SATA3 PHY on 28nm Broadcom STB SoCs.
> +	  Enable this to support the SATA3 PHY on 28nm or 40nm Broadcom STB SoCs.
>  	  Likely useful only with CONFIG_SATA_BRCMSTB enabled.
>  
>  endmenu
> 

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Brian Norris]

On Thu, Oct 22, 2015 at 09:51:30PM -0700, Florian Fainelli wrote:
> 2015-10-22 20:58 GMT-07:00 Tejun Heo <tj@kernel.org>:
> I think we have a bit too many compatible strings defined, I need to
> lookup tomorrow when I am back in the office which BCM7xxx started
> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
> sure

I thought it was BCM7425, but you probably have the resources to check
better than I do.

There were also some small (probably mostly undocumented) bugfixes at
some point. I think the early cores actually had problems with the
upstream libahci. You might look at AHCI_HFLAG_DELAY_ENGINE for that, if
you care.

You might also notice that the "strict-ahci" stuff we were using got
dropped:

commit f1df8641e27b7edb978bdc7aaf50c235bc9e8be9
Author: Hans de Goede <hdegoede@redhat.com>
Date:   Sat Feb 22 17:22:53 2014 +0100

    ahci_platform: Drop support for ahci-strict platform device type

But that's less relevant, now that there's a proper brcmstb driver.

Brian

Re: [PATCH 05/10] phy: phy_brcmstb_sata: remove unused definitions

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:18AM +0900, Jaedon Shin wrote:
> Remove unused definitions.

The first one is actually a duplicate (oops!), so is that technically
"unused" or just redundant?

Pedantry aside:

Acked-by: Brian Norris <computersforpeace@gmail.com>

> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 8a2cb16a1937..0be55dafe9ea 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -26,8 +26,6 @@
>  
>  #define SATA_MDIO_BANK_OFFSET				0x23c
>  #define SATA_MDIO_REG_OFFSET(ofs)			((ofs) * 4)
> -#define SATA_MDIO_REG_SPACE_SIZE			0x1000
> -#define SATA_MDIO_REG_LENGTH				0x1f00
>  
>  #define MAX_PORTS					2
>  
> -- 
> 2.6.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 07/10] phy: phy_brcmstb_sata: add support 40nm platforms

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:20AM +0900, Jaedon Shin wrote:
> Add offsets for 40nm BMIPS based set-top box platforms.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 21 ++++++++++++++-------
>  1 file changed, 14 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 41c7535d706b..1cc80743b1b6 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -30,7 +30,8 @@
>  #define MAX_PORTS					2
>  
>  /* Register offset between PHYs in PCB space */
> -#define SATA_MDIO_REG_SPACE_SIZE			0x1000
> +#define SATA_MDIO_REG_28NM_SPACE_SIZE			0x1000
> +#define SATA_MDIO_REG_40NM_SPACE_SIZE			0x10

Hmm, I thought there were other differences than just the offsets
between ports when rev'ing from 40nm to 28nm. But revisiting the only
documentation I have [1], this looks OK. I'd recommend double checking
the other registers, even if they're currently unused though.

>  
>  struct brcm_sata_port {
>  	int portnum;
> @@ -47,7 +48,7 @@ struct brcm_sata_phy {
>  	struct brcm_sata_port phys[MAX_PORTS];
>  };
>  
> -enum sata_mdio_phy_regs_28nm {
> +enum sata_mdio_phy_regs {
>  	PLL_REG_BANK_0				= 0x50,
>  	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,
>  
> @@ -85,7 +86,7 @@ static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
>  #define FMAX_VAL_DEFAULT	0x3df
>  #define FMAX_VAL_SSC		0x83
>  
> -static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
> +static void brcm_sata_cfg_ssc(struct brcm_sata_port *port)
>  {
>  	void __iomem *base = brcm_sata_phy_base(port);
>  	struct brcm_sata_phy *priv = port->phy_priv;
> @@ -116,19 +117,25 @@ static int brcm_sata_phy_init(struct phy *phy)
>  {
>  	struct brcm_sata_port *port = phy_get_drvdata(phy);
>  
> -	brcm_sata_cfg_ssc_28nm(port);
> +	brcm_sata_cfg_ssc(port);
>  
>  	return 0;
>  }
>  
> -static const struct phy_ops phy_ops_28nm = {
> +static const struct phy_ops phy_ops = {
>  	.init		= brcm_sata_phy_init,
>  	.owner		= THIS_MODULE,
>  };
>  
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
>  	{ .compatible	= "brcm,bcm7445-sata-phy",
> -			.data = (void *)SATA_MDIO_REG_SPACE_SIZE },
> +			.data = (void *)SATA_MDIO_REG_28NM_SPACE_SIZE },
> +	{ .compatible   = "brcm,bcm7346-sata-phy",
> +			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +	{ .compatible   = "brcm,bcm7360-sata-phy",
> +			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },
> +	{ .compatible   = "brcm,bcm7362-sata-phy",
> +			.data = (void *)SATA_MDIO_REG_40NM_SPACE_SIZE },

Like Florian suggested, this should probably be consolidated to the
first SoC that had this core on it. I think bcm7425, but I could be
wrong.

>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -185,7 +192,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>  		port = &priv->phys[id];
>  		port->portnum = id;
>  		port->phy_priv = priv;
> -		port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
> +		port->phy = devm_phy_create(dev, child, &phy_ops);
>  		port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
>  		if (IS_ERR(port->phy)) {
>  			dev_err(dev, "failed to create PHY\n");
> -- 
> 2.6.2
> 

With that:

Reviewed-by: Brian Norris <computersforpeace@gmail.com>

[1] https://github.com/Broadcom/stblinux-3.8/blob/master/linux/drivers/ata/sata_brcmstb_phy.c
    https://github.com/Broadcom/stblinux-3.8/blob/master/linux/drivers/ata/sata_brcmstb.h

Re: [PATCH 06/10] phy: phy_brcmstb_sata: add data for phy offset

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:19AM +0900, Jaedon Shin wrote:
> Add data of device node for phy offset.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/phy/phy-brcmstb-sata.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/phy/phy-brcmstb-sata.c b/drivers/phy/phy-brcmstb-sata.c
> index 0be55dafe9ea..41c7535d706b 100644
> --- a/drivers/phy/phy-brcmstb-sata.c
> +++ b/drivers/phy/phy-brcmstb-sata.c
> @@ -42,6 +42,7 @@ struct brcm_sata_port {
>  struct brcm_sata_phy {
>  	struct device *dev;
>  	void __iomem *phy_base;
> +	u32 phy_offset;
>  
>  	struct brcm_sata_port phys[MAX_PORTS];
>  };
> @@ -65,7 +66,7 @@ static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
>  {
>  	struct brcm_sata_phy *priv = port->phy_priv;
>  
> -	return priv->phy_base + (port->portnum * SATA_MDIO_REG_SPACE_SIZE);
> +	return priv->phy_base + (port->portnum * priv->phy_offset);
>  }
>  
>  static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
> @@ -126,7 +127,8 @@ static const struct phy_ops phy_ops_28nm = {
>  };
>  
>  static const struct of_device_id brcm_sata_phy_of_match[] = {
> -	{ .compatible	= "brcm,bcm7445-sata-phy" },
> +	{ .compatible	= "brcm,bcm7445-sata-phy",
> +			.data = (void *)SATA_MDIO_REG_SPACE_SIZE },
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
> @@ -135,6 +137,7 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	struct device_node *dn = dev->of_node, *child;
> +	const struct of_device_id *of_id = NULL;

Drop the '= NULL', since it's unncessary. Then the compiler will
complain if you ever end up dereferencing it before (properly)
initializing it.

>  	struct brcm_sata_phy *priv;
>  	struct resource *res;
>  	struct phy_provider *provider;
> @@ -154,6 +157,12 @@ static int brcm_sata_phy_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->phy_base))
>  		return PTR_ERR(priv->phy_base);
>  
> +	of_id = of_match_node(brcm_sata_phy_of_match, dn);
> +	if (!of_id)
> +		return -EINVAL;
> +
> +	priv->phy_offset = (u32)of_id->data;

Using my mental compiler, I expect you'll get warnings on 64-bit systems
about casting from a pointer to an integer of different size. Using
uintptr_t would get around that. And if you wanted to be really clear
that you are purposely truncating, maybe an ugly double cast?

	priv->phy_offset = (u32)(uintptr_t)of_id->data;

With that:

Reviewed-by: Brian Norris <computersforpeace@gmail.com>

> +
>  	for_each_available_child_of_node(dn, child) {
>  		unsigned int id;
>  		struct brcm_sata_port *port;
> -- 
> 2.6.2

Re: [PATCH 04/10] phy: phy_brcmstb_sata: make the driver buildable on BMIPS_GENERIC

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:17AM +0900, Jaedon Shin wrote:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3 PHY.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Brian Norris <computersforpeace@gmail.com>

Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Brian Norris]

Hi Jadeon,

Hmm, my suspicions about the PHY driver are probably meant to be applied
here. I don't think this change is sufficient.

On Fri, Oct 23, 2015 at 10:44:16AM +0900, Jaedon Shin wrote:
> Add offsets for 40nm BMIPS based set-top box platforms.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/ata/ahci_brcmstb.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 8cf6f7d4798f..59eb526cf4f6 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -50,7 +50,8 @@
>    #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
>    #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
>    #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
> - #define SATA_TOP_CTRL_PHY_OFFS				0x8
> + #define SATA_TOP_CTRL_28NM_PHY_OFFS			0x8
> + #define SATA_TOP_CTRL_40NM_PHY_OFFS			0x4

I don't remember the exact 40nm vs. 28nm map that well, but judging by
the code-is-the-documentation, the 28nm layout is like this:

base + 0x0C = port 0, phy control 1
base + 0x10 = port 0, phy control 2
base + 0x14 = port 1, phy control 1
base + 0x18 = port 1, phy control 2

but the 40nm layout is differnt, where the ports are interleaved:

base + 0x0C = port 0, phy control 1
base + 0x10 = port 1, phy control 1
base + 0x14 = port 0, phy control 2
base + 0x18 = port 1, phy control 2

So, your patch gets phy control 1 correct for both ports, but it doesn't
get phy control 2 correct. (Or at least, even if my guess at the 40nm
layout is wrong, your patch makes "port 0, phy control 2" collide with
"port 1, phy control 1", which is most certainly a bug.)

Are you sure you're testing this properly? Did you try using both ports
at the same time? And please, apply the same scrutiny to the PHY driver.
(e.g., did you test SSC? did you test both ports?)

Brian

>   #define SATA_TOP_MAX_PHYS				2
>  #define SATA_TOP_CTRL_SATA_TP_OUT			0x1c
>  #define SATA_TOP_CTRL_CLIENT_INIT_CTRL			0x20
> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>  
>  static const struct of_device_id ahci_of_match[] = {
>  	{.compatible = "brcm,bcm7445-ahci",
> -			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> +			.data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
> +	{.compatible = "brcm,bcm7346-ahci",
> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> +	{.compatible = "brcm,bcm7360-ahci",
> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
> +	{.compatible = "brcm,bcm7362-ahci",
> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>  	{},
>  };
>  MODULE_DEVICE_TABLE(of, ahci_of_match);
> -- 
> 2.6.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 01/10] ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:14AM +0900, Jaedon Shin wrote:
> The BCM7xxx ARM and MIPS platforms share a similar hardware block for AHCI
> SATA3.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>

Acked-by: Brian Norris <computersforpeace@gmail.com>

Re: [PATCH 02/10] ata: ahch_brcmstb: add data for port offset

[Brian Norris]

On Fri, Oct 23, 2015 at 10:44:15AM +0900, Jaedon Shin wrote:
> Add data of device node for port offset.
> 
> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
> ---
>  drivers/ata/ahci_brcmstb.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
> index 14b7305d2ba0..8cf6f7d4798f 100644
> --- a/drivers/ata/ahci_brcmstb.c
> +++ b/drivers/ata/ahci_brcmstb.c
> @@ -72,6 +72,7 @@
>  struct brcm_ahci_priv {
>  	struct device *dev;
>  	void __iomem *top_ctrl;
> +	u32 port_offset;

You're gonna need to vary more than just the port offset for 40nm vs.
28nm, I think. See my comments on patch 3.

Brian

>  	u32 port_mask;
>  };
>  
> @@ -110,7 +111,7 @@ static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
>  static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>  {
>  	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> -				(port * SATA_TOP_CTRL_PHY_OFFS);
> +				(port * priv->port_offset);
>  	void __iomem *p;
>  	u32 reg;
>  
> @@ -139,7 +140,7 @@ static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
>  static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
>  {
>  	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
> -				(port * SATA_TOP_CTRL_PHY_OFFS);
> +				(port * priv->port_offset);
>  	void __iomem *p;
>  	u32 reg;
>  
> @@ -234,6 +235,13 @@ static int brcm_ahci_resume(struct device *dev)
>  }
>  #endif
>  
> +static const struct of_device_id ahci_of_match[] = {
> +	{.compatible = "brcm,bcm7445-ahci",
> +			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, ahci_of_match);
> +
>  static struct scsi_host_template ahci_platform_sht = {
>  	AHCI_SHT(DRV_NAME),
>  };
> @@ -241,6 +249,7 @@ static struct scsi_host_template ahci_platform_sht = {
>  static int brcm_ahci_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
> +	const struct of_device_id *of_id = NULL;
>  	struct brcm_ahci_priv *priv;
>  	struct ahci_host_priv *hpriv;
>  	struct resource *res;
> @@ -256,6 +265,12 @@ static int brcm_ahci_probe(struct platform_device *pdev)
>  	if (IS_ERR(priv->top_ctrl))
>  		return PTR_ERR(priv->top_ctrl);
>  
> +	of_id = of_match_node(ahci_of_match, dev->of_node);
> +	if (!of_id)
> +		return -EINVAL;
> +
> +	priv->port_offset = (u32)of_id->data;
> +
>  	brcm_sata_init(priv);
>  
>  	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
> @@ -299,12 +314,6 @@ static int brcm_ahci_remove(struct platform_device *pdev)
>  	return 0;
>  }
>  
> -static const struct of_device_id ahci_of_match[] = {
> -	{.compatible = "brcm,bcm7445-ahci"},
> -	{},
> -};
> -MODULE_DEVICE_TABLE(of, ahci_of_match);
> -
>  static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
>  
>  static struct platform_driver brcm_ahci_driver = {
> -- 
> 2.6.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Kevin Cernekee]

On Fri, Oct 23, 2015 at 1:35 PM, Brian Norris
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On Thu, Oct 22, 2015 at 09:51:30PM -0700, Florian Fainelli wrote:
>> 2015-10-22 20:58 GMT-07:00 Tejun Heo <tj-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
>> I think we have a bit too many compatible strings defined, I need to
>> lookup tomorrow when I am back in the office which BCM7xxx started
>> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
>> sure
>
> I thought it was BCM7425, but you probably have the resources to check
> better than I do.

It was originally introduced on 7422 A0 (40nm) and the test chip that
preceded it.  The production rev of 7422 uses the 7425 die, so
"BCM7425" is a good enough answer for our purposes.

BCM7420, BCM7400, and other 65nm SoCs had a ServerWorks SATA2 core on
an internal PCI-X bus.  These ran a modified version of sata_svw.c,
and could support QDMA.
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Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Kevin Cernekee]

On Fri, Oct 23, 2015 at 1:35 PM, Brian Norris
<computersforpeace@gmail.com> wrote:
> On Thu, Oct 22, 2015 at 09:51:30PM -0700, Florian Fainelli wrote:
>> 2015-10-22 20:58 GMT-07:00 Tejun Heo <tj@kernel.org>:
>> I think we have a bit too many compatible strings defined, I need to
>> lookup tomorrow when I am back in the office which BCM7xxx started
>> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
>> sure
>
> I thought it was BCM7425, but you probably have the resources to check
> better than I do.

It was originally introduced on 7422 A0 (40nm) and the test chip that
preceded it.  The production rev of 7422 uses the 7425 die, so
"BCM7425" is a good enough answer for our purposes.

BCM7420, BCM7400, and other 65nm SoCs had a ServerWorks SATA2 core on
an internal PCI-X bus.  These ran a modified version of sata_svw.c,
and could support QDMA.

Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Jaedon Shin]

Hi Brian,

On Oct 24, 2015, at 6:25 AM, Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> 
> Hi Jadeon,
> 
> Hmm, my suspicions about the PHY driver are probably meant to be applied
> here. I don't think this change is sufficient.
> 
> On Fri, Oct 23, 2015 at 10:44:16AM +0900, Jaedon Shin wrote:
>> Add offsets for 40nm BMIPS based set-top box platforms.
>> 
>> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> drivers/ata/ahci_brcmstb.c | 11 +++++++++--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
>> index 8cf6f7d4798f..59eb526cf4f6 100644
>> --- a/drivers/ata/ahci_brcmstb.c
>> +++ b/drivers/ata/ahci_brcmstb.c
>> @@ -50,7 +50,8 @@
>>   #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
>>   #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
>>   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
>> - #define SATA_TOP_CTRL_PHY_OFFS				0x8
>> + #define SATA_TOP_CTRL_28NM_PHY_OFFS			0x8
>> + #define SATA_TOP_CTRL_40NM_PHY_OFFS			0x4
> 
> I don't remember the exact 40nm vs. 28nm map that well, but judging by
> the code-is-the-documentation, the 28nm layout is like this:
> 
> base + 0x0C = port 0, phy control 1
> base + 0x10 = port 0, phy control 2
> base + 0x14 = port 1, phy control 1
> base + 0x18 = port 1, phy control 2
> 
> but the 40nm layout is differnt, where the ports are interleaved:
> 
> base + 0x0C = port 0, phy control 1
> base + 0x10 = port 1, phy control 1
> base + 0x14 = port 0, phy control 2
> base + 0x18 = port 1, phy control 2
> 
> So, your patch gets phy control 1 correct for both ports, but it doesn't
> get phy control 2 correct. (Or at least, even if my guess at the 40nm
> layout is wrong, your patch makes "port 0, phy control 2" collide with
> "port 1, phy control 1", which is most certainly a bug.)
> 
> Are you sure you're testing this properly? Did you try using both ports
> at the same time? And please, apply the same scrutiny to the PHY driver.
> (e.g., did you test SSC? did you test both ports?)
> 
> Brian
> 

You are right. This must be changed. 

I found the 28nm chipsets have four phy interface control registers. But, 
the the 40nm chipsets have only three registers. I did not testing with 
two ports at the same time. It seems we should check more.

Thanks.

Jaedon

>>  #define SATA_TOP_MAX_PHYS				2
>> #define SATA_TOP_CTRL_SATA_TP_OUT			0x1c
>> #define SATA_TOP_CTRL_CLIENT_INIT_CTRL			0x20
>> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>> 
>> static const struct of_device_id ahci_of_match[] = {
>> 	{.compatible = "brcm,bcm7445-ahci",
>> -			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
>> +			.data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7346-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7360-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7362-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> 	{},
>> };
>> MODULE_DEVICE_TABLE(of, ahci_of_match);
>> -- 
>> 2.6.2
>> 
>> --
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>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Jaedon Shin]

Hi Brian,

On Oct 24, 2015, at 6:25 AM, Brian Norris <computersforpeace@gmail.com> wrote:
> 
> Hi Jadeon,
> 
> Hmm, my suspicions about the PHY driver are probably meant to be applied
> here. I don't think this change is sufficient.
> 
> On Fri, Oct 23, 2015 at 10:44:16AM +0900, Jaedon Shin wrote:
>> Add offsets for 40nm BMIPS based set-top box platforms.
>> 
>> Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
>> ---
>> drivers/ata/ahci_brcmstb.c | 11 +++++++++--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/ata/ahci_brcmstb.c b/drivers/ata/ahci_brcmstb.c
>> index 8cf6f7d4798f..59eb526cf4f6 100644
>> --- a/drivers/ata/ahci_brcmstb.c
>> +++ b/drivers/ata/ahci_brcmstb.c
>> @@ -50,7 +50,8 @@
>>   #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
>>   #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
>>   #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
>> - #define SATA_TOP_CTRL_PHY_OFFS				0x8
>> + #define SATA_TOP_CTRL_28NM_PHY_OFFS			0x8
>> + #define SATA_TOP_CTRL_40NM_PHY_OFFS			0x4
> 
> I don't remember the exact 40nm vs. 28nm map that well, but judging by
> the code-is-the-documentation, the 28nm layout is like this:
> 
> base + 0x0C = port 0, phy control 1
> base + 0x10 = port 0, phy control 2
> base + 0x14 = port 1, phy control 1
> base + 0x18 = port 1, phy control 2
> 
> but the 40nm layout is differnt, where the ports are interleaved:
> 
> base + 0x0C = port 0, phy control 1
> base + 0x10 = port 1, phy control 1
> base + 0x14 = port 0, phy control 2
> base + 0x18 = port 1, phy control 2
> 
> So, your patch gets phy control 1 correct for both ports, but it doesn't
> get phy control 2 correct. (Or at least, even if my guess at the 40nm
> layout is wrong, your patch makes "port 0, phy control 2" collide with
> "port 1, phy control 1", which is most certainly a bug.)
> 
> Are you sure you're testing this properly? Did you try using both ports
> at the same time? And please, apply the same scrutiny to the PHY driver.
> (e.g., did you test SSC? did you test both ports?)
> 
> Brian
> 

You are right. This must be changed. 

I found the 28nm chipsets have four phy interface control registers. But, 
the the 40nm chipsets have only three registers. I did not testing with 
two ports at the same time. It seems we should check more.

Thanks.

Jaedon

>>  #define SATA_TOP_MAX_PHYS				2
>> #define SATA_TOP_CTRL_SATA_TP_OUT			0x1c
>> #define SATA_TOP_CTRL_CLIENT_INIT_CTRL			0x20
>> @@ -237,7 +238,13 @@ static int brcm_ahci_resume(struct device *dev)
>> 
>> static const struct of_device_id ahci_of_match[] = {
>> 	{.compatible = "brcm,bcm7445-ahci",
>> -			.data = (void *)SATA_TOP_CTRL_PHY_OFFS},
>> +			.data = (void *)SATA_TOP_CTRL_28NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7346-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7360-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> +	{.compatible = "brcm,bcm7362-ahci",
>> +			.data = (void *)SATA_TOP_CTRL_40NM_PHY_OFFS},
>> 	{},
>> };
>> MODULE_DEVICE_TABLE(of, ahci_of_match);
>> -- 
>> 2.6.2
>> 
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Jaedon Shin]

On Oct 23, 2015, at 1:51 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
> 
> 2015-10-22 20:58 GMT-07:00 Tejun Heo <tj@kernel.org>:
>> On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote:
>>> Hi all,
>>> 
>>> This patch series adds support SATA for BMIPS_GENERIC.
>>> 
>>> Ralf,
>>> I request you to drop already submitted patches for NAND device nodes.
>>> It is merge conflicts with this patches.
>>> http://patchwork.linux-mips.org/patch/10577/
>>> http://patchwork.linux-mips.org/patch/10578/
>>> http://patchwork.linux-mips.org/patch/10579/
>>> http://patchwork.linux-mips.org/patch/10580/
>>> 
>>> Jaedon Shin (10):
>>>  ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
>>>  ata: ahch_brcmstb: add data for port offset
>>>  ata: ahci_brcmstb: add support 40nm platforms
>> 
>> ata part looks fine to me.  Let me know when the other parts get in.
>> I'll apply the ata ones to libata/for-4.4.
> 
> There are a few comments coming on the ATA and Device Tree part, and I
> also would like Brian Norris (who submitted the patches) to take a
> look at these. But overall, this looks great.
> 
> I think we have a bit too many compatible strings defined, I need to
> lookup tomorrow when I am back in the office which BCM7xxx started
> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
> sure
> 

I agree with you. If you have good opinion, I want you to tell me.

> Thanks!
> -- 
> Florian

I will review carefully and submit v2 revision.

Regards,

Jaedon

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Florian Fainelli]

Le 23/10/2015 21:51, Jaedon Shin a écrit :
> On Oct 23, 2015, at 1:51 PM, Florian Fainelli <f.fainelli@gmail.com> wrote:
>>
>> 2015-10-22 20:58 GMT-07:00 Tejun Heo <tj@kernel.org>:
>>> On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote:
>>>> Hi all,
>>>>
>>>> This patch series adds support SATA for BMIPS_GENERIC.
>>>>
>>>> Ralf,
>>>> I request you to drop already submitted patches for NAND device nodes.
>>>> It is merge conflicts with this patches.
>>>> http://patchwork.linux-mips.org/patch/10577/
>>>> http://patchwork.linux-mips.org/patch/10578/
>>>> http://patchwork.linux-mips.org/patch/10579/
>>>> http://patchwork.linux-mips.org/patch/10580/
>>>>
>>>> Jaedon Shin (10):
>>>>  ata: ahci_brcmstb: make the driver buildable on BMIPS_GENERIC
>>>>  ata: ahch_brcmstb: add data for port offset
>>>>  ata: ahci_brcmstb: add support 40nm platforms
>>>
>>> ata part looks fine to me.  Let me know when the other parts get in.
>>> I'll apply the ata ones to libata/for-4.4.
>>
>> There are a few comments coming on the ATA and Device Tree part, and I
>> also would like Brian Norris (who submitted the patches) to take a
>> look at these. But overall, this looks great.
>>
>> I think we have a bit too many compatible strings defined, I need to
>> lookup tomorrow when I am back in the office which BCM7xxx started
>> featuring a SATA3 AHCI compliant core, it might be 7420, but I am not
>> sure
>>
> 
> I agree with you. If you have good opinion, I want you to tell me.

Based on Kevin's feedback, we should be using 7425 as the compatible
string for these AHCI controllers.

Thanks!
-- 
Florian

Re: [PATCH 03/10] ata: ahci_brcmstb: add support 40nm platforms

[Brian Norris]

Hi Jaedon,

On Sat, Oct 24, 2015 at 01:50:54PM +0900, Jaedon Shin wrote:
> On Oct 24, 2015, at 6:25 AM, Brian Norris <computersforpeace@gmail.com> wrote:
> > On Fri, Oct 23, 2015 at 10:44:16AM +0900, Jaedon Shin wrote:
> > So, your patch gets phy control 1 correct for both ports, but it doesn't
> > get phy control 2 correct. (Or at least, even if my guess at the 40nm
> > layout is wrong, your patch makes "port 0, phy control 2" collide with
> > "port 1, phy control 1", which is most certainly a bug.)
> > 
> > Are you sure you're testing this properly? Did you try using both ports
> > at the same time? And please, apply the same scrutiny to the PHY driver.
> > (e.g., did you test SSC? did you test both ports?)
> > 
> > Brian
> > 
> 
> You are right. This must be changed. 
> 
> I found the 28nm chipsets have four phy interface control registers. But, 
> the the 40nm chipsets have only three registers. I did not testing with 
> two ports at the same time. It seems we should check more.

OK. So you don't just need more testing, you need to make sure the code
actually matches the documentation at all. If there are only 3 PHY
control registers for 40nm, then this driver (as patched by you) doesn't
make any sense. It will need a much different patch than what you gave.

Brian

Re: [PATCH 00/10] add support SATA for BMIPS_GENERIC

[Ralf Baechle]

On Fri, Oct 23, 2015 at 10:44:13AM +0900, Jaedon Shin wrote:

> Ralf,
> I request you to drop already submitted patches for NAND device nodes.
> It is merge conflicts with this patches.
> http://patchwork.linux-mips.org/patch/10577/
> http://patchwork.linux-mips.org/patch/10578/
> http://patchwork.linux-mips.org/patch/10579/
> http://patchwork.linux-mips.org/patch/10580/

Done - but you can drop patches you have submitted from patchwork yourself.

  Ralf