* [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
@ 2020-02-26 11:15 ` H. Nikolaus Schaller
2020-02-27 14:47 ` Paul Cercueil
2020-02-26 11:15 ` [PATCH v6 2/6] Bindings: nvmem: add bindings " H. Nikolaus Schaller
` (4 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:15 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and nvmem cells.
To fetch for example the MAC address:
dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/nvmem/Kconfig | 12 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/jz4780-efuse.c | 239 +++++++++++++++++++++++++++++++++++
3 files changed, 253 insertions(+)
create mode 100644 drivers/nvmem/jz4780-efuse.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 35efab1ba8d9..d7b7f6d688e7 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
This is a driver for the SCU On-Chip OTP Controller (OCOTP)
available on i.MX8 SoCs.
+config JZ4780_EFUSE
+ tristate "JZ4780 EFUSE Memory Support"
+ depends on MACH_INGENIC || COMPILE_TEST
+ depends on HAS_IOMEM
+ depends on OF
+ select REGMAP_MMIO
+ help
+ Say Y here to include support for JZ4780 efuse memory found on
+ all JZ4780 SoC based devices.
+ To compile this driver as a module, choose M here: the module
+ will be called nvmem_jz4780_efuse.
+
config NVMEM_LPC18XX_EEPROM
tristate "NXP LPC18XX EEPROM Memory Support"
depends on ARCH_LPC18XX || COMPILE_TEST
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 6b466cd1427b..65a268d17807 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
nvmem-imx-ocotp-y := imx-ocotp.o
obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o
nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o
+obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o
+nvmem_jz4780_efuse-y := jz4780-efuse.o
obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o
obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o
diff --git a/drivers/nvmem/jz4780-efuse.c b/drivers/nvmem/jz4780-efuse.c
new file mode 100644
index 000000000000..4b8077a8d251
--- /dev/null
+++ b/drivers/nvmem/jz4780-efuse.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * JZ4780 EFUSE Memory Support driver
+ *
+ * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+ * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
+ */
+
+/*
+ * Currently supports JZ4780 efuse which has 8K programmable bit.
+ * Efuse is separated into seven segments as below:
+ *
+ * -----------------------------------------------------------------------
+ * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
+ * -----------------------------------------------------------------------
+ *
+ * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
+ * which reads/writes based on strobes. The strobe is configured in the config
+ * register and is based on number of cycles of the bus clock.
+ *
+ * Driver supports read only as the writes are done in the Factory.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/timer.h>
+
+#define JZ_EFUCTRL (0x0) /* Control Register */
+#define JZ_EFUCFG (0x4) /* Configure Register*/
+#define JZ_EFUSTATE (0x8) /* Status Register */
+#define JZ_EFUDATA(n) (0xC + (n) * 4)
+
+/* We read 32 byte chunks to avoid complexity in the driver. */
+#define JZ_EFU_READ_SIZE 32
+
+#define EFUCTRL_ADDR_MASK 0x3FF
+#define EFUCTRL_ADDR_SHIFT 21
+#define EFUCTRL_LEN_MASK 0x1F
+#define EFUCTRL_LEN_SHIFT 16
+#define EFUCTRL_PG_EN BIT(15)
+#define EFUCTRL_WR_EN BIT(1)
+#define EFUCTRL_RD_EN BIT(0)
+
+#define EFUCFG_INT_EN BIT(31)
+#define EFUCFG_RD_ADJ_MASK 0xF
+#define EFUCFG_RD_ADJ_SHIFT 20
+#define EFUCFG_RD_STR_MASK 0xF
+#define EFUCFG_RD_STR_SHIFT 16
+#define EFUCFG_WR_ADJ_MASK 0xF
+#define EFUCFG_WR_ADJ_SHIFT 12
+#define EFUCFG_WR_STR_MASK 0xFFF
+#define EFUCFG_WR_STR_SHIFT 0
+
+#define EFUSTATE_WR_DONE BIT(1)
+#define EFUSTATE_RD_DONE BIT(0)
+
+struct jz4780_efuse {
+ struct device *dev;
+ struct regmap *map;
+ struct clk *clk;
+};
+
+/* main entry point */
+static int jz4780_efuse_read(void *context, unsigned int offset,
+ void *val, size_t bytes)
+{
+ struct jz4780_efuse *efuse = context;
+
+ while (bytes > 0) {
+ unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1);
+ unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
+ - offset);
+ char buf[JZ_EFU_READ_SIZE];
+ unsigned int tmp;
+ u32 ctrl;
+ int ret;
+
+ ctrl = (start << EFUCTRL_ADDR_SHIFT)
+ | ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
+ | EFUCTRL_RD_EN;
+
+ regmap_update_bits(efuse->map, JZ_EFUCTRL,
+ (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
+ (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
+ EFUCTRL_PG_EN | EFUCTRL_WR_EN |
+ EFUCTRL_RD_EN,
+ ctrl);
+
+ ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
+ tmp, tmp & EFUSTATE_RD_DONE,
+ 1 * MSEC_PER_SEC,
+ 50 * MSEC_PER_SEC);
+ if (ret < 0) {
+ dev_err(efuse->dev, "Time out while reading efuse data");
+ return ret;
+ }
+
+ ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
+ buf, JZ_EFU_READ_SIZE / sizeof(u32));
+ if (ret < 0)
+ return ret;
+
+ memcpy(val, &buf[offset - start], chunk);
+
+ val += chunk;
+ offset += chunk;
+ bytes -= chunk;
+ }
+
+ return 0;
+}
+
+static struct nvmem_config jz4780_efuse_nvmem_config = {
+ .name = "jz4780-efuse",
+ .size = 1024,
+ .word_size = 1,
+ .stride = 1,
+ .owner = THIS_MODULE,
+ .reg_read = jz4780_efuse_read,
+};
+
+static const struct regmap_config jz4780_efuse_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = JZ_EFUDATA(7),
+};
+
+static int jz4780_efuse_probe(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem;
+ struct jz4780_efuse *efuse;
+ struct nvmem_config cfg;
+ unsigned long clk_rate;
+ unsigned long rd_adj;
+ unsigned long rd_strobe;
+ struct device *dev = &pdev->dev;
+ void __iomem *regs;
+ int ret;
+
+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
+ if (!efuse)
+ return -ENOMEM;
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ efuse->map = devm_regmap_init_mmio(dev, regs,
+ &jz4780_efuse_regmap_config);
+ if (IS_ERR(efuse->map))
+ return PTR_ERR(efuse->map);
+
+ efuse->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(efuse->clk))
+ return PTR_ERR(efuse->clk);
+
+ ret = clk_prepare_enable(efuse->clk);
+ if (ret < 0)
+ return ret;
+
+ clk_rate = clk_get_rate(efuse->clk);
+
+ efuse->dev = dev;
+
+ /*
+ * rd_adj and rd_strobe are 4 bit values
+ * conditions:
+ * bus clk_period * (rd_adj + 1) > 6.5ns
+ * bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
+ * i.e. rd_adj >= 6.5ns / clk_period
+ * i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
+ * constants:
+ * 1 / 6.5ns == 153846154 Hz
+ * 1 / 35ns == 28571429 Hz
+ */
+
+ rd_adj = clk_rate / 153846154;
+ rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
+
+ if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {
+ dev_err(&pdev->dev, "Cannot set clock configuration\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(efuse->map, JZ_EFUCFG,
+ (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
+ (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
+ (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
+ (rd_strobe << EFUCFG_RD_STR_SHIFT));
+
+ cfg = jz4780_efuse_nvmem_config;
+ cfg.dev = &pdev->dev;
+ cfg.priv = efuse;
+
+ nvmem = devm_nvmem_register(dev, &cfg);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
+ platform_set_drvdata(pdev, efuse);
+
+ return 0;
+}
+
+static int jz4780_efuse_remove(struct platform_device *pdev)
+{
+ struct jz4780_efuse *efuse = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(efuse->clk);
+
+ return 0;
+}
+
+static const struct of_device_id jz4780_efuse_match[] = {
+ { .compatible = "ingenic,jz4780-efuse" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
+
+static struct platform_driver jz4780_efuse_driver = {
+ .probe = jz4780_efuse_probe,
+ .remove = jz4780_efuse_remove,
+ .driver = {
+ .name = "jz4780-efuse",
+ .of_match_table = jz4780_efuse_match,
+ },
+};
+module_platform_driver(jz4780_efuse_driver);
+
+MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
+MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
+MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
+MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
+MODULE_LICENSE("GPL v2");
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse
2020-02-26 11:15 ` [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse H. Nikolaus Schaller
@ 2020-02-27 14:47 ` Paul Cercueil
2020-02-27 15:26 ` H. Nikolaus Schaller
0 siblings, 1 reply; 15+ messages in thread
From: Paul Cercueil @ 2020-02-27 14:47 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Hi Nikolaus,
Le mer., févr. 26, 2020 at 12:15, H. Nikolaus Schaller
<hns@goldelico.com> a écrit :
> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>
> This patch brings support for the JZ4780 efuse. Currently it only
> exposes
> a read only access to the entire 8K bits efuse memory and nvmem cells.
>
> To fetch for example the MAC address:
>
> dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1
> skip=34 count=6 status=none | xxd
>
> Tested-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
> drivers/nvmem/Kconfig | 12 ++
> drivers/nvmem/Makefile | 2 +
> drivers/nvmem/jz4780-efuse.c | 239
> +++++++++++++++++++++++++++++++++++
> 3 files changed, 253 insertions(+)
> create mode 100644 drivers/nvmem/jz4780-efuse.c
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 35efab1ba8d9..d7b7f6d688e7 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
> This is a driver for the SCU On-Chip OTP Controller (OCOTP)
> available on i.MX8 SoCs.
>
> +config JZ4780_EFUSE
> + tristate "JZ4780 EFUSE Memory Support"
> + depends on MACH_INGENIC || COMPILE_TEST
> + depends on HAS_IOMEM
> + depends on OF
> + select REGMAP_MMIO
> + help
> + Say Y here to include support for JZ4780 efuse memory found on
> + all JZ4780 SoC based devices.
> + To compile this driver as a module, choose M here: the module
> + will be called nvmem_jz4780_efuse.
> +
> config NVMEM_LPC18XX_EEPROM
> tristate "NXP LPC18XX EEPROM Memory Support"
> depends on ARCH_LPC18XX || COMPILE_TEST
> diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> index 6b466cd1427b..65a268d17807 100644
> --- a/drivers/nvmem/Makefile
> +++ b/drivers/nvmem/Makefile
> @@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
> nvmem-imx-ocotp-y := imx-ocotp.o
> obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o
> nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o
> +obj-$(CONFIG_JZ4780_EFUSE) += nvmem_jz4780_efuse.o
> +nvmem_jz4780_efuse-y := jz4780-efuse.o
> obj-$(CONFIG_NVMEM_LPC18XX_EEPROM) += nvmem_lpc18xx_eeprom.o
> nvmem_lpc18xx_eeprom-y := lpc18xx_eeprom.o
> obj-$(CONFIG_NVMEM_LPC18XX_OTP) += nvmem_lpc18xx_otp.o
> diff --git a/drivers/nvmem/jz4780-efuse.c
> b/drivers/nvmem/jz4780-efuse.c
> new file mode 100644
> index 000000000000..4b8077a8d251
> --- /dev/null
> +++ b/drivers/nvmem/jz4780-efuse.c
> @@ -0,0 +1,239 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * JZ4780 EFUSE Memory Support driver
> + *
> + * Copyright (c) 2017 PrasannaKumar Muralidharan
> <prasannatsmkumar@gmail.com>
> + * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
> + */
> +
> +/*
> + * Currently supports JZ4780 efuse which has 8K programmable bit.
> + * Efuse is separated into seven segments as below:
> + *
> + *
> -----------------------------------------------------------------------
> + * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048
> bit |
> + *
> -----------------------------------------------------------------------
> + *
> + * The rom itself is accessed using a 9 bit address line and an 8
> word wide bus
> + * which reads/writes based on strobes. The strobe is configured in
> the config
> + * register and is based on number of cycles of the bus clock.
> + *
> + * Driver supports read only as the writes are done in the Factory.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/timer.h>
> +
> +#define JZ_EFUCTRL (0x0) /* Control Register */
> +#define JZ_EFUCFG (0x4) /* Configure Register*/
> +#define JZ_EFUSTATE (0x8) /* Status Register */
> +#define JZ_EFUDATA(n) (0xC + (n) * 4)
> +
> +/* We read 32 byte chunks to avoid complexity in the driver. */
> +#define JZ_EFU_READ_SIZE 32
> +
> +#define EFUCTRL_ADDR_MASK 0x3FF
> +#define EFUCTRL_ADDR_SHIFT 21
> +#define EFUCTRL_LEN_MASK 0x1F
> +#define EFUCTRL_LEN_SHIFT 16
> +#define EFUCTRL_PG_EN BIT(15)
> +#define EFUCTRL_WR_EN BIT(1)
> +#define EFUCTRL_RD_EN BIT(0)
> +
> +#define EFUCFG_INT_EN BIT(31)
> +#define EFUCFG_RD_ADJ_MASK 0xF
> +#define EFUCFG_RD_ADJ_SHIFT 20
> +#define EFUCFG_RD_STR_MASK 0xF
> +#define EFUCFG_RD_STR_SHIFT 16
> +#define EFUCFG_WR_ADJ_MASK 0xF
> +#define EFUCFG_WR_ADJ_SHIFT 12
> +#define EFUCFG_WR_STR_MASK 0xFFF
> +#define EFUCFG_WR_STR_SHIFT 0
> +
> +#define EFUSTATE_WR_DONE BIT(1)
> +#define EFUSTATE_RD_DONE BIT(0)
> +
> +struct jz4780_efuse {
> + struct device *dev;
> + struct regmap *map;
> + struct clk *clk;
> +};
> +
> +/* main entry point */
> +static int jz4780_efuse_read(void *context, unsigned int offset,
> + void *val, size_t bytes)
> +{
> + struct jz4780_efuse *efuse = context;
> +
> + while (bytes > 0) {
> + unsigned int start = offset & ~(JZ_EFU_READ_SIZE - 1);
> + unsigned int chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
> + - offset);
> + char buf[JZ_EFU_READ_SIZE];
> + unsigned int tmp;
> + u32 ctrl;
> + int ret;
> +
> + ctrl = (start << EFUCTRL_ADDR_SHIFT)
> + | ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
> + | EFUCTRL_RD_EN;
> +
> + regmap_update_bits(efuse->map, JZ_EFUCTRL,
> + (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
> + (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
> + EFUCTRL_PG_EN | EFUCTRL_WR_EN |
> + EFUCTRL_RD_EN,
> + ctrl);
> +
> + ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
> + tmp, tmp & EFUSTATE_RD_DONE,
> + 1 * MSEC_PER_SEC,
> + 50 * MSEC_PER_SEC);
> + if (ret < 0) {
> + dev_err(efuse->dev, "Time out while reading efuse data");
> + return ret;
> + }
> +
> + ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
> + buf, JZ_EFU_READ_SIZE / sizeof(u32));
> + if (ret < 0)
> + return ret;
> +
> + memcpy(val, &buf[offset - start], chunk);
> +
> + val += chunk;
> + offset += chunk;
> + bytes -= chunk;
> + }
> +
> + return 0;
> +}
> +
> +static struct nvmem_config jz4780_efuse_nvmem_config = {
> + .name = "jz4780-efuse",
> + .size = 1024,
> + .word_size = 1,
> + .stride = 1,
> + .owner = THIS_MODULE,
> + .reg_read = jz4780_efuse_read,
> +};
> +
> +static const struct regmap_config jz4780_efuse_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .max_register = JZ_EFUDATA(7),
> +};
> +
> +static int jz4780_efuse_probe(struct platform_device *pdev)
> +{
> + struct nvmem_device *nvmem;
> + struct jz4780_efuse *efuse;
> + struct nvmem_config cfg;
> + unsigned long clk_rate;
> + unsigned long rd_adj;
> + unsigned long rd_strobe;
> + struct device *dev = &pdev->dev;
> + void __iomem *regs;
> + int ret;
> +
> + efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
> + if (!efuse)
> + return -ENOMEM;
> +
> + regs = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(regs))
> + return PTR_ERR(regs);
> +
> + efuse->map = devm_regmap_init_mmio(dev, regs,
> + &jz4780_efuse_regmap_config);
> + if (IS_ERR(efuse->map))
> + return PTR_ERR(efuse->map);
> +
> + efuse->clk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(efuse->clk))
> + return PTR_ERR(efuse->clk);
> +
> + ret = clk_prepare_enable(efuse->clk);
> + if (ret < 0)
> + return ret;
> +
> + clk_rate = clk_get_rate(efuse->clk);
> +
> + efuse->dev = dev;
> +
> + /*
> + * rd_adj and rd_strobe are 4 bit values
> + * conditions:
> + * bus clk_period * (rd_adj + 1) > 6.5ns
> + * bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
> + * i.e. rd_adj >= 6.5ns / clk_period
> + * i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
> + * constants:
> + * 1 / 6.5ns == 153846154 Hz
> + * 1 / 35ns == 28571429 Hz
> + */
> +
> + rd_adj = clk_rate / 153846154;
> + rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
> +
> + if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {
Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1
> + dev_err(&pdev->dev, "Cannot set clock configuration\n");
> + return -EINVAL;
You need to clk_disable_unprepare() before you return now, since the
clock has been enabled. I'd suggest registering a cleanup function
(with devm_add_action_or_reset) after clk_prepare_enable() is called,
then you don't need extra handling in the rest of the probe, and the
.remove function (and platform_set_drvdata) can be dropped too.
The rest looks pretty good.
Cheers,
-Paul
> + }
> +
> + regmap_update_bits(efuse->map, JZ_EFUCFG,
> + (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
> + (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
> + (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
> + (rd_strobe << EFUCFG_RD_STR_SHIFT));
> +
> + cfg = jz4780_efuse_nvmem_config;
> + cfg.dev = &pdev->dev;
> + cfg.priv = efuse;
> +
> + nvmem = devm_nvmem_register(dev, &cfg);
> + if (IS_ERR(nvmem))
> + return PTR_ERR(nvmem);
> +
> + platform_set_drvdata(pdev, efuse);
> +
> + return 0;
> +}
> +
> +static int jz4780_efuse_remove(struct platform_device *pdev)
> +{
> + struct jz4780_efuse *efuse = platform_get_drvdata(pdev);
> +
> + clk_disable_unprepare(efuse->clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id jz4780_efuse_match[] = {
> + { .compatible = "ingenic,jz4780-efuse" },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
> +
> +static struct platform_driver jz4780_efuse_driver = {
> + .probe = jz4780_efuse_probe,
> + .remove = jz4780_efuse_remove,
> + .driver = {
> + .name = "jz4780-efuse",
> + .of_match_table = jz4780_efuse_match,
> + },
> +};
> +module_platform_driver(jz4780_efuse_driver);
> +
> +MODULE_AUTHOR("PrasannaKumar Muralidharan
> <prasannatsmkumar@gmail.com>");
> +MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
> +MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
> +MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.23.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse
2020-02-27 14:47 ` Paul Cercueil
@ 2020-02-27 15:26 ` H. Nikolaus Schaller
2020-02-28 12:16 ` H. Nikolaus Schaller
0 siblings, 1 reply; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-27 15:26 UTC (permalink / raw)
To: Paul Cercueil
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Hi Paul,
> Am 27.02.2020 um 15:47 schrieb Paul Cercueil <paul@crapouillou.net>:
>
> Hi Nikolaus,
>
>
> Le mer., févr. 26, 2020 at 12:15, H. Nikolaus Schaller <hns@goldelico.com> a écrit :
>> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> This patch brings support for the JZ4780 efuse. Currently it only exposes
>> a read only access to the entire 8K bits efuse memory and nvmem cells.
>> To fetch for example the MAC address:
>> dd if=/sys/devices/platform/134100d0.efuse/jz4780-efuse0/nvmem bs=1 skip=34 count=6 status=none | xxd
>> Tested-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> Signed-off-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>> ---
>> drivers/nvmem/Kconfig | 12 ++
>> drivers/nvmem/Makefile | 2 +
>> drivers/nvmem/jz4780-efuse.c | 239 +++++++++++++++++++++++++++++++++++
>> 3 files changed, 253 insertions(+)
>> create mode 100644 drivers/nvmem/jz4780-efuse.c
>> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
>> index 35efab1ba8d9..d7b7f6d688e7 100644
>> --- a/drivers/nvmem/Kconfig
>> +++ b/drivers/nvmem/Kconfig
>> @@ -55,6 +55,18 @@ config NVMEM_IMX_OCOTP_SCU
>> + clk_rate = clk_get_rate(efuse->clk);
>> +
>> + efuse->dev = dev;
>> +
>> + /*
>> + * rd_adj and rd_strobe are 4 bit values
>> + * conditions:
>> + * bus clk_period * (rd_adj + 1) > 6.5ns
>> + * bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
>> + * i.e. rd_adj >= 6.5ns / clk_period
>> + * i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
>> + * constants:
>> + * 1 / 6.5ns == 153846154 Hz
>> + * 1 / 35ns == 28571429 Hz
>> + */
>> +
>> + rd_adj = clk_rate / 153846154;
>> + rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
>> +
>> + if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {
>
> Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1
Or would rd_adj >= BIT(4) be better since this is not used as a mask?
This would also correspond to that the register is 4 bits wide.
>
>> + dev_err(&pdev->dev, "Cannot set clock configuration\n");
>> + return -EINVAL;
>
> You need to clk_disable_unprepare() before you return now, since the clock has been enabled.
Ah, ok! Forgot about that.
> I'd suggest registering a cleanup function (with devm_add_action_or_reset) after clk_prepare_enable() is called, then you don't need extra handling in the rest of the probe, and the .remove function (and platform_set_drvdata) can be dropped too.
Ok, this will indeed be simpler that the remove function if we take the error path into account.
Noted for v7.
>
> The rest looks pretty good.
>
> Cheers,
> -Paul
BR,
Nikolaus
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse
2020-02-27 15:26 ` H. Nikolaus Schaller
@ 2020-02-28 12:16 ` H. Nikolaus Schaller
0 siblings, 0 replies; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-28 12:16 UTC (permalink / raw)
To: Paul Cercueil
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
>>> + rd_adj = clk_rate / 153846154;
>>> + rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
>>> +
>>> + if (rd_adj > BIT(4) - 1 || rd_strobe > BIT(4) - 1) {
>>
>> Just use 0xF or GENMASK(3, 0) instead of BIT(4) - 1
>
> Or would rd_adj >= BIT(4) be better since this is not used as a mask?
> This would also correspond to that the register is 4 bits wide.
I just recognized that we already have these constants defined:
So I'll add
if (rd_adj > EFUCFG_RD_ADJ_MASK || rd_strobe > EFUCFG_RD_STR_MASK) {
to v7.
BR,
Nikolaus
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 2/6] Bindings: nvmem: add bindings for JZ4780 efuse
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
2020-02-26 11:15 ` [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse H. Nikolaus Schaller
@ 2020-02-26 11:15 ` H. Nikolaus Schaller
2020-02-27 14:49 ` Paul Cercueil
2020-02-26 11:15 ` [PATCH v6 3/6] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI H. Nikolaus Schaller
` (3 subsequent siblings)
5 siblings, 1 reply; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:15 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
[converted to yaml]
Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
.../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
new file mode 100644
index 000000000000..b9c0ea09b335
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic JZ EFUSE driver bindings
+
+maintainers:
+ - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+
+allOf:
+ - $ref: "nvmem.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4780-efuse
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ # Handle for the ahb for the efuse.
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ahb2
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+
+ efuse@134100d0 {
+ compatible = "ingenic,jz4780-efuse";
+ reg = <0x134100d0 0x2c>;
+
+ clocks = <&cgu JZ4780_CLK_AHB2>;
+ clock-names = "ahb2";
+ };
+
+...
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 2/6] Bindings: nvmem: add bindings for JZ4780 efuse
2020-02-26 11:15 ` [PATCH v6 2/6] Bindings: nvmem: add bindings " H. Nikolaus Schaller
@ 2020-02-27 14:49 ` Paul Cercueil
2020-02-27 14:55 ` H. Nikolaus Schaller
0 siblings, 1 reply; 15+ messages in thread
From: Paul Cercueil @ 2020-02-27 14:49 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Hi Nikolaus,
Le mer., févr. 26, 2020 at 12:15, H. Nikolaus Schaller
<hns@goldelico.com> a écrit :
> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>
> This patch brings support for the JZ4780 efuse. Currently it only
> exposes
> a read only access to the entire 8K bits efuse memory.
>
> Tested-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> [converted to yaml]
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> ---
> .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50
> +++++++++++++++++++
> 1 file changed, 50 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
> b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
> new file mode 100644
> index 000000000000..b9c0ea09b335
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
> @@ -0,0 +1,50 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Ingenic JZ EFUSE driver bindings
> +
> +maintainers:
> + - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> +
> +allOf:
> + - $ref: "nvmem.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - ingenic,jz4780-efuse
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + # Handle for the ahb for the efuse.
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: ahb2
Your driver does not actually require the clock to be 'ahb2', it will
take the first clock independently of its name. So 'clock-names' can be
dropped.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/jz4780-cgu.h>
> +
> + efuse@134100d0 {
> + compatible = "ingenic,jz4780-efuse";
> + reg = <0x134100d0 0x2c>;
> +
> + clocks = <&cgu JZ4780_CLK_AHB2>;
> + clock-names = "ahb2";
Same here.
Cheers,
-Paul
> + };
> +
> +...
> --
> 2.23.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 2/6] Bindings: nvmem: add bindings for JZ4780 efuse
2020-02-27 14:49 ` Paul Cercueil
@ 2020-02-27 14:55 ` H. Nikolaus Schaller
0 siblings, 0 replies; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-27 14:55 UTC (permalink / raw)
To: Paul Cercueil
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
> Am 27.02.2020 um 15:49 schrieb Paul Cercueil <paul@crapouillou.net>:
>
> Hi Nikolaus,
>
>
> Le mer., févr. 26, 2020 at 12:15, H. Nikolaus Schaller <hns@goldelico.com> a écrit :
>> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> This patch brings support for the JZ4780 efuse. Currently it only exposes
>> a read only access to the entire 8K bits efuse memory.
>> Tested-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> Signed-off-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> [converted to yaml]
>> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
>> ---
>> .../bindings/nvmem/ingenic,jz4780-efuse.yaml | 50 +++++++++++++++++++
>> 1 file changed, 50 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
>> diff --git a/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
>> new file mode 100644
>> index 000000000000..b9c0ea09b335
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/nvmem/ingenic,jz4780-efuse.yaml
>> @@ -0,0 +1,50 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Ingenic JZ EFUSE driver bindings
>> +
>> +maintainers:
>> + - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> +
>> +allOf:
>> + - $ref: "nvmem.yaml#"
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - ingenic,jz4780-efuse
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + # Handle for the ahb for the efuse.
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: ahb2
>
> Your driver does not actually require the clock to be 'ahb2', it will take the first clock independently of its name. So 'clock-names' can be dropped.
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/jz4780-cgu.h>
>> +
>> + efuse@134100d0 {
>> + compatible = "ingenic,jz4780-efuse";
>> + reg = <0x134100d0 0x2c>;
>> +
>> + clocks = <&cgu JZ4780_CLK_AHB2>;
>> + clock-names = "ahb2";
>
> Same here.
Ok! Will also update in the real .dts.
BR and thanks,
Nikolaus
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 3/6] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
2020-02-26 11:15 ` [PATCH v6 1/6] nvmem: add driver for JZ4780 efuse H. Nikolaus Schaller
2020-02-26 11:15 ` [PATCH v6 2/6] Bindings: nvmem: add bindings " H. Nikolaus Schaller
@ 2020-02-26 11:15 ` H. Nikolaus Schaller
2020-02-26 11:15 ` [PATCH v6 4/6] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver H. Nikolaus Schaller
` (2 subsequent siblings)
5 siblings, 0 replies; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:15 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
---
.../ABI/testing/sysfs-driver-jz4780-efuse | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-jz4780-efuse
diff --git a/Documentation/ABI/testing/sysfs-driver-jz4780-efuse b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse
new file mode 100644
index 000000000000..bb6f5d6ceea0
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-jz4780-efuse
@@ -0,0 +1,16 @@
+What: /sys/devices/*/<our-device>/nvmem
+Date: December 2017
+Contact: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+Description: read-only access to the efuse on the Ingenic JZ4780 SoC
+ The SoC has a one time programmable 8K efuse that is
+ split into segments. The driver supports read only.
+ The segments are
+ 0x000 64 bit Random Number
+ 0x008 128 bit Ingenic Chip ID
+ 0x018 128 bit Customer ID
+ 0x028 3520 bit Reserved
+ 0x1E0 8 bit Protect Segment
+ 0x1E1 2296 bit HDMI Key
+ 0x300 2048 bit Security boot key
+Users: any user space application which wants to read the Chip
+ and Customer ID
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 4/6] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
` (2 preceding siblings ...)
2020-02-26 11:15 ` [PATCH v6 3/6] Documentation: ABI: nvmem: add documentation for JZ4780 efuse ABI H. Nikolaus Schaller
@ 2020-02-26 11:15 ` H. Nikolaus Schaller
2020-02-26 11:16 ` [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse H. Nikolaus Schaller
2020-02-26 11:16 ` [PATCH v6 6/6] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address H. Nikolaus Schaller
5 siblings, 0 replies; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:15 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory.
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index fcd79fc38928..fcb8d89c2b2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8271,6 +8271,11 @@ M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
S: Maintained
F: drivers/dma/dma-jz4780.c
+INGENIC JZ4780 EFUSE Driver
+M: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
+S: Maintained
+F: drivers/nvmem/jz4780-efuse.c
+
INGENIC JZ4780 NAND DRIVER
M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mtd@lists.infradead.org
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
` (3 preceding siblings ...)
2020-02-26 11:15 ` [PATCH v6 4/6] nvmem: MAINTAINERS: add maintainer for JZ4780 efuse driver H. Nikolaus Schaller
@ 2020-02-26 11:16 ` H. Nikolaus Schaller
2020-02-27 14:57 ` Paul Cercueil
2020-02-26 11:16 ` [PATCH v6 6/6] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address H. Nikolaus Schaller
5 siblings, 1 reply; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:16 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
This patch brings support for the JZ4780 efuse. Currently it only exposes
a read only access to the entire 8K bits efuse memory and the
ethernet mac address for the davicom dm9000 chip on the CI20 board.
It also changes the nemc reg range to avoid overlap.
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
Signed-off-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index f928329b034b..1e266be28096 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -358,7 +358,7 @@
nemc: nemc@13410000 {
compatible = "ingenic,jz4780-nemc";
- reg = <0x13410000 0x10000>;
+ reg = <0x13410000 0x4c>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <1 0 0x1b000000 0x1000000
@@ -373,6 +373,21 @@
status = "disabled";
};
+ efuse: efuse@134100d0 {
+ compatible = "ingenic,jz4780-efuse";
+ reg = <0x134100d0 0x2c>;
+
+ clocks = <&cgu JZ4780_CLK_AHB2>;
+ clock-names = "ahb2";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eth0_addr: eth-mac-addr@0x22 {
+ reg = <0x22 0x6>;
+ };
+ };
+
dma: dma@13420000 {
compatible = "ingenic,jz4780-dma";
reg = <0x13420000 0x400
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse
2020-02-26 11:16 ` [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse H. Nikolaus Schaller
@ 2020-02-27 14:57 ` Paul Cercueil
2020-02-27 15:26 ` H. Nikolaus Schaller
0 siblings, 1 reply; 15+ messages in thread
From: Paul Cercueil @ 2020-02-27 14:57 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Hi Nikolaus,
Le mer., févr. 26, 2020 at 12:16, H. Nikolaus Schaller
<hns@goldelico.com> a écrit :
> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>
> This patch brings support for the JZ4780 efuse. Currently it only
> exposes
> a read only access to the entire 8K bits efuse memory and the
> ethernet mac address for the davicom dm9000 chip on the CI20 board.
>
> It also changes the nemc reg range to avoid overlap.
>
> Tested-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
> ---
> arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> index f928329b034b..1e266be28096 100644
> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
> @@ -358,7 +358,7 @@
>
> nemc: nemc@13410000 {
> compatible = "ingenic,jz4780-nemc";
> - reg = <0x13410000 0x10000>;
> + reg = <0x13410000 0x4c>;
This is wrong, the real size of the register area is 1x15c.
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <1 0 0x1b000000 0x1000000
> @@ -373,6 +373,21 @@
> status = "disabled";
> };
>
> + efuse: efuse@134100d0 {
> + compatible = "ingenic,jz4780-efuse";
> + reg = <0x134100d0 0x2c>;
> +
> + clocks = <&cgu JZ4780_CLK_AHB2>;
> + clock-names = "ahb2";
As explained in my response to the other patch, 'clock-names' can go
away.
Cheers,
-Paul
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + eth0_addr: eth-mac-addr@0x22 {
> + reg = <0x22 0x6>;
> + };
> + };
> +
> dma: dma@13420000 {
> compatible = "ingenic,jz4780-dma";
> reg = <0x13420000 0x400
> --
> 2.23.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse
2020-02-27 14:57 ` Paul Cercueil
@ 2020-02-27 15:26 ` H. Nikolaus Schaller
2020-02-27 15:39 ` Paul Cercueil
0 siblings, 1 reply; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-27 15:26 UTC (permalink / raw)
To: Paul Cercueil
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Hi Paul,
> Am 27.02.2020 um 15:57 schrieb Paul Cercueil <paul@crapouillou.net>:
>
> Hi Nikolaus,
>
>
> Le mer., févr. 26, 2020 at 12:16, H. Nikolaus Schaller <hns@goldelico.com> a écrit :
>> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> This patch brings support for the JZ4780 efuse. Currently it only exposes
>> a read only access to the entire 8K bits efuse memory and the
>> ethernet mac address for the davicom dm9000 chip on the CI20 board.
>> It also changes the nemc reg range to avoid overlap.
>> Tested-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>> Signed-off-by: Mathieu Malaterre <malat@debian.org>
>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>> ---
>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
>> 1 file changed, 16 insertions(+), 1 deletion(-)
>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> index f928329b034b..1e266be28096 100644
>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>> @@ -358,7 +358,7 @@
>> nemc: nemc@13410000 {
>> compatible = "ingenic,jz4780-nemc";
>> - reg = <0x13410000 0x10000>;
>> + reg = <0x13410000 0x4c>;
>
> This is wrong, the real size of the register area is 1x15c.
It should not overlap with the efuse reg range which is:
<0x134100d0 0x2c>
If I look at JZ4780 Mobile Application Processor Programming Manual
section 16.4.1 Register Description Table 16-4 Static Memory Interface Registers,
I see
SMCR1 at 0x13410014 and
SACR6 at 0x13410048 and all 32 bits wide. I.e. a total size of 0x4c.
Ah, now I see. There is also Table 16-5 NAND Flash Interface Registers
starting with NFCSR at 0x13410050 and ending with TGHH register at 0x13410154.
Hm. With this we are probably at "go back and start over"...
Either nemc must be separated into two drivers for Static Memory and one
for NAND Flash. Or must become able to handle two register ranges.
Or the e-fuse driver must become a part of the nemc driver.
Well, another assumption is that there is no NAND driver. AFAIR it
was even removed from the kernel because the maintainer did say
it is not fixable (if I really remember correctly).
>
>> #address-cells = <2>;
>> #size-cells = <1>;
>> ranges = <1 0 0x1b000000 0x1000000
>> @@ -373,6 +373,21 @@
>> status = "disabled";
>> };
>> + efuse: efuse@134100d0 {
>> + compatible = "ingenic,jz4780-efuse";
>> + reg = <0x134100d0 0x2c>;
>> +
>> + clocks = <&cgu JZ4780_CLK_AHB2>;
>> + clock-names = "ahb2";
>
> As explained in my response to the other patch, 'clock-names' can go away.
Yes.
BR,
Nikolaus
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse
2020-02-27 15:26 ` H. Nikolaus Schaller
@ 2020-02-27 15:39 ` Paul Cercueil
0 siblings, 0 replies; 15+ messages in thread
From: Paul Cercueil @ 2020-02-27 15:39 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: PrasannaKumar Muralidharan, Andreas Kemnade, Mathieu Malaterre,
Srinivas Kandagatla, Rob Herring, Mark Rutland, Ralf Baechle,
Paul Burton, Mauro Carvalho Chehab, David S. Miller,
Greg Kroah-Hartman, Jonathan Cameron, Krzysztof Kozlowski,
Kees Cook, Andi Kleen, Geert Uytterhoeven, linux-kernel,
devicetree, linux-mips, letux-kernel, kernel
Le jeu., févr. 27, 2020 at 16:26, H. Nikolaus Schaller
<hns@goldelico.com> a écrit :
> Hi Paul,
>
>> Am 27.02.2020 um 15:57 schrieb Paul Cercueil <paul@crapouillou.net>:
>>
>> Hi Nikolaus,
>>
>>
>> Le mer., févr. 26, 2020 at 12:16, H. Nikolaus Schaller
>> <hns@goldelico.com> a écrit :
>>> From: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
>>> This patch brings support for the JZ4780 efuse. Currently it only
>>> exposes
>>> a read only access to the entire 8K bits efuse memory and the
>>> ethernet mac address for the davicom dm9000 chip on the CI20 board.
>>> It also changes the nemc reg range to avoid overlap.
>>> Tested-by: Mathieu Malaterre <malat@debian.org>
>>> Signed-off-by: PrasannaKumar Muralidharan
>>> <prasannatsmkumar@gmail.com>
>>> Signed-off-by: Mathieu Malaterre <malat@debian.org>
>>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>>> ---
>>> arch/mips/boot/dts/ingenic/jz4780.dtsi | 17 ++++++++++++++++-
>>> 1 file changed, 16 insertions(+), 1 deletion(-)
>>> diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> index f928329b034b..1e266be28096 100644
>>> --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
>>> @@ -358,7 +358,7 @@
>>> nemc: nemc@13410000 {
>>> compatible = "ingenic,jz4780-nemc";
>>> - reg = <0x13410000 0x10000>;
>>> + reg = <0x13410000 0x4c>;
>>
>> This is wrong, the real size of the register area is 1x15c.
>
> It should not overlap with the efuse reg range which is:
>
> <0x134100d0 0x2c>
>
> If I look at JZ4780 Mobile Application Processor Programming Manual
> section 16.4.1 Register Description Table 16-4 Static Memory
> Interface Registers,
> I see
>
> SMCR1 at 0x13410014 and
> SACR6 at 0x13410048 and all 32 bits wide. I.e. a total size of 0x4c.
>
> Ah, now I see. There is also Table 16-5 NAND Flash Interface Registers
> starting with NFCSR at 0x13410050 and ending with TGHH register at
> 0x13410154.
>
> Hm. With this we are probably at "go back and start over"...
>
> Either nemc must be separated into two drivers for Static Memory and
> one
> for NAND Flash. Or must become able to handle two register ranges.
>
> Or the e-fuse driver must become a part of the nemc driver.
Nothing that bad. I'll make the NEMC driver request only the area it
needs, out of the 0x10000 register space.
Then, you can move the efuse node *inside* the nemc node (with proper
#address-cells/#size-cells/ranges and "simple-mfd" compatible string)
and everything will work.
> Well, another assumption is that there is no NAND driver. AFAIR it
> was even removed from the kernel because the maintainer did say
> it is not fixable (if I really remember correctly).
It's still there:
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
What was dropped from the kernel is MLC NAND support in UBI.
Cheers,
-Paul
>>
>>> #address-cells = <2>;
>>> #size-cells = <1>;
>>> ranges = <1 0 0x1b000000 0x1000000
>>> @@ -373,6 +373,21 @@
>>> status = "disabled";
>>> };
>>> + efuse: efuse@134100d0 {
>>> + compatible = "ingenic,jz4780-efuse";
>>> + reg = <0x134100d0 0x2c>;
>>> +
>>> + clocks = <&cgu JZ4780_CLK_AHB2>;
>>> + clock-names = "ahb2";
>>
>> As explained in my response to the other patch, 'clock-names' can
>> go away.
>
> Yes.
>
> BR,
> Nikolaus
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v6 6/6] MIPS: DTS: CI20: make DM9000 Ethernet controller use NVMEM to find the default MAC address
2020-02-26 11:15 [PATCH v6 0/6] MIPS: CI20: Add efuse driver for Ingenic JZ4780 and attach to DM9000 for stable MAC addresses H. Nikolaus Schaller
` (4 preceding siblings ...)
2020-02-26 11:16 ` [PATCH v6 5/6] MIPS: DTS: JZ4780: define node for JZ4780 efuse H. Nikolaus Schaller
@ 2020-02-26 11:16 ` H. Nikolaus Schaller
5 siblings, 0 replies; 15+ messages in thread
From: H. Nikolaus Schaller @ 2020-02-26 11:16 UTC (permalink / raw)
To: PrasannaKumar Muralidharan, Andreas Kemnade, Paul Cercueil,
Mathieu Malaterre, Srinivas Kandagatla, Rob Herring,
Mark Rutland, Ralf Baechle, Paul Burton, Mauro Carvalho Chehab,
David S. Miller, Greg Kroah-Hartman, Jonathan Cameron,
H. Nikolaus Schaller, Krzysztof Kozlowski, Kees Cook, Andi Kleen,
Geert Uytterhoeven
Cc: linux-kernel, devicetree, linux-mips, letux-kernel, kernel
There is a unique MAC address programmed into the eFuses
of the JZ4780 chip in the CI20 factory. By using this
for initializing the DM9000 Ethernet controller, every
CI20 board has an individual - but stable - MAC address
and DHCP can assign stable IP addresses.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
---
arch/mips/boot/dts/ingenic/ci20.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 37b93166bf22..6dc1f9eeff00 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -355,6 +355,9 @@
interrupt-parent = <&gpe>;
interrupts = <19 4>;
+
+ nvmem-cells = <ð0_addr>;
+ nvmem-cell-names = "mac-address";
};
};
--
2.23.0
^ permalink raw reply related [flat|nested] 15+ messages in thread