[PATCH 0/7] drm/i915: Clean up ilk+ csc stuff

[PATCH 0/7] drm/i915: Clean up ilk+ csc stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

I wanted to make some progress towards exposing more fancy gamma modes,
and actually usin them. As a start I ended up with some 30 patches
to clean up the mess that is intel_color_check(). Fortunately I can
split this up into a few mostly independent chunks. The first of which
is this series that cleans up the ilk+ csc code a bit. And I included
a small piece for the CHV CGM as well.

Ville Syrjälä (7):
  drm/i915: Readout and check csc_mode
  drm/i915: Preocmpute/readout/check CHV CGM mode
  drm/i915: Extract ilk_csc_limited_range()
  drm/i915: Clean up ilk/icl pipe/output CSC programming
  drm/i915: Extract ilk_csc_convert_ctm()
  drm/i915: Clean the csc limited range/identity programming
  drm/i915: Split ilk vs. icl csc matrix handling

 drivers/gpu/drm/i915/intel_color.c   | 384 +++++++++++++++------------
 drivers/gpu/drm/i915/intel_display.c |  11 +
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 3 files changed, 233 insertions(+), 171 deletions(-)

-- 
2.19.2

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[PATCH 1/7] drm/i915: Readout and check csc_mode

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add the missing readout and PIPE_CONF_CHECK() for csc_mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 4 ++--
 drivers/gpu/drm/i915/intel_display.c | 5 +++++
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index da7a07d5ccea..d813b9d0f5c0 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -788,6 +788,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	if (ret)
 		return ret;
 
+	crtc_state->csc_mode = 0;
+
 	/* Always allow legacy gamma LUT with no further checking. */
 	if (!crtc_state->gamma_enable ||
 	    crtc_state_is_legacy_gamma(crtc_state)) {
@@ -814,8 +816,6 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 	else
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 
-	crtc_state->csc_mode = 0;
-
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index afa21daaae51..2e4d33634e0c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9267,6 +9267,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
 		PIPECONF_GAMMA_MODE_SHIFT;
 
+	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
+
 	i9xx_get_pipe_color_config(pipe_config);
 
 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
@@ -9903,6 +9905,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode =
 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
+	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
+
 	if (INTEL_GEN(dev_priv) >= 9) {
 		u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
 
@@ -12146,6 +12150,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
 
 		PIPE_CONF_CHECK_X(gamma_mode);
+		PIPE_CONF_CHECK_X(csc_mode);
 		PIPE_CONF_CHECK_BOOL(gamma_enable);
 		PIPE_CONF_CHECK_BOOL(csc_enable);
 	}
-- 
2.19.2

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Re: [PATCH 1/7] drm/i915: Readout and check csc_mode

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 1/7] drm/i915: Readout and check csc_mode
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Add the missing readout and PIPE_CONF_CHECK() for csc_mode.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c   | 4 ++--
> drivers/gpu/drm/i915/intel_display.c | 5 +++++
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index da7a07d5ccea..d813b9d0f5c0 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -788,6 +788,8 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> 	if (ret)
> 		return ret;
>
>+	crtc_state->csc_mode = 0;
>+
> 	/* Always allow legacy gamma LUT with no further checking. */
> 	if (!crtc_state->gamma_enable ||
> 	    crtc_state_is_legacy_gamma(crtc_state)) { @@ -814,8 +816,6 @@ int
>intel_color_check(struct intel_crtc_state *crtc_state)
> 	else
> 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>
>-	crtc_state->csc_mode = 0;
>-
> 	if (INTEL_GEN(dev_priv) >= 11) {
> 		if (crtc_state->output_format ==
>INTEL_OUTPUT_FORMAT_YCBCR420 ||
> 		    crtc_state->output_format ==
>INTEL_OUTPUT_FORMAT_YCBCR444) diff --git
>a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index afa21daaae51..2e4d33634e0c 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -9267,6 +9267,8 @@ static bool ironlake_get_pipe_config(struct intel_crtc
>*crtc,
> 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK)
>>>
> 		PIPECONF_GAMMA_MODE_SHIFT;
>
>+	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
>+
> 	i9xx_get_pipe_color_config(pipe_config);
>
> 	if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { @@ -
>9903,6 +9905,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> 	pipe_config->gamma_mode =
> 		I915_READ(GAMMA_MODE(crtc->pipe)) &
>GAMMA_MODE_MODE_MASK;
>
>+	pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe));
>+
> 	if (INTEL_GEN(dev_priv) >= 9) {
> 		u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe));
>
>@@ -12146,6 +12150,7 @@ intel_pipe_config_compare(struct drm_i915_private
>*dev_priv,
> 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
>
> 		PIPE_CONF_CHECK_X(gamma_mode);
>+		PIPE_CONF_CHECK_X(csc_mode);
> 		PIPE_CONF_CHECK_BOOL(gamma_enable);
> 		PIPE_CONF_CHECK_BOOL(csc_enable);
> 	}
>--
>2.19.2

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[PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Let's precompte the CGM mode for CHV. And naturally we
also read it out and check it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c   | 28 +++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_display.c |  8 +++++++-
 drivers/gpu/drm/i915/intel_drv.h     |  9 +++++++--
 3 files changed, 35 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index d813b9d0f5c0..93428d86510a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -294,7 +294,6 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	u32 mode;
 
 	if (crtc_state->base.ctm) {
 		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
@@ -328,12 +327,7 @@ static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state
 		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
 	}
 
-	mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
-	if (!crtc_state_is_legacy_gamma(crtc_state)) {
-		mode |= (crtc_state->base.degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
-			(crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
-	}
-	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
+	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
 }
 
 /* Loads the legacy palette/gamma unit for the CRTC. */
@@ -753,6 +747,23 @@ static int check_lut_size(const struct drm_property_blob *lut, int expected)
 	return 0;
 }
 
+static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state)
+{
+	u32 cgm_mode = 0;
+
+	if (crtc_state_is_legacy_gamma(crtc_state))
+		return 0;
+
+	if (crtc_state->base.degamma_lut)
+		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
+	if (crtc_state->base.ctm)
+		cgm_mode |= CGM_PIPE_MODE_CSC;
+	if (crtc_state->base.gamma_lut)
+		cgm_mode |= CGM_PIPE_MODE_GAMMA;
+
+	return cgm_mode;
+}
+
 int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@@ -790,6 +801,9 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 
 	crtc_state->csc_mode = 0;
 
+	if (IS_CHERRYVIEW(dev_priv))
+		crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
+
 	/* Always allow legacy gamma LUT with no further checking. */
 	if (!crtc_state->gamma_enable ||
 	    crtc_state_is_legacy_gamma(crtc_state)) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2e4d33634e0c..d2f3174e10d6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8187,6 +8187,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >>
 		PIPECONF_GAMMA_MODE_SHIFT;
 
+	if (IS_CHERRYVIEW(dev_priv))
+		pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe));
+
 	i9xx_get_pipe_color_config(pipe_config);
 
 	if (INTEL_GEN(dev_priv) < 4)
@@ -12150,7 +12153,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
 
 		PIPE_CONF_CHECK_X(gamma_mode);
-		PIPE_CONF_CHECK_X(csc_mode);
+		if (IS_CHERRYVIEW(dev_priv))
+			PIPE_CONF_CHECK_X(cgm_mode);
+		else
+			PIPE_CONF_CHECK_X(csc_mode);
 		PIPE_CONF_CHECK_BOOL(gamma_enable);
 		PIPE_CONF_CHECK_BOOL(csc_enable);
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index eec4ed93c335..bbe9cf7e20d6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -942,8 +942,13 @@ struct intel_crtc_state {
 	/* Gamma mode programmed on the pipe */
 	u32 gamma_mode;
 
-	/* CSC mode programmed on the pipe */
-	u32 csc_mode;
+	union {
+		/* CSC mode programmed on the pipe */
+		u32 csc_mode;
+
+		/* CHV CGM mode */
+		u32 cgm_mode;
+	};
 
 	/* bitmask of visible planes (enum plane_id) */
 	u8 active_planes;
-- 
2.19.2

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Re: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode

Typo in precompute

>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Let's precompte the CGM mode for CHV. And naturally we also read it out and check

Same here.

Rest looks good to me. With the above minor nits fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>it.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c   | 28 +++++++++++++++++++++-------
> drivers/gpu/drm/i915/intel_display.c |  8 +++++++-
> drivers/gpu/drm/i915/intel_drv.h     |  9 +++++++--
> 3 files changed, 35 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index d813b9d0f5c0..93428d86510a 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -294,7 +294,6 @@ static void cherryview_load_csc_matrix(const struct
>intel_crtc_state *crtc_state
> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	enum pipe pipe = crtc->pipe;
>-	u32 mode;
>
> 	if (crtc_state->base.ctm) {
> 		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; @@
>-328,12 +327,7 @@ static void cherryview_load_csc_matrix(const struct
>intel_crtc_state *crtc_state
> 		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
> 	}
>
>-	mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
>-	if (!crtc_state_is_legacy_gamma(crtc_state)) {
>-		mode |= (crtc_state->base.degamma_lut ?
>CGM_PIPE_MODE_DEGAMMA : 0) |
>-			(crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA :
>0);
>-	}
>-	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
>+	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
> }
>
> /* Loads the legacy palette/gamma unit for the CRTC. */ @@ -753,6 +747,23 @@
>static int check_lut_size(const struct drm_property_blob *lut, int expected)
> 	return 0;
> }
>
>+static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) {
>+	u32 cgm_mode = 0;
>+
>+	if (crtc_state_is_legacy_gamma(crtc_state))
>+		return 0;
>+
>+	if (crtc_state->base.degamma_lut)
>+		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
>+	if (crtc_state->base.ctm)
>+		cgm_mode |= CGM_PIPE_MODE_CSC;
>+	if (crtc_state->base.gamma_lut)
>+		cgm_mode |= CGM_PIPE_MODE_GAMMA;
>+
>+	return cgm_mode;
>+}
>+
> int intel_color_check(struct intel_crtc_state *crtc_state)  {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>@@ -790,6 +801,9 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>
> 	crtc_state->csc_mode = 0;
>
>+	if (IS_CHERRYVIEW(dev_priv))
>+		crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
>+
> 	/* Always allow legacy gamma LUT with no further checking. */
> 	if (!crtc_state->gamma_enable ||
> 	    crtc_state_is_legacy_gamma(crtc_state)) { diff --git
>a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 2e4d33634e0c..d2f3174e10d6 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -8187,6 +8187,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> 	pipe_config->gamma_mode = (tmp &
>PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> 		PIPECONF_GAMMA_MODE_SHIFT;
>
>+	if (IS_CHERRYVIEW(dev_priv))
>+		pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc-
>>pipe));
>+
> 	i9xx_get_pipe_color_config(pipe_config);
>
> 	if (INTEL_GEN(dev_priv) < 4)
>@@ -12150,7 +12153,10 @@ intel_pipe_config_compare(struct drm_i915_private
>*dev_priv,
> 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
>
> 		PIPE_CONF_CHECK_X(gamma_mode);
>-		PIPE_CONF_CHECK_X(csc_mode);
>+		if (IS_CHERRYVIEW(dev_priv))
>+			PIPE_CONF_CHECK_X(cgm_mode);
>+		else
>+			PIPE_CONF_CHECK_X(csc_mode);
> 		PIPE_CONF_CHECK_BOOL(gamma_enable);
> 		PIPE_CONF_CHECK_BOOL(csc_enable);
> 	}
>diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>index eec4ed93c335..bbe9cf7e20d6 100644
>--- a/drivers/gpu/drm/i915/intel_drv.h
>+++ b/drivers/gpu/drm/i915/intel_drv.h
>@@ -942,8 +942,13 @@ struct intel_crtc_state {
> 	/* Gamma mode programmed on the pipe */
> 	u32 gamma_mode;
>
>-	/* CSC mode programmed on the pipe */
>-	u32 csc_mode;
>+	union {
>+		/* CSC mode programmed on the pipe */
>+		u32 csc_mode;
>+
>+		/* CHV CGM mode */
>+		u32 cgm_mode;
>+	};
>
> 	/* bitmask of visible planes (enum plane_id) */
> 	u8 active_planes;
>--
>2.19.2

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Re: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode

[Ville Syrjälä]

On Wed, Mar 13, 2019 at 03:11:55PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> >Sent: Tuesday, February 19, 2019 1:02 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
> ><matthew.d.roper@intel.com>
> >Subject: [PATCH 2/7] drm/i915: Preocmpute/readout/check CHV CGM mode
> 
> Typo in precompute

(Hopefully) all typos fixed, and series pushed to dinq.

Thanks for the review.

> 
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Let's precompte the CGM mode for CHV. And naturally we also read it out and check
> 
> Same here.
> 
> Rest looks good to me. With the above minor nits fixed.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> >it.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/intel_color.c   | 28 +++++++++++++++++++++-------
> > drivers/gpu/drm/i915/intel_display.c |  8 +++++++-
> > drivers/gpu/drm/i915/intel_drv.h     |  9 +++++++--
> > 3 files changed, 35 insertions(+), 10 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> >index d813b9d0f5c0..93428d86510a 100644
> >--- a/drivers/gpu/drm/i915/intel_color.c
> >+++ b/drivers/gpu/drm/i915/intel_color.c
> >@@ -294,7 +294,6 @@ static void cherryview_load_csc_matrix(const struct
> >intel_crtc_state *crtc_state
> > 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > 	enum pipe pipe = crtc->pipe;
> >-	u32 mode;
> >
> > 	if (crtc_state->base.ctm) {
> > 		const struct drm_color_ctm *ctm = crtc_state->base.ctm->data; @@
> >-328,12 +327,7 @@ static void cherryview_load_csc_matrix(const struct
> >intel_crtc_state *crtc_state
> > 		I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
> > 	}
> >
> >-	mode = (crtc_state->base.ctm ? CGM_PIPE_MODE_CSC : 0);
> >-	if (!crtc_state_is_legacy_gamma(crtc_state)) {
> >-		mode |= (crtc_state->base.degamma_lut ?
> >CGM_PIPE_MODE_DEGAMMA : 0) |
> >-			(crtc_state->base.gamma_lut ? CGM_PIPE_MODE_GAMMA :
> >0);
> >-	}
> >-	I915_WRITE(CGM_PIPE_MODE(pipe), mode);
> >+	I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
> > }
> >
> > /* Loads the legacy palette/gamma unit for the CRTC. */ @@ -753,6 +747,23 @@
> >static int check_lut_size(const struct drm_property_blob *lut, int expected)
> > 	return 0;
> > }
> >
> >+static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) {
> >+	u32 cgm_mode = 0;
> >+
> >+	if (crtc_state_is_legacy_gamma(crtc_state))
> >+		return 0;
> >+
> >+	if (crtc_state->base.degamma_lut)
> >+		cgm_mode |= CGM_PIPE_MODE_DEGAMMA;
> >+	if (crtc_state->base.ctm)
> >+		cgm_mode |= CGM_PIPE_MODE_CSC;
> >+	if (crtc_state->base.gamma_lut)
> >+		cgm_mode |= CGM_PIPE_MODE_GAMMA;
> >+
> >+	return cgm_mode;
> >+}
> >+
> > int intel_color_check(struct intel_crtc_state *crtc_state)  {
> > 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >@@ -790,6 +801,9 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> >
> > 	crtc_state->csc_mode = 0;
> >
> >+	if (IS_CHERRYVIEW(dev_priv))
> >+		crtc_state->cgm_mode = chv_cgm_mode(crtc_state);
> >+
> > 	/* Always allow legacy gamma LUT with no further checking. */
> > 	if (!crtc_state->gamma_enable ||
> > 	    crtc_state_is_legacy_gamma(crtc_state)) { diff --git
> >a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> >index 2e4d33634e0c..d2f3174e10d6 100644
> >--- a/drivers/gpu/drm/i915/intel_display.c
> >+++ b/drivers/gpu/drm/i915/intel_display.c
> >@@ -8187,6 +8187,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> > 	pipe_config->gamma_mode = (tmp &
> >PIPECONF_GAMMA_MODE_MASK_I9XX) >>
> > 		PIPECONF_GAMMA_MODE_SHIFT;
> >
> >+	if (IS_CHERRYVIEW(dev_priv))
> >+		pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc-
> >>pipe));
> >+
> > 	i9xx_get_pipe_color_config(pipe_config);
> >
> > 	if (INTEL_GEN(dev_priv) < 4)
> >@@ -12150,7 +12153,10 @@ intel_pipe_config_compare(struct drm_i915_private
> >*dev_priv,
> > 		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
> >
> > 		PIPE_CONF_CHECK_X(gamma_mode);
> >-		PIPE_CONF_CHECK_X(csc_mode);
> >+		if (IS_CHERRYVIEW(dev_priv))
> >+			PIPE_CONF_CHECK_X(cgm_mode);
> >+		else
> >+			PIPE_CONF_CHECK_X(csc_mode);
> > 		PIPE_CONF_CHECK_BOOL(gamma_enable);
> > 		PIPE_CONF_CHECK_BOOL(csc_enable);
> > 	}
> >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >index eec4ed93c335..bbe9cf7e20d6 100644
> >--- a/drivers/gpu/drm/i915/intel_drv.h
> >+++ b/drivers/gpu/drm/i915/intel_drv.h
> >@@ -942,8 +942,13 @@ struct intel_crtc_state {
> > 	/* Gamma mode programmed on the pipe */
> > 	u32 gamma_mode;
> >
> >-	/* CSC mode programmed on the pipe */
> >-	u32 csc_mode;
> >+	union {
> >+		/* CSC mode programmed on the pipe */
> >+		u32 csc_mode;
> >+
> >+		/* CHV CGM mode */
> >+		u32 cgm_mode;
> >+	};
> >
> > 	/* bitmask of visible planes (enum plane_id) */
> > 	u8 active_planes;
> >--
> >2.19.2
> 

-- 
Ville Syrjälä
Intel
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[PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract a helper which determines if we need to use the
pipe CSC for limited range RGB output.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 93428d86510a..ddc48c0d45ac 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -161,22 +161,28 @@ static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
 	}
 }
 
+static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+	/*
+	 * FIXME if there's a gamma LUT after the CSC, we should
+	 * do the range compression using the gamma LUT instead.
+	 */
+	return crtc_state->limited_color_range &&
+		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
+		 IS_GEN_RANGE(dev_priv, 9, 10));
+}
+
 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	bool limited_color_range = false;
+	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 	enum pipe pipe = crtc->pipe;
 	u16 coeffs[9] = {};
 	int i;
 
-	/*
-	 * FIXME if there's a gamma LUT after the CSC, we should
-	 * do the range compression using the gamma LUT instead.
-	 */
-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
-		limited_color_range = crtc_state->limited_color_range;
-
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
 		ilk_load_ycbcr_conversion_matrix(crtc);
-- 
2.19.2

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Re: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Extract a helper which determines if we need to use the pipe CSC for limited range
>RGB output.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 22 ++++++++++++++--------
> 1 file changed, 14 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index 93428d86510a..ddc48c0d45ac 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -161,22 +161,28 @@ static void ilk_load_ycbcr_conversion_matrix(struct
>intel_crtc *crtc)
> 	}
> }
>
>+static bool ilk_csc_limited_range(const struct intel_crtc_state
>+*crtc_state) {
>+	struct drm_i915_private *dev_priv =
>+to_i915(crtc_state->base.crtc->dev);
>+
>+	/*
>+	 * FIXME if there's a gamma LUT after the CSC, we should
>+	 * do the range compression using the gamma LUT instead.
>+	 */
>+	return crtc_state->limited_color_range &&
>+		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
>+		 IS_GEN_RANGE(dev_priv, 9, 10));

We should include Gen8 also to this list. Is it intentional to drop that ?
With this fixed or justified reasoning, 
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>+}
>+
> static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)  {
> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>-	bool limited_color_range = false;
>+	bool limited_color_range = ilk_csc_limited_range(crtc_state);
> 	enum pipe pipe = crtc->pipe;
> 	u16 coeffs[9] = {};
> 	int i;
>
>-	/*
>-	 * FIXME if there's a gamma LUT after the CSC, we should
>-	 * do the range compression using the gamma LUT instead.
>-	 */
>-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>-		limited_color_range = crtc_state->limited_color_range;
>-
> 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> 		ilk_load_ycbcr_conversion_matrix(crtc);
>--
>2.19.2

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Re: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

[Ville Syrjälä]

On Wed, Mar 13, 2019 at 03:30:43PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> >Sent: Tuesday, February 19, 2019 1:02 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
> ><matthew.d.roper@intel.com>
> >Subject: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Extract a helper which determines if we need to use the pipe CSC for limited range
> >RGB output.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/intel_color.c | 22 ++++++++++++++--------
> > 1 file changed, 14 insertions(+), 8 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> >index 93428d86510a..ddc48c0d45ac 100644
> >--- a/drivers/gpu/drm/i915/intel_color.c
> >+++ b/drivers/gpu/drm/i915/intel_color.c
> >@@ -161,22 +161,28 @@ static void ilk_load_ycbcr_conversion_matrix(struct
> >intel_crtc *crtc)
> > 	}
> > }
> >
> >+static bool ilk_csc_limited_range(const struct intel_crtc_state
> >+*crtc_state) {
> >+	struct drm_i915_private *dev_priv =
> >+to_i915(crtc_state->base.crtc->dev);
> >+
> >+	/*
> >+	 * FIXME if there's a gamma LUT after the CSC, we should
> >+	 * do the range compression using the gamma LUT instead.
> >+	 */
> >+	return crtc_state->limited_color_range &&
> >+		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> >+		 IS_GEN_RANGE(dev_priv, 9, 10));
> 
> We should include Gen8 also to this list. Is it intentional to drop that ?

IS_BROADWELL is the gen8 we care about.

> With this fixed or justified reasoning, 
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> >+}
> >+
> > static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)  {
> > 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >-	bool limited_color_range = false;
> >+	bool limited_color_range = ilk_csc_limited_range(crtc_state);
> > 	enum pipe pipe = crtc->pipe;
> > 	u16 coeffs[9] = {};
> > 	int i;
> >
> >-	/*
> >-	 * FIXME if there's a gamma LUT after the CSC, we should
> >-	 * do the range compression using the gamma LUT instead.
> >-	 */
> >-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
> >-		limited_color_range = crtc_state->limited_color_range;
> >-
> > 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> > 		ilk_load_ycbcr_conversion_matrix(crtc);
> >--
> >2.19.2
> 

-- 
Ville Syrjälä
Intel
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Re: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Wednesday, March 13, 2019 10:01 PM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: Re: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()
>
>On Wed, Mar 13, 2019 at 03:30:43PM +0000, Shankar, Uma wrote:
>>
>>
>> >-----Original Message-----
>> >From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>> >Sent: Tuesday, February 19, 2019 1:02 AM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
>> ><matthew.d.roper@intel.com>
>> >Subject: [PATCH 3/7] drm/i915: Extract ilk_csc_limited_range()
>> >
>> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> >Extract a helper which determines if we need to use the pipe CSC for
>> >limited range RGB output.
>> >
>> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >---
>> > drivers/gpu/drm/i915/intel_color.c | 22 ++++++++++++++--------
>> > 1 file changed, 14 insertions(+), 8 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/intel_color.c
>> >b/drivers/gpu/drm/i915/intel_color.c
>> >index 93428d86510a..ddc48c0d45ac 100644
>> >--- a/drivers/gpu/drm/i915/intel_color.c
>> >+++ b/drivers/gpu/drm/i915/intel_color.c
>> >@@ -161,22 +161,28 @@ static void
>> >ilk_load_ycbcr_conversion_matrix(struct
>> >intel_crtc *crtc)
>> > 	}
>> > }
>> >
>> >+static bool ilk_csc_limited_range(const struct intel_crtc_state
>> >+*crtc_state) {
>> >+	struct drm_i915_private *dev_priv =
>> >+to_i915(crtc_state->base.crtc->dev);
>> >+
>> >+	/*
>> >+	 * FIXME if there's a gamma LUT after the CSC, we should
>> >+	 * do the range compression using the gamma LUT instead.
>> >+	 */
>> >+	return crtc_state->limited_color_range &&
>> >+		(IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
>> >+		 IS_GEN_RANGE(dev_priv, 9, 10));
>>
>> We should include Gen8 also to this list. Is it intentional to drop that ?
>
>IS_BROADWELL is the gen8 we care about.

Ok, thanks for clarification.

>> With this fixed or justified reasoning,
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>>
>> >+}
>> >+
>> > static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)  {
>> > 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >-	bool limited_color_range = false;
>> >+	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>> > 	enum pipe pipe = crtc->pipe;
>> > 	u16 coeffs[9] = {};
>> > 	int i;
>> >
>> >-	/*
>> >-	 * FIXME if there's a gamma LUT after the CSC, we should
>> >-	 * do the range compression using the gamma LUT instead.
>> >-	 */
>> >-	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
>> >-		limited_color_range = crtc_state->limited_color_range;
>> >-
>> > 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> > 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>> > 		ilk_load_ycbcr_conversion_matrix(crtc);
>> >--
>> >2.19.2
>>
>
>--
>Ville Syrjälä
>Intel
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[PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We have far too much messy duplicated code in the
pipe/output CSC programming. Simply provide two functions
(ilk_update_pipe_csc() and icl_update_output_csc()) to
program the relevant CSC registers. The desired offsets
and coefficients are passed in as parameters.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 168 ++++++++++++++---------------
 1 file changed, 82 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index ddc48c0d45ac..61cb69058b35 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -40,23 +40,6 @@
 #define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))
 
 #define LEGACY_LUT_LENGTH		256
-
-/* Post offset values for RGB->YCBCR conversion */
-#define POSTOFF_RGB_TO_YUV_HI 0x800
-#define POSTOFF_RGB_TO_YUV_ME 0x100
-#define POSTOFF_RGB_TO_YUV_LO 0x800
-
-/*
- * These values are direct register values specified in the Bspec,
- * for RGB->YUV conversion matrix (colorspace BT709)
- */
-#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8
-#define CSC_RGB_TO_YUV_BU 0x37e80000
-#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0
-#define CSC_RGB_TO_YUV_BY 0xb5280000
-#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8
-#define CSC_RGB_TO_YUV_BV 0x1e080000
-
 /*
  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
  * format). This macro takes the coefficient we want transformed and the
@@ -74,6 +57,31 @@
 #define ILK_CSC_COEFF_1_0		\
 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
 
+#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
+
+static const u16 ilk_csc_off_zero[3] = {};
+
+static const u16 ilk_csc_postoff_limited_range[3] = {
+	ILK_CSC_POSTOFF_LIMITED_RANGE,
+	ILK_CSC_POSTOFF_LIMITED_RANGE,
+	ILK_CSC_POSTOFF_LIMITED_RANGE,
+};
+
+/*
+ * These values are direct register values specified in the Bspec,
+ * for RGB->YUV conversion matrix (colorspace BT709)
+ */
+static const u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
+	0x1e08, 0x9cc0, 0xb528,
+	0x2ba8, 0x09d8, 0x37e8,
+	0xbce8, 0x9ad8, 0x1e08,
+};
+
+/* Post offset values for RGB->YCBCR conversion */
+static const u16 ilk_csc_postoff_rgb_to_ycbcr[3] = {
+	0x0800, 0x0100, 0x0800,
+};
+
 static bool lut_is_legacy(const struct drm_property_blob *lut)
 {
 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH;
@@ -113,54 +121,60 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
 	return result;
 }
 
-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
+static void ilk_update_pipe_csc(struct intel_crtc *crtc,
+				const u16 preoff[3],
+				const u16 coeff[9],
+				const u16 postoff[3])
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (INTEL_GEN(dev_priv) < 11) {
-		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
-		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
-		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
+	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
+	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
+	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
 
-		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU);
-		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
+	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
+	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
 
-		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY);
-		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
+	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
+	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
 
-		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV);
-		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
+	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
+	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
 
-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), POSTOFF_RGB_TO_YUV_HI);
-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), POSTOFF_RGB_TO_YUV_ME);
-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), POSTOFF_RGB_TO_YUV_LO);
-	} else {
-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
-
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
-			   CSC_RGB_TO_YUV_RU_GU);
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
-
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
-			   CSC_RGB_TO_YUV_RY_GY);
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
-
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
-			   CSC_RGB_TO_YUV_RV_GV);
-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
-
-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
-			   POSTOFF_RGB_TO_YUV_HI);
-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
-			   POSTOFF_RGB_TO_YUV_ME);
-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
-			   POSTOFF_RGB_TO_YUV_LO);
+	if (INTEL_GEN(dev_priv) >= 7) {
+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
 	}
 }
 
+static void icl_update_output_csc(struct intel_crtc *crtc,
+				  const u16 preoff[3],
+				  const u16 coeff[9],
+				  const u16 postoff[3])
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+
+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
+
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
+
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
+
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
+
+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]);
+}
+
 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@@ -185,7 +199,15 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
-		ilk_load_ycbcr_conversion_matrix(crtc);
+		if (INTEL_GEN(dev_priv) >= 11)
+			icl_update_output_csc(crtc, ilk_csc_off_zero,
+					      ilk_csc_coeff_rgb_to_ycbcr,
+					      ilk_csc_postoff_rgb_to_ycbcr);
+		else
+			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
+					    ilk_csc_coeff_rgb_to_ycbcr,
+					    ilk_csc_postoff_rgb_to_ycbcr);
+
 		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
 		/*
 		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC
@@ -258,38 +280,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		}
 	}
 
-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
-
-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
-
-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
+	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
+			    limited_color_range ?
+			    ilk_csc_postoff_limited_range :
+			    ilk_csc_off_zero);
 
-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
-
-	if (INTEL_GEN(dev_priv) > 6) {
-		u16 postoff = 0;
-
-		if (limited_color_range)
-			postoff = (16 * (1 << 12) / 255) & 0x1fff;
-
-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
-
-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
-	} else {
-		u32 mode = CSC_MODE_YUV_TO_RGB;
-
-		if (limited_color_range)
-			mode |= CSC_BLACK_SCREEN_OFFSET;
-
-		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
-	}
+	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
 }
 
 /*
-- 
2.19.2

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Re: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>We have far too much messy duplicated code in the pipe/output CSC programming.
>Simply provide two functions
>(ilk_update_pipe_csc() and icl_update_output_csc()) to program the relevant CSC
>registers. The desired offsets and coefficients are passed in as parameters.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 168 ++++++++++++++---------------
> 1 file changed, 82 insertions(+), 86 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index ddc48c0d45ac..61cb69058b35 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -40,23 +40,6 @@
> #define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))
>
> #define LEGACY_LUT_LENGTH		256
>-
>-/* Post offset values for RGB->YCBCR conversion */ -#define
>POSTOFF_RGB_TO_YUV_HI 0x800 -#define POSTOFF_RGB_TO_YUV_ME 0x100 -
>#define POSTOFF_RGB_TO_YUV_LO 0x800
>-
>-/*
>- * These values are direct register values specified in the Bspec,
>- * for RGB->YUV conversion matrix (colorspace BT709)
>- */
>-#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 -#define CSC_RGB_TO_YUV_BU
>0x37e80000 -#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 -#define
>CSC_RGB_TO_YUV_BY 0xb5280000 -#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 -
>#define CSC_RGB_TO_YUV_BV 0x1e080000
>-
> /*
>  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
>  * format). This macro takes the coefficient we want transformed and the @@ -74,6
>+57,31 @@
> #define ILK_CSC_COEFF_1_0		\
> 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>
>+#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
>+
>+static const u16 ilk_csc_off_zero[3] = {};
>+
>+static const u16 ilk_csc_postoff_limited_range[3] = {
>+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>+};
>+
>+/*
>+ * These values are direct register values specified in the Bspec,
>+ * for RGB->YUV conversion matrix (colorspace BT709)  */ static const
>+u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
>+	0x1e08, 0x9cc0, 0xb528,
>+	0x2ba8, 0x09d8, 0x37e8,
>+	0xbce8, 0x9ad8, 0x1e08,
>+};

I am not sure if the matrix coefficients are correct. Can you please cross check, if I am
missing something. Spec has these as values (hoping table doesn’t get distorted while sending :))
	Bt.601			Bt.709
	Value	Program	Value		Program
RU	0.2990	0x1990		0.21260		0x2D98
GU	0.5870	0x0968		0.71520		0x0B70
BU	0.1140	0x3E98		0.07220		0x3940
RV	-0.1687	0xAAC8		-0.11460	0xBEA8
GV	-0.3313	0x9A98		-0.38540	0x9C58
BV	0.5000	0x0800		0.50000		0x0800
RY	0.5000	0x0800		0.50000		0x0800
GY	-0.4187	0x9D68		-0.45420	0x9E88
BY	-0.0813	0xBA68		-0.04580	0xB5E0


>+
>+/* Post offset values for RGB->YCBCR conversion */ static const u16
>+ilk_csc_postoff_rgb_to_ycbcr[3] = {
>+	0x0800, 0x0100, 0x0800,
>+};
>+
> static bool lut_is_legacy(const struct drm_property_blob *lut)  {
> 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -113,54
>+121,60 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
> 	return result;
> }
>
>-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
>+static void ilk_update_pipe_csc(struct intel_crtc *crtc,
>+				const u16 preoff[3],
>+				const u16 coeff[9],
>+				const u16 postoff[3])
> {
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	enum pipe pipe = crtc->pipe;
>
>-	if (INTEL_GEN(dev_priv) < 11) {
>-		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>-		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>-		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>+	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
>+	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
>+	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
>
>-		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe),
>CSC_RGB_TO_YUV_RU_GU);
>-		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
>+	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
>+	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
>
>-		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe),
>CSC_RGB_TO_YUV_RY_GY);
>-		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
>+	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
>+	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
>
>-		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe),
>CSC_RGB_TO_YUV_RV_GV);
>-		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
>+	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
>+	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
>
>-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe),
>POSTOFF_RGB_TO_YUV_HI);
>-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
>POSTOFF_RGB_TO_YUV_ME);
>-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe),
>POSTOFF_RGB_TO_YUV_LO);
>-	} else {
>-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
>-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
>-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
>-
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
>-			   CSC_RGB_TO_YUV_RU_GU);
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe),
>CSC_RGB_TO_YUV_BU);
>-
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
>-			   CSC_RGB_TO_YUV_RY_GY);
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe),
>CSC_RGB_TO_YUV_BY);
>-
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
>-			   CSC_RGB_TO_YUV_RV_GV);
>-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe),
>CSC_RGB_TO_YUV_BV);
>-
>-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
>-			   POSTOFF_RGB_TO_YUV_HI);
>-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
>-			   POSTOFF_RGB_TO_YUV_ME);
>-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
>-			   POSTOFF_RGB_TO_YUV_LO);
>+	if (INTEL_GEN(dev_priv) >= 7) {
>+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
>+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
>+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
> 	}
> }
>
>+static void icl_update_output_csc(struct intel_crtc *crtc,
>+				  const u16 preoff[3],
>+				  const u16 coeff[9],
>+				  const u16 postoff[3])
>+{
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+	enum pipe pipe = crtc->pipe;
>+
>+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
>+
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
>coeff[1]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
>+
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
>coeff[4]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
>+
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
>coeff[7]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
>+
>+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
>+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); }
>+
> static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)  {
> 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
>@@ -185,7 +199,15 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
>*crtc_state)
>
> 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>-		ilk_load_ycbcr_conversion_matrix(crtc);
>+		if (INTEL_GEN(dev_priv) >= 11)
>+			icl_update_output_csc(crtc, ilk_csc_off_zero,
>+					      ilk_csc_coeff_rgb_to_ycbcr,
>+					      ilk_csc_postoff_rgb_to_ycbcr);
>+		else
>+			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>+					    ilk_csc_coeff_rgb_to_ycbcr,
>+					    ilk_csc_postoff_rgb_to_ycbcr);
>+
> 		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> 		/*
> 		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC @@ -
>258,38 +280,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
>*crtc_state)
> 		}
> 	}
>
>-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
>-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
>-
>-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
>-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
>-
>-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
>-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
>+	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
>+			    limited_color_range ?
>+			    ilk_csc_postoff_limited_range :
>+			    ilk_csc_off_zero);
>
>-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>-
>-	if (INTEL_GEN(dev_priv) > 6) {
>-		u16 postoff = 0;
>-
>-		if (limited_color_range)
>-			postoff = (16 * (1 << 12) / 255) & 0x1fff;
>-
>-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
>-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>-
>-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>-	} else {
>-		u32 mode = CSC_MODE_YUV_TO_RGB;
>-
>-		if (limited_color_range)
>-			mode |= CSC_BLACK_SCREEN_OFFSET;
>-
>-		I915_WRITE(PIPE_CSC_MODE(pipe), mode);

Looks like this is not handled and got dropped. Pre Gen7 stuff.

>-	}
>+	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> }
>
> /*
>--
>2.19.2

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Re: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

[Ville Syrjälä]

On Wed, Mar 13, 2019 at 04:38:01PM +0000, Shankar, Uma wrote:
> 
> 
> >-----Original Message-----
> >From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
> >Sent: Tuesday, February 19, 2019 1:02 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
> ><matthew.d.roper@intel.com>
> >Subject: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >We have far too much messy duplicated code in the pipe/output CSC programming.
> >Simply provide two functions
> >(ilk_update_pipe_csc() and icl_update_output_csc()) to program the relevant CSC
> >registers. The desired offsets and coefficients are passed in as parameters.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/intel_color.c | 168 ++++++++++++++---------------
> > 1 file changed, 82 insertions(+), 86 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> >index ddc48c0d45ac..61cb69058b35 100644
> >--- a/drivers/gpu/drm/i915/intel_color.c
> >+++ b/drivers/gpu/drm/i915/intel_color.c
> >@@ -40,23 +40,6 @@
> > #define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))
> >
> > #define LEGACY_LUT_LENGTH		256
> >-
> >-/* Post offset values for RGB->YCBCR conversion */ -#define
> >POSTOFF_RGB_TO_YUV_HI 0x800 -#define POSTOFF_RGB_TO_YUV_ME 0x100 -
> >#define POSTOFF_RGB_TO_YUV_LO 0x800
> >-
> >-/*
> >- * These values are direct register values specified in the Bspec,
> >- * for RGB->YUV conversion matrix (colorspace BT709)
> >- */
> >-#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 -#define CSC_RGB_TO_YUV_BU
> >0x37e80000 -#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 -#define
> >CSC_RGB_TO_YUV_BY 0xb5280000 -#define CSC_RGB_TO_YUV_RV_GV 0xbce89ad8 -
> >#define CSC_RGB_TO_YUV_BV 0x1e080000
> >-
> > /*
> >  * Extract the CSC coefficient from a CTM coefficient (in U32.32 fixed point
> >  * format). This macro takes the coefficient we want transformed and the @@ -74,6
> >+57,31 @@
> > #define ILK_CSC_COEFF_1_0		\
> > 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
> >
> >+#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
> >+
> >+static const u16 ilk_csc_off_zero[3] = {};
> >+
> >+static const u16 ilk_csc_postoff_limited_range[3] = {
> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
> >+};
> >+
> >+/*
> >+ * These values are direct register values specified in the Bspec,
> >+ * for RGB->YUV conversion matrix (colorspace BT709)  */ static const
> >+u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
> >+	0x1e08, 0x9cc0, 0xb528,
> >+	0x2ba8, 0x09d8, 0x37e8,
> >+	0xbce8, 0x9ad8, 0x1e08,
> >+};
> 
> I am not sure if the matrix coefficients are correct. Can you please cross check, if I am
> missing something. Spec has these as values (hoping table doesn’t get distorted while sending :))
> 	Bt.601			Bt.709
> 	Value	Program	Value		Program
> RU	0.2990	0x1990		0.21260		0x2D98
> GU	0.5870	0x0968		0.71520		0x0B70
> BU	0.1140	0x3E98		0.07220		0x3940
> RV	-0.1687	0xAAC8		-0.11460	0xBEA8
> GV	-0.3313	0x9A98		-0.38540	0x9C58
> BV	0.5000	0x0800		0.50000		0x0800
> RY	0.5000	0x0800		0.50000		0x0800
> GY	-0.4187	0x9D68		-0.45420	0x9E88
> BY	-0.0813	0xBA68		-0.04580	0xB5E0

My calculations are giving me this:
	0x1e10, 0x9cc8, 0xb528,
	0x2bb0, 0x09d0, 0x37f0,
	0xbce0, 0x9ad8, 0x1e10,

The difference between my numbers and the ones in the code seem
to be more or less just due to rounding.

The numbers in the spec would appear to be for full range output,
but we want limited range.

> 
> 
> >+
> >+/* Post offset values for RGB->YCBCR conversion */ static const u16
> >+ilk_csc_postoff_rgb_to_ycbcr[3] = {
> >+	0x0800, 0x0100, 0x0800,
> >+};
> >+
> > static bool lut_is_legacy(const struct drm_property_blob *lut)  {
> > 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -113,54
> >+121,60 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64 *input)
> > 	return result;
> > }
> >
> >-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc *crtc)
> >+static void ilk_update_pipe_csc(struct intel_crtc *crtc,
> >+				const u16 preoff[3],
> >+				const u16 coeff[9],
> >+				const u16 postoff[3])
> > {
> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > 	enum pipe pipe = crtc->pipe;
> >
> >-	if (INTEL_GEN(dev_priv) < 11) {
> >-		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> >-		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> >-		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
> >+	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
> >+	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
> >+	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
> >
> >-		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe),
> >CSC_RGB_TO_YUV_RU_GU);
> >-		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
> >+	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
> >+	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
> >
> >-		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe),
> >CSC_RGB_TO_YUV_RY_GY);
> >-		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
> >+	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
> >+	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
> >
> >-		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe),
> >CSC_RGB_TO_YUV_RV_GV);
> >-		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
> >+	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
> >+	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
> >
> >-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe),
> >POSTOFF_RGB_TO_YUV_HI);
> >-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
> >POSTOFF_RGB_TO_YUV_ME);
> >-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe),
> >POSTOFF_RGB_TO_YUV_LO);
> >-	} else {
> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
> >-
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
> >-			   CSC_RGB_TO_YUV_RU_GU);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe),
> >CSC_RGB_TO_YUV_BU);
> >-
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
> >-			   CSC_RGB_TO_YUV_RY_GY);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe),
> >CSC_RGB_TO_YUV_BY);
> >-
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
> >-			   CSC_RGB_TO_YUV_RV_GV);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe),
> >CSC_RGB_TO_YUV_BV);
> >-
> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
> >-			   POSTOFF_RGB_TO_YUV_HI);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
> >-			   POSTOFF_RGB_TO_YUV_ME);
> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
> >-			   POSTOFF_RGB_TO_YUV_LO);
> >+	if (INTEL_GEN(dev_priv) >= 7) {
> >+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
> >+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
> >+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
> > 	}
> > }
> >
> >+static void icl_update_output_csc(struct intel_crtc *crtc,
> >+				  const u16 preoff[3],
> >+				  const u16 coeff[9],
> >+				  const u16 postoff[3])
> >+{
> >+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >+	enum pipe pipe = crtc->pipe;
> >+
> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
> >+
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
> >coeff[1]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
> >+
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
> >coeff[4]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
> >+
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
> >coeff[7]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
> >+
> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); }
> >+
> > static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)  {
> > 	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
> >@@ -185,7 +199,15 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
> >*crtc_state)
> >
> > 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> > 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> >-		ilk_load_ycbcr_conversion_matrix(crtc);
> >+		if (INTEL_GEN(dev_priv) >= 11)
> >+			icl_update_output_csc(crtc, ilk_csc_off_zero,
> >+					      ilk_csc_coeff_rgb_to_ycbcr,
> >+					      ilk_csc_postoff_rgb_to_ycbcr);
> >+		else
> >+			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
> >+					    ilk_csc_coeff_rgb_to_ycbcr,
> >+					    ilk_csc_postoff_rgb_to_ycbcr);
> >+
> > 		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> > 		/*
> > 		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC @@ -
> >258,38 +280,12 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
> >*crtc_state)
> > 		}
> > 	}
> >
> >-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
> >-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
> >-
> >-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
> >-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
> >-
> >-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
> >-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
> >+	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
> >+			    limited_color_range ?
> >+			    ilk_csc_postoff_limited_range :
> >+			    ilk_csc_off_zero);
> >
> >-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
> >-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
> >-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
> >-
> >-	if (INTEL_GEN(dev_priv) > 6) {
> >-		u16 postoff = 0;
> >-
> >-		if (limited_color_range)
> >-			postoff = (16 * (1 << 12) / 255) & 0x1fff;
> >-
> >-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
> >-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
> >-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
> >-
> >-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> >-	} else {
> >-		u32 mode = CSC_MODE_YUV_TO_RGB;
> >-
> >-		if (limited_color_range)
> >-			mode |= CSC_BLACK_SCREEN_OFFSET;
> >-
> >-		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
> 
> Looks like this is not handled and got dropped. Pre Gen7 stuff.

Yeah, we don't use the CSC (yet) on pre-HSW. Even if we start to
use it we'll not be using it for RGB full->limited conversion.
So we won't actually program it like this in the end.

> 
> >-	}
> >+	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
> > }
> >
> > /*
> >--
> >2.19.2
> 

-- 
Ville Syrjälä
Intel
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Re: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
>Sent: Thursday, March 14, 2019 1:21 AM
>To: Shankar, Uma <uma.shankar@intel.com>
>Cc: intel-gfx@lists.freedesktop.org; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: Re: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC programming
>
>On Wed, Mar 13, 2019 at 04:38:01PM +0000, Shankar, Uma wrote:
>>
>>
>> >-----Original Message-----
>> >From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>> >Sent: Tuesday, February 19, 2019 1:02 AM
>> >To: intel-gfx@lists.freedesktop.org
>> >Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
>> ><matthew.d.roper@intel.com>
>> >Subject: [PATCH 4/7] drm/i915: Clean up ilk/icl pipe/output CSC
>> >programming
>> >
>> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> >We have far too much messy duplicated code in the pipe/output CSC
>programming.
>> >Simply provide two functions
>> >(ilk_update_pipe_csc() and icl_update_output_csc()) to program the
>> >relevant CSC registers. The desired offsets and coefficients are passed in as
>parameters.
>> >
>> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >---
>> > drivers/gpu/drm/i915/intel_color.c | 168
>> >++++++++++++++---------------
>> > 1 file changed, 82 insertions(+), 86 deletions(-)
>> >
>> >diff --git a/drivers/gpu/drm/i915/intel_color.c
>> >b/drivers/gpu/drm/i915/intel_color.c
>> >index ddc48c0d45ac..61cb69058b35 100644
>> >--- a/drivers/gpu/drm/i915/intel_color.c
>> >+++ b/drivers/gpu/drm/i915/intel_color.c
>> >@@ -40,23 +40,6 @@
>> > #define CTM_COEFF_ABS(coeff)		((coeff) & (CTM_COEFF_SIGN - 1))
>> >
>> > #define LEGACY_LUT_LENGTH		256
>> >-
>> >-/* Post offset values for RGB->YCBCR conversion */ -#define
>> >POSTOFF_RGB_TO_YUV_HI 0x800 -#define POSTOFF_RGB_TO_YUV_ME 0x100 -
>> >#define POSTOFF_RGB_TO_YUV_LO 0x800
>> >-
>> >-/*
>> >- * These values are direct register values specified in the Bspec,
>> >- * for RGB->YUV conversion matrix (colorspace BT709)
>> >- */
>> >-#define CSC_RGB_TO_YUV_RU_GU 0x2ba809d8 -#define CSC_RGB_TO_YUV_BU
>> >0x37e80000 -#define CSC_RGB_TO_YUV_RY_GY 0x1e089cc0 -#define
>> >CSC_RGB_TO_YUV_BY 0xb5280000 -#define CSC_RGB_TO_YUV_RV_GV
>0xbce89ad8
>> >- #define CSC_RGB_TO_YUV_BV 0x1e080000
>> >-
>> > /*
>> >  * Extract the CSC coefficient from a CTM coefficient (in U32.32
>> >fixed point
>> >  * format). This macro takes the coefficient we want transformed and
>> >the @@ -74,6
>> >+57,31 @@
>> > #define ILK_CSC_COEFF_1_0		\
>> > 	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>> >
>> >+#define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
>> >+
>> >+static const u16 ilk_csc_off_zero[3] = {};
>> >+
>> >+static const u16 ilk_csc_postoff_limited_range[3] = {
>> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>> >+	ILK_CSC_POSTOFF_LIMITED_RANGE,
>> >+};
>> >+
>> >+/*
>> >+ * These values are direct register values specified in the Bspec,
>> >+ * for RGB->YUV conversion matrix (colorspace BT709)  */ static
>> >+const
>> >+u16 ilk_csc_coeff_rgb_to_ycbcr[9] = {
>> >+	0x1e08, 0x9cc0, 0xb528,
>> >+	0x2ba8, 0x09d8, 0x37e8,
>> >+	0xbce8, 0x9ad8, 0x1e08,
>> >+};
>>
>> I am not sure if the matrix coefficients are correct. Can you please
>> cross check, if I am missing something. Spec has these as values (hoping table
>doesn’t get distorted while sending :))
>> 	Bt.601			Bt.709
>> 	Value	Program	Value		Program
>> RU	0.2990	0x1990		0.21260		0x2D98
>> GU	0.5870	0x0968		0.71520		0x0B70
>> BU	0.1140	0x3E98		0.07220		0x3940
>> RV	-0.1687	0xAAC8		-0.11460	0xBEA8
>> GV	-0.3313	0x9A98		-0.38540	0x9C58
>> BV	0.5000	0x0800		0.50000		0x0800
>> RY	0.5000	0x0800		0.50000		0x0800
>> GY	-0.4187	0x9D68		-0.45420	0x9E88
>> BY	-0.0813	0xBA68		-0.04580	0xB5E0
>
>My calculations are giving me this:
>	0x1e10, 0x9cc8, 0xb528,
>	0x2bb0, 0x09d0, 0x37f0,
>	0xbce0, 0x9ad8, 0x1e10,
>
>The difference between my numbers and the ones in the code seem to be more or
>less just due to rounding.
>
>The numbers in the spec would appear to be for full range output, but we want
>limited range.

Hmm yes indeed the spec is putting full range there.  So this is fine then.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>>
>>
>> >+
>> >+/* Post offset values for RGB->YCBCR conversion */ static const u16
>> >+ilk_csc_postoff_rgb_to_ycbcr[3] = {
>> >+	0x0800, 0x0100, 0x0800,
>> >+};
>> >+
>> > static bool lut_is_legacy(const struct drm_property_blob *lut)  {
>> > 	return drm_color_lut_size(lut) == LEGACY_LUT_LENGTH; @@ -113,54
>> >+121,60 @@ static u64 *ctm_mult_by_limited(u64 *result, const u64
>> >+*input)
>> > 	return result;
>> > }
>> >
>> >-static void ilk_load_ycbcr_conversion_matrix(struct intel_crtc
>> >*crtc)
>> >+static void ilk_update_pipe_csc(struct intel_crtc *crtc,
>> >+				const u16 preoff[3],
>> >+				const u16 coeff[9],
>> >+				const u16 postoff[3])
>> > {
>> > 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> > 	enum pipe pipe = crtc->pipe;
>> >
>> >-	if (INTEL_GEN(dev_priv) < 11) {
>> >-		I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>> >-		I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>> >-		I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>> >+	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]);
>> >+	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]);
>> >+	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]);
>> >
>> >-		I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe),
>> >CSC_RGB_TO_YUV_RU_GU);
>> >-		I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU);
>> >+	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]);
>> >+	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16);
>> >
>> >-		I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe),
>> >CSC_RGB_TO_YUV_RY_GY);
>> >-		I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY);
>> >+	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]);
>> >+	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16);
>> >
>> >-		I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe),
>> >CSC_RGB_TO_YUV_RV_GV);
>> >-		I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV);
>> >+	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]);
>> >+	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16);
>> >
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe),
>> >POSTOFF_RGB_TO_YUV_HI);
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe),
>> >POSTOFF_RGB_TO_YUV_ME);
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe),
>> >POSTOFF_RGB_TO_YUV_LO);
>> >-	} else {
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), 0);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), 0);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), 0);
>> >-
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe),
>> >-			   CSC_RGB_TO_YUV_RU_GU);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe),
>> >CSC_RGB_TO_YUV_BU);
>> >-
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe),
>> >-			   CSC_RGB_TO_YUV_RY_GY);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe),
>> >CSC_RGB_TO_YUV_BY);
>> >-
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe),
>> >-			   CSC_RGB_TO_YUV_RV_GV);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe),
>> >CSC_RGB_TO_YUV_BV);
>> >-
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe),
>> >-			   POSTOFF_RGB_TO_YUV_HI);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe),
>> >-			   POSTOFF_RGB_TO_YUV_ME);
>> >-		I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe),
>> >-			   POSTOFF_RGB_TO_YUV_LO);
>> >+	if (INTEL_GEN(dev_priv) >= 7) {
>> >+		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]);
>> >+		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]);
>> >+		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]);
>> > 	}
>> > }
>> >
>> >+static void icl_update_output_csc(struct intel_crtc *crtc,
>> >+				  const u16 preoff[3],
>> >+				  const u16 coeff[9],
>> >+				  const u16 postoff[3])
>> >+{
>> >+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> >+	enum pipe pipe = crtc->pipe;
>> >+
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]);
>> >+
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 |
>> >coeff[1]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2]);
>> >+
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 |
>> >coeff[4]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5]);
>> >+
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 |
>> >coeff[7]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8]);
>> >+
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]);
>> >+	I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); }
>> >+
>> > static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)  {
>> > 	struct drm_i915_private *dev_priv =
>> >to_i915(crtc_state->base.crtc->dev);
>> >@@ -185,7 +199,15 @@ static void ilk_load_csc_matrix(const struct
>> >intel_crtc_state
>> >*crtc_state)
>> >
>> > 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>> > 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>> >-		ilk_load_ycbcr_conversion_matrix(crtc);
>> >+		if (INTEL_GEN(dev_priv) >= 11)
>> >+			icl_update_output_csc(crtc, ilk_csc_off_zero,
>> >+					      ilk_csc_coeff_rgb_to_ycbcr,
>> >+					      ilk_csc_postoff_rgb_to_ycbcr);
>> >+		else
>> >+			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>> >+					    ilk_csc_coeff_rgb_to_ycbcr,
>> >+					    ilk_csc_postoff_rgb_to_ycbcr);
>> >+
>> > 		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>> > 		/*
>> > 		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC @@ -
>> >258,38 +280,12 @@ static void ilk_load_csc_matrix(const struct
>> >intel_crtc_state
>> >*crtc_state)
>> > 		}
>> > 	}
>> >
>> >-	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeffs[0] << 16 | coeffs[1]);
>> >-	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeffs[2] << 16);
>> >-
>> >-	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeffs[3] << 16 | coeffs[4]);
>> >-	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeffs[5] << 16);
>> >-
>> >-	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeffs[6] << 16 | coeffs[7]);
>> >-	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeffs[8] << 16);
>> >+	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
>> >+			    limited_color_range ?
>> >+			    ilk_csc_postoff_limited_range :
>> >+			    ilk_csc_off_zero);
>> >
>> >-	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
>> >-	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
>> >-	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
>> >-
>> >-	if (INTEL_GEN(dev_priv) > 6) {
>> >-		u16 postoff = 0;
>> >-
>> >-		if (limited_color_range)
>> >-			postoff = (16 * (1 << 12) / 255) & 0x1fff;
>> >-
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>> >-		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>> >-
>> >-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>> >-	} else {
>> >-		u32 mode = CSC_MODE_YUV_TO_RGB;
>> >-
>> >-		if (limited_color_range)
>> >-			mode |= CSC_BLACK_SCREEN_OFFSET;
>> >-
>> >-		I915_WRITE(PIPE_CSC_MODE(pipe), mode);
>>
>> Looks like this is not handled and got dropped. Pre Gen7 stuff.
>
>Yeah, we don't use the CSC (yet) on pre-HSW. Even if we start to use it we'll not be
>using it for RGB full->limited conversion.
>So we won't actually program it like this in the end.

Hmm ok, got it. In that case, its ok to drop it. 

>>
>> >-	}
>> >+	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>> > }
>> >
>> > /*
>> >--
>> >2.19.2
>>
>
>--
>Ville Syrjälä
>Intel
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[PATCH 5/7] drm/i915: Extract ilk_csc_convert_ctm()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Start splitting low level nuts and bots stuff from
ilk_load_csc_matrix(). The goal is to leave only the clear
high level logic in place.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 97 ++++++++++++++++--------------
 1 file changed, 53 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 61cb69058b35..0be7b7e802f5 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -188,6 +188,58 @@ static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state)
 		 IS_GEN_RANGE(dev_priv, 9, 10));
 }
 
+static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
+				u16 coeffs[9])
+{
+	const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
+	const u64 *input;
+	u64 temp[9];
+	int i;
+
+	if (ilk_csc_limited_range(crtc_state))
+		input = ctm_mult_by_limited(temp, ctm->matrix);
+	else
+		input = ctm->matrix;
+
+	/*
+	 * Convert fixed point S31.32 input to format supported by the
+	 * hardware.
+	 */
+	for (i = 0; i < 9; i++) {
+		u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
+
+		/*
+		 * Clamp input value to min/max supported by
+		 * hardware.
+		 */
+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
+
+		coeffs[i] = 0;
+
+		/* sign bit */
+		if (CTM_COEFF_NEGATIVE(input[i]))
+			coeffs[i] |= 1 << 15;
+
+		if (abs_coeff < CTM_COEFF_0_125)
+			coeffs[i] |= (3 << 12) |
+				ILK_CSC_COEFF_FP(abs_coeff, 12);
+		else if (abs_coeff < CTM_COEFF_0_25)
+			coeffs[i] |= (2 << 12) |
+				ILK_CSC_COEFF_FP(abs_coeff, 11);
+		else if (abs_coeff < CTM_COEFF_0_5)
+			coeffs[i] |= (1 << 12) |
+				ILK_CSC_COEFF_FP(abs_coeff, 10);
+		else if (abs_coeff < CTM_COEFF_1_0)
+			coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
+		else if (abs_coeff < CTM_COEFF_2_0)
+			coeffs[i] |= (7 << 12) |
+				ILK_CSC_COEFF_FP(abs_coeff, 8);
+		else
+			coeffs[i] |= (6 << 12) |
+				ILK_CSC_COEFF_FP(abs_coeff, 7);
+	}
+}
+
 static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -218,50 +270,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	}
 
 	if (crtc_state->base.ctm) {
-		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
-		const u64 *input;
-		u64 temp[9];
-
-		if (limited_color_range)
-			input = ctm_mult_by_limited(temp, ctm->matrix);
-		else
-			input = ctm->matrix;
-
-		/*
-		 * Convert fixed point S31.32 input to format supported by the
-		 * hardware.
-		 */
-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
-			u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
-
-			/*
-			 * Clamp input value to min/max supported by
-			 * hardware.
-			 */
-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
-
-			/* sign bit */
-			if (CTM_COEFF_NEGATIVE(input[i]))
-				coeffs[i] |= 1 << 15;
-
-			if (abs_coeff < CTM_COEFF_0_125)
-				coeffs[i] |= (3 << 12) |
-					ILK_CSC_COEFF_FP(abs_coeff, 12);
-			else if (abs_coeff < CTM_COEFF_0_25)
-				coeffs[i] |= (2 << 12) |
-					ILK_CSC_COEFF_FP(abs_coeff, 11);
-			else if (abs_coeff < CTM_COEFF_0_5)
-				coeffs[i] |= (1 << 12) |
-					ILK_CSC_COEFF_FP(abs_coeff, 10);
-			else if (abs_coeff < CTM_COEFF_1_0)
-				coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
-			else if (abs_coeff < CTM_COEFF_2_0)
-				coeffs[i] |= (7 << 12) |
-					ILK_CSC_COEFF_FP(abs_coeff, 8);
-			else
-				coeffs[i] |= (6 << 12) |
-					ILK_CSC_COEFF_FP(abs_coeff, 7);
-		}
+		ilk_csc_convert_ctm(crtc_state, coeffs);
 	} else {
 		/*
 		 * Load an identity matrix if no coefficients are provided.
-- 
2.19.2

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Re: [PATCH 5/7] drm/i915: Extract ilk_csc_convert_ctm()

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 5/7] drm/i915: Extract ilk_csc_convert_ctm()
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Start splitting low level nuts and bots stuff from ilk_load_csc_matrix(). The goal is to

Typo in bolts. 

Else change looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>leave only the clear high level logic in place.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 97 ++++++++++++++++--------------
> 1 file changed, 53 insertions(+), 44 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index 61cb69058b35..0be7b7e802f5 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -188,6 +188,58 @@ static bool ilk_csc_limited_range(const struct
>intel_crtc_state *crtc_state)
> 		 IS_GEN_RANGE(dev_priv, 9, 10));
> }
>
>+static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state,
>+				u16 coeffs[9])
>+{
>+	const struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>+	const u64 *input;
>+	u64 temp[9];
>+	int i;
>+
>+	if (ilk_csc_limited_range(crtc_state))
>+		input = ctm_mult_by_limited(temp, ctm->matrix);
>+	else
>+		input = ctm->matrix;
>+
>+	/*
>+	 * Convert fixed point S31.32 input to format supported by the
>+	 * hardware.
>+	 */
>+	for (i = 0; i < 9; i++) {
>+		u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
>+
>+		/*
>+		 * Clamp input value to min/max supported by
>+		 * hardware.
>+		 */
>+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
>+
>+		coeffs[i] = 0;
>+
>+		/* sign bit */
>+		if (CTM_COEFF_NEGATIVE(input[i]))
>+			coeffs[i] |= 1 << 15;
>+
>+		if (abs_coeff < CTM_COEFF_0_125)
>+			coeffs[i] |= (3 << 12) |
>+				ILK_CSC_COEFF_FP(abs_coeff, 12);
>+		else if (abs_coeff < CTM_COEFF_0_25)
>+			coeffs[i] |= (2 << 12) |
>+				ILK_CSC_COEFF_FP(abs_coeff, 11);
>+		else if (abs_coeff < CTM_COEFF_0_5)
>+			coeffs[i] |= (1 << 12) |
>+				ILK_CSC_COEFF_FP(abs_coeff, 10);
>+		else if (abs_coeff < CTM_COEFF_1_0)
>+			coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
>+		else if (abs_coeff < CTM_COEFF_2_0)
>+			coeffs[i] |= (7 << 12) |
>+				ILK_CSC_COEFF_FP(abs_coeff, 8);
>+		else
>+			coeffs[i] |= (6 << 12) |
>+				ILK_CSC_COEFF_FP(abs_coeff, 7);
>+	}
>+}
>+
> static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)  {
> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>@@ -218,50 +270,7 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
>*crtc_state)
> 	}
>
> 	if (crtc_state->base.ctm) {
>-		struct drm_color_ctm *ctm = crtc_state->base.ctm->data;
>-		const u64 *input;
>-		u64 temp[9];
>-
>-		if (limited_color_range)
>-			input = ctm_mult_by_limited(temp, ctm->matrix);
>-		else
>-			input = ctm->matrix;
>-
>-		/*
>-		 * Convert fixed point S31.32 input to format supported by the
>-		 * hardware.
>-		 */
>-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
>-			u64 abs_coeff = ((1ULL << 63) - 1) & input[i];
>-
>-			/*
>-			 * Clamp input value to min/max supported by
>-			 * hardware.
>-			 */
>-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_4_0 - 1);
>-
>-			/* sign bit */
>-			if (CTM_COEFF_NEGATIVE(input[i]))
>-				coeffs[i] |= 1 << 15;
>-
>-			if (abs_coeff < CTM_COEFF_0_125)
>-				coeffs[i] |= (3 << 12) |
>-					ILK_CSC_COEFF_FP(abs_coeff, 12);
>-			else if (abs_coeff < CTM_COEFF_0_25)
>-				coeffs[i] |= (2 << 12) |
>-					ILK_CSC_COEFF_FP(abs_coeff, 11);
>-			else if (abs_coeff < CTM_COEFF_0_5)
>-				coeffs[i] |= (1 << 12) |
>-					ILK_CSC_COEFF_FP(abs_coeff, 10);
>-			else if (abs_coeff < CTM_COEFF_1_0)
>-				coeffs[i] |= ILK_CSC_COEFF_FP(abs_coeff, 9);
>-			else if (abs_coeff < CTM_COEFF_2_0)
>-				coeffs[i] |= (7 << 12) |
>-					ILK_CSC_COEFF_FP(abs_coeff, 8);
>-			else
>-				coeffs[i] |= (6 << 12) |
>-					ILK_CSC_COEFF_FP(abs_coeff, 7);
>-		}
>+		ilk_csc_convert_ctm(crtc_state, coeffs);
> 	} else {
> 		/*
> 		 * Load an identity matrix if no coefficients are provided.
>--
>2.19.2

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[PATCH 6/7] drm/i915: Clean the csc limited range/identity programming

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Just provide precomputed CSC matrices for the identfy and
limite range cases. This removes the remaining nuts and bolts
stuff from ilk_load_csc_matrix(), allowing one to actually
see the high level logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 53 +++++++++++++++---------------
 1 file changed, 27 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 0be7b7e802f5..adc5c25a6fcd 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -52,21 +52,31 @@
 #define ILK_CSC_COEFF_FP(coeff, fbits)	\
 	(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
 
-#define ILK_CSC_COEFF_LIMITED_RANGE	\
-	ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
-#define ILK_CSC_COEFF_1_0		\
-	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
+#define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0
+#define ILK_CSC_COEFF_1_0 0x7800
 
 #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
 
 static const u16 ilk_csc_off_zero[3] = {};
 
+static const u16 ilk_csc_coeff_identity[9] = {
+	ILK_CSC_COEFF_1_0, 0, 0,
+	0, ILK_CSC_COEFF_1_0, 0,
+	0, 0, ILK_CSC_COEFF_1_0,
+};
+
 static const u16 ilk_csc_postoff_limited_range[3] = {
 	ILK_CSC_POSTOFF_LIMITED_RANGE,
 	ILK_CSC_POSTOFF_LIMITED_RANGE,
 	ILK_CSC_POSTOFF_LIMITED_RANGE,
 };
 
+static const u16 ilk_csc_coeff_limited_range[9] = {
+	ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
+	0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
+	0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
+};
+
 /*
  * These values are direct register values specified in the Bspec,
  * for RGB->YUV conversion matrix (colorspace BT709)
@@ -247,7 +257,6 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
 	enum pipe pipe = crtc->pipe;
 	u16 coeffs[9] = {};
-	int i;
 
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
@@ -271,28 +280,20 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 
 	if (crtc_state->base.ctm) {
 		ilk_csc_convert_ctm(crtc_state, coeffs);
-	} else {
-		/*
-		 * Load an identity matrix if no coefficients are provided.
-		 *
-		 * TODO: Check what kind of values actually come out of the
-		 * pipe with these coeff/postoff values and adjust to get the
-		 * best accuracy. Perhaps we even need to take the bpc value
-		 * into consideration.
-		 */
-		for (i = 0; i < 3; i++) {
-			if (limited_color_range)
-				coeffs[i * 3 + i] =
-					ILK_CSC_COEFF_LIMITED_RANGE;
-			else
-				coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
-		}
-	}
 
-	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
-			    limited_color_range ?
-			    ilk_csc_postoff_limited_range :
-			    ilk_csc_off_zero);
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
+				    limited_color_range ?
+				    ilk_csc_postoff_limited_range :
+				    ilk_csc_off_zero);
+	} else if (limited_color_range) {
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
+				    ilk_csc_coeff_limited_range,
+				    ilk_csc_postoff_limited_range);
+	} else if (crtc_state->csc_enable) {
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
+				    ilk_csc_coeff_identity,
+				    ilk_csc_off_zero);
+	}
 
 	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
 }
-- 
2.19.2

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Re: [PATCH 6/7] drm/i915: Clean the csc limited range/identity programming

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 6/7] drm/i915: Clean the csc limited range/identity programming
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Just provide precomputed CSC matrices for the identfy and limite range cases. This

Some typo's here.

>removes the remaining nuts and bolts stuff from ilk_load_csc_matrix(), allowing one
>to actually see the high level logic.

With the above fixed.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 53 +++++++++++++++---------------
> 1 file changed, 27 insertions(+), 26 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index 0be7b7e802f5..adc5c25a6fcd 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -52,21 +52,31 @@
> #define ILK_CSC_COEFF_FP(coeff, fbits)	\
> 	(clamp_val(((coeff) >> (32 - (fbits) - 3)) + 4, 0, 0xfff) & 0xff8)
>
>-#define ILK_CSC_COEFF_LIMITED_RANGE	\
>-	ILK_CSC_COEFF_FP(CTM_COEFF_LIMITED_RANGE, 9)
>-#define ILK_CSC_COEFF_1_0		\
>-	((7 << 12) | ILK_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
>+#define ILK_CSC_COEFF_LIMITED_RANGE 0x0dc0 #define ILK_CSC_COEFF_1_0
>+0x7800
>
> #define ILK_CSC_POSTOFF_LIMITED_RANGE (16 * (1 << 12) / 255)
>
> static const u16 ilk_csc_off_zero[3] = {};
>
>+static const u16 ilk_csc_coeff_identity[9] = {
>+	ILK_CSC_COEFF_1_0, 0, 0,
>+	0, ILK_CSC_COEFF_1_0, 0,
>+	0, 0, ILK_CSC_COEFF_1_0,
>+};
>+
> static const u16 ilk_csc_postoff_limited_range[3] = {
> 	ILK_CSC_POSTOFF_LIMITED_RANGE,
> 	ILK_CSC_POSTOFF_LIMITED_RANGE,
> 	ILK_CSC_POSTOFF_LIMITED_RANGE,
> };
>
>+static const u16 ilk_csc_coeff_limited_range[9] = {
>+	ILK_CSC_COEFF_LIMITED_RANGE, 0, 0,
>+	0, ILK_CSC_COEFF_LIMITED_RANGE, 0,
>+	0, 0, ILK_CSC_COEFF_LIMITED_RANGE,
>+};
>+
> /*
>  * These values are direct register values specified in the Bspec,
>  * for RGB->YUV conversion matrix (colorspace BT709) @@ -247,7 +257,6 @@ static
>void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
> 	enum pipe pipe = crtc->pipe;
> 	u16 coeffs[9] = {};
>-	int i;
>
> 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
> 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) { @@
>-271,28 +280,20 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
>*crtc_state)
>
> 	if (crtc_state->base.ctm) {
> 		ilk_csc_convert_ctm(crtc_state, coeffs);
>-	} else {
>-		/*
>-		 * Load an identity matrix if no coefficients are provided.
>-		 *
>-		 * TODO: Check what kind of values actually come out of the
>-		 * pipe with these coeff/postoff values and adjust to get the
>-		 * best accuracy. Perhaps we even need to take the bpc value
>-		 * into consideration.
>-		 */
>-		for (i = 0; i < 3; i++) {
>-			if (limited_color_range)
>-				coeffs[i * 3 + i] =
>-					ILK_CSC_COEFF_LIMITED_RANGE;
>-			else
>-				coeffs[i * 3 + i] = ILK_CSC_COEFF_1_0;
>-		}
>-	}
>
>-	ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
>-			    limited_color_range ?
>-			    ilk_csc_postoff_limited_range :
>-			    ilk_csc_off_zero);
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
>+				    limited_color_range ?
>+				    ilk_csc_postoff_limited_range :
>+				    ilk_csc_off_zero);
>+	} else if (limited_color_range) {
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>+				    ilk_csc_coeff_limited_range,
>+				    ilk_csc_postoff_limited_range);
>+	} else if (crtc_state->csc_enable) {
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>+				    ilk_csc_coeff_identity,
>+				    ilk_csc_off_zero);
>+	}
>
> 	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);  }
>--
>2.19.2

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[PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split the csc matrix handling to ilk+ and icl+ functions.
This keeps the logic clear on what is loaded into which
CSC unit on the hardware.

We also fix the icl+ code to load the full->limited range
conversion matrix into the output CSC rather than the pipe
CSC which was used on earlier platforms. And we also turn
on the pipe CSC only when the ctm is present.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_color.c | 71 ++++++++++++++++++------------
 1 file changed, 42 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index adc5c25a6fcd..ae91a4db71cf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -255,36 +255,19 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
-	enum pipe pipe = crtc->pipe;
-	u16 coeffs[9] = {};
-
-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
-		if (INTEL_GEN(dev_priv) >= 11)
-			icl_update_output_csc(crtc, ilk_csc_off_zero,
-					      ilk_csc_coeff_rgb_to_ycbcr,
-					      ilk_csc_postoff_rgb_to_ycbcr);
-		else
-			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
-					    ilk_csc_coeff_rgb_to_ycbcr,
-					    ilk_csc_postoff_rgb_to_ycbcr);
-
-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
-		/*
-		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC
-		 * RGB to YUV conversion can be done. No need to go further
-		 */
-		if (INTEL_GEN(dev_priv) < 11)
-			return;
-	}
 
 	if (crtc_state->base.ctm) {
-		ilk_csc_convert_ctm(crtc_state, coeffs);
+		u16 coeff[9];
 
-		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
+		ilk_csc_convert_ctm(crtc_state, coeff);
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
 				    limited_color_range ?
 				    ilk_csc_postoff_limited_range :
 				    ilk_csc_off_zero);
+	} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
+				    ilk_csc_coeff_rgb_to_ycbcr,
+				    ilk_csc_postoff_rgb_to_ycbcr);
 	} else if (limited_color_range) {
 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
 				    ilk_csc_coeff_limited_range,
@@ -295,7 +278,33 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 				    ilk_csc_off_zero);
 	}
 
-	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
+	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
+}
+
+static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	if (crtc_state->base.ctm) {
+		u16 coeff[9];
+
+		ilk_csc_convert_ctm(crtc_state, coeff);
+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
+				    coeff, ilk_csc_off_zero);
+	}
+
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
+		icl_update_output_csc(crtc, ilk_csc_off_zero,
+				      ilk_csc_coeff_rgb_to_ycbcr,
+				      ilk_csc_postoff_rgb_to_ycbcr);
+	} else if (crtc_state->limited_color_range) {
+		icl_update_output_csc(crtc, ilk_csc_off_zero,
+				      ilk_csc_coeff_limited_range,
+				      ilk_csc_postoff_limited_range);
+	}
+
+	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
 }
 
 /*
@@ -445,7 +454,10 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 
 	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
 
-	ilk_load_csc_matrix(crtc_state);
+	if (INTEL_GEN(dev_priv) >= 11)
+		icl_load_csc_matrix(crtc_state);
+	else
+		ilk_load_csc_matrix(crtc_state);
 }
 
 static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state)
@@ -843,11 +855,12 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
-		    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
+		if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
+		    crtc_state->limited_color_range)
 			crtc_state->csc_mode |= ICL_OUTPUT_CSC_ENABLE;
 
-		crtc_state->csc_mode |= ICL_CSC_ENABLE;
+		if (crtc_state->base.ctm)
+			crtc_state->csc_mode |= ICL_CSC_ENABLE;
 	}
 
 	return 0;
-- 
2.19.2

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Re: [PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling

[Shankar, Uma]

>-----Original Message-----
>From: Ville Syrjala [mailto:ville.syrjala@linux.intel.com]
>Sent: Tuesday, February 19, 2019 1:02 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Shankar, Uma <uma.shankar@intel.com>; Roper, Matthew D
><matthew.d.roper@intel.com>
>Subject: [PATCH 7/7] drm/i915: Split ilk vs. icl csc matrix handling
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Split the csc matrix handling to ilk+ and icl+ functions.
>This keeps the logic clear on what is loaded into which CSC unit on the hardware.
>
>We also fix the icl+ code to load the full->limited range conversion matrix into the
>output CSC rather than the pipe CSC which was used on earlier platforms. And we also
>turn on the pipe CSC only when the ctm is present.

Look good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/intel_color.c | 71 ++++++++++++++++++------------
> 1 file changed, 42 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
>index adc5c25a6fcd..ae91a4db71cf 100644
>--- a/drivers/gpu/drm/i915/intel_color.c
>+++ b/drivers/gpu/drm/i915/intel_color.c
>@@ -255,36 +255,19 @@ static void ilk_load_csc_matrix(const struct
>intel_crtc_state *crtc_state)
> 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> 	bool limited_color_range = ilk_csc_limited_range(crtc_state);
>-	enum pipe pipe = crtc->pipe;
>-	u16 coeffs[9] = {};
>-
>-	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
>-	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
>-		if (INTEL_GEN(dev_priv) >= 11)
>-			icl_update_output_csc(crtc, ilk_csc_off_zero,
>-					      ilk_csc_coeff_rgb_to_ycbcr,
>-					      ilk_csc_postoff_rgb_to_ycbcr);
>-		else
>-			ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>-					    ilk_csc_coeff_rgb_to_ycbcr,
>-					    ilk_csc_postoff_rgb_to_ycbcr);
>-
>-		I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>-		/*
>-		 * On pre GEN11 output CSC is not there, so with 1 pipe CSC
>-		 * RGB to YUV conversion can be done. No need to go further
>-		 */
>-		if (INTEL_GEN(dev_priv) < 11)
>-			return;
>-	}
>
> 	if (crtc_state->base.ctm) {
>-		ilk_csc_convert_ctm(crtc_state, coeffs);
>+		u16 coeff[9];
>
>-		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeffs,
>+		ilk_csc_convert_ctm(crtc_state, coeff);
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero, coeff,
> 				    limited_color_range ?
> 				    ilk_csc_postoff_limited_range :
> 				    ilk_csc_off_zero);
>+	} else if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>+				    ilk_csc_coeff_rgb_to_ycbcr,
>+				    ilk_csc_postoff_rgb_to_ycbcr);
> 	} else if (limited_color_range) {
> 		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
> 				    ilk_csc_coeff_limited_range,
>@@ -295,7 +278,33 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state
>*crtc_state)
> 				    ilk_csc_off_zero);
> 	}
>
>-	I915_WRITE(PIPE_CSC_MODE(pipe), crtc_state->csc_mode);
>+	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); }
>+
>+static void icl_load_csc_matrix(const struct intel_crtc_state
>+*crtc_state) {
>+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+
>+	if (crtc_state->base.ctm) {
>+		u16 coeff[9];
>+
>+		ilk_csc_convert_ctm(crtc_state, coeff);
>+		ilk_update_pipe_csc(crtc, ilk_csc_off_zero,
>+				    coeff, ilk_csc_off_zero);
>+	}
>+
>+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) {
>+		icl_update_output_csc(crtc, ilk_csc_off_zero,
>+				      ilk_csc_coeff_rgb_to_ycbcr,
>+				      ilk_csc_postoff_rgb_to_ycbcr);
>+	} else if (crtc_state->limited_color_range) {
>+		icl_update_output_csc(crtc, ilk_csc_off_zero,
>+				      ilk_csc_coeff_limited_range,
>+				      ilk_csc_postoff_limited_range);
>+	}
>+
>+	I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode);
> }
>
> /*
>@@ -445,7 +454,10 @@ static void skl_color_commit(const struct intel_crtc_state
>*crtc_state)
>
> 	I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
>
>-	ilk_load_csc_matrix(crtc_state);
>+	if (INTEL_GEN(dev_priv) >= 11)
>+		icl_load_csc_matrix(crtc_state);
>+	else
>+		ilk_load_csc_matrix(crtc_state);
> }
>
> static void bdw_load_degamma_lut(const struct intel_crtc_state *crtc_state) @@ -
>843,11 +855,12 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
> 		crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
>
> 	if (INTEL_GEN(dev_priv) >= 11) {
>-		if (crtc_state->output_format ==
>INTEL_OUTPUT_FORMAT_YCBCR420 ||
>-		    crtc_state->output_format ==
>INTEL_OUTPUT_FORMAT_YCBCR444)
>+		if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB ||
>+		    crtc_state->limited_color_range)
> 			crtc_state->csc_mode |= ICL_OUTPUT_CSC_ENABLE;
>
>-		crtc_state->csc_mode |= ICL_CSC_ENABLE;
>+		if (crtc_state->base.ctm)
>+			crtc_state->csc_mode |= ICL_CSC_ENABLE;
> 	}
>
> 	return 0;
>--
>2.19.2

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✗ Fi.CI.SPARSE: warning for drm/i915: Clean up ilk+ csc stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up ilk+ csc stuff
URL   : https://patchwork.freedesktop.org/series/56857/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Readout and check csc_mode
Okay!

Commit: drm/i915: Preocmpute/readout/check CHV CGM mode
Okay!

Commit: drm/i915: Extract ilk_csc_limited_range()
Okay!

Commit: drm/i915: Clean up ilk/icl pipe/output CSC programming
Okay!

Commit: drm/i915: Extract ilk_csc_convert_ctm()
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:241:37: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:249:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:252:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:255:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:257:46: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:260:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_color.c:263:41: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:215:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:225:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:228:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:231:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:233:38: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:236:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_color.c:239:33: warning: expression using sizeof(void)

Commit: drm/i915: Clean the csc limited range/identity programming
Okay!

Commit: drm/i915: Split ilk vs. icl csc matrix handling
Okay!

_______________________________________________
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✗ Fi.CI.BAT: failure for drm/i915: Clean up ilk+ csc stuff

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up ilk+ csc stuff
URL   : https://patchwork.freedesktop.org/series/56857/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5628 -> Patchwork_12251
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12251 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12251, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56857/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12251:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7567u:       PASS -> FAIL +2

  
Known issues
------------

  Here are the changes found in Patchwork_12251 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]

  * igt@gem_exec_suspend@basic-s3:
    - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]

  * igt@i915_module_load@reload:
    - fi-blb-e6850:       NOTRUN -> INCOMPLETE [fdo#107718]

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-7567u:       PASS -> DMESG-FAIL [fdo#105079]

  * igt@pm_rpm@module-reload:
    - fi-kbl-7567u:       NOTRUN -> DMESG-WARN [fdo#108529]

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315


Participating hosts (47 -> 40)
------------------------------

  Additional (1): fi-icl-u3 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-skl-6700k2 


Build changes
-------------

    * Linux: CI_DRM_5628 -> Patchwork_12251

  CI_DRM_5628: 7f6ace5f10a9d6c5d277b95e39f862eff87fdb45 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4836: 51d069e07b3f7697f06fa8947ee92a196356d8b3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12251: b73647fba7bc7cc31ceb1049e8ef419a81e7d02e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

b73647fba7bc drm/i915: Split ilk vs. icl csc matrix handling
d2e4313a1339 drm/i915: Clean the csc limited range/identity programming
3519fcb20e99 drm/i915: Extract ilk_csc_convert_ctm()
34d9c779bc86 drm/i915: Clean up ilk/icl pipe/output CSC programming
13b47b302e6a drm/i915: Extract ilk_csc_limited_range()
b20e16c5b848 drm/i915: Preocmpute/readout/check CHV CGM mode
b09761d15ddf drm/i915: Readout and check csc_mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12251/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.BAT: failure for drm/i915: Clean up ilk+ csc stuff

[Ville Syrjälä]

On Mon, Feb 18, 2019 at 08:35:33PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Clean up ilk+ csc stuff
> URL   : https://patchwork.freedesktop.org/series/56857/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5628 -> Patchwork_12251
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_12251 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_12251, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://patchwork.freedesktop.org/api/1.0/series/56857/revisions/1/mbox/
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_12251:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_chamelium@hdmi-edid-read:
>     - fi-kbl-7567u:       PASS -> FAIL +2
> 

LSPCON stuck its head in the sand during suspend. Later on a second suspend
cycle seems to have roused it back up.

   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_12251 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@debugfs_test@read_all_entries:
>     - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105602]
> 
>   * igt@gem_exec_suspend@basic-s3:
>     - fi-kbl-7567u:       PASS -> DMESG-WARN [fdo#103558] / [fdo#105079] / [fdo#105602]
> 
>   * igt@i915_module_load@reload:
>     - fi-blb-e6850:       NOTRUN -> INCOMPLETE [fdo#107718]
> 
>   * igt@i915_selftest@live_execlists:
>     - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927]
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
>     - fi-kbl-7567u:       PASS -> DMESG-FAIL [fdo#105079]
> 
>   * igt@pm_rpm@module-reload:
>     - fi-kbl-7567u:       NOTRUN -> DMESG-WARN [fdo#108529]
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_suspend@basic-s4-devices:
>     - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
>   [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
>   [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
>   [fdo#108529]: https://bugs.freedesktop.org/show_bug.cgi?id=108529
>   [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
>   [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
>   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
>   [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> 
> 
> Participating hosts (47 -> 40)
> ------------------------------
> 
>   Additional (1): fi-icl-u3 
>   Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus fi-skl-6700k2 
> 
> 
> Build changes
> -------------
> 
>     * Linux: CI_DRM_5628 -> Patchwork_12251
> 
>   CI_DRM_5628: 7f6ace5f10a9d6c5d277b95e39f862eff87fdb45 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4836: 51d069e07b3f7697f06fa8947ee92a196356d8b3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_12251: b73647fba7bc7cc31ceb1049e8ef419a81e7d02e @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> 
> == Linux commits ==
> 
> b73647fba7bc drm/i915: Split ilk vs. icl csc matrix handling
> d2e4313a1339 drm/i915: Clean the csc limited range/identity programming
> 3519fcb20e99 drm/i915: Extract ilk_csc_convert_ctm()
> 34d9c779bc86 drm/i915: Clean up ilk/icl pipe/output CSC programming
> 13b47b302e6a drm/i915: Extract ilk_csc_limited_range()
> b20e16c5b848 drm/i915: Preocmpute/readout/check CHV CGM mode
> b09761d15ddf drm/i915: Readout and check csc_mode
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12251/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915: Clean up ilk+ csc stuff (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up ilk+ csc stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/56857/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5753 -> Patchwork_12478
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56857/revisions/2/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12478 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-kbl-8809g:       NOTRUN -> FAIL [fdo#108094]

  * igt@amdgpu/amd_cs_nop@sync-gfx0:
    - fi-kbl-7567u:       NOTRUN -> SKIP [fdo#109271] +33

  * igt@gem_exec_basic@gtt-bsd:
    - fi-bwr-2160:        NOTRUN -> SKIP [fdo#109271] +103

  * igt@gem_exec_basic@readonly-bsd2:
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] +76

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-icl-u3:          PASS -> DMESG-WARN [fdo#109638]

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]

  * igt@kms_busy@basic-flip-c:
    - fi-bwr-2160:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
    - fi-pnv-d510:        NOTRUN -> SKIP [fdo#109271] / [fdo#109278]

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-8809g:       NOTRUN -> SKIP [fdo#109271] +65

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-kbl-7560u:       NOTRUN -> SKIP [fdo#109271] +33

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - fi-blb-e6850:       NOTRUN -> SKIP [fdo#109271] +48

  * igt@runner@aborted:
    - fi-apl-guc:         NOTRUN -> FAIL [fdo#108622] / [fdo#109720]

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-kbl-7560u:       INCOMPLETE [fdo#103665] -> PASS

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       INCOMPLETE [fdo#107718] -> PASS

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         FAIL [fdo#103182] -> PASS +1

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          FAIL [fdo#103167] -> PASS

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-byt-clapper:     FAIL [fdo#103191] / [fdo#107362] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
  [fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720


Participating hosts (44 -> 43)
------------------------------

  Additional (4): fi-kbl-7567u fi-kbl-8809g fi-bwr-2160 fi-pnv-d510 
  Missing    (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 


Build changes
-------------

    * Linux: CI_DRM_5753 -> Patchwork_12478

  CI_DRM_5753: 0eb0838c0c26378949de6816166117c8b2d73caa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12478: ad1b68919282082c87040e7d6bf6697865c23797 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad1b68919282 drm/i915: Split ilk vs. icl csc matrix handling
a60b33b91254 drm/i915: Clean the csc limited range/identity programming
62a85894dc0d drm/i915: Extract ilk_csc_convert_ctm()
458b09e3c25d drm/i915: Clean up ilk/icl pipe/output CSC programming
7a8744563ab5 drm/i915: Extract ilk_csc_limited_range()
aeb702736320 drm/i915: Preocmpute/readout/check CHV CGM mode
99eabeb8a7fc drm/i915: Readout and check csc_mode

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12478/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.IGT: failure for drm/i915: Clean up ilk+ csc stuff (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Clean up ilk+ csc stuff (rev2)
URL   : https://patchwork.freedesktop.org/series/56857/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_5753_full -> Patchwork_12478_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_12478_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_12478_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12478_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         PASS -> FAIL

  
Known issues
------------

  Here are the changes found in Patchwork_12478_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@bsd1:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] +78

  * igt@gem_exec_params@no-blt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109283]

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-iclb:         NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#109766] / [fdo#109801]

  * igt@gem_pwrite@huge-gtt-random:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109290]

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107847]

  * igt@i915_pm_rpm@drm-resources-equal:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  * igt@i915_pm_rps@reset:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108059] +1

  * igt@kms_busy@basic-modeset-e:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1

  * igt@kms_busy@extended-modeset-hang-newfb-render-b:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +4

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-iclb:         PASS -> DMESG-WARN [fdo#107956]
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1

  * igt@kms_chamelium@vga-edid-read:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +1

  * igt@kms_color@pipe-b-degamma:
    - shard-skl:          PASS -> FAIL [fdo#104782]

  * igt@kms_color@pipe-b-legacy-gamma:
    - shard-iclb:         NOTRUN -> FAIL [fdo#104782]

  * igt@kms_cursor_crc@cursor-128x128-onscreen:
    - shard-skl:          NOTRUN -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x256-suspend:
    - shard-skl:          PASS -> FAIL [fdo#103191] / [fdo#103232]

  * igt@kms_cursor_crc@cursor-256x85-random:
    - shard-apl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          PASS -> FAIL [fdo#104873] +1

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          PASS -> FAIL [fdo#105454]

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-snb:          PASS -> SKIP [fdo#109271]

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-iclb:         PASS -> FAIL [fdo#103355] +1

  * igt@kms_dp_dsc@basic-dsc-enable-edp:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109358]

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +1

  * igt@kms_flip@dpms-vs-vblank-race:
    - shard-kbl:          PASS -> FAIL [fdo#103060]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-skl:          NOTRUN -> FAIL [fdo#103167]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +14

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-snb:          NOTRUN -> SKIP [fdo#109271] +44

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#103167] +5

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109247] +2

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
    - shard-iclb:         NOTRUN -> FAIL [fdo#103167] +4

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
    - shard-iclb:         PASS -> FAIL [fdo#109247] +21

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
    - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
    - shard-iclb:         NOTRUN -> FAIL [fdo#109052]

  * igt@kms_psr@cursor_plane_onoff:
    - shard-iclb:         NOTRUN -> FAIL [fdo#107383]

  * igt@kms_psr@cursor_render:
    - shard-iclb:         PASS -> FAIL [fdo#107383] +3

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         PASS -> SKIP [fdo#109441] +1

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109289]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> FAIL [fdo#109016]

  * igt@kms_universal_plane@cursor-fb-leak-pipe-d:
    - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-iclb:         PASS -> FAIL [fdo#104894]

  * igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109291] +3

  * igt@prime_vgem@coherency-gtt:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109292]

  * igt@prime_vgem@fence-wait-bsd1:
    - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +11

  
#### Possible fixes ####

  * igt@gem_exec_schedule@wide-blt:
    - shard-iclb:         DMESG-WARN [fdo#109638] -> PASS

  * igt@gem_exec_suspend@basic-s3:
    - shard-skl:          INCOMPLETE [fdo#104108] -> PASS

  * igt@gem_mmap_gtt@big-copy-xy:
    - shard-iclb:         TIMEOUT [fdo#109673] -> PASS

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS

  * igt@gem_ppgtt@blt-vs-render-ctx0:
    - shard-iclb:         INCOMPLETE [fdo#109100] / [fdo#109766] / [fdo#109801] -> PASS

  * igt@i915_selftest@live_workarounds:
    - shard-iclb:         DMESG-FAIL [fdo#108954] -> PASS

  * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108470] -> PASS

  * igt@kms_busy@extended-pageflip-hang-newfb-render-a:
    - shard-glk:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
    - shard-iclb:         FAIL [fdo#107725] -> PASS

  * igt@kms_color@pipe-b-legacy-gamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-128x128-sliding:
    - shard-apl:          FAIL [fdo#103232] -> PASS +1

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          FAIL [fdo#105454] / [fdo#106509] -> PASS

  * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
    - shard-iclb:         FAIL [fdo#103355] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-iclb:         FAIL [fdo#103167] -> PASS +6

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
    - shard-apl:          FAIL [fdo#103167] -> PASS +2

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-glk:          FAIL [fdo#103167] -> PASS +1

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
    - shard-iclb:         FAIL [fdo#109247] -> PASS +14

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - shard-skl:          FAIL [fdo#107362] -> PASS

  * {igt@kms_plane@plane-position-covered-pipe-a-planes}:
    - shard-apl:          FAIL [fdo#110038] -> PASS

  * {igt@kms_plane@plane-position-covered-pipe-b-planes}:
    - shard-iclb:         FAIL [fdo#110038] -> PASS +1

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS

  * {igt@kms_plane_multiple@atomic-pipe-a-tiling-none}:
    - shard-iclb:         FAIL [fdo#110037] -> PASS

  * {igt@kms_plane_multiple@atomic-pipe-a-tiling-x}:
    - shard-apl:          FAIL [fdo#110037] -> PASS +2

  * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS

  * igt@kms_psr@cursor_mmap_cpu:
    - shard-iclb:         FAIL [fdo#107383] -> PASS

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         SKIP [fdo#109441] -> PASS +3

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          DMESG-FAIL [fdo#105763] -> PASS

  * igt@kms_setmode@basic:
    - shard-apl:          FAIL [fdo#99912] -> PASS

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-skl:          FAIL [fdo#103167] -> INCOMPLETE [fdo#104108] / [fdo#106978]

  * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
    - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098]

  * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
    - shard-glk:          FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
  [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
  [fdo#109358]: https://bugs.freedesktop.org/show_bug.cgi?id=109358
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
  [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
  [fdo#109766]: https://bugs.freedesktop.org/show_bug.cgi?id=109766
  [fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
  [fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
  [fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
  [fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

    * Linux: CI_DRM_5753 -> Patchwork_12478

  CI_DRM_5753: 0eb0838c0c26378949de6816166117c8b2d73caa @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12478: ad1b68919282082c87040e7d6bf6697865c23797 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12478/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: ✗ Fi.CI.IGT: failure for drm/i915: Clean up ilk+ csc stuff (rev2)

[Ville Syrjälä]

On Fri, Mar 15, 2019 at 06:19:08PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Clean up ilk+ csc stuff (rev2)
> URL   : https://patchwork.freedesktop.org/series/56857/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_5753_full -> Patchwork_12478_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_12478_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_12478_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_12478_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@kms_psr@psr2_sprite_plane_move:
>     - shard-iclb:         PASS -> FAIL

Some kind of psr fail.

Starting subtest: psr2_sprite_plane_move
(kms_psr:13846) CRITICAL: Test assertion failure function test_setup, file ../tests/kms_psr.c:394:
(kms_psr:13846) CRITICAL: Failed assertion: psr_wait_entry_if_enabled(data)
Subtest psr2_sprite_plane_move failed.

> 
>   
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_12478_full that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_exec_parallel@bsd1:
>     - shard-skl:          NOTRUN -> SKIP [fdo#109271] +78
> 
>   * igt@gem_exec_params@no-blt:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109283]
> 
>   * igt@gem_ppgtt@blt-vs-render-ctxn:
>     - shard-iclb:         NOTRUN -> INCOMPLETE [fdo#107713] / [fdo#109766] / [fdo#109801]
> 
>   * igt@gem_pwrite@huge-gtt-random:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109290]
> 
>   * igt@i915_pm_backlight@fade_with_suspend:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#107847]
> 
>   * igt@i915_pm_rpm@drm-resources-equal:
>     - shard-apl:          PASS -> INCOMPLETE [fdo#103927]
> 
>   * igt@i915_pm_rps@reset:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#108059] +1
> 
>   * igt@kms_busy@basic-modeset-e:
>     - shard-snb:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
> 
>   * igt@kms_busy@extended-modeset-hang-newfb-render-b:
>     - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]
> 
>   * igt@kms_busy@extended-pageflip-hang-oldfb-render-d:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109278] +4
> 
>   * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
>     - shard-iclb:         PASS -> DMESG-WARN [fdo#107956]
>     - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956] +1
> 
>   * igt@kms_chamelium@vga-edid-read:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109284] +1
> 
>   * igt@kms_color@pipe-b-degamma:
>     - shard-skl:          PASS -> FAIL [fdo#104782]
> 
>   * igt@kms_color@pipe-b-legacy-gamma:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#104782]
> 
>   * igt@kms_cursor_crc@cursor-128x128-onscreen:
>     - shard-skl:          NOTRUN -> FAIL [fdo#103232]
> 
>   * igt@kms_cursor_crc@cursor-256x256-suspend:
>     - shard-skl:          PASS -> FAIL [fdo#103191] / [fdo#103232]
> 
>   * igt@kms_cursor_crc@cursor-256x85-random:
>     - shard-apl:          PASS -> FAIL [fdo#103232]
> 
>   * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
>     - shard-glk:          PASS -> FAIL [fdo#104873] +1
> 
>   * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
>     - shard-glk:          PASS -> FAIL [fdo#105454]
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
>     - shard-snb:          PASS -> SKIP [fdo#109271]
> 
>   * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
>     - shard-iclb:         PASS -> FAIL [fdo#103355] +1
> 
>   * igt@kms_dp_dsc@basic-dsc-enable-edp:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#109358]
> 
>   * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109274] +1
> 
>   * igt@kms_flip@dpms-vs-vblank-race:
>     - shard-kbl:          PASS -> FAIL [fdo#103060]
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
>     - shard-skl:          NOTRUN -> FAIL [fdo#103167]
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
>     - shard-apl:          PASS -> FAIL [fdo#103167] +1
> 
>   * igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109280] +14
> 
>   * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
>     - shard-snb:          NOTRUN -> SKIP [fdo#109271] +44
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
>     - shard-iclb:         PASS -> FAIL [fdo#103167] +5
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#109247] +2
> 
>   * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#103167] +4
> 
>   * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
>     - shard-iclb:         PASS -> FAIL [fdo#109247] +21
> 
>   * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
>     - shard-skl:          NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
> 
>   * igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
>     - shard-skl:          NOTRUN -> FAIL [fdo#108145] +2
> 
>   * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
>     - shard-skl:          PASS -> FAIL [fdo#108145]
> 
>   * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
>     - shard-skl:          PASS -> FAIL [fdo#107815]
> 
>   * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#109052]
> 
>   * igt@kms_psr@cursor_plane_onoff:
>     - shard-iclb:         NOTRUN -> FAIL [fdo#107383]
> 
>   * igt@kms_psr@cursor_render:
>     - shard-iclb:         PASS -> FAIL [fdo#107383] +3
> 
>   * igt@kms_psr@psr2_dpms:
>     - shard-iclb:         PASS -> SKIP [fdo#109441] +1
> 
>   * igt@kms_rotation_crc@bad-pixel-format:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109289]
> 
>   * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
>     - shard-kbl:          PASS -> FAIL [fdo#109016]
> 
>   * igt@kms_universal_plane@cursor-fb-leak-pipe-d:
>     - shard-skl:          NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +10
> 
>   * igt@kms_vblank@pipe-c-ts-continuation-suspend:
>     - shard-iclb:         PASS -> FAIL [fdo#104894]
> 
>   * igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109291] +3
> 
>   * igt@prime_vgem@coherency-gtt:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109292]
> 
>   * igt@prime_vgem@fence-wait-bsd1:
>     - shard-iclb:         NOTRUN -> SKIP [fdo#109276] +11
> 
>   
> #### Possible fixes ####
> 
>   * igt@gem_exec_schedule@wide-blt:
>     - shard-iclb:         DMESG-WARN [fdo#109638] -> PASS
> 
>   * igt@gem_exec_suspend@basic-s3:
>     - shard-skl:          INCOMPLETE [fdo#104108] -> PASS
> 
>   * igt@gem_mmap_gtt@big-copy-xy:
>     - shard-iclb:         TIMEOUT [fdo#109673] -> PASS
> 
>   * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
>     - shard-iclb:         INCOMPLETE [fdo#107713] -> PASS
> 
>   * igt@gem_ppgtt@blt-vs-render-ctx0:
>     - shard-iclb:         INCOMPLETE [fdo#109100] / [fdo#109766] / [fdo#109801] -> PASS
> 
>   * igt@i915_selftest@live_workarounds:
>     - shard-iclb:         DMESG-FAIL [fdo#108954] -> PASS
> 
>   * igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
>     - shard-skl:          FAIL [fdo#107815] / [fdo#108470] -> PASS
> 
>   * igt@kms_busy@extended-pageflip-hang-newfb-render-a:
>     - shard-glk:          DMESG-WARN [fdo#107956] -> PASS
> 
>   * igt@kms_ccs@pipe-b-crc-sprite-planes-basic:
>     - shard-iclb:         FAIL [fdo#107725] -> PASS
> 
>   * igt@kms_color@pipe-b-legacy-gamma:
>     - shard-apl:          FAIL [fdo#104782] -> PASS
> 
>   * igt@kms_cursor_crc@cursor-128x128-sliding:
>     - shard-apl:          FAIL [fdo#103232] -> PASS +1
> 
>   * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
>     - shard-glk:          FAIL [fdo#105454] / [fdo#106509] -> PASS
> 
>   * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
>     - shard-iclb:         FAIL [fdo#103355] -> PASS +1
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
>     - shard-iclb:         FAIL [fdo#103167] -> PASS +6
> 
>   * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
>     - shard-apl:          FAIL [fdo#103167] -> PASS +2
> 
>   * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
>     - shard-glk:          FAIL [fdo#103167] -> PASS +1
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
>     - shard-iclb:         FAIL [fdo#109247] -> PASS +14
> 
>   * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
>     - shard-skl:          FAIL [fdo#107362] -> PASS
> 
>   * {igt@kms_plane@plane-position-covered-pipe-a-planes}:
>     - shard-apl:          FAIL [fdo#110038] -> PASS
> 
>   * {igt@kms_plane@plane-position-covered-pipe-b-planes}:
>     - shard-iclb:         FAIL [fdo#110038] -> PASS +1
> 
>   * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
>     - shard-skl:          FAIL [fdo#107815] / [fdo#108145] -> PASS
> 
>   * {igt@kms_plane_multiple@atomic-pipe-a-tiling-none}:
>     - shard-iclb:         FAIL [fdo#110037] -> PASS
> 
>   * {igt@kms_plane_multiple@atomic-pipe-a-tiling-x}:
>     - shard-apl:          FAIL [fdo#110037] -> PASS +2
> 
>   * igt@kms_plane_scaling@pipe-b-scaler-with-clipping-clamping:
>     - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> PASS
> 
>   * igt@kms_psr@cursor_mmap_cpu:
>     - shard-iclb:         FAIL [fdo#107383] -> PASS
> 
>   * igt@kms_psr@psr2_primary_page_flip:
>     - shard-iclb:         SKIP [fdo#109441] -> PASS +3
> 
>   * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
>     - shard-kbl:          DMESG-FAIL [fdo#105763] -> PASS
> 
>   * igt@kms_setmode@basic:
>     - shard-apl:          FAIL [fdo#99912] -> PASS
> 
>   
> #### Warnings ####
> 
>   * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
>     - shard-skl:          FAIL [fdo#103167] -> INCOMPLETE [fdo#104108] / [fdo#106978]
> 
>   * igt@kms_plane_scaling@pipe-a-scaler-with-pixel-format:
>     - shard-glk:          SKIP [fdo#109271] / [fdo#109278] -> FAIL [fdo#110098]
> 
>   * igt@kms_plane_scaling@pipe-c-scaler-with-pixel-format:
>     - shard-glk:          FAIL [fdo#110098] -> SKIP [fdo#109271] / [fdo#109278]
> 
>   
>   {name}: This element is suppressed. This means it is ignored when computing
>           the status of the difference (SUCCESS, WARNING, or FAILURE).
> 
>   [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
>   [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
>   [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
>   [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
>   [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
>   [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
>   [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
>   [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
>   [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
>   [fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
>   [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
>   [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
>   [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
>   [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
>   [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
>   [fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
>   [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
>   [fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
>   [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
>   [fdo#107847]: https://bugs.freedesktop.org/show_bug.cgi?id=107847
>   [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
>   [fdo#108059]: https://bugs.freedesktop.org/show_bug.cgi?id=108059
>   [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
>   [fdo#108470]: https://bugs.freedesktop.org/show_bug.cgi?id=108470
>   [fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
>   [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
>   [fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
>   [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
>   [fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
>   [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
>   [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
>   [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
>   [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
>   [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
>   [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
>   [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
>   [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
>   [fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
>   [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
>   [fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
>   [fdo#109358]: https://bugs.freedesktop.org/show_bug.cgi?id=109358
>   [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
>   [fdo#109638]: https://bugs.freedesktop.org/show_bug.cgi?id=109638
>   [fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
>   [fdo#109766]: https://bugs.freedesktop.org/show_bug.cgi?id=109766
>   [fdo#109801]: https://bugs.freedesktop.org/show_bug.cgi?id=109801
>   [fdo#110037]: https://bugs.freedesktop.org/show_bug.cgi?id=110037
>   [fdo#110038]: https://bugs.freedesktop.org/show_bug.cgi?id=110038
>   [fdo#110098]: https://bugs.freedesktop.org/show_bug.cgi?id=110098
>   [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> Participating hosts (10 -> 10)
> ------------------------------
> 
>   No changes in participating hosts
> 
> 
> Build changes
> -------------
> 
>     * Linux: CI_DRM_5753 -> Patchwork_12478
> 
>   CI_DRM_5753: 0eb0838c0c26378949de6816166117c8b2d73caa @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4887: 5a7c7575b5bb9542f722ed6ba095b9d62609cd56 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_12478: ad1b68919282082c87040e7d6bf6697865c23797 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12478/

-- 
Ville Syrjälä
Intel
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