From: "Shankar, Uma" <uma.shankar@intel.com>
To: "Kulkarni, Vandita" <vandita.kulkarni@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>,
"Syrjala, Ville" <ville.syrjala@intel.com>
Subject: Re: [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi
Date: Tue, 26 Mar 2019 06:07:10 +0000 [thread overview]
Message-ID: <E7C9878FBA1C6D42A1CA3F62AEB6945F81F8DF21@BGSMSX104.gar.corp.intel.com> (raw)
In-Reply-To: <1553513202-13863-2-git-send-email-vandita.kulkarni@intel.com>
>-----Original Message-----
>From: Kulkarni, Vandita
>Sent: Monday, March 25, 2019 4:57 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>Chauhan, Madhav <madhav.chauhan@intel.com>; Deak, Imre
><imre.deak@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>; Kulkarni, Vandita
><vandita.kulkarni@intel.com>
>Subject: [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi
>
>Re-enable clock gating of DDI clocks.
>
>v2: Fix the default ddi clk state for mipi-dsi (Imre)
>
>Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
>Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>---
> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/intel_ddi.c | 6 +++---
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index
>4aef5dd..39d6410 100644
>--- a/drivers/gpu/drm/i915/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/icl_dsi.c
>@@ -1123,7 +1123,7 @@ static void gen11_dsi_disable_port(struct intel_encoder
>*encoder)
> DRM_ERROR("DDI port:%c buffer not idle\n",
> port_name(port));
> }
>- gen11_dsi_ungate_clocks(encoder);
>+ gen11_dsi_gate_clocks(encoder);
> }
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) diff --git
>a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>index 933df3a..976c010 100644
>--- a/drivers/gpu/drm/i915/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/intel_ddi.c
>@@ -2821,10 +2821,10 @@ void icl_sanitize_encoder_pll_mapping(struct
>intel_encoder *encoder)
> return;
> }
> /*
>- * DSI ports should have their DDI clock ungated when disabled
>- * and gated when enabled.
>+ * For DSI we keep the ddi clocks gated
>+ * except during enable/disable sequence.
> */
Looks ok to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>- ddi_clk_needed = !encoder->base.crtc;
>+ ddi_clk_needed = false;
> }
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
>--
>1.9.1
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next prev parent reply other threads:[~2019-03-26 6:07 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-25 11:26 [v3 1/2] drm/i915/icl: Ungate ddi clocks before IO enable Vandita Kulkarni
2019-03-25 11:26 ` [v3 2/2] drm/i915/icl: Fix port disable sequence for mipi-dsi Vandita Kulkarni
2019-03-26 6:07 ` Shankar, Uma [this message]
2019-03-25 12:33 ` ✗ Fi.CI.BAT: failure for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable Patchwork
2019-03-27 15:04 ` [v3 1/2] " Jani Nikula
2019-03-27 19:36 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev2) Patchwork
2019-03-28 15:04 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-04-02 18:48 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO enable (rev3) Patchwork
2019-04-03 6:52 ` ✓ Fi.CI.IGT: " Patchwork
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