* [Intel-gfx] [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-10-24 12:21 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-10-24 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make CHICKEN_TRANS() a bit less special looking by using _PICK().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++-------
drivers/gpu/drm/i915/display/intel_psr.c | 22 +---------------------
drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++----
3 files changed, 17 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1a49266f4f57..127dd2d736d4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3870,12 +3870,12 @@ static i915_reg_t
gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
enum port port)
{
- static const i915_reg_t regs[] = {
- [PORT_A] = CHICKEN_TRANS_EDP,
- [PORT_B] = CHICKEN_TRANS_A,
- [PORT_C] = CHICKEN_TRANS_B,
- [PORT_D] = CHICKEN_TRANS_C,
- [PORT_E] = CHICKEN_TRANS_A,
+ static const enum transcoder trans[] = {
+ [PORT_A] = TRANSCODER_EDP,
+ [PORT_B] = TRANSCODER_A,
+ [PORT_C] = TRANSCODER_B,
+ [PORT_D] = TRANSCODER_C,
+ [PORT_E] = TRANSCODER_A,
};
WARN_ON(INTEL_GEN(dev_priv) < 9);
@@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
if (WARN_ON(port < PORT_A || port > PORT_E))
port = PORT_A;
- return regs[port];
+ return CHICKEN_TRANS(trans[port]);
}
static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index dfbedff98ea8..1643c35484d8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
dev_priv->psr.active = true;
}
-static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
- enum transcoder cpu_transcoder)
-{
- static const i915_reg_t regs[] = {
- [TRANSCODER_A] = CHICKEN_TRANS_A,
- [TRANSCODER_B] = CHICKEN_TRANS_B,
- [TRANSCODER_C] = CHICKEN_TRANS_C,
- [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
- };
-
- WARN_ON(INTEL_GEN(dev_priv) < 9);
-
- if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
- !regs[cpu_transcoder].reg))
- cpu_transcoder = TRANSCODER_A;
-
- return regs[cpu_transcoder];
-}
-
static void intel_psr_enable_source(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state)
{
@@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
!IS_GEMINILAKE(dev_priv))) {
- i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
- cpu_transcoder);
+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
u32 chicken = I915_READ(reg);
chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 855db888516c..38071d0c8020 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7616,10 +7616,15 @@ enum {
#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define CHICKEN_TRANS_A _MMIO(0x420c0)
-#define CHICKEN_TRANS_B _MMIO(0x420c4)
-#define CHICKEN_TRANS_C _MMIO(0x420c8)
-#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
+#define _CHICKEN_TRANS_A 0x420c0
+#define _CHICKEN_TRANS_B 0x420c4
+#define _CHICKEN_TRANS_C 0x420c8
+#define _CHICKEN_TRANS_EDP 0x420cc
+#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
+ [TRANSCODER_C] = _CHICKEN_TRANS_C))
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-10-24 12:21 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-10-24 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add CHICKEN_TRANS definition for transcoder D.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38071d0c8020..50c2fa0f2cab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7620,11 +7620,13 @@ enum {
#define _CHICKEN_TRANS_B 0x420c4
#define _CHICKEN_TRANS_C 0x420c8
#define _CHICKEN_TRANS_EDP 0x420cc
+#define _CHICKEN_TRANS_D 0x420d8
#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
[TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
[TRANSCODER_A] = _CHICKEN_TRANS_A, \
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
- [TRANSCODER_C] = _CHICKEN_TRANS_C))
+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-10-24 12:21 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-10-24 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add CHICKEN_TRANS definition for transcoder D.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38071d0c8020..50c2fa0f2cab 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7620,11 +7620,13 @@ enum {
#define _CHICKEN_TRANS_B 0x420c4
#define _CHICKEN_TRANS_C 0x420c8
#define _CHICKEN_TRANS_EDP 0x420cc
+#define _CHICKEN_TRANS_D 0x420d8
#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
[TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
[TRANSCODER_A] = _CHICKEN_TRANS_A, \
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
- [TRANSCODER_C] = _CHICKEN_TRANS_C))
+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
--
2.21.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-10-24 22:36 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-10-24 22:36 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add CHICKEN_TRANS definition for transcoder D.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 38071d0c8020..50c2fa0f2cab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7620,11 +7620,13 @@ enum {
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
> +#define _CHICKEN_TRANS_D 0x420d8
> #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> - [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C, \
> + [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-10-24 22:36 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-10-24 22:36 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add CHICKEN_TRANS definition for transcoder D.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 38071d0c8020..50c2fa0f2cab 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7620,11 +7620,13 @@ enum {
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
> +#define _CHICKEN_TRANS_D 0x420d8
> #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> - [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C, \
> + [TRANSCODER_D] =
> _CHICKEN_TRANS_D))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-11-15 17:11 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-15 17:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Oct 24, 2019 at 03:21:37PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Add CHICKEN_TRANS definition for transcoder D.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 38071d0c8020..50c2fa0f2cab 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7620,11 +7620,13 @@ enum {
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
>+#define _CHICKEN_TRANS_D 0x420d8
> #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
> [TRANSCODER_A] = _CHICKEN_TRANS_A, \
> [TRANSCODER_B] = _CHICKEN_TRANS_B, \
>- [TRANSCODER_C] = _CHICKEN_TRANS_C))
>+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
>+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 2/3] drm/i915: Add CHICKEN_TRANS_D
@ 2019-11-15 17:11 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-15 17:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Oct 24, 2019 at 03:21:37PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Add CHICKEN_TRANS definition for transcoder D.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 38071d0c8020..50c2fa0f2cab 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7620,11 +7620,13 @@ enum {
> #define _CHICKEN_TRANS_B 0x420c4
> #define _CHICKEN_TRANS_C 0x420c8
> #define _CHICKEN_TRANS_EDP 0x420cc
>+#define _CHICKEN_TRANS_D 0x420d8
> #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
> [TRANSCODER_A] = _CHICKEN_TRANS_A, \
> [TRANSCODER_B] = _CHICKEN_TRANS_B, \
>- [TRANSCODER_C] = _CHICKEN_TRANS_C))
>+ [TRANSCODER_C] = _CHICKEN_TRANS_C, \
>+ [TRANSCODER_D] = _CHICKEN_TRANS_D))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>--
>2.21.0
>
>_______________________________________________
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>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-10-24 12:21 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-10-24 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we're blindly poking at the frame start delay bits
in PIPECONF when trying to sanitize the hardware state. Those
bits decided to move elsewhere on HSW, so on many platforms
we're not doing anything at all here. Also we're forgetting
about the PCH transcoder entirely.
Add all the bit definitions for the various homes these bits
have had throughout the years, and reset them all to zero.
However I'm not entirely sure this is a safe thing to do. If
not I guess we'd want full readout+statecheck for this stuff.
For now let's stick to the current logic and hope for the
best.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 12 ++-
drivers/gpu/drm/i915/intel_pm.c | 1 -
3 files changed, 95 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 579655675b08..2896cf864f61 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
assert_fdi_rx_enabled(dev_priv, pipe);
if (HAS_PCH_CPT(dev_priv)) {
- /* Workaround: Set the timing override bit before enabling the
- * pch transcoder. */
reg = TRANS_CHICKEN2(pipe);
val = I915_READ(reg);
+ /*
+ * Workaround: Set the timing override bit
+ * before enabling the pch transcoder.
+ */
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
I915_WRITE(reg, val);
}
@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
pipeconf_val = I915_READ(PIPECONF(pipe));
if (HAS_PCH_IBX(dev_priv)) {
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_FRAME_START_DELAY_MASK;
+ val |= TRANS_FRAME_START_DELAY(0);
+
/*
* Make the BPC in transcoder be consistent with
* that in pipeconf reg. For HDMI we must use 8bpc
@@ -1695,9 +1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
assert_fdi_rx_enabled(dev_priv, PIPE_A);
+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
/* Workaround: set timing override bit. */
- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
val = TRANS_ENABLE;
@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~HSW_FRAME_START_DELAY_MASK;
+ val |= HSW_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+}
+
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
&pipe_config->fdi_m_n, NULL);
}
- if (!transcoder_is_dsi(cpu_transcoder))
+ if (!transcoder_is_dsi(cpu_transcoder)) {
+ hsw_set_frame_start_delay(pipe_config);
haswell_set_pipeconf(pipe_config);
+ }
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
+
I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
POSTING_READ(PIPECONF(crtc->pipe));
}
@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ val |= PIPECONF_FRAME_START_DELAY(0);
+
I915_WRITE(PIPECONF(pipe), val);
POSTING_READ(PIPECONF(pipe));
}
@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
(HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
}
+static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
+ u32 val;
+
+ if (transcoder_is_dsi(cpu_transcoder))
+ return;
+
+ val = I915_READ(reg);
+ val &= ~HSW_FRAME_START_DELAY_MASK;
+ val |= HSW_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ } else {
+ i915_reg_t reg = PIPECONF(cpu_transcoder);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
+ val |= PIPECONF_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ }
+
+ if (!crtc_state->has_pch_encoder)
+ return;
+
+ if (HAS_PCH_IBX(dev_priv)) {
+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~TRANS_FRAME_START_DELAY_MASK;
+ val |= TRANS_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ } else {
+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ }
+}
+
static void intel_sanitize_crtc(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
- /* Clear any frame start delays used for debugging left by the BIOS */
- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
- i915_reg_t reg = PIPECONF(cpu_transcoder);
-
- I915_WRITE(reg,
- I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
- }
if (crtc_state->base.active) {
struct intel_plane *plane;
+ /* Clear any frame start delays used for debugging left by the BIOS */
+ intel_sanitize_frame_start_delay(crtc_state);
+
/* Disable everything but the primary plane */
for_each_intel_plane_on_crtc(dev, crtc, plane) {
const struct intel_plane_state *plane_state =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50c2fa0f2cab..cb2e0f4679c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5671,7 +5671,8 @@ enum {
#define PIPECONF_DOUBLE_WIDE (1 << 30)
#define I965_PIPECONF_ACTIVE (1 << 30)
#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
#define PIPECONF_SINGLE_WIDE 0
#define PIPECONF_PIPE_UNLOCKED 0
#define PIPECONF_PIPE_LOCKED (1 << 25)
@@ -7627,6 +7628,8 @@ enum {
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
[TRANSCODER_C] = _CHICKEN_TRANS_C, \
[TRANSCODER_D] = _CHICKEN_TRANS_D))
+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
@@ -8341,10 +8344,8 @@ enum {
#define TRANS_STATE_MASK (1 << 30)
#define TRANS_STATE_DISABLE (0 << 30)
#define TRANS_STATE_ENABLE (1 << 30)
-#define TRANS_FSYNC_DELAY_HB1 (0 << 27)
-#define TRANS_FSYNC_DELAY_HB2 (1 << 27)
-#define TRANS_FSYNC_DELAY_HB3 (2 << 27)
-#define TRANS_FSYNC_DELAY_HB4 (3 << 27)
+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
#define TRANS_INTERLACE_MASK (7 << 21)
#define TRANS_PROGRESSIVE (0 << 21)
#define TRANS_INTERLACED (3 << 21)
@@ -8365,6 +8366,7 @@ enum {
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 362234449087..8b1fbdb36537 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
if (dev_priv->vbt.fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
I915_WRITE(TRANS_CHICKEN2(pipe), val);
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-10-24 12:21 ` Ville Syrjala
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjala @ 2019-10-24 12:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Currently we're blindly poking at the frame start delay bits
in PIPECONF when trying to sanitize the hardware state. Those
bits decided to move elsewhere on HSW, so on many platforms
we're not doing anything at all here. Also we're forgetting
about the PCH transcoder entirely.
Add all the bit definitions for the various homes these bits
have had throughout the years, and reset them all to zero.
However I'm not entirely sure this is a safe thing to do. If
not I guess we'd want full readout+statecheck for this stuff.
For now let's stick to the current logic and hope for the
best.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 12 ++-
drivers/gpu/drm/i915/intel_pm.c | 1 -
3 files changed, 95 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 579655675b08..2896cf864f61 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
assert_fdi_rx_enabled(dev_priv, pipe);
if (HAS_PCH_CPT(dev_priv)) {
- /* Workaround: Set the timing override bit before enabling the
- * pch transcoder. */
reg = TRANS_CHICKEN2(pipe);
val = I915_READ(reg);
+ /*
+ * Workaround: Set the timing override bit
+ * before enabling the pch transcoder.
+ */
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
I915_WRITE(reg, val);
}
@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
pipeconf_val = I915_READ(PIPECONF(pipe));
if (HAS_PCH_IBX(dev_priv)) {
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_FRAME_START_DELAY_MASK;
+ val |= TRANS_FRAME_START_DELAY(0);
+
/*
* Make the BPC in transcoder be consistent with
* that in pipeconf reg. For HDMI we must use 8bpc
@@ -1695,9 +1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
assert_fdi_rx_enabled(dev_priv, PIPE_A);
+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
/* Workaround: set timing override bit. */
- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+ /* Configure frame start delay to match the CPU */
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
val = TRANS_ENABLE;
@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);
}
+static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~HSW_FRAME_START_DELAY_MASK;
+ val |= HSW_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+}
+
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
&pipe_config->fdi_m_n, NULL);
}
- if (!transcoder_is_dsi(cpu_transcoder))
+ if (!transcoder_is_dsi(cpu_transcoder)) {
+ hsw_set_frame_start_delay(pipe_config);
haswell_set_pipeconf(pipe_config);
+ }
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
+
I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
POSTING_READ(PIPECONF(crtc->pipe));
}
@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ val |= PIPECONF_FRAME_START_DELAY(0);
+
I915_WRITE(PIPECONF(pipe), val);
POSTING_READ(PIPECONF(pipe));
}
@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
(HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A);
}
+static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ if (INTEL_GEN(dev_priv) >= 9 ||
+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
+ u32 val;
+
+ if (transcoder_is_dsi(cpu_transcoder))
+ return;
+
+ val = I915_READ(reg);
+ val &= ~HSW_FRAME_START_DELAY_MASK;
+ val |= HSW_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ } else {
+ i915_reg_t reg = PIPECONF(cpu_transcoder);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
+ val |= PIPECONF_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ }
+
+ if (!crtc_state->has_pch_encoder)
+ return;
+
+ if (HAS_PCH_IBX(dev_priv)) {
+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~TRANS_FRAME_START_DELAY_MASK;
+ val |= TRANS_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ } else {
+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
+ u32 val;
+
+ val = I915_READ(reg);
+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
+ I915_WRITE(reg, val);
+ }
+}
+
static void intel_sanitize_crtc(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-
- /* Clear any frame start delays used for debugging left by the BIOS */
- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
- i915_reg_t reg = PIPECONF(cpu_transcoder);
-
- I915_WRITE(reg,
- I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
- }
if (crtc_state->base.active) {
struct intel_plane *plane;
+ /* Clear any frame start delays used for debugging left by the BIOS */
+ intel_sanitize_frame_start_delay(crtc_state);
+
/* Disable everything but the primary plane */
for_each_intel_plane_on_crtc(dev, crtc, plane) {
const struct intel_plane_state *plane_state =
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 50c2fa0f2cab..cb2e0f4679c4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5671,7 +5671,8 @@ enum {
#define PIPECONF_DOUBLE_WIDE (1 << 30)
#define I965_PIPECONF_ACTIVE (1 << 30)
#define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3 */
#define PIPECONF_SINGLE_WIDE 0
#define PIPECONF_PIPE_UNLOCKED 0
#define PIPECONF_PIPE_LOCKED (1 << 25)
@@ -7627,6 +7628,8 @@ enum {
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
[TRANSCODER_C] = _CHICKEN_TRANS_C, \
[TRANSCODER_D] = _CHICKEN_TRANS_D))
+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
#define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
#define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
@@ -8341,10 +8344,8 @@ enum {
#define TRANS_STATE_MASK (1 << 30)
#define TRANS_STATE_DISABLE (0 << 30)
#define TRANS_STATE_ENABLE (1 << 30)
-#define TRANS_FSYNC_DELAY_HB1 (0 << 27)
-#define TRANS_FSYNC_DELAY_HB2 (1 << 27)
-#define TRANS_FSYNC_DELAY_HB3 (2 << 27)
-#define TRANS_FSYNC_DELAY_HB4 (3 << 27)
+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
#define TRANS_INTERLACE_MASK (7 << 21)
#define TRANS_PROGRESSIVE (0 << 21)
#define TRANS_INTERLACED (3 << 21)
@@ -8365,6 +8366,7 @@ enum {
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 362234449087..8b1fbdb36537 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
if (dev_priv->vbt.fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
I915_WRITE(TRANS_CHICKEN2(pipe), val);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-11-15 16:08 ` Shankar, Uma
0 siblings, 0 replies; 22+ messages in thread
From: Shankar, Uma @ 2019-11-15 16:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Thursday, October 24, 2019 5:52 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to
>sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on
>many platforms we're not doing anything at all here. Also we're forgetting about the
>PCH transcoder entirely.
>
>Add all the bit definitions for the various homes these bits have had throughout the
>years, and reset them all to zero.
>
>However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full
>readout+statecheck for this stuff.
>For now let's stick to the current logic and hope for the best.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++-
> drivers/gpu/drm/i915/intel_pm.c | 1 -
> 3 files changed, 95 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 579655675b08..2896cf864f61 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct
>intel_crtc_state *crtc_s
> assert_fdi_rx_enabled(dev_priv, pipe);
>
> if (HAS_PCH_CPT(dev_priv)) {
>- /* Workaround: Set the timing override bit before enabling the
>- * pch transcoder. */
> reg = TRANS_CHICKEN2(pipe);
> val = I915_READ(reg);
>+ /*
>+ * Workaround: Set the timing override bit
>+ * before enabling the pch transcoder.
>+ */
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> I915_WRITE(reg, val);
> }
>
>@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct
>intel_crtc_state *crtc_s
> pipeconf_val = I915_READ(PIPECONF(pipe));
>
> if (HAS_PCH_IBX(dev_priv)) {
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_FRAME_START_DELAY_MASK;
>+ val |= TRANS_FRAME_START_DELAY(0);
>+
> /*
> * Make the BPC in transcoder be consistent with
> * that in pipeconf reg. For HDMI we must use 8bpc @@ -1695,9
>+1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private
>*dev_priv,
> assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> assert_fdi_rx_enabled(dev_priv, PIPE_A);
>
>+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> /* Workaround: set timing override bit. */
>- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>
> val = TRANS_ENABLE;
>@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); }
>
>+static void hsw_set_frame_start_delay(const struct intel_crtc_state
>+*crtc_state) {
>+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~HSW_FRAME_START_DELAY_MASK;
>+ val |= HSW_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+}
>+
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
>@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state
>*pipe_config,
> &pipe_config->fdi_m_n, NULL);
> }
>
>- if (!transcoder_is_dsi(cpu_transcoder))
>+ if (!transcoder_is_dsi(cpu_transcoder)) {
>+ hsw_set_frame_start_delay(pipe_config);
> haswell_set_pipeconf(pipe_config);
>+ }
>
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(pipe_config);
>@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state
>*crtc_state)
>
> pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
>+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
>+
> I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> POSTING_READ(PIPECONF(crtc->pipe));
> }
>@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct
>intel_crtc_state *crtc_state)
>
> val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
>+ val |= PIPECONF_FRAME_START_DELAY(0);
>+
> I915_WRITE(PIPECONF(pipe), val);
> POSTING_READ(PIPECONF(pipe));
> }
>@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct
>drm_i915_private *dev_priv,
> (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); }
>
>+static void intel_sanitize_frame_start_delay(const struct
>+intel_crtc_state *crtc_state) {
>+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>+
>+ if (INTEL_GEN(dev_priv) >= 9 ||
>+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
>+ u32 val;
>+
>+ if (transcoder_is_dsi(cpu_transcoder))
>+ return;
>+
>+ val = I915_READ(reg);
>+ val &= ~HSW_FRAME_START_DELAY_MASK;
>+ val |= HSW_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ } else {
>+ i915_reg_t reg = PIPECONF(cpu_transcoder);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
>+ val |= PIPECONF_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ }
>+
>+ if (!crtc_state->has_pch_encoder)
>+ return;
>+
>+ if (HAS_PCH_IBX(dev_priv)) {
>+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~TRANS_FRAME_START_DELAY_MASK;
>+ val |= TRANS_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ } else {
>+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ }
>+}
>+
> static void intel_sanitize_crtc(struct intel_crtc *crtc,
> struct drm_modeset_acquire_ctx *ctx) {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
>- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>-
>- /* Clear any frame start delays used for debugging left by the BIOS */
>- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
>- i915_reg_t reg = PIPECONF(cpu_transcoder);
>-
>- I915_WRITE(reg,
>- I915_READ(reg) &
>~PIPECONF_FRAME_START_DELAY_MASK);
>- }
>
> if (crtc_state->base.active) {
> struct intel_plane *plane;
>
>+ /* Clear any frame start delays used for debugging left by the BIOS */
>+ intel_sanitize_frame_start_delay(crtc_state);
>+
> /* Disable everything but the primary plane */
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> const struct intel_plane_state *plane_state = diff --git
>a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>50c2fa0f2cab..cb2e0f4679c4 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -5671,7 +5671,8 @@ enum {
> #define PIPECONF_DOUBLE_WIDE (1 << 30)
> #define I965_PIPECONF_ACTIVE (1 << 30)
> #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
>-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
>+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
>+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3
>*/
> #define PIPECONF_SINGLE_WIDE 0
> #define PIPECONF_PIPE_UNLOCKED 0
> #define PIPECONF_PIPE_LOCKED (1 << 25)
>@@ -7627,6 +7628,8 @@ enum {
> [TRANSCODER_B] = _CHICKEN_TRANS_B,
>\
> [TRANSCODER_C] = _CHICKEN_TRANS_C,
>\
> [TRANSCODER_D] =
>_CHICKEN_TRANS_D))
>+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
>+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>@@ -8341,10 +8344,8 @@ enum {
> #define TRANS_STATE_MASK (1 << 30)
> #define TRANS_STATE_DISABLE (0 << 30)
> #define TRANS_STATE_ENABLE (1 << 30)
>-#define TRANS_FSYNC_DELAY_HB1 (0 << 27) -#define TRANS_FSYNC_DELAY_HB2
>(1 << 27) -#define TRANS_FSYNC_DELAY_HB3 (2 << 27) -#define
>TRANS_FSYNC_DELAY_HB4 (3 << 27)
>+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
>+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> #define TRANS_INTERLACE_MASK (7 << 21)
> #define TRANS_PROGRESSIVE (0 << 21)
> #define TRANS_INTERLACED (3 << 21)
>@@ -8365,6 +8366,7 @@ enum {
> #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
> #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
> #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
>+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
> #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index
>362234449087..8b1fbdb36537 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private
>*dev_priv)
> val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> if (dev_priv->vbt.fdi_rx_polarity_inverted)
> val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
Is there any reason not to let it be set at 0.
Overall, I looked at the register and bit definitions for various platforms and this looks
a very reasonable change rectifying the frame start delay programming.
However I am not sure if for all platforms 0 will be the preferred value. If the default values
of these bits are 0 in hardware register (or the BIOS set them at 0 itself), this should
work seamlessly. Only caveat will be if the defaults are not 0 on all platforms, we may have
issues.
Good way to figure this out I guess is our CI results. So if the CI passes, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> I915_WRITE(TRANS_CHICKEN2(pipe), val);
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-11-15 16:08 ` Shankar, Uma
0 siblings, 0 replies; 22+ messages in thread
From: Shankar, Uma @ 2019-11-15 16:08 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
>-----Original Message-----
>From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
>Sent: Thursday, October 24, 2019 5:52 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
>
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to
>sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on
>many platforms we're not doing anything at all here. Also we're forgetting about the
>PCH transcoder entirely.
>
>Add all the bit definitions for the various homes these bits have had throughout the
>years, and reset them all to zero.
>
>However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full
>readout+statecheck for this stuff.
>For now let's stick to the current logic and hope for the best.
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 12 ++-
> drivers/gpu/drm/i915/intel_pm.c | 1 -
> 3 files changed, 95 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 579655675b08..2896cf864f61 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct
>intel_crtc_state *crtc_s
> assert_fdi_rx_enabled(dev_priv, pipe);
>
> if (HAS_PCH_CPT(dev_priv)) {
>- /* Workaround: Set the timing override bit before enabling the
>- * pch transcoder. */
> reg = TRANS_CHICKEN2(pipe);
> val = I915_READ(reg);
>+ /*
>+ * Workaround: Set the timing override bit
>+ * before enabling the pch transcoder.
>+ */
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> I915_WRITE(reg, val);
> }
>
>@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct
>intel_crtc_state *crtc_s
> pipeconf_val = I915_READ(PIPECONF(pipe));
>
> if (HAS_PCH_IBX(dev_priv)) {
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_FRAME_START_DELAY_MASK;
>+ val |= TRANS_FRAME_START_DELAY(0);
>+
> /*
> * Make the BPC in transcoder be consistent with
> * that in pipeconf reg. For HDMI we must use 8bpc @@ -1695,9
>+1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private
>*dev_priv,
> assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> assert_fdi_rx_enabled(dev_priv, PIPE_A);
>
>+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> /* Workaround: set timing override bit. */
>- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
>+ /* Configure frame start delay to match the CPU */
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
>
> val = TRANS_ENABLE;
>@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); }
>
>+static void hsw_set_frame_start_delay(const struct intel_crtc_state
>+*crtc_state) {
>+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~HSW_FRAME_START_DELAY_MASK;
>+ val |= HSW_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+}
>+
> static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> struct intel_atomic_state *state)
> {
>@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state
>*pipe_config,
> &pipe_config->fdi_m_n, NULL);
> }
>
>- if (!transcoder_is_dsi(cpu_transcoder))
>+ if (!transcoder_is_dsi(cpu_transcoder)) {
>+ hsw_set_frame_start_delay(pipe_config);
> haswell_set_pipeconf(pipe_config);
>+ }
>
> if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> bdw_set_pipemisc(pipe_config);
>@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state
>*crtc_state)
>
> pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
>+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
>+
> I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> POSTING_READ(PIPECONF(crtc->pipe));
> }
>@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct
>intel_crtc_state *crtc_state)
>
> val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>
>+ val |= PIPECONF_FRAME_START_DELAY(0);
>+
> I915_WRITE(PIPECONF(pipe), val);
> POSTING_READ(PIPECONF(pipe));
> }
>@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct
>drm_i915_private *dev_priv,
> (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); }
>
>+static void intel_sanitize_frame_start_delay(const struct
>+intel_crtc_state *crtc_state) {
>+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
>+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>+
>+ if (INTEL_GEN(dev_priv) >= 9 ||
>+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
>+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
>+ u32 val;
>+
>+ if (transcoder_is_dsi(cpu_transcoder))
>+ return;
>+
>+ val = I915_READ(reg);
>+ val &= ~HSW_FRAME_START_DELAY_MASK;
>+ val |= HSW_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ } else {
>+ i915_reg_t reg = PIPECONF(cpu_transcoder);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
>+ val |= PIPECONF_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ }
>+
>+ if (!crtc_state->has_pch_encoder)
>+ return;
>+
>+ if (HAS_PCH_IBX(dev_priv)) {
>+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~TRANS_FRAME_START_DELAY_MASK;
>+ val |= TRANS_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ } else {
>+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
>+ u32 val;
>+
>+ val = I915_READ(reg);
>+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
>+ I915_WRITE(reg, val);
>+ }
>+}
>+
> static void intel_sanitize_crtc(struct intel_crtc *crtc,
> struct drm_modeset_acquire_ctx *ctx) {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
>- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>-
>- /* Clear any frame start delays used for debugging left by the BIOS */
>- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
>- i915_reg_t reg = PIPECONF(cpu_transcoder);
>-
>- I915_WRITE(reg,
>- I915_READ(reg) &
>~PIPECONF_FRAME_START_DELAY_MASK);
>- }
>
> if (crtc_state->base.active) {
> struct intel_plane *plane;
>
>+ /* Clear any frame start delays used for debugging left by the BIOS */
>+ intel_sanitize_frame_start_delay(crtc_state);
>+
> /* Disable everything but the primary plane */
> for_each_intel_plane_on_crtc(dev, crtc, plane) {
> const struct intel_plane_state *plane_state = diff --git
>a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
>50c2fa0f2cab..cb2e0f4679c4 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -5671,7 +5671,8 @@ enum {
> #define PIPECONF_DOUBLE_WIDE (1 << 30)
> #define I965_PIPECONF_ACTIVE (1 << 30)
> #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
>-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
>+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
>+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3
>*/
> #define PIPECONF_SINGLE_WIDE 0
> #define PIPECONF_PIPE_UNLOCKED 0
> #define PIPECONF_PIPE_LOCKED (1 << 25)
>@@ -7627,6 +7628,8 @@ enum {
> [TRANSCODER_B] = _CHICKEN_TRANS_B,
>\
> [TRANSCODER_C] = _CHICKEN_TRANS_C,
>\
> [TRANSCODER_D] =
>_CHICKEN_TRANS_D))
>+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
>+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>@@ -8341,10 +8344,8 @@ enum {
> #define TRANS_STATE_MASK (1 << 30)
> #define TRANS_STATE_DISABLE (0 << 30)
> #define TRANS_STATE_ENABLE (1 << 30)
>-#define TRANS_FSYNC_DELAY_HB1 (0 << 27) -#define TRANS_FSYNC_DELAY_HB2
>(1 << 27) -#define TRANS_FSYNC_DELAY_HB3 (2 << 27) -#define
>TRANS_FSYNC_DELAY_HB4 (3 << 27)
>+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
>+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> #define TRANS_INTERLACE_MASK (7 << 21)
> #define TRANS_PROGRESSIVE (0 << 21)
> #define TRANS_INTERLACED (3 << 21)
>@@ -8365,6 +8366,7 @@ enum {
> #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
> #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
> #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
>+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
> #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
>
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index
>362234449087..8b1fbdb36537 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private
>*dev_priv)
> val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> if (dev_priv->vbt.fdi_rx_polarity_inverted)
> val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
>- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
Is there any reason not to let it be set at 0.
Overall, I looked at the register and bit definitions for various platforms and this looks
a very reasonable change rectifying the frame start delay programming.
However I am not sure if for all platforms 0 will be the preferred value. If the default values
of these bits are 0 in hardware register (or the BIOS set them at 0 itself), this should
work seamlessly. Only caveat will be if the defaults are not 0 on all platforms, we may have
issues.
Good way to figure this out I guess is our CI results. So if the CI passes, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> I915_WRITE(TRANS_CHICKEN2(pipe), val);
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-11-15 17:19 ` Ville Syrjälä
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2019-11-15 17:19 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
On Fri, Nov 15, 2019 at 04:08:45PM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> >Sent: Thursday, October 24, 2019 5:52 PM
> >To: intel-gfx@lists.freedesktop.org
> >Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to
> >sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on
> >many platforms we're not doing anything at all here. Also we're forgetting about the
> >PCH transcoder entirely.
> >
> >Add all the bit definitions for the various homes these bits have had throughout the
> >years, and reset them all to zero.
> >
> >However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full
> >readout+statecheck for this stuff.
> >For now let's stick to the current logic and hope for the best.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 12 ++-
> > drivers/gpu/drm/i915/intel_pm.c | 1 -
> > 3 files changed, 95 insertions(+), 19 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >b/drivers/gpu/drm/i915/display/intel_display.c
> >index 579655675b08..2896cf864f61 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display.c
> >@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct
> >intel_crtc_state *crtc_s
> > assert_fdi_rx_enabled(dev_priv, pipe);
> >
> > if (HAS_PCH_CPT(dev_priv)) {
> >- /* Workaround: Set the timing override bit before enabling the
> >- * pch transcoder. */
> > reg = TRANS_CHICKEN2(pipe);
> > val = I915_READ(reg);
> >+ /*
> >+ * Workaround: Set the timing override bit
> >+ * before enabling the pch transcoder.
> >+ */
> > val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > I915_WRITE(reg, val);
> > }
> >
> >@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct
> >intel_crtc_state *crtc_s
> > pipeconf_val = I915_READ(PIPECONF(pipe));
> >
> > if (HAS_PCH_IBX(dev_priv)) {
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_FRAME_START_DELAY(0);
> >+
> > /*
> > * Make the BPC in transcoder be consistent with
> > * that in pipeconf reg. For HDMI we must use 8bpc @@ -1695,9
> >+1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private
> >*dev_priv,
> > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> > assert_fdi_rx_enabled(dev_priv, PIPE_A);
> >
> >+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> > /* Workaround: set timing override bit. */
> >- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> > val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
> >
> > val = TRANS_ENABLE;
> >@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); }
> >
> >+static void hsw_set_frame_start_delay(const struct intel_crtc_state
> >+*crtc_state) {
> >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~HSW_FRAME_START_DELAY_MASK;
> >+ val |= HSW_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+}
> >+
> > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > struct intel_atomic_state *state)
> > {
> >@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state
> >*pipe_config,
> > &pipe_config->fdi_m_n, NULL);
> > }
> >
> >- if (!transcoder_is_dsi(cpu_transcoder))
> >+ if (!transcoder_is_dsi(cpu_transcoder)) {
> >+ hsw_set_frame_start_delay(pipe_config);
> > haswell_set_pipeconf(pipe_config);
> >+ }
> >
> > if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > bdw_set_pipemisc(pipe_config);
> >@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state
> >*crtc_state)
> >
> > pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >
> >+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
> >+
> > I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> > POSTING_READ(PIPECONF(crtc->pipe));
> > }
> >@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct
> >intel_crtc_state *crtc_state)
> >
> > val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >
> >+ val |= PIPECONF_FRAME_START_DELAY(0);
> >+
> > I915_WRITE(PIPECONF(pipe), val);
> > POSTING_READ(PIPECONF(pipe));
> > }
> >@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct
> >drm_i915_private *dev_priv,
> > (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); }
> >
> >+static void intel_sanitize_frame_start_delay(const struct
> >+intel_crtc_state *crtc_state) {
> >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >+
> >+ if (INTEL_GEN(dev_priv) >= 9 ||
> >+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> >+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> >+ u32 val;
> >+
> >+ if (transcoder_is_dsi(cpu_transcoder))
> >+ return;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~HSW_FRAME_START_DELAY_MASK;
> >+ val |= HSW_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ } else {
> >+ i915_reg_t reg = PIPECONF(cpu_transcoder);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
> >+ val |= PIPECONF_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ }
> >+
> >+ if (!crtc_state->has_pch_encoder)
> >+ return;
> >+
> >+ if (HAS_PCH_IBX(dev_priv)) {
> >+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~TRANS_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ } else {
> >+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ }
> >+}
> >+
> > static void intel_sanitize_crtc(struct intel_crtc *crtc,
> > struct drm_modeset_acquire_ctx *ctx) {
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> >- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >-
> >- /* Clear any frame start delays used for debugging left by the BIOS */
> >- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
> >- i915_reg_t reg = PIPECONF(cpu_transcoder);
> >-
> >- I915_WRITE(reg,
> >- I915_READ(reg) &
> >~PIPECONF_FRAME_START_DELAY_MASK);
> >- }
> >
> > if (crtc_state->base.active) {
> > struct intel_plane *plane;
> >
> >+ /* Clear any frame start delays used for debugging left by the BIOS */
> >+ intel_sanitize_frame_start_delay(crtc_state);
> >+
> > /* Disable everything but the primary plane */
> > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > const struct intel_plane_state *plane_state = diff --git
> >a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> >50c2fa0f2cab..cb2e0f4679c4 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -5671,7 +5671,8 @@ enum {
> > #define PIPECONF_DOUBLE_WIDE (1 << 30)
> > #define I965_PIPECONF_ACTIVE (1 << 30)
> > #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
> >-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
> >+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
> >+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3
> >*/
> > #define PIPECONF_SINGLE_WIDE 0
> > #define PIPECONF_PIPE_UNLOCKED 0
> > #define PIPECONF_PIPE_LOCKED (1 << 25)
> >@@ -7627,6 +7628,8 @@ enum {
> > [TRANSCODER_B] = _CHICKEN_TRANS_B,
> >\
> > [TRANSCODER_C] = _CHICKEN_TRANS_C,
> >\
> > [TRANSCODER_D] =
> >_CHICKEN_TRANS_D))
> >+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
> >+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> > #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> > #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> > #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
> >@@ -8341,10 +8344,8 @@ enum {
> > #define TRANS_STATE_MASK (1 << 30)
> > #define TRANS_STATE_DISABLE (0 << 30)
> > #define TRANS_STATE_ENABLE (1 << 30)
> >-#define TRANS_FSYNC_DELAY_HB1 (0 << 27) -#define TRANS_FSYNC_DELAY_HB2
> >(1 << 27) -#define TRANS_FSYNC_DELAY_HB3 (2 << 27) -#define
> >TRANS_FSYNC_DELAY_HB4 (3 << 27)
> >+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
> >+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> > #define TRANS_INTERLACE_MASK (7 << 21)
> > #define TRANS_PROGRESSIVE (0 << 21)
> > #define TRANS_INTERLACED (3 << 21)
> >@@ -8365,6 +8366,7 @@ enum {
> > #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
> > #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
> > #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
> >+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> > #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
> > #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index
> >362234449087..8b1fbdb36537 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private
> >*dev_priv)
> > val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > if (dev_priv->vbt.fdi_rx_polarity_inverted)
> > val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> >- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>
> Is there any reason not to let it be set at 0.
>
> Overall, I looked at the register and bit definitions for various platforms and this looks
> a very reasonable change rectifying the frame start delay programming.
>
> However I am not sure if for all platforms 0 will be the preferred value. If the default values
> of these bits are 0 in hardware register (or the BIOS set them at 0 itself), this should
> work seamlessly. Only caveat will be if the defaults are not 0 on all platforms, we may have
> issues.
Default is 0, but supposedly some VBIOSen have left other values
in there for whatever reason. Or else we probably wouldn't have this
code to sanitize things.
I *may* want to try bumping this to 3 across the board to give
gamma programming more breathing room during the vblank, but I'm
not sure that's entirely safe to do. Hence I started with just
cleaning up the current mess.
IIRC there was also some obnoxious workaround on LVDS+IBX (or maybe
it was CPT) that would require some extra handling if we were to
program this to some non-zero value.
>
> Good way to figure this out I guess is our CI results. So if the CI passes, this is
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Ta.
>
> > val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> > val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> > I915_WRITE(TRANS_CHICKEN2(pipe), val);
> >--
> >2.21.0
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
@ 2019-11-15 17:19 ` Ville Syrjälä
0 siblings, 0 replies; 22+ messages in thread
From: Ville Syrjälä @ 2019-11-15 17:19 UTC (permalink / raw)
To: Shankar, Uma; +Cc: intel-gfx
On Fri, Nov 15, 2019 at 04:08:45PM +0000, Shankar, Uma wrote:
>
>
> >-----Original Message-----
> >From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> >Sent: Thursday, October 24, 2019 5:52 PM
> >To: intel-gfx@lists.freedesktop.org
> >Subject: [Intel-gfx] [PATCH 3/3] drm/i915: Fix frame start delay programming
> >
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Currently we're blindly poking at the frame start delay bits in PIPECONF when trying to
> >sanitize the hardware state. Those bits decided to move elsewhere on HSW, so on
> >many platforms we're not doing anything at all here. Also we're forgetting about the
> >PCH transcoder entirely.
> >
> >Add all the bit definitions for the various homes these bits have had throughout the
> >years, and reset them all to zero.
> >
> >However I'm not entirely sure this is a safe thing to do. If not I guess we'd want full
> >readout+statecheck for this stuff.
> >For now let's stick to the current logic and hope for the best.
> >
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++++++++---
> > drivers/gpu/drm/i915/i915_reg.h | 12 ++-
> > drivers/gpu/drm/i915/intel_pm.c | 1 -
> > 3 files changed, 95 insertions(+), 19 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> >b/drivers/gpu/drm/i915/display/intel_display.c
> >index 579655675b08..2896cf864f61 100644
> >--- a/drivers/gpu/drm/i915/display/intel_display.c
> >+++ b/drivers/gpu/drm/i915/display/intel_display.c
> >@@ -1645,11 +1645,16 @@ static void ironlake_enable_pch_transcoder(const struct
> >intel_crtc_state *crtc_s
> > assert_fdi_rx_enabled(dev_priv, pipe);
> >
> > if (HAS_PCH_CPT(dev_priv)) {
> >- /* Workaround: Set the timing override bit before enabling the
> >- * pch transcoder. */
> > reg = TRANS_CHICKEN2(pipe);
> > val = I915_READ(reg);
> >+ /*
> >+ * Workaround: Set the timing override bit
> >+ * before enabling the pch transcoder.
> >+ */
> > val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > I915_WRITE(reg, val);
> > }
> >
> >@@ -1658,6 +1663,10 @@ static void ironlake_enable_pch_transcoder(const struct
> >intel_crtc_state *crtc_s
> > pipeconf_val = I915_READ(PIPECONF(pipe));
> >
> > if (HAS_PCH_IBX(dev_priv)) {
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_FRAME_START_DELAY(0);
> >+
> > /*
> > * Make the BPC in transcoder be consistent with
> > * that in pipeconf reg. For HDMI we must use 8bpc @@ -1695,9
> >+1704,12 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private
> >*dev_priv,
> > assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
> > assert_fdi_rx_enabled(dev_priv, PIPE_A);
> >
> >+ val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> > /* Workaround: set timing override bit. */
> >- val = I915_READ(TRANS_CHICKEN2(PIPE_A));
> > val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> >+ /* Configure frame start delay to match the CPU */
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> > I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
> >
> > val = TRANS_ENABLE;
> >@@ -6452,6 +6464,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc)
> > I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); }
> >
> >+static void hsw_set_frame_start_delay(const struct intel_crtc_state
> >+*crtc_state) {
> >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >+ i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~HSW_FRAME_START_DELAY_MASK;
> >+ val |= HSW_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+}
> >+
> > static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
> > struct intel_atomic_state *state)
> > {
> >@@ -6494,8 +6519,10 @@ static void haswell_crtc_enable(struct intel_crtc_state
> >*pipe_config,
> > &pipe_config->fdi_m_n, NULL);
> > }
> >
> >- if (!transcoder_is_dsi(cpu_transcoder))
> >+ if (!transcoder_is_dsi(cpu_transcoder)) {
> >+ hsw_set_frame_start_delay(pipe_config);
> > haswell_set_pipeconf(pipe_config);
> >+ }
> >
> > if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> > bdw_set_pipemisc(pipe_config);
> >@@ -8394,6 +8421,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state
> >*crtc_state)
> >
> > pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >
> >+ pipeconf |= PIPECONF_FRAME_START_DELAY(0);
> >+
> > I915_WRITE(PIPECONF(crtc->pipe), pipeconf);
> > POSTING_READ(PIPECONF(crtc->pipe));
> > }
> >@@ -9474,6 +9503,8 @@ static void ironlake_set_pipeconf(const struct
> >intel_crtc_state *crtc_state)
> >
> > val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >
> >+ val |= PIPECONF_FRAME_START_DELAY(0);
> >+
> > I915_WRITE(PIPECONF(pipe), val);
> > POSTING_READ(PIPECONF(pipe));
> > }
> >@@ -16919,25 +16950,69 @@ static bool has_pch_trancoder(struct
> >drm_i915_private *dev_priv,
> > (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == PIPE_A); }
> >
> >+static void intel_sanitize_frame_start_delay(const struct
> >+intel_crtc_state *crtc_state) {
> >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> >+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >+
> >+ if (INTEL_GEN(dev_priv) >= 9 ||
> >+ IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
> >+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> >+ u32 val;
> >+
> >+ if (transcoder_is_dsi(cpu_transcoder))
> >+ return;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~HSW_FRAME_START_DELAY_MASK;
> >+ val |= HSW_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ } else {
> >+ i915_reg_t reg = PIPECONF(cpu_transcoder);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~PIPECONF_FRAME_START_DELAY_MASK;
> >+ val |= PIPECONF_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ }
> >+
> >+ if (!crtc_state->has_pch_encoder)
> >+ return;
> >+
> >+ if (HAS_PCH_IBX(dev_priv)) {
> >+ i915_reg_t reg = PCH_TRANSCONF(crtc->pipe);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~TRANS_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ } else {
> >+ i915_reg_t reg = TRANS_CHICKEN2(crtc->pipe);
> >+ u32 val;
> >+
> >+ val = I915_READ(reg);
> >+ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
> >+ val |= TRANS_CHICKEN2_FRAME_START_DELAY(0);
> >+ I915_WRITE(reg, val);
> >+ }
> >+}
> >+
> > static void intel_sanitize_crtc(struct intel_crtc *crtc,
> > struct drm_modeset_acquire_ctx *ctx) {
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> >- enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >-
> >- /* Clear any frame start delays used for debugging left by the BIOS */
> >- if (crtc->active && !transcoder_is_dsi(cpu_transcoder)) {
> >- i915_reg_t reg = PIPECONF(cpu_transcoder);
> >-
> >- I915_WRITE(reg,
> >- I915_READ(reg) &
> >~PIPECONF_FRAME_START_DELAY_MASK);
> >- }
> >
> > if (crtc_state->base.active) {
> > struct intel_plane *plane;
> >
> >+ /* Clear any frame start delays used for debugging left by the BIOS */
> >+ intel_sanitize_frame_start_delay(crtc_state);
> >+
> > /* Disable everything but the primary plane */
> > for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > const struct intel_plane_state *plane_state = diff --git
> >a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index
> >50c2fa0f2cab..cb2e0f4679c4 100644
> >--- a/drivers/gpu/drm/i915/i915_reg.h
> >+++ b/drivers/gpu/drm/i915/i915_reg.h
> >@@ -5671,7 +5671,8 @@ enum {
> > #define PIPECONF_DOUBLE_WIDE (1 << 30)
> > #define I965_PIPECONF_ACTIVE (1 << 30)
> > #define PIPECONF_DSI_PLL_LOCKED (1 << 29) /* vlv & pipe A only */
> >-#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27)
> >+#define PIPECONF_FRAME_START_DELAY_MASK (3 << 27) /* pre-hsw */
> >+#define PIPECONF_FRAME_START_DELAY(x) ((x) << 27) /* pre-hsw: 0-3
> >*/
> > #define PIPECONF_SINGLE_WIDE 0
> > #define PIPECONF_PIPE_UNLOCKED 0
> > #define PIPECONF_PIPE_LOCKED (1 << 25)
> >@@ -7627,6 +7628,8 @@ enum {
> > [TRANSCODER_B] = _CHICKEN_TRANS_B,
> >\
> > [TRANSCODER_C] = _CHICKEN_TRANS_C,
> >\
> > [TRANSCODER_D] =
> >_CHICKEN_TRANS_D))
> >+#define HSW_FRAME_START_DELAY_MASK (3 << 27)
> >+#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> > #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> > #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> > #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
> >@@ -8341,10 +8344,8 @@ enum {
> > #define TRANS_STATE_MASK (1 << 30)
> > #define TRANS_STATE_DISABLE (0 << 30)
> > #define TRANS_STATE_ENABLE (1 << 30)
> >-#define TRANS_FSYNC_DELAY_HB1 (0 << 27) -#define TRANS_FSYNC_DELAY_HB2
> >(1 << 27) -#define TRANS_FSYNC_DELAY_HB3 (2 << 27) -#define
> >TRANS_FSYNC_DELAY_HB4 (3 << 27)
> >+#define TRANS_FRAME_START_DELAY_MASK (3 << 27) /* ibx */
> >+#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> > #define TRANS_INTERLACE_MASK (7 << 21)
> > #define TRANS_PROGRESSIVE (0 << 21)
> > #define TRANS_INTERLACED (3 << 21)
> >@@ -8365,6 +8366,7 @@ enum {
> > #define TRANS_CHICKEN2_TIMING_OVERRIDE (1 << 31)
> > #define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1 << 29)
> > #define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3 << 27)
> >+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
> > #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1 << 26)
> > #define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1 << 25)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index
> >362234449087..8b1fbdb36537 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -8079,7 +8079,6 @@ static void cpt_init_clock_gating(struct drm_i915_private
> >*dev_priv)
> > val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> > if (dev_priv->vbt.fdi_rx_polarity_inverted)
> > val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> >- val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
>
> Is there any reason not to let it be set at 0.
>
> Overall, I looked at the register and bit definitions for various platforms and this looks
> a very reasonable change rectifying the frame start delay programming.
>
> However I am not sure if for all platforms 0 will be the preferred value. If the default values
> of these bits are 0 in hardware register (or the BIOS set them at 0 itself), this should
> work seamlessly. Only caveat will be if the defaults are not 0 on all platforms, we may have
> issues.
Default is 0, but supposedly some VBIOSen have left other values
in there for whatever reason. Or else we probably wouldn't have this
code to sanitize things.
I *may* want to try bumping this to 3 across the board to give
gamma programming more breathing room during the vblank, but I'm
not sure that's entirely safe to do. Hence I started with just
cleaning up the current mess.
IIRC there was also some obnoxious workaround on LVDS+IBX (or maybe
it was CPT) that would require some extra handling if we were to
program this to some non-zero value.
>
> Good way to figure this out I guess is our CI results. So if the CI passes, this is
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Ta.
>
> > val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> > val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> > I915_WRITE(TRANS_CHICKEN2(pipe), val);
> >--
> >2.21.0
> >
> >_______________________________________________
> >Intel-gfx mailing list
> >Intel-gfx@lists.freedesktop.org
> >https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-10-24 18:21 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-10-24 18:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
URL : https://patchwork.freedesktop.org/series/68517/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7174 -> Patchwork_14967
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/index.html
Known issues
------------
Here are the changes found in Patchwork_14967 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-read-write-distinct:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u3/igt@gem_mmap_gtt@basic-read-write-distinct.html
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [PASS][3] -> [FAIL][4] ([fdo#109635 ] / [fdo#110387])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#111407])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_flink_basic@double-flink:
- fi-icl-u3: [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-u3/igt@gem_flink_basic@double-flink.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-u3/igt@gem_flink_basic@double-flink.html
* {igt@i915_selftest@live_gt_heartbeat}:
- fi-kbl-8809g: [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-kbl-8809g/igt@i915_selftest@live_gt_heartbeat.html
- {fi-cml-s}: [DMESG-FAIL][11] ([fdo#112096]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-cml-s/igt@i915_selftest@live_gt_heartbeat.html
* igt@vgem_basic@debugfs:
- {fi-icl-dsi}: [DMESG-WARN][13] ([fdo#106107]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/fi-icl-dsi/igt@vgem_basic@debugfs.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/fi-icl-dsi/igt@vgem_basic@debugfs.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111647]: https://bugs.freedesktop.org/show_bug.cgi?id=111647
[fdo#112046]: https://bugs.freedesktop.org/show_bug.cgi?id=112046
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (50 -> 44)
------------------------------
Additional (2): fi-hsw-peppy fi-pnv-d510
Missing (8): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7174 -> Patchwork_14967
CI-20190529: 20190529
CI_DRM_7174: c320b9b5667a773952b1d6dfdc0fff5aac2d0fb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14967: 6de246f804ed25b6cb50a49a1cff95764056bb29 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
6de246f804ed drm/i915: Fix frame start delay programming
0e839c74920b drm/i915: Add CHICKEN_TRANS_D
521a17601844 drm/i915: Use _PICK() for CHICKEN_TRANS()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-10-24 22:36 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-10-24 22:36 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make CHICKEN_TRANS() a bit less special looking by using _PICK().
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +---------------------
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++----
> 3 files changed, 17 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1a49266f4f57..127dd2d736d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3870,12 +3870,12 @@ static i915_reg_t
> gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - static const i915_reg_t regs[] = {
> - [PORT_A] = CHICKEN_TRANS_EDP,
> - [PORT_B] = CHICKEN_TRANS_A,
> - [PORT_C] = CHICKEN_TRANS_B,
> - [PORT_D] = CHICKEN_TRANS_C,
> - [PORT_E] = CHICKEN_TRANS_A,
> + static const enum transcoder trans[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> };
>
> WARN_ON(INTEL_GEN(dev_priv) < 9);
> @@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct
> drm_i915_private *dev_priv,
> if (WARN_ON(port < PORT_A || port > PORT_E))
> port = PORT_A;
>
> - return regs[port];
> + return CHICKEN_TRANS(trans[port]);
> }
>
> static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dfbedff98ea8..1643c35484d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> dev_priv->psr.active = true;
> }
>
> -static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private
> *dev_priv,
> - enum transcoder
> cpu_transcoder)
> -{
> - static const i915_reg_t regs[] = {
> - [TRANSCODER_A] = CHICKEN_TRANS_A,
> - [TRANSCODER_B] = CHICKEN_TRANS_B,
> - [TRANSCODER_C] = CHICKEN_TRANS_C,
> - [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
> - };
> -
> - WARN_ON(INTEL_GEN(dev_priv) < 9);
> -
> - if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
> - !regs[cpu_transcoder].reg))
> - cpu_transcoder = TRANSCODER_A;
> -
> - return regs[cpu_transcoder];
> -}
> -
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state)
> {
> @@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
> - i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
> - cpu_transcoder)
> ;
> + i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = I915_READ(reg);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..38071d0c8020 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7616,10 +7616,15 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A,
> _CHICKEN_PIPESL_1_B)
>
> -#define CHICKEN_TRANS_A _MMIO(0x420c0)
> -#define CHICKEN_TRANS_B _MMIO(0x420c4)
> -#define CHICKEN_TRANS_C _MMIO(0x420c8)
> -#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_EDP 0x420cc
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> + [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> + [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> + [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-10-24 22:36 ` Souza, Jose
0 siblings, 0 replies; 22+ messages in thread
From: Souza, Jose @ 2019-10-24 22:36 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2019-10-24 at 15:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make CHICKEN_TRANS() a bit less special looking by using _PICK().
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +---------------------
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++----
> 3 files changed, 17 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1a49266f4f57..127dd2d736d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3870,12 +3870,12 @@ static i915_reg_t
> gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - static const i915_reg_t regs[] = {
> - [PORT_A] = CHICKEN_TRANS_EDP,
> - [PORT_B] = CHICKEN_TRANS_A,
> - [PORT_C] = CHICKEN_TRANS_B,
> - [PORT_D] = CHICKEN_TRANS_C,
> - [PORT_E] = CHICKEN_TRANS_A,
> + static const enum transcoder trans[] = {
> + [PORT_A] = TRANSCODER_EDP,
> + [PORT_B] = TRANSCODER_A,
> + [PORT_C] = TRANSCODER_B,
> + [PORT_D] = TRANSCODER_C,
> + [PORT_E] = TRANSCODER_A,
> };
>
> WARN_ON(INTEL_GEN(dev_priv) < 9);
> @@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct
> drm_i915_private *dev_priv,
> if (WARN_ON(port < PORT_A || port > PORT_E))
> port = PORT_A;
>
> - return regs[port];
> + return CHICKEN_TRANS(trans[port]);
> }
>
> static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index dfbedff98ea8..1643c35484d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp
> *intel_dp)
> dev_priv->psr.active = true;
> }
>
> -static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private
> *dev_priv,
> - enum transcoder
> cpu_transcoder)
> -{
> - static const i915_reg_t regs[] = {
> - [TRANSCODER_A] = CHICKEN_TRANS_A,
> - [TRANSCODER_B] = CHICKEN_TRANS_B,
> - [TRANSCODER_C] = CHICKEN_TRANS_C,
> - [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
> - };
> -
> - WARN_ON(INTEL_GEN(dev_priv) < 9);
> -
> - if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
> - !regs[cpu_transcoder].reg))
> - cpu_transcoder = TRANSCODER_A;
> -
> - return regs[cpu_transcoder];
> -}
> -
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state)
> {
> @@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
> - i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
> - cpu_transcoder)
> ;
> + i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = I915_READ(reg);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 855db888516c..38071d0c8020 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7616,10 +7616,15 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A,
> _CHICKEN_PIPESL_1_B)
>
> -#define CHICKEN_TRANS_A _MMIO(0x420c0)
> -#define CHICKEN_TRANS_B _MMIO(0x420c4)
> -#define CHICKEN_TRANS_C _MMIO(0x420c8)
> -#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
> +#define _CHICKEN_TRANS_A 0x420c0
> +#define _CHICKEN_TRANS_B 0x420c4
> +#define _CHICKEN_TRANS_C 0x420c8
> +#define _CHICKEN_TRANS_EDP 0x420cc
> +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
> + [TRANSCODER_EDP] =
> _CHICKEN_TRANS_EDP, \
> + [TRANSCODER_A] =
> _CHICKEN_TRANS_A, \
> + [TRANSCODER_B] =
> _CHICKEN_TRANS_B, \
> + [TRANSCODER_C] =
> _CHICKEN_TRANS_C))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and
> CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-10-26 2:55 ` Patchwork
0 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2019-10-26 2:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
URL : https://patchwork.freedesktop.org/series/68517/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7174_full -> Patchwork_14967_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14967_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14967_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14967_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
- shard-glk: [PASS][1] -> [TIMEOUT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-glk4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-glk8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@perf_pmu@semaphore-busy-vcs0}:
- {shard-tglb}: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb5/igt@perf_pmu@semaphore-busy-vcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb3/igt@perf_pmu@semaphore-busy-vcs0.html
Known issues
------------
Here are the changes found in Patchwork_14967_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +14 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb4/igt@gem_busy@busy-vcs1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb6/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb4/igt@gem_ctx_isolation@vcs1-dirty-create.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][9] -> [FAIL][10] ([fdo#109661])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-snb4/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#111325]) +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_linear_blits@interruptible:
- shard-apl: [PASS][13] -> [INCOMPLETE][14] ([fdo#103927] / [fdo#112067])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-apl6/igt@gem_linear_blits@interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-apl3/igt@gem_linear_blits@interruptible.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-snb: [PASS][15] -> [DMESG-WARN][16] ([fdo#111870])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-snb7/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@i915_selftest@live_hangcheck:
- shard-iclb: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] / [fdo#108569])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb2/igt@i915_selftest@live_hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb2/igt@i915_selftest@live_hangcheck.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [fdo#110403])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#103166])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-apl: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-apl2/igt@kms_rotation_crc@primary-rotation-270.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-apl2/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109276]) +17 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-default:
- {shard-tglb}: [INCOMPLETE][31] ([fdo# 111852 ]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb4/igt@gem_ctx_shared@q-smoketest-default.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb7/igt@gem_ctx_shared@q-smoketest-default.html
* igt@gem_ctx_switch@vcs1:
- shard-iclb: [SKIP][33] ([fdo#112080]) -> [PASS][34] +11 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb5/igt@gem_ctx_switch@vcs1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb1/igt@gem_ctx_switch@vcs1.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][35] ([fdo#111325]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb5/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [SKIP][37] ([fdo#109276]) -> [PASS][38] +19 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb6/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb4/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* {igt@gem_mmap_gtt@close-race}:
- shard-apl: [INCOMPLETE][39] ([fdo#103927]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-apl6/igt@gem_mmap_gtt@close-race.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-apl2/igt@gem_mmap_gtt@close-race.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [FAIL][41] ([fdo#112037]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* {igt@i915_pm_dc@dc6-psr}:
- shard-iclb: [FAIL][43] ([fdo#110548]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@system-suspend:
- {shard-tglb}: [INCOMPLETE][45] ([fdo#111747] / [fdo#111850]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb2/igt@i915_pm_rpm@system-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb2/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@sysfs-reader:
- {shard-tglb}: [INCOMPLETE][47] ([fdo#111832] / [fdo#111850]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb4/igt@i915_suspend@sysfs-reader.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb7/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-random:
- shard-skl: [FAIL][49] ([fdo#103232]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x21-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][51] ([fdo#108566]) -> [PASS][52] +4 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-tglb}: [INCOMPLETE][53] ([fdo#111747] / [fdo#111832] / [fdo#111850]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb8/igt@kms_fbcon_fbt@fbc-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [INCOMPLETE][55] ([fdo#109507]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-skl4/igt@kms_flip@flip-vs-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-skl4/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-iclb: [FAIL][57] ([fdo#103167]) -> [PASS][58] +5 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- {shard-tglb}: [FAIL][59] ([fdo#103167]) -> [PASS][60] +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-iclb: [INCOMPLETE][61] ([fdo#106978] / [fdo#107713]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][63] ([fdo#108145]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][67] ([fdo#111330]) -> [SKIP][68] ([fdo#109276])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][69] ([fdo#109276]) -> [FAIL][70] ([fdo#111330])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7174/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111852 ]: https://bugs.freedesktop.org/show_bug.cgi?id= 111852
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110548]: https://bugs.freedesktop.org/show_bug.cgi?id=110548
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111646]: https://bugs.freedesktop.org/show_bug.cgi?id=111646
[fdo#111671]: https://bugs.freedesktop.org/show_bug.cgi?id=111671
[fdo#111703]: https://bugs.freedesktop.org/show_bug.cgi?id=111703
[fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
[fdo#111780 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111780
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112037]: https://bugs.freedesktop.org/show_bug.cgi?id=112037
[fdo#112067]: https://bugs.freedesktop.org/show_bug.cgi?id=112067
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7174 -> Patchwork_14967
CI-20190529: 20190529
CI_DRM_7174: c320b9b5667a773952b1d6dfdc0fff5aac2d0fb1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14967: 6de246f804ed25b6cb50a49a1cff95764056bb29 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14967/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-11-15 17:10 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-15 17:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Oct 24, 2019 at 03:21:36PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Make CHICKEN_TRANS() a bit less special looking by using _PICK().
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +---------------------
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++----
> 3 files changed, 17 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 1a49266f4f57..127dd2d736d4 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3870,12 +3870,12 @@ static i915_reg_t
> gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> enum port port)
> {
>- static const i915_reg_t regs[] = {
>- [PORT_A] = CHICKEN_TRANS_EDP,
>- [PORT_B] = CHICKEN_TRANS_A,
>- [PORT_C] = CHICKEN_TRANS_B,
>- [PORT_D] = CHICKEN_TRANS_C,
>- [PORT_E] = CHICKEN_TRANS_A,
>+ static const enum transcoder trans[] = {
>+ [PORT_A] = TRANSCODER_EDP,
>+ [PORT_B] = TRANSCODER_A,
>+ [PORT_C] = TRANSCODER_B,
>+ [PORT_D] = TRANSCODER_C,
>+ [PORT_E] = TRANSCODER_A,
> };
>
> WARN_ON(INTEL_GEN(dev_priv) < 9);
>@@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> if (WARN_ON(port < PORT_A || port > PORT_E))
> port = PORT_A;
>
>- return regs[port];
>+ return CHICKEN_TRANS(trans[port]);
> }
>
> static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index dfbedff98ea8..1643c35484d8 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> dev_priv->psr.active = true;
> }
>
>-static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
>- enum transcoder cpu_transcoder)
>-{
>- static const i915_reg_t regs[] = {
>- [TRANSCODER_A] = CHICKEN_TRANS_A,
>- [TRANSCODER_B] = CHICKEN_TRANS_B,
>- [TRANSCODER_C] = CHICKEN_TRANS_C,
>- [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
>- };
>-
>- WARN_ON(INTEL_GEN(dev_priv) < 9);
>-
>- if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
>- !regs[cpu_transcoder].reg))
>- cpu_transcoder = TRANSCODER_A;
>-
>- return regs[cpu_transcoder];
>-}
>-
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
>@@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
>- i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
>- cpu_transcoder);
>+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = I915_READ(reg);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 855db888516c..38071d0c8020 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7616,10 +7616,15 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
>-#define CHICKEN_TRANS_A _MMIO(0x420c0)
>-#define CHICKEN_TRANS_B _MMIO(0x420c4)
>-#define CHICKEN_TRANS_C _MMIO(0x420c8)
>-#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
>+#define _CHICKEN_TRANS_A 0x420c0
>+#define _CHICKEN_TRANS_B 0x420c4
>+#define _CHICKEN_TRANS_C 0x420c8
>+#define _CHICKEN_TRANS_EDP 0x420cc
>+#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
>+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
>+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
>+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
>+ [TRANSCODER_C] = _CHICKEN_TRANS_C))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [Intel-gfx] [PATCH 1/3] drm/i915: Use _PICK() for CHICKEN_TRANS()
@ 2019-11-15 17:10 ` Lucas De Marchi
0 siblings, 0 replies; 22+ messages in thread
From: Lucas De Marchi @ 2019-11-15 17:10 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Oct 24, 2019 at 03:21:36PM +0300, Ville Syrjälä wrote:
>From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>Make CHICKEN_TRANS() a bit less special looking by using _PICK().
>
>Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/i915/display/intel_ddi.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_psr.c | 22 +---------------------
> drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++----
> 3 files changed, 17 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 1a49266f4f57..127dd2d736d4 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -3870,12 +3870,12 @@ static i915_reg_t
> gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> enum port port)
> {
>- static const i915_reg_t regs[] = {
>- [PORT_A] = CHICKEN_TRANS_EDP,
>- [PORT_B] = CHICKEN_TRANS_A,
>- [PORT_C] = CHICKEN_TRANS_B,
>- [PORT_D] = CHICKEN_TRANS_C,
>- [PORT_E] = CHICKEN_TRANS_A,
>+ static const enum transcoder trans[] = {
>+ [PORT_A] = TRANSCODER_EDP,
>+ [PORT_B] = TRANSCODER_A,
>+ [PORT_C] = TRANSCODER_B,
>+ [PORT_D] = TRANSCODER_C,
>+ [PORT_E] = TRANSCODER_A,
> };
>
> WARN_ON(INTEL_GEN(dev_priv) < 9);
>@@ -3883,7 +3883,7 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
> if (WARN_ON(port < PORT_A || port > PORT_E))
> port = PORT_A;
>
>- return regs[port];
>+ return CHICKEN_TRANS(trans[port]);
> }
>
> static void intel_enable_ddi_hdmi(struct intel_encoder *encoder,
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index dfbedff98ea8..1643c35484d8 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -740,25 +740,6 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> dev_priv->psr.active = true;
> }
>
>-static i915_reg_t gen9_chicken_trans_reg(struct drm_i915_private *dev_priv,
>- enum transcoder cpu_transcoder)
>-{
>- static const i915_reg_t regs[] = {
>- [TRANSCODER_A] = CHICKEN_TRANS_A,
>- [TRANSCODER_B] = CHICKEN_TRANS_B,
>- [TRANSCODER_C] = CHICKEN_TRANS_C,
>- [TRANSCODER_EDP] = CHICKEN_TRANS_EDP,
>- };
>-
>- WARN_ON(INTEL_GEN(dev_priv) < 9);
>-
>- if (WARN_ON(cpu_transcoder >= ARRAY_SIZE(regs) ||
>- !regs[cpu_transcoder].reg))
>- cpu_transcoder = TRANSCODER_A;
>-
>- return regs[cpu_transcoder];
>-}
>-
> static void intel_psr_enable_source(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state)
> {
>@@ -774,8 +755,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
>
> if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) &&
> !IS_GEMINILAKE(dev_priv))) {
>- i915_reg_t reg = gen9_chicken_trans_reg(dev_priv,
>- cpu_transcoder);
>+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
> u32 chicken = I915_READ(reg);
>
> chicken |= PSR2_VSC_ENABLE_PROG_HEADER |
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 855db888516c..38071d0c8020 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7616,10 +7616,15 @@ enum {
> #define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
> #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>
>-#define CHICKEN_TRANS_A _MMIO(0x420c0)
>-#define CHICKEN_TRANS_B _MMIO(0x420c4)
>-#define CHICKEN_TRANS_C _MMIO(0x420c8)
>-#define CHICKEN_TRANS_EDP _MMIO(0x420cc)
>+#define _CHICKEN_TRANS_A 0x420c0
>+#define _CHICKEN_TRANS_B 0x420c4
>+#define _CHICKEN_TRANS_C 0x420c8
>+#define _CHICKEN_TRANS_EDP 0x420cc
>+#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
>+ [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
>+ [TRANSCODER_A] = _CHICKEN_TRANS_A, \
>+ [TRANSCODER_B] = _CHICKEN_TRANS_B, \
>+ [TRANSCODER_C] = _CHICKEN_TRANS_C))
> #define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
> #define DDI_TRAINING_OVERRIDE_ENABLE (1 << 19)
> #define DDI_TRAINING_OVERRIDE_VALUE (1 << 18)
>--
>2.21.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread