* [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA
@ 2020-04-07 16:18 Uma Shankar
2020-04-07 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev4) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Uma Shankar @ 2020-04-07 16:18 UTC (permalink / raw)
To: intel-gfx; +Cc: kai.vehmanen
For certain DP VDSC bpp settings, hblank asserts before hblank_early,
leading to a bad audio state. Driver need to program "hblank early
enable" and "samples per line" parameters in AUDIO_CONFIG_BE
register.
This is Display Audio WA #1406928334 for 4k+VDSC usecase
applicable on DP encoders. Implemented the same.
v2: Fixed build failures on 32bit machine.
v3: Dropped u64, added helpers for sample room calculation,
other general comments as per Jani Nikula's feedback.
Also fixed connector type check (spotted by Anshuman)
v4: Addressed Jani Nikula and Kai's review comments.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 147 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 16 +++
2 files changed, 163 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 950160f1a89f..87118cb4a3ae 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -512,6 +512,149 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
mutex_unlock(&dev_priv->av_mutex);
}
+/* Add a factor to take care of rounding and truncations */
+#define ROUNDING_FACTOR 10000
+
+static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ unsigned int link_clks_available, link_clks_required;
+ unsigned int tu_data, tu_line, link_clks_active;
+ unsigned int hblank_rise, hblank_early_prog;
+ unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
+ unsigned int fec_coeff, refresh_rate, cdclk;
+
+ h_active = crtc_state->hw.adjusted_mode.hdisplay;
+ h_total = crtc_state->hw.adjusted_mode.htotal;
+ v_total = crtc_state->hw.adjusted_mode.vtotal;
+ hblank_rise = crtc_state->hw.adjusted_mode.hsync_start;
+ pixel_clk = crtc_state->hw.adjusted_mode.clock;
+ refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
+ cdclk = i915->cdclk.hw.cdclk;
+ /* fec= 0.972261, using rounding multiplier of 1000000 */
+ fec_coeff = 972261;
+
+ drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
+ "lanes = %u vdsc_bpp = %u cdclk = %u\n",
+ h_active, crtc_state->port_clock, crtc_state->lane_count,
+ crtc_state->pipe_bpp, cdclk);
+
+ link_clks_available = ((((h_total - h_active) *
+ ((crtc_state->port_clock * ROUNDING_FACTOR) /
+ pixel_clk)) / ROUNDING_FACTOR) - 28);
+
+ link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
+ v_total)) * ((48 /
+ crtc_state->lane_count) + 2);
+
+ if (link_clks_available > link_clks_required)
+ hblank_delta = 32;
+ else
+ hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
+ crtc_state->port_clock) + ((5 *
+ ROUNDING_FACTOR) /
+ cdclk)) * pixel_clk),
+ ROUNDING_FACTOR);
+
+ tu_data = (pixel_clk * crtc_state->pipe_bpp * 8) /
+ ((crtc_state->port_clock *
+ crtc_state->lane_count * fec_coeff) / 1000000);
+ tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
+ 1000000) / (64 * pixel_clk));
+ link_clks_active = (tu_line - 1) * 64 + tu_data;
+
+ hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
+ 250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
+ crtc_state->port_clock)) / ROUNDING_FACTOR;
+
+ hblank_early_prog = h_active - hblank_rise + hblank_delta;
+
+ return hblank_early_prog;
+}
+
+static unsigned int get_sample_room_req_config(const struct intel_crtc_state *crtc_state)
+{
+ unsigned int h_active, h_total, pixel_clk;
+ unsigned int samples_room;
+
+ h_active = crtc_state->hw.adjusted_mode.hdisplay;
+ h_total = crtc_state->hw.adjusted_mode.htotal;
+ pixel_clk = crtc_state->hw.adjusted_mode.clock;
+
+ samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
+ ROUNDING_FACTOR) / pixel_clk)) /
+ ROUNDING_FACTOR) - 12) / ((48 /
+ crtc_state->lane_count) + 2);
+
+ return samples_room;
+}
+
+static void enable_audio_dsc_wa(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
+ unsigned int hblank_early_prog, samples_room, h_active;
+ unsigned int val;
+
+ if (INTEL_GEN(i915) < 11)
+ return;
+
+ h_active = crtc_state->hw.adjusted_mode.hdisplay;
+
+ if (!(h_active && crtc_state->port_clock && crtc_state->lane_count &&
+ crtc_state->pipe_bpp && i915->cdclk.hw.cdclk)) {
+ drm_err(&i915->drm, "Null Params rcvd for hblank early enabling\n");
+ WARN_ON(1);
+ return;
+ }
+
+ val = intel_de_read(i915, AUD_CONFIG_BE);
+
+ if (INTEL_GEN(i915) == 11)
+ val |= HBLANK_EARLY_ENABLE_ICL(pipe);
+ else if (INTEL_GEN(i915) >= 12)
+ val |= HBLANK_EARLY_ENABLE_TGL(pipe);
+
+ if (crtc_state->dsc.compression_enable &&
+ (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
+ crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
+ /* Get hblank early enable value required */
+ hblank_early_prog = get_hblank_early_enable_config(encoder,
+ crtc_state);
+ if (hblank_early_prog < 32) {
+ val &= ~HBLANK_START_COUNT_MASK(pipe);
+ val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
+ } else if (hblank_early_prog < 64) {
+ val &= ~HBLANK_START_COUNT_MASK(pipe);
+ val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
+ } else if (hblank_early_prog < 96) {
+ val &= ~HBLANK_START_COUNT_MASK(pipe);
+ val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
+ } else {
+ val &= ~HBLANK_START_COUNT_MASK(pipe);
+ val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
+ }
+
+ /* Get samples room value required */
+ samples_room = get_sample_room_req_config(crtc_state);
+ if (samples_room < 3) {
+ val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
+ val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
+ } else {
+ /* Program 0 i.e "All Samples available in buffer" */
+ val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
+ val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
+ }
+ }
+
+ intel_de_write(i915, AUD_CONFIG_BE, val);
+}
+
+#undef ROUNDING_FACTOR
+
static void hsw_audio_codec_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
@@ -529,6 +672,10 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
mutex_lock(&dev_priv->av_mutex);
+ /* Enable Audio WA for 4k DSC usecases */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
+ enable_audio_dsc_wa(encoder, crtc_state);
+
/* Enable audio presence detect, invalidate ELD */
tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cebb7a86b8c..f72ea2c2a8e3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9395,6 +9395,22 @@ enum {
#define AUD_PIN_BUF_CTL _MMIO(0x48414)
#define AUD_PIN_BUF_ENABLE REG_BIT(31)
+/* Display Audio Config Reg */
+#define AUD_CONFIG_BE _MMIO(0x65ef0)
+#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
+#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
+#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
+#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
+#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
+#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
+
+#define HBLANK_START_COUNT_8 0
+#define HBLANK_START_COUNT_16 1
+#define HBLANK_START_COUNT_32 2
+#define HBLANK_START_COUNT_64 3
+#define HBLANK_START_COUNT_96 4
+#define HBLANK_START_COUNT_128 5
+
/*
* HSW - ICL power wells
*
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev4)
2020-04-07 16:18 [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Uma Shankar
@ 2020-04-07 16:53 ` Patchwork
2020-04-07 22:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-04-14 14:17 ` [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Anshuman Gupta
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-04-07 16:53 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: Enable DP Display Audio WA (rev4)
URL : https://patchwork.freedesktop.org/series/75582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8265 -> Patchwork_17239
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/index.html
Known issues
------------
Here are the changes found in Patchwork_17239 that come from known issues:
### IGT changes ###
#### Warnings ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-x1275: [SKIP][1] ([fdo#109271]) -> [DMESG-FAIL][2] ([i915#62])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][3] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][4] ([i915#62] / [i915#92]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/fi-kbl-x1275/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][5] ([i915#62] / [i915#92]) -> [DMESG-WARN][6] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (53 -> 46)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8265 -> Patchwork_17239
CI-20190529: 20190529
CI_DRM_8265: 8b080eb87f391af5371ab721d1221bea6c03ef5b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5574: 15e8ffecfd55d3d632491b73ed981e4467145a4b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17239: ffb88276fd354868e66d6e8a189963ff20778f3d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ffb88276fd35 drm/i915/display: Enable DP Display Audio WA
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Enable DP Display Audio WA (rev4)
2020-04-07 16:18 [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Uma Shankar
2020-04-07 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev4) Patchwork
@ 2020-04-07 22:45 ` Patchwork
2020-04-14 14:17 ` [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Anshuman Gupta
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2020-04-07 22:45 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: Enable DP Display Audio WA (rev4)
URL : https://patchwork.freedesktop.org/series/75582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8265_full -> Patchwork_17239_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17239_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-shared-iova@rcs0}:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-iclb2/igt@gem_exec_schedule@pi-shared-iova@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-iclb3/igt@gem_exec_schedule@pi-shared-iova@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_17239_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#716])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-glk2/igt@gen9_exec_parse@allowed-all.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-skl: [PASS][5] -> [FAIL][6] ([i915#182])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl7/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#72])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#52] / [i915#54])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-glk2/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#79])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#34]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-glk4/igt@kms_flip@plain-flip-ts-check-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-glk5/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#1188])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][21] -> [FAIL][22] ([fdo#108145] / [i915#265])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109441]) +2 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_universal_plane@universal-plane-pipe-b-functional:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#331])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl3/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl7/igt@kms_universal_plane@universal-plane-pipe-b-functional.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#69]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
#### Possible fixes ####
* {igt@gem_ctx_isolation@preservation-s3@rcs0}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-apl1/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-apl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* {igt@gem_ctx_isolation@preservation-s3@vecs0}:
- shard-kbl: [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][33] ([i915#454]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-snb: [FAIL][35] ([i915#1066]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-snb5/igt@i915_pm_rc6_residency@rc6-idle.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-snb4/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@requests:
- shard-tglb: [INCOMPLETE][37] ([i915#1531]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-tglb5/igt@i915_selftest@live@requests.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-tglb7/igt@i915_selftest@live@requests.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-iclb: [INCOMPLETE][39] ([i915#1185] / [i915#1237]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][41] ([IGT#5]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-render-untiled:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-snb6/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-snb6/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible:
- shard-skl: [FAIL][45] ([i915#34]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][47] ([fdo#108145] / [i915#265]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][49] ([i915#31]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl5/igt@kms_setmode@basic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl2/igt@kms_setmode@basic.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [FAIL][51] ([i915#454]) -> [SKIP][52] ([i915#468])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@gem-mmap-type:
- shard-snb: [INCOMPLETE][53] ([i915#82]) -> [SKIP][54] ([fdo#109271])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-snb7/igt@i915_pm_rpm@gem-mmap-type.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-snb4/igt@i915_pm_rpm@gem-mmap-type.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][55] ([i915#1188]) -> [INCOMPLETE][56] ([i915#198])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8265/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1066]: https://gitlab.freedesktop.org/drm/intel/issues/1066
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1237]: https://gitlab.freedesktop.org/drm/intel/issues/1237
[i915#1531]: https://gitlab.freedesktop.org/drm/intel/issues/1531
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#182]: https://gitlab.freedesktop.org/drm/intel/issues/182
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#331]: https://gitlab.freedesktop.org/drm/intel/issues/331
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8265 -> Patchwork_17239
CI-20190529: 20190529
CI_DRM_8265: 8b080eb87f391af5371ab721d1221bea6c03ef5b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5574: 15e8ffecfd55d3d632491b73ed981e4467145a4b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17239: ffb88276fd354868e66d6e8a189963ff20778f3d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17239/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA
2020-04-07 16:18 [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Uma Shankar
2020-04-07 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev4) Patchwork
2020-04-07 22:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-04-14 14:17 ` Anshuman Gupta
2020-04-16 7:12 ` Shankar, Uma
2 siblings, 1 reply; 5+ messages in thread
From: Anshuman Gupta @ 2020-04-14 14:17 UTC (permalink / raw)
To: Uma Shankar; +Cc: kai.vehmanen, intel-gfx
On 2020-04-07 at 21:48:57 +0530, Uma Shankar wrote:
> For certain DP VDSC bpp settings, hblank asserts before hblank_early,
> leading to a bad audio state. Driver need to program "hblank early
> enable" and "samples per line" parameters in AUDIO_CONFIG_BE
> register.
>
> This is Display Audio WA #1406928334 for 4k+VDSC usecase
> applicable on DP encoders. Implemented the same.
>
> v2: Fixed build failures on 32bit machine.
>
> v3: Dropped u64, added helpers for sample room calculation,
> other general comments as per Jani Nikula's feedback.
> Also fixed connector type check (spotted by Anshuman)
>
> v4: Addressed Jani Nikula and Kai's review comments.
There are some minor comment below.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 147 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 16 +++
> 2 files changed, 163 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 950160f1a89f..87118cb4a3ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -512,6 +512,149 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
> mutex_unlock(&dev_priv->av_mutex);
> }
>
> +/* Add a factor to take care of rounding and truncations */
> +#define ROUNDING_FACTOR 10000
> +
> +static unsigned int get_hblank_early_enable_config(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + unsigned int link_clks_available, link_clks_required;
> + unsigned int tu_data, tu_line, link_clks_active;
> + unsigned int hblank_rise, hblank_early_prog;
> + unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
> + unsigned int fec_coeff, refresh_rate, cdclk;
> +
> + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> + h_total = crtc_state->hw.adjusted_mode.htotal;
> + v_total = crtc_state->hw.adjusted_mode.vtotal;
IMO we should adjusted_mode.crtc_x param for any crtc timing
realted math , as crtc_x params are actual hw params.
please correct me if i am wrong.
> + hblank_rise = crtc_state->hw.adjusted_mode.hsync_start;
IMO we don't need to intilize this with hsync_start.
> + pixel_clk = crtc_state->hw.adjusted_mode.clock;
> + refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
> + cdclk = i915->cdclk.hw.cdclk;
> + /* fec= 0.972261, using rounding multiplier of 1000000 */
> + fec_coeff = 972261;
> +
> + drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
> + "lanes = %u vdsc_bpp = %u cdclk = %u\n",
B.Specs says "If not using compression, vdsc_bpp = input_bpp",
if i am correct is it vdsc comression ?
and we program hblank_early when dsc comression is enabled,
so from this logic vdsc_bpp != pipe_bpp ?
> + h_active, crtc_state->port_clock, crtc_state->lane_count,
> + crtc_state->pipe_bpp, cdclk);
> +
> + link_clks_available = ((((h_total - h_active) *
> + ((crtc_state->port_clock * ROUNDING_FACTOR) /
> + pixel_clk)) / ROUNDING_FACTOR) - 28);
> +
> + link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
> + v_total)) * ((48 /
> + crtc_state->lane_count) + 2);
> +
> + if (link_clks_available > link_clks_required)
> + hblank_delta = 32;
> + else
> + hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
> + crtc_state->port_clock) + ((5 *
> + ROUNDING_FACTOR) /
> + cdclk)) * pixel_clk),
> + ROUNDING_FACTOR);
> +
> + tu_data = (pixel_clk * crtc_state->pipe_bpp * 8) /
> + ((crtc_state->port_clock *
> + crtc_state->lane_count * fec_coeff) / 1000000);
> + tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
> + 1000000) / (64 * pixel_clk));
> + link_clks_active = (tu_line - 1) * 64 + tu_data;
> +
> + hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
> + 250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
> + crtc_state->port_clock)) / ROUNDING_FACTOR;
> +
> + hblank_early_prog = h_active - hblank_rise + hblank_delta;
> +
> + return hblank_early_prog;
> +}
> +
> +static unsigned int get_sample_room_req_config(const struct intel_crtc_state *crtc_state)
> +{
> + unsigned int h_active, h_total, pixel_clk;
> + unsigned int samples_room;
> +
> + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> + h_total = crtc_state->hw.adjusted_mode.htotal;
> + pixel_clk = crtc_state->hw.adjusted_mode.clock;
> +
> + samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
> + ROUNDING_FACTOR) / pixel_clk)) /
> + ROUNDING_FACTOR) - 12) / ((48 /
> + crtc_state->lane_count) + 2);
> +
> + return samples_room;
> +}
> +
> +static void enable_audio_dsc_wa(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + enum pipe pipe = crtc->pipe;
> + unsigned int hblank_early_prog, samples_room, h_active;
> + unsigned int val;
> +
> + if (INTEL_GEN(i915) < 11)
> + return;
> +
> + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> +
> + if (!(h_active && crtc_state->port_clock && crtc_state->lane_count &&
> + crtc_state->pipe_bpp && i915->cdclk.hw.cdclk)) {
> + drm_err(&i915->drm, "Null Params rcvd for hblank early enabling\n");
> + WARN_ON(1);
> + return;
> + }
> +
> + val = intel_de_read(i915, AUD_CONFIG_BE);
> +
> + if (INTEL_GEN(i915) == 11)
> + val |= HBLANK_EARLY_ENABLE_ICL(pipe);
> + else if (INTEL_GEN(i915) >= 12)
> + val |= HBLANK_EARLY_ENABLE_TGL(pipe);
> +
> + if (crtc_state->dsc.compression_enable &&
> + (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
> + crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
> + /* Get hblank early enable value required */
> + hblank_early_prog = get_hblank_early_enable_config(encoder,
> + crtc_state);
> + if (hblank_early_prog < 32) {
> + val &= ~HBLANK_START_COUNT_MASK(pipe);
> + val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_32);
> + } else if (hblank_early_prog < 64) {
> + val &= ~HBLANK_START_COUNT_MASK(pipe);
> + val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_64);
> + } else if (hblank_early_prog < 96) {
> + val &= ~HBLANK_START_COUNT_MASK(pipe);
> + val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_96);
> + } else {
> + val &= ~HBLANK_START_COUNT_MASK(pipe);
> + val |= HBLANK_START_COUNT(pipe, HBLANK_START_COUNT_128);
> + }
> +
> + /* Get samples room value required */
> + samples_room = get_sample_room_req_config(crtc_state);
> + if (samples_room < 3) {
> + val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
> + val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
> + } else {
> + /* Program 0 i.e "All Samples available in buffer" */
> + val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
> + val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
> + }
> + }
> +
> + intel_de_write(i915, AUD_CONFIG_BE, val);
> +}
> +
> +#undef ROUNDING_FACTOR
> +
> static void hsw_audio_codec_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> @@ -529,6 +672,10 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
>
> mutex_lock(&dev_priv->av_mutex);
>
> + /* Enable Audio WA for 4k DSC usecases */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
> + enable_audio_dsc_wa(encoder, crtc_state);
> +
> /* Enable audio presence detect, invalidate ELD */
> tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
> tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8cebb7a86b8c..f72ea2c2a8e3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9395,6 +9395,22 @@ enum {
> #define AUD_PIN_BUF_CTL _MMIO(0x48414)
> #define AUD_PIN_BUF_ENABLE REG_BIT(31)
>
> +/* Display Audio Config Reg */
> +#define AUD_CONFIG_BE _MMIO(0x65ef0)
> +#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
> +#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
> +#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
> +#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 + ((pipe)) * 6))
> +#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
> +#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) * 6))
Earlier Nikula Jani has provided suggestion to use REG_FIELD_PREP.
Thanks ,
Anshuman Gupta.
> +
> +#define HBLANK_START_COUNT_8 0
> +#define HBLANK_START_COUNT_16 1
> +#define HBLANK_START_COUNT_32 2
> +#define HBLANK_START_COUNT_64 3
> +#define HBLANK_START_COUNT_96 4
> +#define HBLANK_START_COUNT_128 5
> +
> /*
> * HSW - ICL power wells
> *
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA
2020-04-14 14:17 ` [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Anshuman Gupta
@ 2020-04-16 7:12 ` Shankar, Uma
0 siblings, 0 replies; 5+ messages in thread
From: Shankar, Uma @ 2020-04-16 7:12 UTC (permalink / raw)
To: Gupta, Anshuman; +Cc: Vehmanen, Kai, intel-gfx
> -----Original Message-----
> From: Gupta, Anshuman <anshuman.gupta@intel.com>
> Sent: Tuesday, April 14, 2020 7:47 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Vehmanen, Kai <kai.vehmanen@intel.com>;
> jani.nikula@linux.intel.com
> Subject: Re: [PATCH v4] drm/i915/display: Enable DP Display Audio WA
>
> On 2020-04-07 at 21:48:57 +0530, Uma Shankar wrote:
> > For certain DP VDSC bpp settings, hblank asserts before hblank_early,
> > leading to a bad audio state. Driver need to program "hblank early
> > enable" and "samples per line" parameters in AUDIO_CONFIG_BE register.
> >
> > This is Display Audio WA #1406928334 for 4k+VDSC usecase applicable on
> > DP encoders. Implemented the same.
> >
> > v2: Fixed build failures on 32bit machine.
> >
> > v3: Dropped u64, added helpers for sample room calculation,
> > other general comments as per Jani Nikula's feedback.
> > Also fixed connector type check (spotted by Anshuman)
> >
> > v4: Addressed Jani Nikula and Kai's review comments.
> There are some minor comment below.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_audio.c | 147 +++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 16 +++
> > 2 files changed, 163 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> > b/drivers/gpu/drm/i915/display/intel_audio.c
> > index 950160f1a89f..87118cb4a3ae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_audio.c
> > +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> > @@ -512,6 +512,149 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> > mutex_unlock(&dev_priv->av_mutex);
> > }
> >
> > +/* Add a factor to take care of rounding and truncations */ #define
> > +ROUNDING_FACTOR 10000
> > +
> > +static unsigned int get_hblank_early_enable_config(struct intel_encoder
> *encoder,
> > + const struct intel_crtc_state
> *crtc_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + unsigned int link_clks_available, link_clks_required;
> > + unsigned int tu_data, tu_line, link_clks_active;
> > + unsigned int hblank_rise, hblank_early_prog;
> > + unsigned int h_active, h_total, hblank_delta, pixel_clk, v_total;
> > + unsigned int fec_coeff, refresh_rate, cdclk;
> > +
> > + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> > + h_total = crtc_state->hw.adjusted_mode.htotal;
> > + v_total = crtc_state->hw.adjusted_mode.vtotal;
> IMO we should adjusted_mode.crtc_x param for any crtc timing
> realted math , as crtc_x params are actual hw params.
> please correct me if i am wrong.
Yeah ok, I will update these to crtc_*
> > + hblank_rise = crtc_state->hw.adjusted_mode.hsync_start;
> IMO we don't need to intilize this with hsync_start.
> > + pixel_clk = crtc_state->hw.adjusted_mode.clock;
> > + refresh_rate = crtc_state->hw.adjusted_mode.vrefresh;
> > + cdclk = i915->cdclk.hw.cdclk;
> > + /* fec= 0.972261, using rounding multiplier of 1000000 */
> > + fec_coeff = 972261;
> > +
> > + drm_dbg_kms(&i915->drm, "h_active = %u link_clk = %u :"
> > + "lanes = %u vdsc_bpp = %u cdclk = %u\n",
> B.Specs says "If not using compression, vdsc_bpp = input_bpp",
> if i am correct is it vdsc comression ?
> and we program hblank_early when dsc comression is enabled,
> so from this logic vdsc_bpp != pipe_bpp ?
> > + h_active, crtc_state->port_clock, crtc_state->lane_count,
> > + crtc_state->pipe_bpp, cdclk);
> > +
> > + link_clks_available = ((((h_total - h_active) *
> > + ((crtc_state->port_clock * ROUNDING_FACTOR) /
> > + pixel_clk)) / ROUNDING_FACTOR) - 28);
> > +
> > + link_clks_required = DIV_ROUND_UP(192000, (refresh_rate *
> > + v_total)) * ((48 /
> > + crtc_state->lane_count) + 2);
> > +
> > + if (link_clks_available > link_clks_required)
> > + hblank_delta = 32;
> > + else
> > + hblank_delta = DIV_ROUND_UP(((((5 * ROUNDING_FACTOR) /
> > + crtc_state->port_clock) + ((5 *
> > + ROUNDING_FACTOR) /
> > + cdclk)) * pixel_clk),
> > + ROUNDING_FACTOR);
> > +
> > + tu_data = (pixel_clk * crtc_state->pipe_bpp * 8) /
> > + ((crtc_state->port_clock *
> > + crtc_state->lane_count * fec_coeff) / 1000000);
> > + tu_line = (((h_active * crtc_state->port_clock * fec_coeff) /
> > + 1000000) / (64 * pixel_clk));
> > + link_clks_active = (tu_line - 1) * 64 + tu_data;
> > +
> > + hblank_rise = ((link_clks_active + 6 * DIV_ROUND_UP(link_clks_active,
> > + 250) + 4) * ((pixel_clk * ROUNDING_FACTOR) /
> > + crtc_state->port_clock)) / ROUNDING_FACTOR;
> > +
> > + hblank_early_prog = h_active - hblank_rise + hblank_delta;
> > +
> > + return hblank_early_prog;
> > +}
> > +
> > +static unsigned int get_sample_room_req_config(const struct
> > +intel_crtc_state *crtc_state) {
> > + unsigned int h_active, h_total, pixel_clk;
> > + unsigned int samples_room;
> > +
> > + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> > + h_total = crtc_state->hw.adjusted_mode.htotal;
> > + pixel_clk = crtc_state->hw.adjusted_mode.clock;
> > +
> > + samples_room = ((((h_total - h_active) * ((crtc_state->port_clock *
> > + ROUNDING_FACTOR) / pixel_clk)) /
> > + ROUNDING_FACTOR) - 12) / ((48 /
> > + crtc_state->lane_count) + 2);
> > +
> > + return samples_room;
> > +}
> > +
> > +static void enable_audio_dsc_wa(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + enum pipe pipe = crtc->pipe;
> > + unsigned int hblank_early_prog, samples_room, h_active;
> > + unsigned int val;
> > +
> > + if (INTEL_GEN(i915) < 11)
> > + return;
> > +
> > + h_active = crtc_state->hw.adjusted_mode.hdisplay;
> > +
> > + if (!(h_active && crtc_state->port_clock && crtc_state->lane_count &&
> > + crtc_state->pipe_bpp && i915->cdclk.hw.cdclk)) {
> > + drm_err(&i915->drm, "Null Params rcvd for hblank early
> enabling\n");
> > + WARN_ON(1);
> > + return;
> > + }
> > +
> > + val = intel_de_read(i915, AUD_CONFIG_BE);
> > +
> > + if (INTEL_GEN(i915) == 11)
> > + val |= HBLANK_EARLY_ENABLE_ICL(pipe);
> > + else if (INTEL_GEN(i915) >= 12)
> > + val |= HBLANK_EARLY_ENABLE_TGL(pipe);
> > +
> > + if (crtc_state->dsc.compression_enable &&
> > + (crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
> > + crtc_state->hw.adjusted_mode.vdisplay >= 2160)) {
> > + /* Get hblank early enable value required */
> > + hblank_early_prog = get_hblank_early_enable_config(encoder,
> > + crtc_state);
> > + if (hblank_early_prog < 32) {
> > + val &= ~HBLANK_START_COUNT_MASK(pipe);
> > + val |= HBLANK_START_COUNT(pipe,
> HBLANK_START_COUNT_32);
> > + } else if (hblank_early_prog < 64) {
> > + val &= ~HBLANK_START_COUNT_MASK(pipe);
> > + val |= HBLANK_START_COUNT(pipe,
> HBLANK_START_COUNT_64);
> > + } else if (hblank_early_prog < 96) {
> > + val &= ~HBLANK_START_COUNT_MASK(pipe);
> > + val |= HBLANK_START_COUNT(pipe,
> HBLANK_START_COUNT_96);
> > + } else {
> > + val &= ~HBLANK_START_COUNT_MASK(pipe);
> > + val |= HBLANK_START_COUNT(pipe,
> HBLANK_START_COUNT_128);
> > + }
> > +
> > + /* Get samples room value required */
> > + samples_room = get_sample_room_req_config(crtc_state);
> > + if (samples_room < 3) {
> > + val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
> > + val |= NUMBER_SAMPLES_PER_LINE(pipe, samples_room);
> > + } else {
> > + /* Program 0 i.e "All Samples available in buffer" */
> > + val &= ~NUMBER_SAMPLES_PER_LINE_MASK(pipe);
> > + val |= NUMBER_SAMPLES_PER_LINE(pipe, 0x0);
> > + }
> > + }
> > +
> > + intel_de_write(i915, AUD_CONFIG_BE, val); }
> > +
> > +#undef ROUNDING_FACTOR
> > +
> > static void hsw_audio_codec_enable(struct intel_encoder *encoder,
> > const struct intel_crtc_state *crtc_state,
> > const struct drm_connector_state *conn_state)
> @@ -529,6
> > +672,10 @@ static void hsw_audio_codec_enable(struct intel_encoder
> > *encoder,
> >
> > mutex_lock(&dev_priv->av_mutex);
> >
> > + /* Enable Audio WA for 4k DSC usecases */
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
> > + enable_audio_dsc_wa(encoder, crtc_state);
> > +
> > /* Enable audio presence detect, invalidate ELD */
> > tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD);
> > tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 8cebb7a86b8c..f72ea2c2a8e3
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9395,6 +9395,22 @@ enum {
> > #define AUD_PIN_BUF_CTL _MMIO(0x48414)
> > #define AUD_PIN_BUF_ENABLE REG_BIT(31)
> >
> > +/* Display Audio Config Reg */
> > +#define AUD_CONFIG_BE _MMIO(0x65ef0)
> > +#define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe)))
> > +#define HBLANK_EARLY_ENABLE_TGL(pipe) (0x1 << (24 + (pipe)))
> > +#define HBLANK_START_COUNT_MASK(pipe) (0x7 << (3 + ((pipe) * 6)))
> > +#define HBLANK_START_COUNT(pipe, val) (((val) & 0x7) << (3 +
> ((pipe)) * 6))
> > +#define NUMBER_SAMPLES_PER_LINE_MASK(pipe) (0x3 << ((pipe) * 6))
> > +#define NUMBER_SAMPLES_PER_LINE(pipe, val) (((val) & 0x3) << ((pipe) *
> 6))
> Earlier Nikula Jani has provided suggestion to use REG_FIELD_PREP.
MASK itself is dependent on pipe, so I feel it is simpler like this.
> Thanks ,
> Anshuman Gupta.
> > +
> > +#define HBLANK_START_COUNT_8 0
> > +#define HBLANK_START_COUNT_16 1
> > +#define HBLANK_START_COUNT_32 2
> > +#define HBLANK_START_COUNT_64 3
> > +#define HBLANK_START_COUNT_96 4
> > +#define HBLANK_START_COUNT_128 5
> > +
> > /*
> > * HSW - ICL power wells
> > *
> > --
> > 2.22.0
> >
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-16 7:12 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-07 16:18 [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Uma Shankar
2020-04-07 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Enable DP Display Audio WA (rev4) Patchwork
2020-04-07 22:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-04-14 14:17 ` [Intel-gfx] [PATCH v4] drm/i915/display: Enable DP Display Audio WA Anshuman Gupta
2020-04-16 7:12 ` Shankar, Uma
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