* Re: [PATCH 6/9] tools: memshr: arm64 support [not found] <mailman.26350.1363354644.1399.xen-devel@lists.xen.org> @ 2013-03-15 14:30 ` Andres Lagar-Cavilla 2013-03-15 14:35 ` Ian Campbell 0 siblings, 1 reply; 5+ messages in thread From: Andres Lagar-Cavilla @ 2013-03-15 14:30 UTC (permalink / raw) To: xen-devel; +Cc: Ian Campbell [-- Attachment #1.1: Type: text/plain, Size: 3691 bytes --] > I'm not mad keen on propagating these sorts of asm atomic operations throughout > our code base. Other options would be: gcc has atomic builtins to do this kind of work. I don't know about arm, but they do the job in x86 http://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html so atomic_inc(val) -> __sync_fetch_and_add(val, 1) and likewise for dec/sub Andres > > - use libatomic-ops, http://www.hpl.hp.com/research/linux/atomic_ops/, although > this doesn't seem to be as widespread as I would like (not in RHEL5 for > example) > - use a pthread lock. This is probably the simplest/best option but I wasn't > able to figure out the locking hierarchy of this code > > So I've coped out and just copied the appropriate inlines here. > > I also nuked some stray ia64 support and fixed a coment in the arm32 version > while I was here. > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> > --- > tools/memshr/bidir-hash.c | 48 +++++++++++++++++++++++++++++++++----------- > 1 files changed, 36 insertions(+), 12 deletions(-) > > diff --git a/tools/memshr/bidir-hash.c b/tools/memshr/bidir-hash.c > index 45d473e..bed8179 100644 > --- a/tools/memshr/bidir-hash.c > +++ b/tools/memshr/bidir-hash.c > @@ -100,22 +100,13 @@ int __hash_iterator(struct __hash *h, > void *d); > static void hash_resize(struct __hash *h); > > -#if defined(__ia64__) > -#define ia64_fetchadd4_rel(p, inc) do { \ > - uint64_t ia64_intri_res; \ > - asm volatile ("fetchadd4.rel %0=[%1],%2" \ > - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ > - : "memory"); \ > -} while (0) > -static inline void atomic_inc(uint32_t *v) { ia64_fetchadd4_rel(v, 1); } > -static inline void atomic_dec(uint32_t *v) { ia64_fetchadd4_rel(v, -1); } > -#elif defined(__arm__) > +#if defined(__arm__) > static inline void atomic_inc(uint32_t *v) > { > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_add\n" > + __asm__ __volatile__("@ atomic_inc\n" > "1: ldrex %0, [%3]\n" > " add %0, %0, #1\n" > " strex %1, %0, [%3]\n" > @@ -130,7 +121,7 @@ static inline void atomic_dec(uint32_t *v) > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_sub\n" > + __asm__ __volatile__("@ atomic_dec\n" > "1: ldrex %0, [%3]\n" > " sub %0, %0, #1\n" > " strex %1, %0, [%3]\n" > @@ -140,6 +131,39 @@ static inline void atomic_dec(uint32_t *v) > : "r" (v) > : "cc"); > } > + > +#elif defined(__aarch64__) > + > +static inline void atomic_inc(uint32_t *v) > +{ > + unsigned long tmp; > + int result; > + > + asm volatile("// atomic_inc\n" > +"1: ldxr %w0, [%3]\n" > +" add %w0, %w0, #1\n" > +" stxr %w1, %w0, [%3]\n" > +" cbnz %w1, 1b" > + : "=&r" (result), "=&r" (tmp), "+o" (v) > + : "r" (v) > + : "cc"); > +} > + > +static inline void atomic_dec(uint32_t *v) > +{ > + unsigned long tmp; > + int result; > + > + asm volatile("// atomic_dec\n" > +"1: ldxr %w0, [%3]\n" > +" sub %w0, %w0, #1\n" > +" stxr %w1, %w0, [%3]\n" > +" cbnz %w1, 1b" > + : "=&r" (result), "=&r" (tmp), "+o" (v) > + : "r" (v) > + : "cc"); > +} > + > #else /* __x86__ */ > static inline void atomic_inc(uint32_t *v) > { > -- > 1.7.2.5 [-- Attachment #1.2: Type: text/html, Size: 6669 bytes --] [-- Attachment #2: Type: text/plain, Size: 126 bytes --] _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 6/9] tools: memshr: arm64 support 2013-03-15 14:30 ` [PATCH 6/9] tools: memshr: arm64 support Andres Lagar-Cavilla @ 2013-03-15 14:35 ` Ian Campbell 0 siblings, 0 replies; 5+ messages in thread From: Ian Campbell @ 2013-03-15 14:35 UTC (permalink / raw) To: Andres Lagar-Cavilla; +Cc: xen-devel On Fri, 2013-03-15 at 14:30 +0000, Andres Lagar-Cavilla wrote: > > I'm not mad keen on propagating these sorts of asm atomic operations > > throughout > > our code base. Other options would be: > > > gcc has atomic builtins to do this kind of work. I don't know about > arm, but they do the job in x86 > http://gcc.gnu.org/onlinedocs/gcc-4.1.1/gcc/Atomic-Builtins.html > so atomic_inc(val) -> __sync_fetch_and_add(val, 1) and likewise for > dec/sub Yes, that might be a suitable replacement, assuming they exist (and work right) in all the x86 gcc's we support (not sure how far back that is) I suppose I could use the builtins on ARM only in the meantime. Thanks! Ian. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 00/09] arm: tools: build for arm64 and enable cross-compiling for both arm32 and arm64 @ 2013-03-15 13:15 Ian Campbell 2013-03-15 13:15 ` [PATCH 6/9] tools: memshr: arm64 support Ian Campbell 0 siblings, 1 reply; 5+ messages in thread From: Ian Campbell @ 2013-03-15 13:15 UTC (permalink / raw) To: xen-devel; +Cc: Tim Deegan, Stefano Stabellini, Ian Jackson The following patches shave some rough edges off the tools build system to allow cross compiling for at least arm32 and arm64 based on the Debian/Ubuntu multiarch infrastructure. They also add the necessary fixes to build for arm64 (which I have only tried cross, not native). I have posted some instructions on how to compile with these patches on the wiki: http://wiki.xen.org/wiki/Xen_ARM_with_Virtualization_Extensions/CrossCompiling Thanks are due to Wookey who gave lots of good advice in the hackrooms at LinaroConnect last week. I consider it an outstanding bug that you need to essentially pass CROSS_COMPILE and XEN_TARGET_ARCH to both configure and make. This is hardly the only remaining annoyance in our build system though... Ian. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 6/9] tools: memshr: arm64 support 2013-03-15 13:15 [PATCH 00/09] arm: tools: build for arm64 and enable cross-compiling for both arm32 and arm64 Ian Campbell @ 2013-03-15 13:15 ` Ian Campbell 2013-03-15 15:29 ` Ian Jackson 2013-03-19 15:52 ` Stefano Stabellini 0 siblings, 2 replies; 5+ messages in thread From: Ian Campbell @ 2013-03-15 13:15 UTC (permalink / raw) To: xen-devel; +Cc: stefano.stabellini, tim, Ian Campbell, ian.jackson I'm not mad keen on propagating these sorts of asm atomic operations throughout our code base. Other options would be: - use libatomic-ops, http://www.hpl.hp.com/research/linux/atomic_ops/, although this doesn't seem to be as widespread as I would like (not in RHEL5 for example) - use a pthread lock. This is probably the simplest/best option but I wasn't able to figure out the locking hierarchy of this code So I've coped out and just copied the appropriate inlines here. I also nuked some stray ia64 support and fixed a coment in the arm32 version while I was here. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- tools/memshr/bidir-hash.c | 48 +++++++++++++++++++++++++++++++++----------- 1 files changed, 36 insertions(+), 12 deletions(-) diff --git a/tools/memshr/bidir-hash.c b/tools/memshr/bidir-hash.c index 45d473e..bed8179 100644 --- a/tools/memshr/bidir-hash.c +++ b/tools/memshr/bidir-hash.c @@ -100,22 +100,13 @@ int __hash_iterator(struct __hash *h, void *d); static void hash_resize(struct __hash *h); -#if defined(__ia64__) -#define ia64_fetchadd4_rel(p, inc) do { \ - uint64_t ia64_intri_res; \ - asm volatile ("fetchadd4.rel %0=[%1],%2" \ - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ - : "memory"); \ -} while (0) -static inline void atomic_inc(uint32_t *v) { ia64_fetchadd4_rel(v, 1); } -static inline void atomic_dec(uint32_t *v) { ia64_fetchadd4_rel(v, -1); } -#elif defined(__arm__) +#if defined(__arm__) static inline void atomic_inc(uint32_t *v) { unsigned long tmp; int result; - __asm__ __volatile__("@ atomic_add\n" + __asm__ __volatile__("@ atomic_inc\n" "1: ldrex %0, [%3]\n" " add %0, %0, #1\n" " strex %1, %0, [%3]\n" @@ -130,7 +121,7 @@ static inline void atomic_dec(uint32_t *v) unsigned long tmp; int result; - __asm__ __volatile__("@ atomic_sub\n" + __asm__ __volatile__("@ atomic_dec\n" "1: ldrex %0, [%3]\n" " sub %0, %0, #1\n" " strex %1, %0, [%3]\n" @@ -140,6 +131,39 @@ static inline void atomic_dec(uint32_t *v) : "r" (v) : "cc"); } + +#elif defined(__aarch64__) + +static inline void atomic_inc(uint32_t *v) +{ + unsigned long tmp; + int result; + + asm volatile("// atomic_inc\n" +"1: ldxr %w0, [%3]\n" +" add %w0, %w0, #1\n" +" stxr %w1, %w0, [%3]\n" +" cbnz %w1, 1b" + : "=&r" (result), "=&r" (tmp), "+o" (v) + : "r" (v) + : "cc"); +} + +static inline void atomic_dec(uint32_t *v) +{ + unsigned long tmp; + int result; + + asm volatile("// atomic_dec\n" +"1: ldxr %w0, [%3]\n" +" sub %w0, %w0, #1\n" +" stxr %w1, %w0, [%3]\n" +" cbnz %w1, 1b" + : "=&r" (result), "=&r" (tmp), "+o" (v) + : "r" (v) + : "cc"); +} + #else /* __x86__ */ static inline void atomic_inc(uint32_t *v) { -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 6/9] tools: memshr: arm64 support 2013-03-15 13:15 ` [PATCH 6/9] tools: memshr: arm64 support Ian Campbell @ 2013-03-15 15:29 ` Ian Jackson 2013-03-19 15:52 ` Stefano Stabellini 1 sibling, 0 replies; 5+ messages in thread From: Ian Jackson @ 2013-03-15 15:29 UTC (permalink / raw) To: Ian Campbell; +Cc: Stefano Stabellini, Tim (Xen.org), xen-devel Ian Campbell writes ("[PATCH 6/9] tools: memshr: arm64 support"): > I'm not mad keen on propagating these sorts of asm atomic operations > throughout our code base. Other options would be: How unpleasant, indeed. > So I've coped out and just copied the appropriate inlines here. Understandable. (YM "copped".) This looks plausible to me so Acked-by: Ian Jackson <ian.jackson@eu.citrix.com> but it needs review by someone who has read the arm64 manual. Ian. ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 6/9] tools: memshr: arm64 support 2013-03-15 13:15 ` [PATCH 6/9] tools: memshr: arm64 support Ian Campbell 2013-03-15 15:29 ` Ian Jackson @ 2013-03-19 15:52 ` Stefano Stabellini 1 sibling, 0 replies; 5+ messages in thread From: Stefano Stabellini @ 2013-03-19 15:52 UTC (permalink / raw) To: Ian Campbell; +Cc: Ian Jackson, Stefano Stabellini, Tim (Xen.org), xen-devel On Fri, 15 Mar 2013, Ian Campbell wrote: > I'm not mad keen on propagating these sorts of asm atomic operations throughout > our code base. Other options would be: > > - use libatomic-ops, http://www.hpl.hp.com/research/linux/atomic_ops/, although > this doesn't seem to be as widespread as I would like (not in RHEL5 for > example) > - use a pthread lock. This is probably the simplest/best option but I wasn't > able to figure out the locking hierarchy of this code > > So I've coped out and just copied the appropriate inlines here. > > I also nuked some stray ia64 support and fixed a coment in the arm32 version > while I was here. > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> > tools/memshr/bidir-hash.c | 48 +++++++++++++++++++++++++++++++++----------- > 1 files changed, 36 insertions(+), 12 deletions(-) > > diff --git a/tools/memshr/bidir-hash.c b/tools/memshr/bidir-hash.c > index 45d473e..bed8179 100644 > --- a/tools/memshr/bidir-hash.c > +++ b/tools/memshr/bidir-hash.c > @@ -100,22 +100,13 @@ int __hash_iterator(struct __hash *h, > void *d); > static void hash_resize(struct __hash *h); > > -#if defined(__ia64__) > -#define ia64_fetchadd4_rel(p, inc) do { \ > - uint64_t ia64_intri_res; \ > - asm volatile ("fetchadd4.rel %0=[%1],%2" \ > - : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \ > - : "memory"); \ > -} while (0) > -static inline void atomic_inc(uint32_t *v) { ia64_fetchadd4_rel(v, 1); } > -static inline void atomic_dec(uint32_t *v) { ia64_fetchadd4_rel(v, -1); } > -#elif defined(__arm__) > +#if defined(__arm__) > static inline void atomic_inc(uint32_t *v) > { > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_add\n" > + __asm__ __volatile__("@ atomic_inc\n" > "1: ldrex %0, [%3]\n" > " add %0, %0, #1\n" > " strex %1, %0, [%3]\n" > @@ -130,7 +121,7 @@ static inline void atomic_dec(uint32_t *v) > unsigned long tmp; > int result; > > - __asm__ __volatile__("@ atomic_sub\n" > + __asm__ __volatile__("@ atomic_dec\n" > "1: ldrex %0, [%3]\n" > " sub %0, %0, #1\n" > " strex %1, %0, [%3]\n" > @@ -140,6 +131,39 @@ static inline void atomic_dec(uint32_t *v) > : "r" (v) > : "cc"); > } > + > +#elif defined(__aarch64__) > + > +static inline void atomic_inc(uint32_t *v) > +{ > + unsigned long tmp; > + int result; > + > + asm volatile("// atomic_inc\n" > +"1: ldxr %w0, [%3]\n" > +" add %w0, %w0, #1\n" > +" stxr %w1, %w0, [%3]\n" > +" cbnz %w1, 1b" > + : "=&r" (result), "=&r" (tmp), "+o" (v) > + : "r" (v) > + : "cc"); > +} > + > +static inline void atomic_dec(uint32_t *v) > +{ > + unsigned long tmp; > + int result; > + > + asm volatile("// atomic_dec\n" > +"1: ldxr %w0, [%3]\n" > +" sub %w0, %w0, #1\n" > +" stxr %w1, %w0, [%3]\n" > +" cbnz %w1, 1b" > + : "=&r" (result), "=&r" (tmp), "+o" (v) > + : "r" (v) > + : "cc"); > +} > + > #else /* __x86__ */ > static inline void atomic_inc(uint32_t *v) > { > -- > 1.7.2.5 > ^ permalink raw reply [flat|nested] 5+ messages in thread
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[not found] <mailman.26350.1363354644.1399.xen-devel@lists.xen.org>
2013-03-15 14:30 ` [PATCH 6/9] tools: memshr: arm64 support Andres Lagar-Cavilla
2013-03-15 14:35 ` Ian Campbell
2013-03-15 13:15 [PATCH 00/09] arm: tools: build for arm64 and enable cross-compiling for both arm32 and arm64 Ian Campbell
2013-03-15 13:15 ` [PATCH 6/9] tools: memshr: arm64 support Ian Campbell
2013-03-15 15:29 ` Ian Jackson
2013-03-19 15:52 ` Stefano Stabellini
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