[PATCH 01/13] Clean up formatting in Documentation/booting-without-of.txt.

[PATCH 01/13] Clean up formatting in Documentation/booting-without-of.txt.

[Scott Wood]

1. Clean up whitespace issues (the indentation level of SOC device bindings
was moving around as one goes through the list).

2. Number QE devices with numbers rather than roman numerals; it's rather
confusing to have two "i)"s right next to each other, especially without
additional indentation.

3. Label flash chip nodes as "j)" (the next one in sequence), not "g)"
(which is used by Freescale SOC SEC Security Engines).

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |   80 +++++++++++++-------------
 1 files changed, 39 insertions(+), 41 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index d4bfae7..aaea829 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1134,20 +1134,20 @@ descriptions for the SOC devices for which new nodes have been
 defined; this list will expand as more and more SOC-containing
 platforms are moved over to use the flattened-device-tree model.
 
-  a) MDIO IO device
+   a) MDIO IO device
 
-  The MDIO is a bus to which the PHY devices are connected.  For each
-  device that exists on this bus, a child node should be created.  See
-  the definition of the PHY node below for an example of how to define
-  a PHY.
+   The MDIO is a bus to which the PHY devices are connected.  For each
+   device that exists on this bus, a child node should be created.  See
+   the definition of the PHY node below for an example of how to define
+   a PHY.
 
-  Required properties:
+   Required properties:
     - reg : Offset and length of the register set for the device
     - device_type : Should be "mdio"
     - compatible : Should define the compatible device type for the
       mdio.  Currently, this is most likely to be "gianfar"
 
-  Example:
+   Example:
 
 	mdio@24520 {
 		reg = <24520 20>;
@@ -1160,9 +1160,9 @@ platforms are moved over to use the flattened-device-tree model.
 	};
 
 
-  b) Gianfar-compatible ethernet nodes
+   b) Gianfar-compatible ethernet nodes
 
-  Required properties:
+   Required properties:
 
     - device_type : Should be "network"
     - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
@@ -1180,14 +1180,14 @@ platforms are moved over to use the flattened-device-tree model.
     - phy-handle : The phandle for the PHY connected to this ethernet
       controller.
 
-  Recommended properties:
+   Recommended properties:
 
     - linux,network-index : This is the intended "index" of this
       network device.  This is used by the bootwrapper to interpret
       MAC addresses passed by the firmware when no information other
       than indices is available to associate an address with a device.
 
-  Example:
+   Example:
 
 	ethernet@24000 {
 		#size-cells = <0>;
@@ -1202,7 +1202,6 @@ platforms are moved over to use the flattened-device-tree model.
 	};
 
 
-
    c) PHY nodes
 
    Required properties:
@@ -1219,7 +1218,6 @@ platforms are moved over to use the flattened-device-tree model.
     - linux,phandle :  phandle for this node; likely referenced by an
       ethernet controller node.
 
-
    Example:
 
 	ethernet-phy@0 {
@@ -1447,7 +1445,7 @@ platforms are moved over to use the flattened-device-tree model.
    The description below applies to the the qe of MPC8360 and
    more nodes and properties would be extended in the future.
 
-   i) Root QE device
+   1) Root QE device
 
    Required properties:
    - device_type : should be "qe";
@@ -1473,7 +1471,7 @@ platforms are moved over to use the flattened-device-tree model.
 	}
 
 
-   ii) SPI (Serial Peripheral Interface)
+   2) SPI (Serial Peripheral Interface)
 
    Required properties:
    - device_type : should be "spi".
@@ -1499,7 +1497,7 @@ platforms are moved over to use the flattened-device-tree model.
 	};
 
 
-   iii) USB (Universal Serial Bus Controller)
+   3) USB (Universal Serial Bus Controller)
 
    Required properties:
    - device_type : should be "usb".
@@ -1525,7 +1523,7 @@ platforms are moved over to use the flattened-device-tree model.
 	};
 
 
-   iv) UCC (Unified Communications Controllers)
+   4) UCC (Unified Communications Controllers)
 
    Required properties:
    - device_type : should be "network", "hldc", "uart", "transparent"
@@ -1582,7 +1580,7 @@ platforms are moved over to use the flattened-device-tree model.
 	};
 
 
-   v) Parallel I/O Ports
+   5) Parallel I/O Ports
 
    This node configures Parallel I/O ports for CPUs with QE support.
    The node should reside in the "soc" node of the tree.  For each
@@ -1607,7 +1605,7 @@ platforms are moved over to use the flattened-device-tree model.
 		};
 
 
-   vi) Pin configuration nodes
+   6) Pin configuration nodes
 
    Required properties:
    - linux,phandle : phandle of this node; likely referenced by a QE
@@ -1666,7 +1664,7 @@ platforms are moved over to use the flattened-device-tree model.
 			2  8  2  0  1  0>;	/* GTX125 - CLK9 */
 	};
 
-   vii) Multi-User RAM (MURAM)
+   7) Multi-User RAM (MURAM)
 
    Required properties:
    - device_type : should be "muram".
@@ -1687,32 +1685,32 @@ platforms are moved over to use the flattened-device-tree model.
 		};
 	};
 
-    g) Flash chip nodes
+   j) Flash chip nodes
 
-    Flash chips (Memory Technology Devices) are often used for solid state
-    file systems on embedded devices.
+   Flash chips (Memory Technology Devices) are often used for solid state
+   file systems on embedded devices.
 
-    Required properties:
+   Required properties:
 
-     - device_type : has to be "rom"
-     - compatible : Should specify what this flash device is compatible with.
-       Currently, this is most likely to be "direct-mapped" (which
-       corresponds to the MTD physmap mapping driver).
-     - reg : Offset and length of the register set (or memory mapping) for
-       the device.
-     - bank-width : Width of the flash data bus in bytes. Required
-       for the NOR flashes (compatible == "direct-mapped" and others) ONLY.
+    - device_type : has to be "rom"
+    - compatible : Should specify what this flash device is compatible with.
+      Currently, this is most likely to be "direct-mapped" (which
+      corresponds to the MTD physmap mapping driver).
+    - reg : Offset and length of the register set (or memory mapping) for
+      the device.
+    - bank-width : Width of the flash data bus in bytes. Required
+      for the NOR flashes (compatible == "direct-mapped" and others) ONLY.
 
-    Recommended properties :
+   Recommended properties :
 
-     - partitions : Several pairs of 32-bit values where the first value is
-       partition's offset from the start of the device and the second one is
-       partition size in bytes with LSB used to signify a read only
-       partition (so, the partition size should always be an even number).
-     - partition-names : The list of concatenated zero terminated strings
-       representing the partition names.
-     - probe-type : The type of probe which should be done for the chip
-       (JEDEC vs CFI actually). Valid ONLY for NOR flashes.
+    - partitions : Several pairs of 32-bit values where the first value is
+      partition's offset from the start of the device and the second one is
+      partition size in bytes with LSB used to signify a read only
+      partition (so, the partition size should always be an even number).
+    - partition-names : The list of concatenated zero terminated strings
+      representing the partition names.
+    - probe-type : The type of probe which should be done for the chip
+      (JEDEC vs CFI actually). Valid ONLY for NOR flashes.
 
    Example:
 
-- 
1.5.0.3

[PATCH 02/13] Document devtree binding for power management controllers.

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index aaea829..fc54511 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1725,6 +1725,19 @@ platforms are moved over to use the flattened-device-tree model.
  		partition-names = "fs\0firmware";
  	};
 
+   k) Power Management Controllers
+
+   Required Properties:
+
+   - compatible : mpc83xx chips should use "fsl,mpc83xx-pmc".  831x chips
+     with additional PMC functionality also list "fsl,mpc831x-pmc".
+   - reg : For fsl,mpc83xx-pmc devices, resource 0 is the PMC reg block,
+     and resource 1 is the Clock Configuration reg block.
+
+   Optional Properties:
+
+   - interrupts : On fsl,mpc83xx-pmc, this is the PMC interrupt.
+
    More devices will be defined as this spec matures.
 
 VII - Specifying interrupt information for devices
-- 
1.5.0.3

[PATCH 03/13] Document the sleep property.

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index fc54511..966c26b 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1738,6 +1738,16 @@ platforms are moved over to use the flattened-device-tree model.
 
    - interrupts : On fsl,mpc83xx-pmc, this is the PMC interrupt.
 
+   l) Device Power Management
+
+   To associate a device with the corresponding bits in a power or
+   clock disable register, a device can contain a "sleep" property.
+
+   The first cell of a sleep node is a phandle to the sleep controller.
+   The remaining cells are interpreted by said controller.  In the case
+   of an fsl,mpc83xx-pmc sleep controller, the second cell represents the
+   bits to clear in SCCR to stop the device's clock.
+
    More devices will be defined as this spec matures.
 
 VII - Specifying interrupt information for devices
-- 
1.5.0.3

[PATCH 04/13] Document the devtree binding for general purpose timers.

[Scott Wood]

The GTM module on the 83xx will be used as a wakeup source for
suspend-to-ram.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 966c26b..0efd8a0 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1750,6 +1750,13 @@ platforms are moved over to use the flattened-device-tree model.
 
    More devices will be defined as this spec matures.
 
+   m) General Purpose Timers
+
+   - compatible : For the GTM module on mpc83xx chips,
+     use "fsl,mpc83xx-gtm".
+   - reg : For fsl,mpc83xx-gtm, resource 0 is the GTM block.
+   - interrupts : This is the timer's interrupt.
+
 VII - Specifying interrupt information for devices
 ===================================================
 
-- 
1.5.0.3

[PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 Documentation/powerpc/booting-without-of.txt |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 0efd8a0..1cd29e1 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1187,6 +1187,10 @@ platforms are moved over to use the flattened-device-tree model.
       MAC addresses passed by the firmware when no information other
       than indices is available to associate an address with a device.
 
+   Optional properties:
+    - fsl,magic-packet : Indicates that this device supports wake
+      on Magic Packet.
+
    Example:
 
 	ethernet@24000 {
-- 
1.5.0.3

[PATCH 06/13] Make swsusp_32.S usable for suspend-to-RAM.

[Scott Wood]

This allows platform suspend code to re-use the generic state saving
code, passing a pointer to the low-level suspend code.

The resume path is modified so that non-hibernate callers skip
hibernate-specific bits, and so that callers can specify that the MMU is
off (and thus BATs should be restored).

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/Kconfig            |   10 +++++++
 arch/powerpc/kernel/Makefile    |    2 +-
 arch/powerpc/kernel/swsusp_32.S |   57 ++++++++++++++++++++++----------------
 3 files changed, 44 insertions(+), 25 deletions(-)

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 49b1ea2..e51781e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -131,6 +131,16 @@ config PPC64_SWSUSP
 	depends on PPC64 && (BROKEN || (PPC_PMAC64 && EXPERIMENTAL))
 	default y
 
+config PPC_SUSPEND
+	bool
+	default n
+
+config PPC_SOFTWARE_SUSPEND
+	bool
+	depends on SOFTWARE_SUSPEND
+	select PPC_SUSPEND
+	default y
+
 menu "Processor support"
 choice
 	prompt "Processor Type"
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 4dc73b8..13cc430 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -37,8 +37,8 @@ obj-$(CONFIG_CRASH_DUMP)	+= crash_dump.o
 obj-$(CONFIG_6xx)		+= idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
 obj-$(CONFIG_TAU)		+= tau_6xx.o
 obj-$(CONFIG_SOFTWARE_SUSPEND)	+= swsusp.o
-obj32-$(CONFIG_SOFTWARE_SUSPEND) += swsusp_32.o
 obj64-$(CONFIG_SOFTWARE_SUSPEND) += swsusp_64.o swsusp_asm64.o
+obj32-$(CONFIG_PPC_SUSPEND)	+= swsusp_32.o
 obj32-$(CONFIG_MODULES)		+= module_32.o
 
 ifeq ($(CONFIG_PPC_MERGE),y)
diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index 69e8f86..bc6dbc8 100644
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -40,8 +40,13 @@ _GLOBAL(swsusp_save_area)
 	.section .text
 	.align	5
 
+#ifdef CONFIG_SOFTWARE_SUSPEND
 _GLOBAL(swsusp_arch_suspend)
+	lis	r3, swsusp_save@h
+	ori	r3, r3, swsusp_save@l
+#endif
 
+_GLOBAL(do_suspend)
 	lis	r11,swsusp_save_area@h
 	ori	r11,r11,swsusp_save_area@l
 
@@ -64,8 +69,8 @@ _GLOBAL(swsusp_arch_suspend)
 	stw	r4,SL_TB(r11)
 	mftb	r5
 	stw	r5,SL_TB+4(r11)
-	mftbu	r3
-	cmpw	r3,r4
+	mftbu	r6
+	cmpw	r6,r4
 	bne	1b
 
 	/* Save SPRGs */
@@ -119,7 +124,8 @@ _GLOBAL(swsusp_arch_suspend)
 	/* Call the low level suspend stuff (we should probably have made
 	 * a stackframe...
 	 */
-	bl	swsusp_save
+	mtctr	r3
+	bctrl
 
 	/* Restore LR from the save area */
 	lis	r11,swsusp_save_area@h
@@ -129,7 +135,7 @@ _GLOBAL(swsusp_arch_suspend)
 
 	blr
 
-
+#ifdef CONFIG_SOFTWARE_SUSPEND
 /* Resume code */
 _GLOBAL(swsusp_arch_resume)
 
@@ -212,6 +218,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	bdnz	1b
 	sync
 
+	li	r3, 0
+#endif
+
+	/* r3 = nonzero if the MMU is completely disabled and
+	 * BATs may be restored, zero otherwise.
+	 */
+_GLOBAL(do_resume)
 	/* Ok, we are now running with the kernel data of the old
 	 * kernel fully restored. We can get to the save area
 	 * easily now. As for the rest of the code, it assumes the
@@ -226,10 +239,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	bl	__restore_cpu_setup
 #endif
 	/* Restore the BATs, and SDR1.  Then we can turn on the MMU.
-	 * This is a bit hairy as we are running out of those BATs,
-	 * but first, our code is probably in the icache, and we are
-	 * writing the same value to the BAT, so that should be fine,
-	 * though a better solution will have to be found long-term
+	 * This can only be done when r3 != 0 (and thus the MMU is
+	 * off).
 	 */
 	lwz	r4,SL_SDR1(r11)
 	mtsdr1	r4
@@ -242,7 +253,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	lwz	r4,SL_SPRG0+12(r11)
 	mtsprg	3,r4
 
-#if 0
+	cmpw	r3, 0
+	beq	1f
+
 	lwz	r4,SL_DBAT0(r11)
 	mtdbatu	0,r4
 	lwz	r4,SL_DBAT0+4(r11)
@@ -275,8 +288,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	mtibatu	3,r4
 	lwz	r4,SL_IBAT3+4(r11)
 	mtibatl	3,r4
-#endif
 
+1:
 BEGIN_FTR_SECTION
 	li	r4,0
 	mtspr	SPRN_DBAT4U,r4
@@ -306,8 +319,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
 
 	/* restore the MSR and turn on the MMU */
 	lwz	r3,SL_MSR(r11)
-	bl	turn_on_mmu
-	tovirt(r11,r11)
+	lis	r4, 1f@h
+	ori	r4, r4, 1f@l
+
+	mtsrr0	r4
+	mtsrr1	r3
+	sync
+	isync
+	rfi
+
+1:	tovirt(r11, r11)
 
 	/* Restore TB */
 	li	r3,0
@@ -334,15 +355,3 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
 
 	li	r3,0
 	blr
-
-/* FIXME:This construct is actually not useful since we don't shut
- * down the instruction MMU, we could just flip back MSR-DR on.
- */
-turn_on_mmu:
-	mflr	r4
-	mtsrr0	r4
-	mtsrr1	r3
-	sync
-	isync
-	rfi
-
-- 
1.5.0.3

[PATCH 07/13] Implement arch disable/enable irq hooks.

[Scott Wood]

These hooks ensure that a decrementer interrupt is not pending when
suspending; otherwise, problems may occur.  For example, with deep sleep
on the 831x, a pending decrementer will cause a system freeze because the
SoC thinks the decrementer interrupt would have woken the system, but the
core must have interrupts disabled due to the setup required for deep
sleep.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/kernel/time.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 7cedef8..46546a3 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -707,6 +707,29 @@ void wakeup_decrementer(void)
 	set_dec(ticks);
 }
 
+/* Overrides the weak version in kernel/power/main.c */
+void arch_suspend_disable_irqs(void)
+{
+	preempt_disable();
+
+	/* Disable the decrementer, so that it doesn't interfere
+	 * with suspending.
+	 */
+
+	set_dec(0x7fffffff);
+	local_irq_disable();
+	set_dec(0x7fffffff);
+}
+
+/* Overrides the weak version in kernel/power/main.c */
+void arch_suspend_enable_irqs(void)
+{
+	wakeup_decrementer();
+
+	local_irq_enable();
+	preempt_enable();
+}
+
 #ifdef CONFIG_SMP
 void __init smp_space_timers(unsigned int max_cpus)
 {
-- 
1.5.0.3

[PATCH 08/13] pm: Handle HID0_SLEEP in the TLF_NAPPING hack.

[Scott Wood]

The e300 core (and probably most other 6xx chips) can only come out of
sleep mode with an interrupt.  However, interrupts are logically disabled
by the power management layer.

This hack extends the existing doze/nap hack to also suppress the running
of the interrupt handler when in sleep mode.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/kernel/idle_6xx.S |   34 +++++++++++++++++++++++++++++++++-
 1 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 01bcd52..f45d634 100644
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -147,6 +147,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	isync
 	b	1b
 
+#ifdef CONFIG_PM
+ret_from_sleep:
+	.long	ret_from_except
+	.long	ret_from_except
+#endif
+
 /*
  * Return from NAP/DOZE mode, restore some CPU specific registers,
  * we are called with DR/IR still off and r2 containing physical
@@ -154,7 +160,33 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  * address).  We have to preserve r10.
  */
 _GLOBAL(power_save_6xx_restore)
-	lwz	r9,_LINK(r11)		/* interrupted in ppc6xx_idle: */
+#ifdef CONFIG_PM
+	mfspr	r9, SPRN_HID0
+	andis.	r9, r9, HID0_SLEEP@h
+	beq+	1f
+
+	/*
+	 * SLEEP mode is invoked through the PM subsystem, which means
+	 * that interrupts should be disabled.  However, the hardware
+	 * requires them to be enabled to wake up.  To prevent the
+	 * interrupt from being visible to Linux, return immediately
+	 * rather than run the interrupt handler.
+	 */
+	lis	r9, ret_from_sleep@h
+	ori	r9, r9, ret_from_sleep@l
+	tophys(r9, r9)
+	mtlr	r9
+
+	/*
+	 * Disable interrupts, so that the interrupt doesn't happen
+	 * again until the PM code sets MSR[EE].
+	 */
+	lwz	r9, _MSR(r11)
+	rlwinm	r9, r9, 0, ~MSR_EE
+	stw	r9, _MSR(r11)
+#endif
+
+1:	lwz	r9,_LINK(r11)		/* interrupted in ppc6xx_idle: */
 	stw	r9,_NIP(r11)		/* make it do a blr */
 
 #ifdef CONFIG_SMP
-- 
1.5.0.3

[PATCH 09/13] fsl_soc: Factor fsl_get_bus_freq() out of the wdt init.

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/sysdev/fsl_soc.c |   44 ++++++++++++++++++++++------------------
 arch/powerpc/sysdev/fsl_soc.h |    1 +
 2 files changed, 25 insertions(+), 20 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 8a123c7..3b99433 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -64,6 +64,27 @@ phys_addr_t get_immrbase(void)
 
 EXPORT_SYMBOL(get_immrbase);
 
+u32 fsl_get_bus_freq(void)
+{
+	struct device_node *soc = of_find_node_by_type(NULL, "soc");
+	const u32 *freq;
+	u32 ret = 0;
+
+	if (!soc)
+		goto err;
+
+	freq = of_get_property(soc, "bus-frequency", NULL);
+	if (!freq)
+		goto err;
+
+	ret = *freq;
+
+err:
+	of_node_put(soc);
+	return ret;
+}
+EXPORT_SYMBOL(fsl_get_bus_freq);
+
 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx)
 
 static u32 brgfreq = -1;
@@ -356,9 +377,9 @@ arch_initcall(fsl_i2c_of_init);
 static int __init mpc83xx_wdt_init(void)
 {
 	struct resource r;
-	struct device_node *soc, *np;
+	struct device_node *np;
 	struct platform_device *dev;
-	const unsigned int *freq;
+	u32 freq = fsl_get_bus_freq();
 	int ret;
 
 	np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
@@ -368,19 +389,6 @@ static int __init mpc83xx_wdt_init(void)
 		goto nodev;
 	}
 
-	soc = of_find_node_by_type(NULL, "soc");
-
-	if (!soc) {
-		ret = -ENODEV;
-		goto nosoc;
-	}
-
-	freq = of_get_property(soc, "bus-frequency", NULL);
-	if (!freq) {
-		ret = -ENODEV;
-		goto err;
-	}
-
 	memset(&r, 0, sizeof(r));
 
 	ret = of_address_to_resource(np, 0, &r);
@@ -393,20 +401,16 @@ static int __init mpc83xx_wdt_init(void)
 		goto err;
 	}
 
-	ret = platform_device_add_data(dev, freq, sizeof(int));
+	ret = platform_device_add_data(dev, &freq, sizeof(int));
 	if (ret)
 		goto unreg;
 
-	of_node_put(soc);
 	of_node_put(np);
-
 	return 0;
 
 unreg:
 	platform_device_unregister(dev);
 err:
-	of_node_put(soc);
-nosoc:
 	of_node_put(np);
 nodev:
 	return ret;
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 04e145b..7a9502d 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -7,6 +7,7 @@
 extern phys_addr_t get_immrbase(void);
 extern u32 get_brgfreq(void);
 extern u32 get_baudrate(void);
+extern u32 fsl_get_bus_freq(void);
 
 #endif
 #endif
-- 
1.5.0.3

[PATCH 10/13] mpc83xx: Power Management support

[Scott Wood]

Basic PM support for 83xx.  Standby is implemented as sleep.
Suspend-to-RAM is implemented as "deep sleep" (with the processor
turned off) on 831x.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/Kconfig                 |    6 +
 arch/powerpc/platforms/83xx/Makefile |    1 +
 arch/powerpc/platforms/83xx/pm.c     |  432 ++++++++++++++++++++++++++++++++++
 arch/powerpc/platforms/83xx/sleep.S  |  320 +++++++++++++++++++++++++
 arch/powerpc/sysdev/fsl_soc.c        |   33 +++
 arch/powerpc/sysdev/fsl_soc.h        |   10 +
 arch/powerpc/sysdev/ipic.c           |   71 ++++++
 include/asm-powerpc/reg.h            |    4 +
 include/linux/fsl_devices.h          |   24 ++
 9 files changed, 901 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/platforms/83xx/pm.c
 create mode 100644 arch/powerpc/platforms/83xx/sleep.S

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index e51781e..b8dc953 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -182,6 +182,12 @@ config PPC_83xx
 	select PPC_FPU
 	select WANT_DEVICE_TREE
 
+config PPC_83xx_PM
+	bool
+	default y
+	depends on PPC_83xx && PM
+	select PPC_SUSPEND
+
 config PPC_85xx
 	bool "Freescale 85xx"
 	select E500
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 31a91b5..65ef61d 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -3,6 +3,7 @@
 #
 obj-y				:= misc.o
 obj-$(CONFIG_PCI)		+= pci.o
+obj-$(CONFIG_PM)		+= pm.o sleep.o
 obj-$(CONFIG_MPC8313_RDB)	+= mpc8313_rdb.o
 obj-$(CONFIG_MPC832x_RDB)	+= mpc832x_rdb.o
 obj-$(CONFIG_MPC834x_MDS)	+= mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/pm.c b/arch/powerpc/platforms/83xx/pm.c
new file mode 100644
index 0000000..eccf263
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/pm.c
@@ -0,0 +1,432 @@
+/*
+ * MPC83xx Power Management support
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/wait.h>
+#include <linux/kthread.h>
+#include <linux/freezer.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/prom.h>
+#include <asm/reg.h>
+#include <asm/io.h>
+#include <asm/time.h>
+#include <asm/of_platform.h>
+
+#include <sysdev/fsl_soc.h>
+
+#define PMCCR1_NEXT_STATE       0x0C /* Next state for power management */
+#define PMCCR1_NEXT_STATE_SHIFT 2
+#define PMCCR1_CURR_STATE       0x03 /* Current state for power management*/
+#define IMMR_RCW_OFFSET         0x900
+#define RCW_PCI_HOST            0x80000000
+
+void mpc83xx_enter_sleep(void);
+void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
+
+struct mpc83xx_pmc {
+	u32 config;
+#define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
+#define PMCCR_SLPEN 1 /* System low power enable */
+
+	u32 event;
+	u32 mask;
+/* All but PMCI are deep-sleep only */
+#define PMCER_GPIO   0x100
+#define PMCER_PCI    0x080
+#define PMCER_USB    0x040
+#define PMCER_ETSEC1 0x020
+#define PMCER_ETSEC2 0x010
+#define PMCER_TIMER  0x008
+#define PMCER_INT1   0x004
+#define PMCER_INT2   0x002
+#define PMCER_PMCI   0x001
+#define PMCER_ALL    0x1FF
+
+	/* deep-sleep only */
+	u32 config1;
+#define PMCCR1_USE_STATE  0x80000000
+#define PMCCR1_PME_EN     0x00000080
+#define PMCCR1_ASSERT_PME 0x00000040
+#define PMCCR1_POWER_OFF  0x00000020
+
+	/* deep-sleep only */
+	u32 config2;
+};
+
+struct mpc83xx_rcw {
+	u32 rcwlr;
+	u32 rcwhr;
+};
+
+struct mpc83xx_clock {
+	u32 spmr;
+	u32 occr;
+	u32 sccr;
+};
+
+struct pmc_type {
+	int has_deep_sleep;
+};
+
+static struct of_device *pmc_dev;
+static int has_deep_sleep, deep_sleeping;
+static int pmc_irq;
+static struct mpc83xx_pmc __iomem *pmc_regs;
+static struct mpc83xx_clock __iomem *clock_regs;
+static int is_pci_agent, wake_from_pci;
+static phys_addr_t immrbase;
+static int pci_pm_state;
+static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
+
+static u32 saved_sccr;
+static DEFINE_SPINLOCK(device_sleep_lock);
+
+void fsl_sleep_device(struct fsl_sleep_platform_data *data)
+{
+	if (clock_regs && data->sccr_mask) {
+		unsigned long flags;
+		u32 sccr;
+
+		spin_lock_irqsave(&device_sleep_lock, flags);
+		sccr = in_be32(&clock_regs->sccr);
+
+		saved_sccr &= ~data->sccr_mask;
+		saved_sccr |= sccr & data->sccr_mask;
+
+		out_be32(&clock_regs->sccr, sccr & ~data->sccr_mask);
+		spin_unlock_irqrestore(&device_sleep_lock, flags);
+	}
+}
+EXPORT_SYMBOL(fsl_sleep_device);
+
+void fsl_wake_device(struct fsl_sleep_platform_data *data)
+{
+	if (clock_regs && data->sccr_mask) {
+		unsigned long flags;
+		u32 sccr;
+
+		spin_lock_irqsave(&device_sleep_lock, flags);
+
+		sccr = in_be32(&clock_regs->sccr);
+		sccr |= saved_sccr & data->sccr_mask;
+		out_be32(&clock_regs->sccr, sccr);
+
+		spin_unlock_irqrestore(&device_sleep_lock, flags);
+	}
+}
+EXPORT_SYMBOL(fsl_wake_device);
+
+int fsl_deep_sleep(void)
+{
+	return deep_sleeping;
+}
+
+static int mpc83xx_change_state(void)
+{
+	u32 curr_state;
+	u32 reg_cfg1 = in_be32(&pmc_regs->config1);
+
+	if (is_pci_agent) {
+		pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
+		               PMCCR1_NEXT_STATE_SHIFT;
+		curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
+
+		if (curr_state != pci_pm_state) {
+			reg_cfg1 &= ~PMCCR1_CURR_STATE;
+			reg_cfg1 |= pci_pm_state;
+			out_be32(&pmc_regs->config1, reg_cfg1);
+
+			wake_up(&agent_wq);
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
+{
+	u32 event = in_be32(&pmc_regs->event);
+	int ret = IRQ_NONE;
+
+	if (mpc83xx_change_state())
+		ret = IRQ_HANDLED;
+
+	if (event) {
+		out_be32(&pmc_regs->event, event);
+		ret = IRQ_HANDLED;
+	}
+
+	return ret;
+}
+
+static int mpc83xx_pm_suspend(void)
+{
+	int ret = -EAGAIN;
+
+	/* Don't go to sleep if there's a race where pci_pm_state changes
+	 * between the agent thread checking it and the PM code disabling
+	 * interrupts.
+	 */
+	if (wake_from_pci) {
+		if (pci_pm_state != (deep_sleeping ? 3 : 2))
+			goto out;
+
+		out_be32(&pmc_regs->config1,
+		         in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
+	}
+
+	/* Put the system into low-power mode and the RAM
+	 * into self-refresh mode once the core goes to
+	 * sleep.
+	 */
+
+	out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
+
+	/* If it has deep sleep (i.e. it's an 831x or compatible),
+	 * disable power to the core upon entering sleep mode.  This will
+	 * require going through the boot firmware upon a wakeup event.
+	 */
+
+	if (deep_sleeping) {
+		out_be32(&pmc_regs->mask, PMCER_ALL);
+
+		out_be32(&pmc_regs->config1,
+		         in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
+
+		enable_kernel_fp();
+
+		mpc83xx_enter_deep_sleep(immrbase);
+
+		out_be32(&pmc_regs->config1,
+		         in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
+
+		out_be32(&pmc_regs->mask, PMCER_PMCI);
+
+		deep_sleeping = 0;
+	} else {
+		out_be32(&pmc_regs->mask, PMCER_PMCI);
+
+		mpc83xx_enter_sleep();
+	}
+
+	ret = 0;
+
+out:
+	out_be32(&pmc_regs->config1,
+	         in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
+
+	return ret;
+}
+
+static int mpc83xx_pm_valid(suspend_state_t state)
+{
+	return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
+}
+
+static int mpc83xx_pm_prepare(suspend_state_t state)
+{
+	switch (state) {
+		case PM_SUSPEND_STANDBY:
+			deep_sleeping = 0;
+			return 0;
+
+		case PM_SUSPEND_MEM:
+			if (has_deep_sleep)
+				deep_sleeping = 1;
+
+			return 0;
+
+		default:
+			return -EINVAL;
+	}
+}
+
+static int mpc83xx_pm_enter(suspend_state_t state)
+{
+	switch (state) {
+		case PM_SUSPEND_STANDBY:
+		case PM_SUSPEND_MEM:
+			return mpc83xx_pm_suspend();
+
+		default:
+			return -EINVAL;
+	}
+}
+
+static int agent_thread_fn(void *data)
+{
+	while (1) {
+		wait_event_interruptible(agent_wq, pci_pm_state >= 2);
+		try_to_freeze();
+
+		if (signal_pending(current) || pci_pm_state < 2)
+			continue;
+
+		/* With a preemptible kernel (or SMP), this could race with a
+		 * userspace-driven suspend request.  It's probably best to
+		 * avoid mixing the two with such a configuration (or else fix
+		 * it by adding a mutex to state_store that we can synchronize
+		 * with).
+		 */
+
+		wake_from_pci = 1;
+
+		pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
+		                               PM_SUSPEND_STANDBY);
+
+		wake_from_pci = 0;
+	}
+
+	return 0;
+}
+
+void mpc83xx_set_agent(void)
+{
+	out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
+	out_be32(&pmc_regs->mask, PMCER_PMCI);
+
+	kthread_run(agent_thread_fn, NULL, "PCI power mgt");
+}
+
+static int mpc83xx_is_pci_agent(void)
+{
+	struct mpc83xx_rcw __iomem *rcw_regs;
+	int ret;
+
+	rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
+	                   sizeof(struct mpc83xx_rcw));
+
+	if (!rcw_regs)
+		return -ENOMEM;
+
+	ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
+
+	iounmap(rcw_regs);
+	return ret;
+}
+
+static struct pm_ops mpc83xx_pm_ops = {
+	.pm_disk_mode = 0,
+	.valid = mpc83xx_pm_valid,
+	.prepare = mpc83xx_pm_prepare,
+	.enter = mpc83xx_pm_enter,
+};
+
+static int pmc_probe(struct of_device *ofdev,
+                     const struct of_device_id *match)
+{
+	struct device_node *np = ofdev->node;
+	struct resource res;
+	struct pmc_type *type = match->data;
+	int ret = 0;
+
+	has_deep_sleep = type->has_deep_sleep;
+	immrbase = get_immrbase();
+	pmc_dev = ofdev;
+
+	is_pci_agent = mpc83xx_is_pci_agent();
+	if (is_pci_agent < 0)
+		return is_pci_agent;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		return -ENODEV;
+
+	pmc_irq = irq_of_parse_and_map(np, 0);
+	if (pmc_irq != NO_IRQ) {
+		ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
+		                  "pmc", ofdev);
+
+		if (ret)
+			return -EBUSY;
+	}
+
+	pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
+
+	if (!pmc_regs) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = of_address_to_resource(np, 1, &res);
+	if (ret) {
+		ret = -ENODEV;
+		goto out_pmc;
+	}
+
+	clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
+
+	if (!clock_regs) {
+		ret = -ENOMEM;
+		goto out_pmc;
+	}
+
+	if (is_pci_agent)
+		mpc83xx_set_agent();
+
+	pm_set_ops(&mpc83xx_pm_ops);
+	return 0;
+
+out_pmc:
+	iounmap(pmc_regs);
+out:
+	if (pmc_irq != NO_IRQ)
+		free_irq(pmc_irq, ofdev);
+
+	return ret;
+}
+
+static int pmc_remove(struct of_device *ofdev)
+{
+	return -EPERM;
+};
+
+static struct pmc_type pmc_types[] = {
+	{
+		.has_deep_sleep = 1,
+	},
+	{
+		.has_deep_sleep = 0,
+	}
+};
+
+static struct of_device_id pmc_match[] = {
+	{
+		.compatible = "fsl,mpc831x-pmc",
+		.data = &pmc_types[0],
+	},
+	{
+		.compatible = "fsl,mpc83xx-pmc",
+		.data = &pmc_types[1],
+	},
+	{}
+};
+
+static struct of_platform_driver pmc_driver = {
+	.name = "mpc83xx-pmc",
+	.match_table = pmc_match,
+	.probe = pmc_probe,
+	.remove = pmc_remove
+};
+
+static int pmc_init(void)
+{
+	return of_register_platform_driver(&pmc_driver);
+}
+
+module_init(pmc_init);
diff --git a/arch/powerpc/platforms/83xx/sleep.S b/arch/powerpc/platforms/83xx/sleep.S
new file mode 100644
index 0000000..9fe11f1
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/sleep.S
@@ -0,0 +1,320 @@
+/*
+ * Enter and leave sleep state on MPC83xx
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <asm/page.h>
+#include <asm/ppc_asm.h>
+#include <asm/reg.h>
+#include <asm/thread_info.h>
+#include <asm/asm-offsets.h>
+
+#define SS_MEMSAVE	0x00
+#define SS_HID		0x08 /* 3 HIDs */
+#define SS_IABR		0x14 /* 2 IABRs */
+#define SS_IBCR		0x1c
+#define SS_DABR		0x20 /* 2 DABRs */
+#define SS_DBCR		0x28
+#define SS_SR		0x2c /* 16 sgement registers */
+#define STATE_SAVE_SIZE 0x6c
+
+	.section .data
+	.align	5
+
+mpc83xx_sleep_save_area:
+	.space	STATE_SAVE_SIZE
+immrbase:
+	.long	0
+
+	.section .text
+	.align	5
+
+	/* r3 = physical address of IMMR */
+_GLOBAL(mpc83xx_enter_deep_sleep)
+	/* Re-use the state saving/restoring code in
+	 * arch/powerpc/kernel/swsusp_32.S, but have
+	 * it call us instead of swsusp_save.
+	 */
+
+	lis	r4, immrbase@ha
+	stw	r3, immrbase@l(r4)
+
+	lis	r3, mpc83xx_do_enter_deep_sleep@h
+	ori	r3, r3, mpc83xx_do_enter_deep_sleep@l
+	b	do_suspend
+
+mpc83xx_do_enter_deep_sleep:
+	/* The first 2 words of memory are used to communicate with the
+	 * bootloader, to tell it how to resume.
+	 *
+	 * The first word is the magic number 0xf5153ae5, and the second
+	 * is the pointer to mpc83xx_deep_resume.
+	 *
+	 * The original content of these two words is saved in the state
+	 * save area.
+	 */
+
+	lis	r3, mpc83xx_sleep_save_area@h
+	ori	r3, r3, mpc83xx_sleep_save_area@l
+
+	lis	r4, KERNELBASE@h
+	lwz	r5, 0(r4)
+	lwz	r6, 4(r4)
+
+	stw	r5, SS_MEMSAVE+0(r3)
+	stw	r6, SS_MEMSAVE+4(r3)
+
+	mfspr	r5, SPRN_HID0
+	mfspr	r6, SPRN_HID1
+	mfspr	r7, SPRN_HID2
+
+	stw	r5, SS_HID+0(r3)
+	stw	r6, SS_HID+4(r3)
+	stw	r7, SS_HID+8(r3)
+
+	mfspr	r4, SPRN_IABR
+	mfspr	r5, SPRN_IABR2
+	mfspr	r6, SPRN_IBCR
+	mfspr	r7, SPRN_DABR
+	mfspr	r8, SPRN_DABR2
+	mfspr	r9, SPRN_DBCR
+
+	stw	r4, SS_IABR+0(r3)
+	stw	r5, SS_IABR+4(r3)
+	stw	r6, SS_IBCR(r3)
+	stw	r7, SS_DABR+0(r3)
+	stw	r8, SS_DABR+4(r3)
+	stw	r9, SS_DBCR(r3)
+
+	li	r4, 0
+	addi	r6, r3, SS_SR-4
+1:	mfsrin	r5, r4
+	stwu	r5, 4(r6)
+	addis	r4, r4, 0x1000
+	cmpwi	r4, 0
+	bne	1b
+
+	lis	r6, 0xf515
+	ori	r6, r6, 0x3ae5
+
+	lis	r7, mpc83xx_deep_resume@h
+	ori	r7, r7, mpc83xx_deep_resume@l
+	tophys(r7, r7)
+
+	lis	r5, KERNELBASE@h
+	stw	r6, 0(r5)
+	stw	r7, 4(r5)
+
+	bl	__flush_disable_L1
+
+	/* Disable machine checks and critical exceptions */
+	mfmsr	r4
+	rlwinm	r4, r4, 0, ~MSR_CE
+	rlwinm	r4, r4, 0, ~MSR_ME
+	mtmsr	r4
+	isync
+
+	mfspr	r3, SPRN_HID0
+	ori	r3, r3, HID0_ICE
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	SPRN_HID0, r4
+	mtspr	SPRN_HID0, r3
+	isync
+
+#define TMP_VIRT_IMMR		0xf0000000
+#define DEFAULT_IMMR_VALUE	0xff400000
+#define IMMRBAR_BASE		0x0000
+
+	lis	r4, immrbase@ha
+	lwz	r4, immrbase@l(r4)
+
+	/* Use DBAT0 to address the current IMMR space */
+
+	ori	r4, r4, 0x002a
+	mtspr	SPRN_DBAT0L, r4
+	lis	r8, TMP_VIRT_IMMR@h
+	ori	r4, r8, 0x001e	/* 1 MByte accessable from Kernel Space only */
+	mtspr	SPRN_DBAT0U, r4
+	isync
+
+	/* Use DBAT1 to address the original IMMR space */
+
+	lis	r4, DEFAULT_IMMR_VALUE@h
+	ori	r4, r4, 0x002a
+	mtspr	SPRN_DBAT1L, r4
+	lis	r9, (TMP_VIRT_IMMR + 0x01000000)@h
+	ori	r4, r9, 0x001e	/* 1 MByte accessable from Kernel Space only */
+	mtspr	SPRN_DBAT1U, r4
+	isync
+
+	/* Reset BARs */
+
+	li	r4, 0
+	stw	r4, 0x0024(r8)
+	stw	r4, 0x002c(r8)
+	stw	r4, 0x0034(r8)
+	stw	r4, 0x003c(r8)
+	stw	r4, 0x0064(r8)
+	stw	r4, 0x006c(r8)
+
+	/* The 8313 has problems with wakeup events that are pending
+	 * during the transition to deep sleep state (such as if the PCI
+	 * host sets the state to D3 and then D0 in rapid succession).
+	 * This check shrinks the race window somewhat.
+	 */
+
+	lwz	r3, 0x0b04(r8)
+	andi.	r3, r3, 1
+	bne-	mpc83xx_deep_resume
+
+	/* Move IMMR back to the default location, following the
+	 * procedure specified in the MPC8313 manual.
+	 */
+	lwz	r4, IMMRBAR_BASE(r8)
+	isync
+	lis	r4, DEFAULT_IMMR_VALUE@h
+	stw	r4, IMMRBAR_BASE(r8)
+	lis	r4, KERNELBASE@h
+	lwz	r4, 0(r4)
+	isync
+	lwz	r4, IMMRBAR_BASE(r9)
+	mr	r8, r9
+	isync
+
+	/* Check the Reset Configuration Word to see whether flash needs
+	 * to be mapped at a low address or a high address.
+	 */
+
+	lwz	r4, 0x0904(r8)
+	andis.	r4, r4, 0x0400
+	li	r4, 0
+	beq	boot_low
+	lis	r4, 0xff80
+boot_low:
+	stw	r4, 0x0020(r8)
+	lis	r7, 0x8000
+	ori	r7, r7, 0x0016
+
+	mfspr	r5, SPRN_HID0
+	rlwinm	r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
+	oris	r5, r5, HID0_SLEEP@h
+	mtspr	SPRN_HID0, r5
+	isync
+
+	mfmsr	r5
+	oris	r5, r5, MSR_POW@h
+
+	/* Enable the flash mapping at the appropriate address.  This
+	 * mapping will override the RAM mapping, so there's no need to
+	 * disable the latter.  This must be done inside the same cache
+	 * line as setting MSR_POW, so that no instruction fetches from
+	 * RAM happen after the flash mapping is turned on.
+	 */
+
+	.align	5
+	stw	r7, 0x0024(r8)
+	sync
+	isync
+	mtmsr	r5
+	isync
+1:	b	1b
+
+mpc83xx_deep_resume:
+	lis	r4, 1f@h
+	ori	r4, r4, 1f@l
+	tophys(r4, r4)
+	mtsrr0	r4
+
+	mfmsr	r4
+	rlwinm	r4, r4, 0, ~(MSR_IR | MSR_DR)
+	mtsrr1	r4
+
+	rfi
+1:	bl	__inval_enable_L1
+
+	lis	r3, mpc83xx_sleep_save_area@h
+	ori	r3, r3, mpc83xx_sleep_save_area@l
+	tophys(r3, r3)
+
+	lwz	r5, SS_MEMSAVE+0(r3)
+	lwz	r6, SS_MEMSAVE+4(r3)
+
+	stw	r5, 0(0)
+	stw	r6, 4(0)
+
+	lwz	r5, SS_HID+0(r3)
+	lwz	r6, SS_HID+4(r3)
+	lwz	r7, SS_HID+8(r3)
+
+	mtspr	SPRN_HID0, r5
+	mtspr	SPRN_HID1, r6
+	mtspr	SPRN_HID2, r7
+
+	lwz	r4, SS_IABR+0(r3)
+	lwz	r5, SS_IABR+4(r3)
+	lwz	r6, SS_IBCR(r3)
+	lwz	r7, SS_DABR+0(r3)
+	lwz	r8, SS_DABR+4(r3)
+	lwz	r9, SS_DBCR(r3)
+
+	mtspr	SPRN_IABR, r4
+	mtspr	SPRN_IABR2, r5
+	mtspr	SPRN_IBCR, r6
+	mtspr	SPRN_DABR, r7
+	mtspr	SPRN_DABR2, r8
+	mtspr	SPRN_DBCR, r9
+
+	li	r4, 0
+	addi	r6, r3, SS_SR-4
+1:	lwzu	r5, 4(r6)
+	mtsrin	r5, r4
+	addis	r4, r4, 0x1000
+	cmpwi	r4, 0
+	bne	1b
+
+	li	r3, 1		/* BAT restore requested */
+	b	do_resume
+
+_GLOBAL(mpc83xx_enter_sleep)
+	mflr	r4
+
+	mfspr	r5, SPRN_HID0
+	rlwinm	r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
+	oris	r5, r5, HID0_SLEEP@h
+	mtspr	SPRN_HID0, r5
+	isync
+
+	lis	r5, ret_from_sleep@h
+	ori	r5, r5, ret_from_sleep@l
+	mtlr	r5
+
+	rlwinm	r5, r1, 0, 0, 31-THREAD_SHIFT
+	lwz	r6, TI_LOCAL_FLAGS(r5)
+	ori	r6, r6, _TLF_NAPPING
+	stw	r6, TI_LOCAL_FLAGS(r5)
+
+	mfmsr	r5
+	ori	r5, r5, MSR_EE
+	mtmsr	r5
+	oris	r5, r5, MSR_POW@h
+	sync
+	mtmsr	r5
+	isync
+
+1:	b	1b
+
+ret_from_sleep:
+	mfspr	r5, SPRN_HID0
+	rlwinm	r5, r5, 0, ~HID0_SLEEP
+	mtspr	SPRN_HID0, r5
+
+	mtlr	r4
+	blr
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 3b99433..1fd9f51 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -138,6 +138,33 @@ u32 get_baudrate(void)
 EXPORT_SYMBOL(get_baudrate);
 #endif /* CONFIG_CPM2 */
 
+int fsl_sleep_init(struct fsl_sleep_platform_data *sleep,
+                   struct device_node *node)
+{
+	int proplen, ret = -ENODEV;
+	const u32 *sleepdata = of_get_property(node, "sleep", &proplen);
+	struct device_node *sleep_controller;
+
+	if (!sleepdata || proplen != 8)
+		return -ENODEV;
+
+	sleep_controller = of_find_node_by_phandle(sleepdata[0]);
+	if (!sleep_controller)
+		return -ENODEV;
+
+	/* There can only be one fsl,mpc83xx-pmc device in the system;
+	 * it is assumed that it is the one that the pmc driver matches.
+	 */
+	if (of_device_is_compatible(sleep_controller, "fsl,mpc83xx-pmc")) {
+		sleep->sccr_mask = sleepdata[1];
+		ret = 0;
+	}
+
+	of_node_put(sleep_controller);
+	return ret;
+}
+EXPORT_SYMBOL(fsl_sleep_init);
+
 static int __init gfar_mdio_of_init(void)
 {
 	struct device_node *np;
@@ -299,6 +326,8 @@ static int __init gfar_of_init(void)
 		of_node_put(phy);
 		of_node_put(mdio);
 
+		fsl_sleep_init(&gfar_data.sleep, np);
+
 		ret =
 		    platform_device_add_data(gfar_dev, &gfar_data,
 					     sizeof(struct
@@ -482,6 +511,8 @@ static int __init fsl_usb_of_init(void)
 		prop = of_get_property(np, "phy_type", NULL);
 		usb_data.phy_mode = determine_usb_phy(prop);
 
+		fsl_sleep_init(&usb_data.sleep, np);
+
 		ret =
 		    platform_device_add_data(usb_dev_mph, &usb_data,
 					     sizeof(struct
@@ -546,6 +577,8 @@ static int __init fsl_usb_of_init(void)
 		prop = of_get_property(np, "phy_type", NULL);
 		usb_data.phy_mode = determine_usb_phy(prop);
 
+		fsl_sleep_init(&usb_data.sleep, np);
+
 		if (usb_dev_dr_host) {
 			usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
 			usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 7a9502d..62a7ce6 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -9,5 +9,15 @@ extern u32 get_brgfreq(void);
 extern u32 get_baudrate(void);
 extern u32 fsl_get_bus_freq(void);
 
+struct fsl_sleep_platform_data;
+struct device_node;
+
+int fsl_sleep_init(struct fsl_sleep_platform_data *sleep,
+                   struct device_node *node);
+
+/* Calls to fsl_sleep_dev and fsl_wake_dev cannot be nested. */
+void fsl_sleep_dev(struct fsl_sleep_platform_data *sleep);
+void fsl_wake_dev(struct fsl_sleep_platform_data *sleep);
+
 #endif
 #endif
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 473c415..8ad84c5 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -22,6 +22,7 @@
 #include <linux/device.h>
 #include <linux/bootmem.h>
 #include <linux/spinlock.h>
+#include <linux/fsl_devices.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/prom.h>
@@ -727,8 +728,78 @@ unsigned int ipic_get_irq(void)
 	return irq_linear_revmap(primary_ipic->irqhost, irq);
 }
 
+#ifdef CONFIG_PM
+static struct {
+	u32 sicfr;
+	u32 siprr[2];
+	u32 simsr[2];
+	u32 sicnr;
+	u32 smprr[2];
+	u32 semsr;
+	u32 secnr;
+	u32 sermr;
+	u32 sercr;
+} ipic_saved_state;
+
+static int ipic_suspend(struct sys_device *sdev, pm_message_t state)
+{
+	struct ipic *ipic = primary_ipic;
+
+	ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
+	ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
+	ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
+	ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
+	ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
+	ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
+	ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
+	ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
+	ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
+	ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
+	ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
+	ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
+
+	if (fsl_deep_sleep()) {
+		/* In deep sleep, make sure there can be no
+		 * pending interrupts, as this can cause
+		 * problems on 831x.
+		 */
+		ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
+		ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
+		ipic_write(ipic->regs, IPIC_SEMSR, 0);
+		ipic_write(ipic->regs, IPIC_SERMR, 0);
+	}
+
+	return 0;
+}
+
+static int ipic_resume(struct sys_device *sdev)
+{
+	struct ipic *ipic = primary_ipic;
+
+	ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
+	ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
+	ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
+	ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
+	ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
+	ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
+	ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
+	ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
+	ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
+	ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
+	ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
+	ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
+
+	return 0;
+}
+#else
+#define ipic_suspend NULL
+#define ipic_resume NULL
+#endif
+
 static struct sysdev_class ipic_sysclass = {
 	set_kset_name("ipic"),
+	.suspend = ipic_suspend,
+	.resume = ipic_resume,
 };
 
 static struct sys_device device_ipic = {
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 749c7f9..5dcfc77 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -153,7 +153,9 @@
 #define   CTRL_RUNLATCH	0x1
 #define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
 #define   DABR_TRANSLATION	(1UL << 2)
+#define SPRN_DABR2	0x13D	/* 83xx */
 #define SPRN_DAR	0x013	/* Data Address Register */
+#define SPRN_DBCR	0x136	/* 83xx Data Breakpoint Control Reg */
 #define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
 #define   DSISR_NOHPTE		0x40000000	/* no translation found */
 #define   DSISR_PROTFAULT	0x08000000	/* protection fault */
@@ -259,6 +261,8 @@
 #define HID1_PS		(1<<16)		/* 750FX PLL selection */
 #define SPRN_HID2	0x3F8		/* Hardware Implementation Register 2 */
 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
+#define SPRN_IABR2	0x3FA		/* 83xx */
+#define SPRN_IBCR	0x135		/* 83xx Insn Breakpoint Control Reg */
 #define SPRN_HID4	0x3F4		/* 970 HID4 */
 #define SPRN_HID5	0x3F6		/* 970 HID5 */
 #define SPRN_HID6	0x3F9	/* BE HID 6 */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 73710d6..9bded66 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -45,10 +45,27 @@
  *
  */
 
+struct fsl_sleep_platform_data {
+	/*
+	 * The bits set in this mask will be cleared in the SCCR
+	 * when put to sleep, and restored on wakeup.
+	 */
+	u32 sccr_mask;
+};
+
+/*
+ * Calls to fsl_sleep_device do not nest -- if you call
+ * sleep twice without an intervening wake, you will not
+ * be able to wake the device again.
+ */
+void fsl_sleep_device(struct fsl_sleep_platform_data *data);
+void fsl_wake_device(struct fsl_sleep_platform_data *data);
+
 struct gianfar_platform_data {
 	/* device specific information */
 	u32	device_flags;
 	/* board specific information */
+	struct fsl_sleep_platform_data sleep;
 	u32	board_flags;
 	u32	bus_id;
 	u32	phy_id;
@@ -103,6 +120,7 @@ struct fsl_usb2_platform_data {
 	enum fsl_usb2_operating_modes	operating_mode;
 	enum fsl_usb2_phy_modes		phy_mode;
 	unsigned int			port_enables;
+	struct fsl_sleep_platform_data sleep;
 };
 
 /* Flags in fsl_usb2_mph_platform_data */
@@ -120,5 +138,11 @@ struct fsl_spi_platform_data {
 	u32	sysclk;
 };
 
+/* Returns non-zero if the current suspend operation would
+ * lead to a deep sleep (i.e. power removed from the core,
+ * instead of just the clock).
+ */
+int fsl_deep_sleep(void);
+
 #endif /* _FSL_DEVICE_H_ */
 #endif /* __KERNEL__ */
-- 
1.5.0.3

[PATCH 11/13] mpc83xx: timer driver for PM wakeup

[Scott Wood]

This is a driver for the mpc83xx's GTM4 timer.  It's functionality
is limited to providing a wakeup source for suspend-to-RAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/platforms/83xx/Kconfig  |   10 +
 arch/powerpc/platforms/83xx/Makefile |    1 +
 arch/powerpc/platforms/83xx/timer.c  |  299 ++++++++++++++++++++++++++++++++++
 3 files changed, 310 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/platforms/83xx/timer.c

diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 19cafdf..3f40dd6 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -75,3 +75,13 @@ config PPC_MPC836x
 	select PPC_UDBG_16550
 	select PPC_INDIRECT_PCI
 	default y if MPC836x_MDS
+
+config MPC83xx_GTM
+	tristate "83xx General-Purpose Timers for PM wakeup"
+	default y if PM
+	help
+	  This enables a driver for the GTM4 timer, to be used
+	  as a wakeup source for suspend-to-RAM.  To arm the
+	  timer, write the number of seconds until expiration
+	  to the "timeout" file in the device's sysfs directory.
+	  To disarm, write 0 to the "timeout" file.
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 65ef61d..bbca0ae 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -4,6 +4,7 @@
 obj-y				:= misc.o
 obj-$(CONFIG_PCI)		+= pci.o
 obj-$(CONFIG_PM)		+= pm.o sleep.o
+obj-$(CONFIG_MPC83xx_GTM)	+= timer.o
 obj-$(CONFIG_MPC8313_RDB)	+= mpc8313_rdb.o
 obj-$(CONFIG_MPC832x_RDB)	+= mpc832x_rdb.o
 obj-$(CONFIG_MPC834x_MDS)	+= mpc834x_mds.o
diff --git a/arch/powerpc/platforms/83xx/timer.c b/arch/powerpc/platforms/83xx/timer.c
new file mode 100644
index 0000000..46c160c
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/timer.c
@@ -0,0 +1,299 @@
+/*
+ * MPC83xx Global Timer4 support
+ *
+ * This driver is currently specific to timer 4 in 16-bit mode,
+ * as that is all that can be used as a wakeup source for deep sleep
+ * on the MPC8313.
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/sysfs.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/of_platform.h>
+
+#include <sysdev/fsl_soc.h>
+
+#define MDR_ICLK_DIV16	0x0004
+
+struct gtm_regs {
+	u8    cfr1; /* Timer1/2 Configuration  */
+	#define CFR1_PCAS 0x80 /* Pair Cascade mode  */
+	#define CFR1_BCM  0x40  /* Backward compatible mode  */
+	#define CFR1_STP2 0x20 /* Stop timer  */
+	#define CFR1_RST2 0x10 /* Reset timer  */
+	#define CFR1_GM2  0x08 /* Gate mode for pin 2  */
+	#define CFR1_GM1  0x04 /* Gate mode for pin 1  */
+	#define CFR1_STP1 0x02 /* Stop timer  */
+	#define CFR1_RST1 0x01 /* Reset timer  */
+	#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
+		CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
+
+	u8    res0[3];
+	u8    cfr2; /* Timer3/4 Configuration  */
+	#define CFR2_PCAS 0x80 /* Pair Cascade mode  */
+	#define CFR2_SCAS 0x40 /* Super Cascade mode  */
+	#define CFR2_STP4 0x20 /* Stop timer  */
+	#define CFR2_RST4 0x10 /* Reset timer  */
+	#define CFR2_GM4  0x08 /* Gate mode for pin 4  */
+	#define CFR2_GM3  0x04 /* Gate mode for pin 3  */
+	#define CFR2_STP3 0x02 /* Stop timer  */
+	#define CFR2_RST3 0x01 /* Reset timer  */
+
+	u8    res1[11];
+	u16   mdr1; /* Timer1 Mode Register  */
+	#define MDR_SPS  0xff00 /* Secondary Prescaler value (256) */
+	#define MDR_CE   0x00c0 /* Capture edge and enable interrupt  */
+	#define MDR_OM   0x0020 /* Output mode  */
+	#define MDR_ORI  0x0010 /* Output reference interrupt enable  */
+	#define MDR_FRR  0x0008 /* Free run/restart  */
+	#define MDR_ICLK 0x0006 /* Input clock source for the timer */
+	#define MDR_GE   0x0001 /* Gate enable  */
+
+	u16   mdr2; /* Timer2 Mode Register  */
+	u16   rfr1; /* Timer1 Reference Register  */
+	u16   rfr2; /* Timer2 Reference Register  */
+	u16   cpr1; /* Timer1 Capture Register  */
+	u16   cpr2; /* Timer2 Capture Register  */
+	u16   cnr1; /* Timer1 Counter Register  */
+	u16   cnr2; /* Timer2 Counter Register  */
+	u16   mdr3; /* Timer3 Mode Register  */
+	u16   mdr4; /* Timer4 Mode Register  */
+	u16   rfr3; /* Timer3 Reference Register  */
+	u16   rfr4; /* Timer4 Reference Register  */
+	u16   cpr3; /* Timer3 Capture Register  */
+	u16   cpr4; /* Timer4 Capture Register  */
+	u16   cnr3; /* Timer3 Counter Register  */
+	u16   cnr4; /* Timer4 Counter Register  */
+	u16   evr1; /* Timer1 Event Register  */
+	u16   evr2; /* Timer2 Event Register  */
+	u16   evr3; /* Timer3 Event Register  */
+	u16   evr4; /* Timer4 Event Register  */
+	#define GTEVR_REF 0x0002 /* Output reference event  */
+	#define GTEVR_CAP 0x0001 /* Counter Capture event   */
+	#define GTEVR_RES ~(EVR_CAP|EVR_REF)
+
+	u16   psr1; /* Timer1 Prescaler Register  */
+	u16   psr2; /* Timer2 Prescaler Register  */
+	u16   psr3; /* Timer3 Prescaler Register  */
+	u16   psr4; /* Timer4 Prescaler Register  */
+	#define GTPSR_PPS  0x00FF /* Primary Prescaler Bits (256). */
+	#define GTPSR_RES  ~(GTPSR_PPS)
+};
+
+struct gtm_priv {
+	struct gtm_regs __iomem *regs;
+	int irq;
+	int ticks_per_sec;
+	spinlock_t lock;
+};
+
+static irqreturn_t fsl_gtm_isr(int irq, void *dev_id)
+{
+	struct gtm_priv *priv = dev_id;
+	unsigned long flags;
+	u16 event;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	event = in_be16(&priv->regs->evr4);
+	out_be16(&priv->regs->evr4, event);
+
+	if (event & GTEVR_REF)
+		out_8(&priv->regs->cfr2, CFR2_STP4);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+	return event ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static ssize_t gtm_timeout_store(struct device *dev,
+                                 struct device_attribute *attr,
+                                 const char *buf, size_t count)
+{
+	struct gtm_priv *priv = dev_get_drvdata(dev);
+	unsigned long interval = simple_strtoul(buf, NULL, 0);
+
+	if (interval > 0xffff) {
+		dev_dbg(dev, "gtm: interval %lu (in ns) too long\n", interval);
+		return -EINVAL;
+	}
+
+	interval *= priv->ticks_per_sec;
+
+	if (interval > 0xffff) {
+		dev_dbg(dev, "gtm: interval %lu (in ticks) too long\n",
+		        interval);
+		return -EINVAL;
+	}
+
+	spin_lock_irq(&priv->lock);
+
+	/* reset timer 4 */
+	out_8(&priv->regs->cfr2, CFR2_STP3 | CFR2_STP4);
+
+	if (interval != 0) {
+		out_8(&priv->regs->cfr2, CFR2_GM4 | CFR2_RST4 | CFR2_STP4);
+		/* clear events */
+		out_be16(&priv->regs->evr4, GTEVR_REF | GTEVR_CAP);
+		/* maximum primary prescale (256) */
+		out_be16(&priv->regs->psr4, GTPSR_PPS);
+		/* clear current counter */
+		out_be16(&priv->regs->cnr4, 0x0);
+		/* set count limit */
+		out_be16(&priv->regs->rfr4, interval);
+		out_be16(&priv->regs->mdr4, MDR_SPS | MDR_ORI | MDR_FRR |
+		                            MDR_ICLK_DIV16);
+		/* start timer */
+		out_8(&priv->regs->cfr2, CFR2_GM4 | CFR2_STP3 | CFR2_RST4);
+	}
+
+	spin_unlock_irq(&priv->lock);
+	return count;
+}
+
+static ssize_t gtm_timeout_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+	struct gtm_priv *priv = dev_get_drvdata(dev);
+	int timeout = 0;
+
+	spin_lock_irq(&priv->lock);
+
+	if (!(in_8(&priv->regs->cfr2) & CFR2_STP4)) {
+		timeout = in_be16(&priv->regs->rfr4) -
+		          in_be16(&priv->regs->cnr4);
+		timeout += priv->ticks_per_sec - 1;
+		timeout /= priv->ticks_per_sec;
+	}
+
+	spin_unlock_irq(&priv->lock);
+	return sprintf(buf, "%u\n", timeout);
+}
+
+static DEVICE_ATTR(timeout, 0660, gtm_timeout_show, gtm_timeout_store);
+
+static int __devinit gtm_probe(struct of_device *dev,
+                               const struct of_device_id *match)
+{
+	struct device_node *np = dev->node;
+	struct resource res;
+	int ret = 0;
+	u32 busfreq = fsl_get_bus_freq();
+	struct gtm_priv *priv;
+
+	if (busfreq == 0) {
+		printk(KERN_ERR "gtm: No bus frequency in device tree.\n");
+		return -ENODEV;
+	}
+
+	priv = kmalloc(sizeof(struct gtm_priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	spin_lock_init(&priv->lock);
+	dev_set_drvdata(&dev->dev, priv);
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		goto out;
+
+	priv->irq = irq_of_parse_and_map(np, 0);
+	if (priv->irq == NO_IRQ) {
+		printk(KERN_ERR "mpc83xx-gtm exists in device tree "
+		                "without an IRQ.\n");
+		ret = -ENODEV;
+		goto out;
+	}
+
+	ret = request_irq(priv->irq, fsl_gtm_isr, 0, "gtm timer", priv);
+	if (ret)
+		goto out;
+
+	priv->regs = ioremap(res.start, sizeof(struct gtm_regs));
+	if (!priv->regs) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	/* Disable the unused clocks to save power. */
+	out_8(&priv->regs->cfr1, CFR1_STP1 | CFR1_STP2);
+	out_8(&priv->regs->cfr2, CFR2_STP3 | CFR2_STP4);
+
+	/*
+	 * Maximum prescaling is used (input clock/16, 256 primary prescaler,
+	 * 256 secondary prescaler) to maximize the timer's range.  With a
+	 * bus clock of 133MHz, this yields a maximum interval of 516
+	 * seconds while retaining subsecond precision.  Since only
+	 * timer 4 is supported for wakeup on the 8313, and timer 4
+	 * is the LSB when chained, we can't use chaining to increase
+	 * the range.
+	 */
+	priv->ticks_per_sec = busfreq / (16*256*256);
+
+	ret = device_create_file(&dev->dev, &dev_attr_timeout);
+	if (ret)
+		goto out;
+
+	return 0;
+
+out:
+	kfree(priv);
+	return ret;
+}
+
+static int __devexit gtm_remove(struct of_device *dev)
+{
+	struct gtm_priv *priv = dev_get_drvdata(&dev->dev);
+
+	device_remove_file(&dev->dev, &dev_attr_timeout);
+	free_irq(priv->irq, priv);
+	iounmap(priv->regs);
+
+	dev_set_drvdata(&dev->dev, NULL);
+	kfree(priv);
+	return 0;
+}
+
+static struct of_device_id gtm_match[] = {
+	{
+		.compatible = "fsl,mpc83xx-gtm",
+	},
+	{},
+};
+
+static struct of_platform_driver gtm_driver = {
+	.name = "mpc83xx-gtm-timer",
+	.match_table = gtm_match,
+	.probe = gtm_probe,
+	.remove = __devexit_p(gtm_remove)
+};
+
+static int __init gtm_init(void)
+{
+	return of_register_platform_driver(&gtm_driver);
+}
+
+static void __exit gtm_exit(void)
+{
+	of_unregister_platform_driver(&gtm_driver);
+}
+
+module_init(gtm_init);
+module_exit(gtm_exit);
-- 
1.5.0.3

[PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Scott Wood]

The magic packet flag indicates that the hardware has this
capability.  The MDIO flag indicates that this device's
registers contain active MDIO registers, and thus this
device should not be put to sleep.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 arch/powerpc/sysdev/fsl_soc.c |    7 +++++++
 include/linux/fsl_devices.h   |    2 ++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 1fd9f51..528c0ca 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -302,6 +302,9 @@ static int __init gfar_of_init(void)
 			    FSL_GIANFAR_DEV_HAS_VLAN |
 			    FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
 
+		if (of_get_property(np, "fsl,magic-packet", NULL))
+			gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
+
 		ph = of_get_property(np, "phy-handle", NULL);
 		phy = of_find_node_by_phandle(*ph);
 
@@ -323,6 +326,10 @@ static int __init gfar_of_init(void)
 		gfar_data.phy_id = *id;
 		gfar_data.bus_id = res.start;
 
+		if (res.start >= gfar_dev->resource[0].start &&
+		    res.start < gfar_dev->resource[0].end)
+			gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MDIO;
+
 		of_node_put(phy);
 		of_node_put(mdio);
 
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 9bded66..e7eac86 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -86,6 +86,8 @@ struct gianfar_mdio_data {
 #define FSL_GIANFAR_DEV_HAS_VLAN		0x00000020
 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH	0x00000040
 #define FSL_GIANFAR_DEV_HAS_PADDING		0x00000080
+#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET	0x00000100
+#define FSL_GIANFAR_DEV_HAS_MDIO		0x00000200
 
 /* Flags in gianfar_platform_data */
 #define FSL_GIANFAR_BRD_HAS_PHY_INTR	0x00000001 /* set or use a timer */
-- 
1.5.0.3

[PATCH 13/13] gianfar: Magic Packet and suspend/resume support.

[Scott Wood]

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 drivers/net/gianfar.c         |  137 ++++++++++++++++++++++++++++++++++++++++-
 drivers/net/gianfar.h         |   13 +++-
 drivers/net/gianfar_ethtool.c |   41 ++++++++++++-
 3 files changed, 185 insertions(+), 6 deletions(-)

diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index b666a0c..4924e8d 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -141,6 +141,7 @@ static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int l
 static void gfar_vlan_rx_register(struct net_device *netdev,
 		                struct vlan_group *grp);
 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
+static void gfar_halt_nodisable(struct net_device *dev);
 void gfar_halt(struct net_device *dev);
 void gfar_start(struct net_device *dev);
 static void gfar_clear_exact_match(struct net_device *dev);
@@ -214,6 +215,7 @@ static int gfar_probe(struct platform_device *pdev)
 
 	spin_lock_init(&priv->txlock);
 	spin_lock_init(&priv->rxlock);
+	spin_lock_init(&priv->bflock);
 
 	platform_set_drvdata(pdev, dev);
 
@@ -397,6 +399,122 @@ static int gfar_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM
+static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct gfar_private *priv = netdev_priv(dev);
+	unsigned long flags;
+	u32 tempval;
+
+	int magic_packet = priv->wol_en &&
+		(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
+
+	netif_device_detach(dev);
+
+	if (netif_running(dev)) {
+		spin_lock_irqsave(&priv->txlock, flags);
+		spin_lock(&priv->rxlock);
+
+		gfar_halt_nodisable(dev);
+
+		/* Disable Tx, and Rx if wake-on-LAN is disabled. */
+		tempval = gfar_read(&priv->regs->maccfg1);
+
+		tempval &= ~MACCFG1_TX_EN;
+
+		if (!magic_packet)
+			tempval &= ~MACCFG1_RX_EN;
+
+		gfar_write(&priv->regs->maccfg1, tempval);
+
+		spin_unlock(&priv->rxlock);
+		spin_unlock_irqrestore(&priv->txlock, flags);
+
+#ifdef CONFIG_GFAR_NAPI
+		netif_poll_disable(dev);
+#endif
+
+		if (magic_packet) {
+			/* Enable interrupt on Magic Packet */
+			gfar_write(&priv->regs->imask, IMASK_MAG);
+
+			/* Enable Magic Packet mode */
+			tempval = gfar_read(&priv->regs->maccfg2);
+			tempval |= MACCFG2_MPEN;
+			gfar_write(&priv->regs->maccfg2, tempval);
+		} else {
+			phy_stop(priv->phydev);
+		}
+	}
+
+	if (!magic_packet || !netif_running(dev)) {
+		/* The device with the MDIO in its register block must
+		 * not be put to sleep if any other network devices
+		 * using the same MDIO are active.  Ideally, some sort
+		 * of reference counting could be done, but for now
+		 * just don't put the MDIO-containing dev to sleep
+		 * at all.
+		 */
+		if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MDIO)) {
+			fsl_sleep_device(&priv->einfo->sleep);
+			priv->suspended = 1;
+		}
+	}
+
+	return 0;
+}
+
+static int gfar_resume(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct gfar_private *priv = netdev_priv(dev);
+	unsigned long flags;
+	u32 tempval;
+	int magic_packet = priv->wol_en &&
+		(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
+
+	if (priv->suspended) {
+		fsl_wake_device(&priv->einfo->sleep);
+		priv->suspended = 0;
+	}
+
+	if (!netif_running(dev)) {
+		netif_device_attach(dev);
+		return 0;
+	}
+
+	if (!magic_packet && priv->phydev)
+		phy_start(priv->phydev);
+
+	/* Disable Magic Packet mode, in case something
+	 * else woke us up.
+	 */
+
+	spin_lock_irqsave(&priv->txlock, flags);
+	spin_lock(&priv->rxlock);
+
+	tempval = gfar_read(&priv->regs->maccfg2);
+	tempval &= ~MACCFG2_MPEN;
+	gfar_write(&priv->regs->maccfg2, tempval);
+
+	gfar_start(dev);
+
+	spin_unlock(&priv->rxlock);
+	spin_unlock_irqrestore(&priv->txlock, flags);
+
+	netif_device_attach(dev);
+
+#ifdef CONFIG_GFAR_NAPI
+	netif_poll_enable(dev);
+#endif
+
+	return 0;
+}
+#else
+#define gfar_suspend NULL
+#define gfar_resume NULL
+#endif
 
 /* Reads the controller's registers to determine what interface
  * connects it to the PHY.
@@ -517,7 +635,7 @@ static void init_registers(struct net_device *dev)
 
 
 /* Halt the receive and transmit queues */
-void gfar_halt(struct net_device *dev)
+static void gfar_halt_nodisable(struct net_device *dev)
 {
 	struct gfar_private *priv = netdev_priv(dev);
 	struct gfar __iomem *regs = priv->regs;
@@ -540,6 +658,14 @@ void gfar_halt(struct net_device *dev)
 			 (IEVENT_GRSC | IEVENT_GTSC)))
 			cpu_relax();
 	}
+}
+
+/* Halt the receive and transmit queues */
+void gfar_halt(struct net_device *dev)
+{
+	struct gfar_private *priv = netdev_priv(dev);
+	struct gfar __iomem *regs = priv->regs;
+	u32 tempval;
 
 	/* Disable Rx and Tx */
 	tempval = gfar_read(&regs->maccfg1);
@@ -1877,7 +2003,12 @@ static irqreturn_t gfar_error(int irq, void *dev_id)
 	u32 events = gfar_read(&priv->regs->ievent);
 
 	/* Clear IEVENT */
-	gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
+	gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
+
+	/* Magic Packet is not an error. */
+	if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
+	    (events & IEVENT_MAG))
+		events &= ~IEVENT_MAG;
 
 	/* Hmm... */
 	if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
@@ -1947,6 +2078,8 @@ static irqreturn_t gfar_error(int irq, void *dev_id)
 static struct platform_driver gfar_driver = {
 	.probe = gfar_probe,
 	.remove = gfar_remove,
+	.suspend = gfar_suspend,
+	.resume = gfar_resume,
 	.driver	= {
 		.name = "fsl-gianfar",
 	},
diff --git a/drivers/net/gianfar.h b/drivers/net/gianfar.h
index 39e9e32..62abb57 100644
--- a/drivers/net/gianfar.h
+++ b/drivers/net/gianfar.h
@@ -157,6 +157,7 @@ extern const char gfar_driver_version[];
 #define MACCFG2_GMII            0x00000200
 #define MACCFG2_HUGEFRAME	0x00000020
 #define MACCFG2_LENGTHCHECK	0x00000010
+#define MACCFG2_MPEN		0x00000008
 
 #define ECNTRL_INIT_SETTINGS	0x00001000
 #define ECNTRL_TBI_MODE         0x00000020
@@ -229,6 +230,7 @@ extern const char gfar_driver_version[];
 #define IEVENT_CRL		0x00020000
 #define IEVENT_XFUN		0x00010000
 #define IEVENT_RXB0		0x00008000
+#define IEVENT_MAG		0x00000800
 #define IEVENT_GRSC		0x00000100
 #define IEVENT_RXF0		0x00000080
 #define IEVENT_FIR		0x00000008
@@ -240,7 +242,8 @@ extern const char gfar_driver_version[];
 #define IEVENT_ERR_MASK         \
 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
  IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
- | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR)
+ | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
+ | IEVENT_MAG)
 
 #define IMASK_INIT_CLEAR	0x00000000
 #define IMASK_BABR              0x80000000
@@ -258,6 +261,7 @@ extern const char gfar_driver_version[];
 #define IMASK_CRL		0x00020000
 #define IMASK_XFUN		0x00010000
 #define IMASK_RXB0              0x00008000
+#define IMASK_MAG		0x00000800
 #define IMASK_GTSC              0x00000100
 #define IMASK_RXFEN0		0x00000080
 #define IMASK_FIR		0x00000008
@@ -718,10 +722,15 @@ struct gfar_private {
 	unsigned int fifo_starve;
 	unsigned int fifo_starve_off;
 
+	/* Bitfield update lock */
+	spinlock_t bflock;
+
 	unsigned char vlan_enable:1,
 		rx_csum_enable:1,
 		extended_hash:1,
-		bd_stash_en:1;
+		bd_stash_en:1,
+		wol_en:1, /* Wake-on-LAN enabled */
+		suspended:1;
 	unsigned short padding;
 
 	unsigned int interruptTransmit;
diff --git a/drivers/net/gianfar_ethtool.c b/drivers/net/gianfar_ethtool.c
index 7b411c1..c7fa24f 100644
--- a/drivers/net/gianfar_ethtool.c
+++ b/drivers/net/gianfar_ethtool.c
@@ -478,14 +478,13 @@ static int gfar_sringparam(struct net_device *dev, struct ethtool_ringparam *rva
 static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
 {
 	struct gfar_private *priv = netdev_priv(dev);
+	unsigned long flags;
 	int err = 0;
 
 	if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM))
 		return -EOPNOTSUPP;
 
 	if (dev->flags & IFF_UP) {
-		unsigned long flags;
-
 		/* Halt TX and RX, and process the frames which
 		 * have already been received */
 		spin_lock_irqsave(&priv->txlock, flags);
@@ -501,7 +500,9 @@ static int gfar_set_rx_csum(struct net_device *dev, uint32_t data)
 		stop_gfar(dev);
 	}
 
+	spin_lock_irqsave(&priv->bflock, flags);
 	priv->rx_csum_enable = data;
+	spin_unlock_irqrestore(&priv->bflock, flags);
 
 	if (dev->flags & IFF_UP)
 		err = startup_gfar(dev);
@@ -563,6 +564,38 @@ static void gfar_set_msglevel(struct net_device *dev, uint32_t data)
 	priv->msg_enable = data;
 }
 
+#ifdef CONFIG_PM
+static void gfar_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+	struct gfar_private *priv = netdev_priv(dev);
+
+	if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) {
+		wol->supported = WAKE_MAGIC;
+		wol->wolopts = priv->wol_en ? WAKE_MAGIC : 0;
+	} else {
+		wol->supported = wol->wolopts = 0;
+	}
+}
+
+static int gfar_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
+{
+	struct gfar_private *priv = netdev_priv(dev);
+	unsigned long flags;
+
+	if (!(priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
+	    wol->wolopts != 0)
+		return -EINVAL;
+
+	if (wol->wolopts & ~WAKE_MAGIC)
+		return -EINVAL;
+
+	spin_lock_irqsave(&priv->bflock, flags);
+	priv->wol_en = wol->wolopts & WAKE_MAGIC ? 1 : 0;
+	spin_unlock_irqrestore(&priv->bflock, flags);
+
+	return 0;
+}
+#endif
 
 const struct ethtool_ops gfar_ethtool_ops = {
 	.get_settings = gfar_gsettings,
@@ -584,4 +617,8 @@ const struct ethtool_ops gfar_ethtool_ops = {
 	.set_tx_csum = gfar_set_tx_csum,
 	.get_msglevel = gfar_get_msglevel,
 	.set_msglevel = gfar_set_msglevel,
+#ifdef CONFIG_PM
+	.get_wol = gfar_get_wol,
+	.set_wol = gfar_set_wol,
+#endif
 };
-- 
1.5.0.3

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Kumar Gala]

On May 7, 2007, at 1:29 PM, Scott Wood wrote:

> The magic packet flag indicates that the hardware has this
> capability.  The MDIO flag indicates that this device's
> registers contain active MDIO registers, and thus this
> device should not be put to sleep.

Can you explain the MDIO part further, do you mean its the tsec that  
has the MDIO registers in its address space or that its actively  
using MDIO for something?

- k

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Scott Wood]

Kumar Gala wrote:
> 
> On May 7, 2007, at 1:29 PM, Scott Wood wrote:
> 
>> The magic packet flag indicates that the hardware has this
>> capability.  The MDIO flag indicates that this device's
>> registers contain active MDIO registers, and thus this
>> device should not be put to sleep.
> 
> 
> Can you explain the MDIO part further, do you mean its the tsec that  
> has the MDIO registers in its address space or that its actively  using 
> MDIO for something?

TSEC1 contains the MDIO registers for both TSEC1 and TSEC2.  Thus, TSEC1 
cannot be put to sleep if TSEC2 is active (plus, the phy timer would 
have to be deactivated).  For now, the simple approach of never sleeping 
TSEC1 is used.

-Scott

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Kumar Gala]

On May 7, 2007, at 2:54 PM, Scott Wood wrote:

> Kumar Gala wrote:
>> On May 7, 2007, at 1:29 PM, Scott Wood wrote:
>>> The magic packet flag indicates that the hardware has this
>>> capability.  The MDIO flag indicates that this device's
>>> registers contain active MDIO registers, and thus this
>>> device should not be put to sleep.
>> Can you explain the MDIO part further, do you mean its the tsec  
>> that  has the MDIO registers in its address space or that its  
>> actively  using MDIO for something?
>
> TSEC1 contains the MDIO registers for both TSEC1 and TSEC2.  Thus,  
> TSEC1 cannot be put to sleep if TSEC2 is active (plus, the phy  
> timer would have to be deactivated).  For now, the simple approach  
> of never sleeping TSEC1 is used.

That's what I guessed was the case, just wasn't clear from the comment.

- k

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Andy Fleming]

On May 7, 2007, at 14:54, Scott Wood wrote:

> Kumar Gala wrote:
>>
>> On May 7, 2007, at 1:29 PM, Scott Wood wrote:
>>
>>> The magic packet flag indicates that the hardware has this
>>> capability.  The MDIO flag indicates that this device's
>>> registers contain active MDIO registers, and thus this
>>> device should not be put to sleep.
>>
>>
>> Can you explain the MDIO part further, do you mean its the tsec that
>> has the MDIO registers in its address space or that its actively   
>> using
>> MDIO for something?
>
> TSEC1 contains the MDIO registers for both TSEC1 and TSEC2.  Thus,  
> TSEC1
> cannot be put to sleep if TSEC2 is active (plus, the phy timer would
> have to be deactivated).  For now, the simple approach of never  
> sleeping
> TSEC1 is used.


The PHY timer is part of the PHY Lib.  The PHY Lib has infrastructure  
to support suspend/resume.  Any thoughts on using that?  More in an  
another email.

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Andy Fleming]

On May 7, 2007, at 13:29, Scott Wood wrote:

> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>  Documentation/powerpc/booting-without-of.txt |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/Documentation/powerpc/booting-without-of.txt b/ 
> Documentation/powerpc/booting-without-of.txt
> index 0efd8a0..1cd29e1 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -1187,6 +1187,10 @@ platforms are moved over to use the  
> flattened-device-tree model.
>        MAC addresses passed by the firmware when no information other
>        than indices is available to associate an address with a  
> device.
>
> +   Optional properties:
> +    - fsl,magic-packet : Indicates that this device supports wake
> +      on Magic Packet.
> +

Isn't this a fairly generic option?  Does it need the "fsl" qualifier?

Andy

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Scott Wood]

Andy Fleming wrote:
> On May 7, 2007, at 13:29, Scott Wood wrote:
>> +   Optional properties:
>> +    - fsl,magic-packet : Indicates that this device supports wake
>> +      on Magic Packet.
>> +
> 
> 
> Isn't this a fairly generic option?  Does it need the "fsl" qualifier?

As I previously wrote internally, it's only needed because some versions 
of the device have it and some don't; what it really means is that 
certain bits in certain registers are valid.  Making it generic would 
imply that all hardware that can do magic packet should have it, which 
isn't true.

-Scott

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Scott Wood]

Andy Fleming wrote:
> On May 7, 2007, at 14:54, Scott Wood wrote:
>> TSEC1 contains the MDIO registers for both TSEC1 and TSEC2.  Thus,  TSEC1
>> cannot be put to sleep if TSEC2 is active (plus, the phy timer would
>> have to be deactivated).  For now, the simple approach of never  sleeping
>> TSEC1 is used.
> 
> The PHY timer is part of the PHY Lib.  The PHY Lib has infrastructure  
> to support suspend/resume.  Any thoughts on using that?  More in an  
> another email.

If the MDIO registers had their own clock disable bit, then sure.  They 
don't.

As for the phy timer issue, it seems that phy_stop() doesn't stop the 
timer, which is probably a bug.

-Scott

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Andy Fleming]

> @@ -323,6 +326,10 @@ static int __init gfar_of_init(void)
>  		gfar_data.phy_id = *id;
>  		gfar_data.bus_id = res.start;
>
> +		if (res.start >= gfar_dev->resource[0].start &&
> +		    res.start < gfar_dev->resource[0].end)
> +			gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MDIO;
> +


Hrm.  I don't think this is a good way to go.  The DEV* flags are all  
features right now, rather than configuration settings.  It seems  
like this is a stop-gap solution for until more robust detection of  
the ability to power down the interface.  I can understand that a  
full solution might be beyond the ambitions of this first set of  
patches, but I'd prefer if we didn't pollute gianfar's device flags  
space with a flag that we should aim at removing eventually.

Andy

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Andy Fleming]

On May 7, 2007, at 16:29, Scott Wood wrote:

> Andy Fleming wrote:
>> On May 7, 2007, at 13:29, Scott Wood wrote:
>>> +   Optional properties:
>>> +    - fsl,magic-packet : Indicates that this device supports wake
>>> +      on Magic Packet.
>>> +
>> Isn't this a fairly generic option?  Does it need the "fsl"  
>> qualifier?
>
> As I previously wrote internally, it's only needed because some  
> versions of the device have it and some don't; what it really means  
> is that certain bits in certain registers are valid.  Making it  
> generic would imply that all hardware that can do magic packet  
> should have it, which isn't true.


Yeah, I just read that.  You should either make that more explicit in  
the documentation, or make it generic.  It's fine if there are  
drivers/devices that don't need to be told or tell anyone that they  
recognize magic packets for them to work.  The lack of the property  
in other controllers won't break anything.

But I'm fine if you just document that the bit indicates,  
specifically, the presence of magic-packet bits in certain registers  
on the eTSEC.

Andy

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Scott Wood]

Andy Fleming wrote:
> Hrm.  I don't think this is a good way to go.  The DEV* flags are all  
> features right now, rather than configuration settings.  It seems  like 
> this is a stop-gap solution for until more robust detection of  the 
> ability to power down the interface.  I can understand that a  full 
> solution might be beyond the ambitions of this first set of  patches, 
> but I'd prefer if we didn't pollute gianfar's device flags  space with a 
> flag that we should aim at removing eventually.

I'd rather "pollute" an existing flags with something that can be 
removed (and the bit reused, if you're concerned about that) later, than 
add a completely new field to accomplish the same thing.

And like the other DEV flags, it's an attribute of the device as it 
exists in the system.

-Scott

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Andy Fleming]

On May 7, 2007, at 16:31, Scott Wood wrote:

> Andy Fleming wrote:
>> On May 7, 2007, at 14:54, Scott Wood wrote:
>>> TSEC1 contains the MDIO registers for both TSEC1 and TSEC2.   
>>> Thus,  TSEC1
>>> cannot be put to sleep if TSEC2 is active (plus, the phy timer would
>>> have to be deactivated).  For now, the simple approach of never   
>>> sleeping
>>> TSEC1 is used.
>> The PHY timer is part of the PHY Lib.  The PHY Lib has  
>> infrastructure  to support suspend/resume.  Any thoughts on using  
>> that?  More in an  another email.
>
> If the MDIO registers had their own clock disable bit, then sure.   
> They don't.

Well, I'm getting into that in my gianfar.c review.  Obviously that  
would be ideal, but we code with the hardware we have.  :)

Mostly this was referring to the comment about phy_timer needing to  
be deactivated.

>
> As for the phy timer issue, it seems that phy_stop() doesn't stop  
> the timer, which is probably a bug.


Nope.  phy_timer is used to manage the state_machine of the PHY.   
phy_stop sets the state to HALTED, which means the PHY doesn't  
register any changes.  But it keeps running so that phy_start can  
bring it back online.  If you want to bring down an interface, you  
want phy_disconnect.  That stops the timer.

Andy

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Andy Fleming]

On May 7, 2007, at 16:53, Scott Wood wrote:

> Andy Fleming wrote:
>> Hrm.  I don't think this is a good way to go.  The DEV* flags are  
>> all  features right now, rather than configuration settings.  It  
>> seems  like this is a stop-gap solution for until more robust  
>> detection of  the ability to power down the interface.  I can  
>> understand that a  full solution might be beyond the ambitions of  
>> this first set of  patches, but I'd prefer if we didn't pollute  
>> gianfar's device flags  space with a flag that we should aim at  
>> removing eventually.
>
> I'd rather "pollute" an existing flags with something that can be  
> removed (and the bit reused, if you're concerned about that) later,  
> than add a completely new field to accomplish the same thing.

Well, I'd rather neither.  :)

>
> And like the other DEV flags, it's an attribute of the device as it  
> exists in the system.

None of those flags are attributes of the system.  They are all flags  
that indicate features of the device, independent of the system.  The  
two board flags are system flags, but they are fully deprecated.   
They only exist in arch/ppc, and the driver never references them.

Andy

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Kumar Gala]

On May 7, 2007, at 4:51 PM, Andy Fleming wrote:

>
> On May 7, 2007, at 16:29, Scott Wood wrote:
>
>> Andy Fleming wrote:
>>> On May 7, 2007, at 13:29, Scott Wood wrote:
>>>> +   Optional properties:
>>>> +    - fsl,magic-packet : Indicates that this device supports wake
>>>> +      on Magic Packet.
>>>> +
>>> Isn't this a fairly generic option?  Does it need the "fsl"
>>> qualifier?
>>
>> As I previously wrote internally, it's only needed because some
>> versions of the device have it and some don't; what it really means
>> is that certain bits in certain registers are valid.  Making it
>> generic would imply that all hardware that can do magic packet
>> should have it, which isn't true.
>
>
> Yeah, I just read that.  You should either make that more explicit in
> the documentation, or make it generic.  It's fine if there are
> drivers/devices that don't need to be told or tell anyone that they
> recognize magic packets for them to work.  The lack of the property
> in other controllers won't break anything.
>
> But I'm fine if you just document that the bit indicates,
> specifically, the presence of magic-packet bits in certain registers
> on the eTSEC.

I'd ask is it really freescale specific?  In that I'd assume its  
support for the standard wake-on-lan packet.

- k

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Kumar Gala]

On May 7, 2007, at 4:45 PM, Andy Fleming wrote:

>
>> @@ -323,6 +326,10 @@ static int __init gfar_of_init(void)
>>  		gfar_data.phy_id = *id;
>>  		gfar_data.bus_id = res.start;
>>
>> +		if (res.start >= gfar_dev->resource[0].start &&
>> +		    res.start < gfar_dev->resource[0].end)
>> +			gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MDIO;
>> +
>
>
> Hrm.  I don't think this is a good way to go.  The DEV* flags are all
> features right now, rather than configuration settings.  It seems
> like this is a stop-gap solution for until more robust detection of
> the ability to power down the interface.  I can understand that a
> full solution might be beyond the ambitions of this first set of
> patches, but I'd prefer if we didn't pollute gianfar's device flags
> space with a flag that we should aim at removing eventually.

I don't follow why this isn't a feature of TSEC1 on the parts and why  
we don't put this into the device tree as a property.

- k

Re: [PATCH 12/13] gianfar: Add flags for magic packet and MDIO.

[Andy Fleming]

On May 7, 2007, at 18:11, Kumar Gala wrote:

>
> On May 7, 2007, at 4:45 PM, Andy Fleming wrote:
>
>>
>>> @@ -323,6 +326,10 @@ static int __init gfar_of_init(void)
>>>  		gfar_data.phy_id = *id;
>>>  		gfar_data.bus_id = res.start;
>>>
>>> +		if (res.start >= gfar_dev->resource[0].start &&
>>> +		    res.start < gfar_dev->resource[0].end)
>>> +			gfar_data.device_flags |= FSL_GIANFAR_DEV_HAS_MDIO;
>>> +
>>
>>
>> Hrm.  I don't think this is a good way to go.  The DEV* flags are all
>> features right now, rather than configuration settings.  It seems
>> like this is a stop-gap solution for until more robust detection of
>> the ability to power down the interface.  I can understand that a
>> full solution might be beyond the ambitions of this first set of
>> patches, but I'd prefer if we didn't pollute gianfar's device flags
>> space with a flag that we should aim at removing eventually.
>
> I don't follow why this isn't a feature of TSEC1 on the parts and  
> why we don't put this into the device tree as a property.


Yeah, I guess.  The dev flags are going away as soon as we yank out  
arch/ppc support for 85xx, but I've been convinced that this is the  
simplest, most straightforward way.

Maybe if it were a device-tree property I would be more comfortable  
with it.  I think I'm just all the work I went through to separate  
them.  :)

Andy

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[David Gibson]

On Mon, May 07, 2007 at 06:06:39PM -0500, Kumar Gala wrote:
> 
> On May 7, 2007, at 4:51 PM, Andy Fleming wrote:
> 
> >
> > On May 7, 2007, at 16:29, Scott Wood wrote:
> >
> >> Andy Fleming wrote:
> >>> On May 7, 2007, at 13:29, Scott Wood wrote:
> >>>> +   Optional properties:
> >>>> +    - fsl,magic-packet : Indicates that this device supports wake
> >>>> +      on Magic Packet.
> >>>> +
> >>> Isn't this a fairly generic option?  Does it need the "fsl"
> >>> qualifier?
> >>
> >> As I previously wrote internally, it's only needed because some
> >> versions of the device have it and some don't; what it really means
> >> is that certain bits in certain registers are valid.  Making it
> >> generic would imply that all hardware that can do magic packet
> >> should have it, which isn't true.
> >
> >
> > Yeah, I just read that.  You should either make that more explicit in
> > the documentation, or make it generic.  It's fine if there are
> > drivers/devices that don't need to be told or tell anyone that they
> > recognize magic packets for them to work.  The lack of the property
> > in other controllers won't break anything.
> >
> > But I'm fine if you just document that the bit indicates,
> > specifically, the presence of magic-packet bits in certain registers
> > on the eTSEC.
> 
> I'd ask is it really freescale specific?  In that I'd assume its  
> support for the standard wake-on-lan packet.

Further, is there already a standard description for WoL capability
described in one of the OF binding documents.  Segher?

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 02/13] Document devtree binding for power management controllers.

[David Gibson]

Yergh.  It would be nice to have a wiki or something for all this
binding information, instead of doing as patches to a monster text
document.

On Mon, May 07, 2007 at 01:29:43PM -0500, Scott Wood wrote:
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>  Documentation/powerpc/booting-without-of.txt |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
> index aaea829..fc54511 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -1725,6 +1725,19 @@ platforms are moved over to use the flattened-device-tree model.
>   		partition-names = "fs\0firmware";
>   	};
>  
> +   k) Power Management Controllers
> +
> +   Required Properties:
> +
> +   - compatible : mpc83xx chips should use "fsl,mpc83xx-pmc".  831x chips
> +     with additional PMC functionality also list "fsl,mpc831x-pmc".
> +   - reg : For fsl,mpc83xx-pmc devices, resource 0 is the PMC reg block,
> +     and resource 1 is the Clock Configuration reg block.
> +
> +   Optional Properties:
> +
> +   - interrupts : On fsl,mpc83xx-pmc, this is the PMC interrupt.
> +
>     More devices will be defined as this spec matures.
>  
>  VII - Specifying interrupt information for devices

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 01/13] Clean up formatting in Documentation/booting-without-of.txt.

[David Gibson]

On Mon, May 07, 2007 at 01:29:07PM -0500, Scott Wood wrote:
> 1. Clean up whitespace issues (the indentation level of SOC device bindings
> was moving around as one goes through the list).
> 
> 2. Number QE devices with numbers rather than roman numerals; it's rather
> confusing to have two "i)"s right next to each other, especially without
> additional indentation.
> 
> 3. Label flash chip nodes as "j)" (the next one in sequence), not "g)"
> (which is used by Freescale SOC SEC Security Engines).
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>

Acked-by: David Gibson <dwg@au1.ibm.com>

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [PATCH 03/13] Document the sleep property.

[Olof Johansson]

On Mon, May 07, 2007 at 01:29:44PM -0500, Scott Wood wrote:
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>  Documentation/powerpc/booting-without-of.txt |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
> index fc54511..966c26b 100644
> --- a/Documentation/powerpc/booting-without-of.txt
> +++ b/Documentation/powerpc/booting-without-of.txt
> @@ -1738,6 +1738,16 @@ platforms are moved over to use the flattened-device-tree model.
>  
>     - interrupts : On fsl,mpc83xx-pmc, this is the PMC interrupt.
>  
> +   l) Device Power Management
> +
> +   To associate a device with the corresponding bits in a power or
> +   clock disable register, a device can contain a "sleep" property.
> +
> +   The first cell of a sleep node is a phandle to the sleep controller.
> +   The remaining cells are interpreted by said controller.  In the case
> +   of an fsl,mpc83xx-pmc sleep controller, the second cell represents the
> +   bits to clear in SCCR to stop the device's clock.

The second part here is completely implementation-dependent. I don't
really see the need to document that in this global document?


-Olof

Re: [PATCH 03/13] Document the sleep property.

[Scott Wood]

Olof Johansson wrote:
> On Mon, May 07, 2007 at 01:29:44PM -0500, Scott Wood wrote:
>>+   The first cell of a sleep node is a phandle to the sleep controller.
>>+   The remaining cells are interpreted by said controller.  In the case
>>+   of an fsl,mpc83xx-pmc sleep controller, the second cell represents the
>>+   bits to clear in SCCR to stop the device's clock.
> 
> The second part here is completely implementation-dependent. I don't
> really see the need to document that in this global document?

In this document, not necessarily (I like David's suggestion of a wiki). 
   It should be documented somewhere, though, so one doesn't have to dig 
through Linux source code to write code for another OS that supports the 
binding.

-Scott

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Scott Wood]

Kumar Gala wrote:
> On May 7, 2007, at 4:51 PM, Andy Fleming wrote:
>> Yeah, I just read that.  You should either make that more explicit in
>> the documentation, or make it generic.  It's fine if there are
>> drivers/devices that don't need to be told or tell anyone that they
>> recognize magic packets for them to work.  The lack of the property
>> in other controllers won't break anything.
>>
>> But I'm fine if you just document that the bit indicates,
>> specifically, the presence of magic-packet bits in certain registers
>> on the eTSEC.
> 
> I'd ask is it really freescale specific?  In that I'd assume its  
> support for the standard wake-on-lan packet.

It is the standard wake-on-lan packet, but the intent of the property is 
not to advertise to the entire system that this device supports it, but 
rather to indicate that the MPEN bit and the like are valid for the 
driver to use.  Making it standard means that someone might use it for 
other purposes, such as pm config tools digging around in 
/proc/device-tree (sure, they could just use ethtool -- but they might 
not), which would mean that all magic-packet-capable devices (gianfar or 
not) would need the property.

If we want to do that, fine -- but that change is at a different scope 
than the one I made.

-Scott

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Segher Boessenkool]

>>>> As I previously wrote internally, it's only needed because some
>>>> versions of the device have it and some don't; what it really means
>>>> is that certain bits in certain registers are valid.

So have the driver detect this based on "compatible"
or "model".

> Further, is there already a standard description for WoL capability
> described in one of the OF binding documents.  Segher?

[Cc: me if you want me to answer, I was reading this
thread with the "d" key, you got lucky].

There is no standard wake-on-lan thing in any binding
as far as I know.  I don't see how it would be useful
anyway, it's all just the device driver's job as far
as I can see.


Segher

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Scott Wood]

On Wed, May 09, 2007 at 04:33:12PM +0200, Segher Boessenkool wrote:
> >>>> As I previously wrote internally, it's only needed because some
> >>>> versions of the device have it and some don't; what it really means
> >>>> is that certain bits in certain registers are valid.
> 
> So have the driver detect this based on "compatible"
> or "model".

Thus requiring the driver to maintain a list of models/compatibles for
every possible combination of features, rather than letting the device
tree specify them individually.  What would be the advantage in that?

-Scott

Re: [PATCH 09/13] fsl_soc: Factor fsl_get_bus_freq() out of the wdt init.

[Kumar Gala]

On Mon, 7 May 2007, Scott Wood wrote:

> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>  arch/powerpc/sysdev/fsl_soc.c |   44 ++++++++++++++++++++++------------------
>  arch/powerpc/sysdev/fsl_soc.h |    1 +
>  2 files changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
> index 8a123c7..3b99433 100644
> --- a/arch/powerpc/sysdev/fsl_soc.c
> +++ b/arch/powerpc/sysdev/fsl_soc.c
> @@ -64,6 +64,27 @@ phys_addr_t get_immrbase(void)
>
>  EXPORT_SYMBOL(get_immrbase);
>
> +u32 fsl_get_bus_freq(void)

Can we call this something more explicit, like fsl_get_sys_freq().
Otherwise this looks fine.

> +{
> +	struct device_node *soc = of_find_node_by_type(NULL, "soc");
> +	const u32 *freq;
> +	u32 ret = 0;
> +
> +	if (!soc)
> +		goto err;
> +
> +	freq = of_get_property(soc, "bus-frequency", NULL);
> +	if (!freq)
> +		goto err;
> +
> +	ret = *freq;
> +
> +err:
> +	of_node_put(soc);
> +	return ret;
> +}
> +EXPORT_SYMBOL(fsl_get_bus_freq);
> +
>  #if defined(CONFIG_CPM2) || defined(CONFIG_8xx)
>
>  static u32 brgfreq = -1;
> @@ -356,9 +377,9 @@ arch_initcall(fsl_i2c_of_init);
>  static int __init mpc83xx_wdt_init(void)
>  {
>  	struct resource r;
> -	struct device_node *soc, *np;
> +	struct device_node *np;
>  	struct platform_device *dev;
> -	const unsigned int *freq;
> +	u32 freq = fsl_get_bus_freq();
>  	int ret;
>
>  	np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
> @@ -368,19 +389,6 @@ static int __init mpc83xx_wdt_init(void)
>  		goto nodev;
>  	}
>
> -	soc = of_find_node_by_type(NULL, "soc");
> -
> -	if (!soc) {
> -		ret = -ENODEV;
> -		goto nosoc;
> -	}
> -
> -	freq = of_get_property(soc, "bus-frequency", NULL);
> -	if (!freq) {
> -		ret = -ENODEV;
> -		goto err;
> -	}
> -
>  	memset(&r, 0, sizeof(r));
>
>  	ret = of_address_to_resource(np, 0, &r);
> @@ -393,20 +401,16 @@ static int __init mpc83xx_wdt_init(void)
>  		goto err;
>  	}
>
> -	ret = platform_device_add_data(dev, freq, sizeof(int));
> +	ret = platform_device_add_data(dev, &freq, sizeof(int));
>  	if (ret)
>  		goto unreg;
>
> -	of_node_put(soc);
>  	of_node_put(np);
> -
>  	return 0;
>
>  unreg:
>  	platform_device_unregister(dev);
>  err:
> -	of_node_put(soc);
> -nosoc:
>  	of_node_put(np);
>  nodev:
>  	return ret;
> diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
> index 04e145b..7a9502d 100644
> --- a/arch/powerpc/sysdev/fsl_soc.h
> +++ b/arch/powerpc/sysdev/fsl_soc.h
> @@ -7,6 +7,7 @@
>  extern phys_addr_t get_immrbase(void);
>  extern u32 get_brgfreq(void);
>  extern u32 get_baudrate(void);
> +extern u32 fsl_get_bus_freq(void);
>
>  #endif
>  #endif
>

Re: [PATCH 05/13] Document the fsl, magic-packet property in gianfar nodes.

[Segher Boessenkool]

>>>>>> As I previously wrote internally, it's only needed because some
>>>>>> versions of the device have it and some don't; what it really 
>>>>>> means
>>>>>> is that certain bits in certain registers are valid.
>>
>> So have the driver detect this based on "compatible"
>> or "model".
>
> Thus requiring the driver to maintain a list of models/compatibles for
> every possible combination of features,

Most likely a very short list.  But you know best
of course.

> rather than letting the device
> tree specify them individually.  What would be the advantage in that?

It's a tradeoff -- describing every single bit of
the hardware in the device tree is a way bigger
maintenance burden, be careful not to go overboard
with it.


Segher

Re: [PATCH 09/13] fsl_soc: Factor fsl_get_bus_freq() out of the wdt init.

[Scott Wood]

Kumar Gala wrote:
> On Mon, 7 May 2007, Scott Wood wrote:
>>+u32 fsl_get_bus_freq(void)
> 
> Can we call this something more explicit, like fsl_get_sys_freq().
> Otherwise this looks fine.

It's bus-frequency in the device tree, not sys-frequency, and the latter 
doesn't seem any more explicit to me...  What about fsl_get_csb_freq()?

-Scott

Re: [PATCH 09/13] fsl_soc: Factor fsl_get_bus_freq() out of the wdt init.

[Kumar Gala]

On May 10, 2007, at 10:49 AM, Scott Wood wrote:

> Kumar Gala wrote:
>> On Mon, 7 May 2007, Scott Wood wrote:
>>> +u32 fsl_get_bus_freq(void)
>> Can we call this something more explicit, like fsl_get_sys_freq().
>> Otherwise this looks fine.
>
> It's bus-frequency in the device tree, not sys-frequency, and the  
> latter doesn't seem any more explicit to me...  What about  
> fsl_get_csb_freq()?

I suggested sys because the 83xx, 85xx, and 86xx all refer to it as  
the system bus. (well they do with regards to setting its frequency).

- k

Re: [PATCH 07/13] Implement arch disable/enable irq hooks.

[Johannes Berg]

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On Mon, 2007-05-07 at 13:29 -0500, Scott Wood wrote:
> These hooks ensure that a decrementer interrupt is not pending when
> suspending; otherwise, problems may occur.  For example, with deep sleep
> on the 831x, a pending decrementer will cause a system freeze because the
> SoC thinks the decrementer interrupt would have woken the system, but the
> core must have interrupts disabled due to the setup required for deep
> sleep.

Interesting to see this first use of these hooks we had to fight for for
so long... Can you put the arch_suspend_{enable,disable}_irqs along with
the actual power management code for 831x?

On the one hand I agree with this patch, this is exactly what we wanted
the hooks for, but on the other hand I would like to have these hooks
free for some more stuff for PMU-based sleep so that I don't need to do
ugly things with platform devices or something for the powermac platform
function stuff.

Then again, if we don't implement these in common code, might we get
link problems when we try building some multiplatform kernel?

johannes

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Re: [PATCH 07/13] Implement arch disable/enable irq hooks.

[Benjamin Herrenschmidt]

On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
> 
> Then again, if we don't implement these in common code, might we get
> link problems when we try building some multiplatform kernel?

That's what ppc_md is for :-)

Ben.

Re: [PATCH 07/13] Implement arch disable/enable irq hooks.

[Johannes Berg]

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On Tue, 2007-05-22 at 17:14 +1000, Benjamin Herrenschmidt wrote:
> On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
> > 
> > Then again, if we don't implement these in common code, might we get
> > link problems when we try building some multiplatform kernel?
> 
> That's what ppc_md is for :-)

So you're saying we should globally implement
arch_suspend_irq_{enable,disable} and then call some ppc_md hook? Sounds
good to me as well, I'd like to ask for a revision of this patch
including that, then I'll update my patches for that.

johannes

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Re: [PATCH 07/13] Implement arch disable/enable irq hooks.

[Benjamin Herrenschmidt]

On Tue, 2007-05-22 at 11:03 +0200, Johannes Berg wrote:
> On Tue, 2007-05-22 at 17:14 +1000, Benjamin Herrenschmidt wrote:
> > On Mon, 2007-05-21 at 17:55 +0200, Johannes Berg wrote:
> > > 
> > > Then again, if we don't implement these in common code, might we get
> > > link problems when we try building some multiplatform kernel?
> > 
> > That's what ppc_md is for :-)
> 
> So you're saying we should globally implement
> arch_suspend_irq_{enable,disable} and then call some ppc_md hook? Sounds
> good to me as well, I'd like to ask for a revision of this patch
> including that, then I'll update my patches for that.

Yup.

Global version calls into the ppc_md hooks and possibly provide a
useable default if no hook is there (Scott's implementation looks like a
reasonably good default).

Ben.

Re: [PATCH 07/13] Implement arch disable/enable irq hooks.

[Johannes Berg]

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On Tue, 2007-05-22 at 19:15 +1000, Benjamin Herrenschmidt wrote:

> Global version calls into the ppc_md hooks and possibly provide a
> useable default if no hook is there (Scott's implementation looks like a
> reasonably good default).

Yes, I agree, for powermac for the pfuncs I'll need to override it but I
doubt Guennadi will for example need to change it for his stuff.

johannes

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Re: [PATCH 10/13] mpc83xx: Power Management support

[Guennadi Liakhovetski]

On Mon, 7 May 2007, Scott Wood wrote:

> diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
> index 3b99433..1fd9f51 100644
> --- a/arch/powerpc/sysdev/fsl_soc.c
> +++ b/arch/powerpc/sysdev/fsl_soc.c
> @@ -138,6 +138,33 @@ u32 get_baudrate(void)
>  EXPORT_SYMBOL(get_baudrate);
>  #endif /* CONFIG_CPM2 */
>  
> +int fsl_sleep_init(struct fsl_sleep_platform_data *sleep,
> +                   struct device_node *node)
> +{
> +	int proplen, ret = -ENODEV;
> +	const u32 *sleepdata = of_get_property(node, "sleep", &proplen);
> +	struct device_node *sleep_controller;
> +
> +	if (!sleepdata || proplen != 8)
> +		return -ENODEV;
> +
> +	sleep_controller = of_find_node_by_phandle(sleepdata[0]);
> +	if (!sleep_controller)
> +		return -ENODEV;
> +
> +	/* There can only be one fsl,mpc83xx-pmc device in the system;
> +	 * it is assumed that it is the one that the pmc driver matches.
> +	 */
> +	if (of_device_is_compatible(sleep_controller, "fsl,mpc83xx-pmc")) {
> +		sleep->sccr_mask = sleepdata[1];
> +		ret = 0;
> +	}

Just wondering - do we really want to special-case 83xx-pmc here? What 
when / if further "sleep controllers" get implemented? Shouldn't this be 
some callback?

BTW, do we have an interface similar to platform-driver/device for of? 
Like of_driver/device. This would be a use case for it. Just register a 
of_driver, which would trigger a dt-scan (just a find_compatible), calling 
driver's probe()... Would it make sense?

Thanks
Guennadi
---
Guennadi Liakhovetski

Re: [PATCH 10/13] mpc83xx: Power Management support

[Scott Wood]

Guennadi Liakhovetski wrote:
>>+	/* There can only be one fsl,mpc83xx-pmc device in the system;
>>+	 * it is assumed that it is the one that the pmc driver matches.
>>+	 */
>>+	if (of_device_is_compatible(sleep_controller, "fsl,mpc83xx-pmc")) {
>>+		sleep->sccr_mask = sleepdata[1];
>>+		ret = 0;
>>+	}
> 
> 
> Just wondering - do we really want to special-case 83xx-pmc here? What 
> when / if further "sleep controllers" get implemented? Shouldn't this be 
> some callback?

The quick and ugly thing would be more if checks.  The ideal solution 
would be a mechanism to look up a device by phandle, returning an ops 
struct corresponding to the requested class (if the device supports it).

> BTW, do we have an interface similar to platform-driver/device for of? 
> Like of_driver/device. This would be a use case for it. Just register a 
> of_driver, which would trigger a dt-scan (just a find_compatible), calling 
> driver's probe()... Would it make sense?

See asm-powerpc/of_platform.h.  However, that won't help find the driver 
  you need to talk to if all you have is a phandle.

-Scott