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From: "Prakhya, Sai Praneeth" <sai.praneeth.prakhya@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Raj, Ashok" <ashok.raj@intel.com>,
	"Pan, Jacob jun" <jacob.jun.pan@intel.com>,
	"Tian, Kevin" <kevin.tian@intel.com>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: RE: [PATCH 1/1] iommu/vt-d: Correctly check format of page table in debugfs
Date: Mon, 22 Jul 2019 05:21:37 +0000	[thread overview]
Message-ID: <FFF73D592F13FD46B8700F0A279B802F4F9354AF@ORSMSX114.amr.corp.intel.com> (raw)
In-Reply-To: <20190720020126.9974-1-baolu.lu@linux.intel.com>

Hi Allen,

> diff --git a/drivers/iommu/intel-iommu-debugfs.c b/drivers/iommu/intel-
> iommu-debugfs.c
> index 73a552914455..e31c3b416351 100644
> --- a/drivers/iommu/intel-iommu-debugfs.c
> +++ b/drivers/iommu/intel-iommu-debugfs.c
> @@ -235,7 +235,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct
> intel_iommu *iommu, u16 bus)
>  		tbl_wlk.ctx_entry = context;
>  		m->private = &tbl_wlk;
> 
> -		if (pasid_supported(iommu) && is_pasid_enabled(context)) {
> +		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) &
> DMA_RTADDR_SMT) {

Thanks for adding this, I do believe this is a good addition but I also think that we might 
need "is_pasid_enabled()" as well. It checks if PASIDE bit in context entry is enabled or not.

I am thinking that even though DMAR might be using scalable root and context table, the entry 
itself should have PASIDE bit set. Did I miss something here?

And I also think a macro would be better so that it could reused elsewhere (if need be).

Regards,
Sai

WARNING: multiple messages have this Message-ID (diff)
From: "Prakhya, Sai Praneeth" <sai.praneeth.prakhya@intel.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
	Joerg Roedel <joro@8bytes.org>,
	David Woodhouse <dwmw2@infradead.org>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
	"Raj, Ashok" <ashok.raj@intel.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"Pan, Jacob jun" <jacob.jun.pan@intel.com>
Subject: RE: [PATCH 1/1] iommu/vt-d: Correctly check format of page table in debugfs
Date: Mon, 22 Jul 2019 05:21:37 +0000	[thread overview]
Message-ID: <FFF73D592F13FD46B8700F0A279B802F4F9354AF@ORSMSX114.amr.corp.intel.com> (raw)
In-Reply-To: <20190720020126.9974-1-baolu.lu@linux.intel.com>

Hi Allen,

> diff --git a/drivers/iommu/intel-iommu-debugfs.c b/drivers/iommu/intel-
> iommu-debugfs.c
> index 73a552914455..e31c3b416351 100644
> --- a/drivers/iommu/intel-iommu-debugfs.c
> +++ b/drivers/iommu/intel-iommu-debugfs.c
> @@ -235,7 +235,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct
> intel_iommu *iommu, u16 bus)
>  		tbl_wlk.ctx_entry = context;
>  		m->private = &tbl_wlk;
> 
> -		if (pasid_supported(iommu) && is_pasid_enabled(context)) {
> +		if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) &
> DMA_RTADDR_SMT) {

Thanks for adding this, I do believe this is a good addition but I also think that we might 
need "is_pasid_enabled()" as well. It checks if PASIDE bit in context entry is enabled or not.

I am thinking that even though DMAR might be using scalable root and context table, the entry 
itself should have PASIDE bit set. Did I miss something here?

And I also think a macro would be better so that it could reused elsewhere (if need be).

Regards,
Sai
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

  reply	other threads:[~2019-07-22  5:21 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-20  2:01 [PATCH 1/1] iommu/vt-d: Correctly check format of page table in debugfs Lu Baolu
2019-07-20  2:01 ` Lu Baolu
2019-07-22  5:21 ` Prakhya, Sai Praneeth [this message]
2019-07-22  5:21   ` Prakhya, Sai Praneeth
2019-07-25  1:40   ` Lu Baolu
2019-07-25  1:40     ` Lu Baolu
2019-07-26 17:17     ` Prakhya, Sai Praneeth
2019-07-26 17:17       ` Prakhya, Sai Praneeth
2019-08-09  5:36 ` Lu Baolu
2019-08-09  5:36   ` Lu Baolu
2019-08-09 15:29 ` Joerg Roedel
2019-08-09 15:29   ` Joerg Roedel

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