From: Wen He <wen.he_1@nxp.com> To: Leo Li <leoyang.li@nxp.com> Cc: Vinod <vkoul@kernel.org>, "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Jiafei Pan <jiafei.pan@nxp.com>, Jiaheng Fan <jiaheng.fan@nxp.com> Subject: [v7,4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Thu, 26 Jul 2018 04:28:36 +0000 [thread overview] Message-ID: <HE1PR0402MB3385D17C161F59D9A5C35A65E22B0@HE1PR0402MB3385.eurprd04.prod.outlook.com> (raw) DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTGkgWWFuZyBbbWFpbHRv Omxlb3lhbmcubGlAbnhwLmNvbV0NCj4gU2VudDogMjAxOOW5tDfmnIgyNuaXpSA1OjE5DQo+IFRv OiBXZW4gSGUgPHdlbi5oZV8xQG54cC5jb20+DQo+IENjOiBWaW5vZCA8dmtvdWxAa2VybmVsLm9y Zz47IGRtYWVuZ2luZUB2Z2VyLmtlcm5lbC5vcmc7IFJvYiBIZXJyaW5nDQo+IDxyb2JoK2R0QGtl cm5lbC5vcmc+OyBvcGVuIGxpc3Q6T1BFTiBGSVJNV0FSRSBBTkQgRkxBVFRFTkVEIERFVklDRQ0K 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WARNING: multiple messages have this Message-ID (diff)
From: Wen He <wen.he_1@nxp.com> To: Leo Li <leoyang.li@nxp.com> Cc: Vinod <vkoul@kernel.org>, "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>, Rob Herring <robh+dt@kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>, Jiafei Pan <jiafei.pan@nxp.com>, Jiaheng Fan <jiaheng.fan@nxp.com> Subject: RE: [v7 4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Thu, 26 Jul 2018 04:28:36 +0000 [thread overview] Message-ID: <HE1PR0402MB3385D17C161F59D9A5C35A65E22B0@HE1PR0402MB3385.eurprd04.prod.outlook.com> (raw) In-Reply-To: <CADRPPNTGODG7h0n8sXv3FQOpL54m6o4rteObR7cnmBymfcRZxg@mail.gmail.com> > -----Original Message----- > From: Li Yang [mailto:leoyang.li@nxp.com] > Sent: 2018年7月26日 5:19 > To: Wen He <wen.he_1@nxp.com> > Cc: Vinod <vkoul@kernel.org>; dmaengine@vger.kernel.org; Rob Herring > <robh+dt@kernel.org>; open list:OPEN FIRMWARE AND FLATTENED DEVICE > TREE BINDINGS <devicetree@vger.kernel.org>; Jiafei Pan > <jiafei.pan@nxp.com>; Jiaheng Fan <jiaheng.fan@nxp.com> > Subject: Re: [v7 4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA > controller bindings > > On Wed, Jul 25, 2018 at 6:29 AM, Wen He <wen.he_1@nxp.com> wrote: > > Document the devicetree bindings for NXP Layerscape qDMA controller > > which could be found on NXP QorIQ Layerscape SoCs. > > > > Signed-off-by: Wen He <wen.he_1@nxp.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > --- > > Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 > ++++++++++++++++++++ > > 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 > > Documentation/devicetree/bindings/dma/fsl-qdma.txt > > > > diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > b/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > new file mode 100644 > > index 0000000..99b3d74 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt > > @@ -0,0 +1,41 @@ > > +NXP Layerscape SoC qDMA Controller > > +================================== > > + > > +This device follows the generic DMA bindings defined in dma/dma.txt. > > + > > +Required properties: > > + > > +- compatible: Must be one of > > + "fsl,ls1021a-qdma": for LS1021A Board > > + "fsl,ls1043a-qdma": for ls1043A Board > > + "fsl,ls1046a-qdma": for ls1046A Board > > Can you align on the case of "ls"? > OK > > +- reg: Should contain the register's base address and > length. > > +- interrupts: Should contain a reference to the interrupt used > by this > > + device. > > +- interrupt-names: Should contain interrupt names: > > + "qdma-error": the error interrupt > > + "qdma-queue": the queue interrupt > > +- fsl,queues: Should contain number of queues supported. > > This property name looks very general. Not sure if making it a little bit more > specific will be better such as "fsl,dma-queues". > Good idea, thank your comments. > > + > > +Optional properties: > > + > > +- dma-channels: Number of DMA channels supported > by the controller. > > +- big-endian: If present registers and hardware scatter/gather > descriptors > > + of the qDMA are implemented in big endian > mode, otherwise in little > > + mode. > > + > > +Examples: > > + > > + qdma: dma-controller@8390000 { > > + compatible = "fsl,ls1021a-qdma"; > > + reg = <0x0 0x8398000 0x0 0x2000 /* Controller > registers */ > > + 0x0 0x839a000 0x0 0x2000>; /* Block registers > */ > > + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 76 > IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "qdma-error", "qdma-queue"; > > + dma-channels = <8>; > > + queues = <2>; > > Not updated after the binding is updated. > What does means? Which one updated after the binding is update? Best Regards, Wen > > + big-endian; > > + }; > > + > > +DMA clients must use the format described in dma/dma.txt file. > > -- > > 1.7.1 > > > > -- > > To unsubscribe from this list: send the line "unsubscribe devicetree" > > in the body of a message to majordomo@vger.kernel.org More majordomo > > info at > > > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fvger > > .kernel.org%2Fmajordomo-info.html&data=02%7C01%7Cwen.he_1%4 > 0nxp.co > > > m%7Cf5c931a910a5410268fc08d5f2743fb2%7C686ea1d3bc2b4c6fa92cd99c > 5c30163 > > > 5%7C0%7C0%7C636681503456939918&sdata=zC57%2Bc9Ji2rjQY0KtNS > d8mlKgpp > > Jg2GqTeclwFy9Xjs%3D&reserved=0
next reply other threads:[~2018-07-26 4:28 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-07-26 4:28 Wen He [this message] 2018-07-26 4:28 ` [v7 4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Wen He -- strict thread matches above, loose matches on Subject: below -- 2018-09-07 19:28 [v7,3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs Li Yang 2018-09-07 19:28 ` [v7 3/7] " Li Yang 2018-08-16 10:42 [v7,3/7] " Vinod Koul 2018-08-16 10:42 ` [v7 3/7] " Vinod 2018-08-16 8:19 [v7,3/7] " Wen He 2018-08-16 8:19 ` [v7 3/7] " Wen He 2018-08-16 4:39 [v7,3/7] " Vinod Koul 2018-08-16 4:39 ` [v7 3/7] " Vinod 2018-08-15 6:46 [v7,3/7] " Wen He 2018-08-15 6:46 ` [v7 3/7] " Wen He 2018-07-26 10:40 [v7,4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Wen He 2018-07-26 10:40 ` [v7 4/7] " Wen He 2018-07-26 7:06 [v7,4/7] " Li Yang 2018-07-26 7:06 ` [v7 4/7] " Leo Li 2018-07-25 21:19 [v7,4/7] " Li Yang 2018-07-25 21:19 ` [v7 4/7] " Li Yang 2018-07-25 11:29 [v7,7/7] arm: dts: ls1021a: add qdma device tree nodes Wen He 2018-07-25 11:29 ` [v7 7/7] " Wen He 2018-07-25 11:29 [v7,6/7] arm64: dts: ls1046a: " Wen He 2018-07-25 11:29 ` [v7 6/7] " Wen He 2018-07-25 11:29 [v7,5/7] arm64: dts: ls1043a: " Wen He 2018-07-25 11:29 ` [v7 5/7] " Wen He 2018-07-25 11:29 [v7,4/7] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Wen He 2018-07-25 11:29 ` [v7 4/7] " Wen He 2018-07-25 11:29 [v7,3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs Wen He 2018-07-25 11:29 ` [v7 3/7] " Wen He 2018-07-25 11:29 [v7,2/7] dmaengine: fsldma: Adding macro FSL_DMA_IN/OUT implement for ARM platform Wen He 2018-07-25 11:29 ` [v7 2/7] " Wen He 2018-07-25 11:29 [v7,1/7] dmaengine: fsldma: Replace DMA_IN/OUT by FSL_DMA_IN/OUT Wen He 2018-07-25 11:29 ` [v7 1/7] " Wen He
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