[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[Zhiqiang Hou]

From: Hou Zhiqiang <B48286@freescale.com>

Expose this API to make it reuseable when u-boot turn into other EL
from EL3.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 24 ++++++++++++++++++++++++
 include/common.h                        |  1 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 6ea28ed..df5670f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -403,6 +403,30 @@ void enable_caches(void)
 	final_mmu_setup();
 	__asm_invalidate_tlb_all();
 }
+
+static void mmu_disable(void)
+{
+	if (get_sctlr() & CR_M)
+		set_sctlr(get_sctlr() & ~CR_M);
+}
+
+static void mmu_enable(void)
+{
+	if (!(get_sctlr() & CR_M))
+		set_sctlr(get_sctlr() | CR_M);
+}
+
+void mmu_init(void)
+{
+	mmu_disable();
+	dcache_disable();
+	icache_disable();
+	final_mmu_setup();
+	__asm_invalidate_tlb_all();
+	mmu_enable();
+	icache_enable();
+	set_sctlr(get_sctlr() | CR_C);
+}
 #endif
 
 static inline u32 initiator_type(u32 cluster, int init_id)
diff --git a/include/common.h b/include/common.h
index 75c78d5..57a9b30 100644
--- a/include/common.h
+++ b/include/common.h
@@ -757,6 +757,7 @@ void	flush_dcache_range(unsigned long start, unsigned long stop);
 void	invalidate_dcache_range(unsigned long start, unsigned long stop);
 void	invalidate_dcache_all(void);
 void	invalidate_icache_all(void);
+void	mmu_init(void);
 
 enum {
 	/* Disable caches (else flush caches but leave them active) */
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support

[Zhiqiang Hou]

From: Hou Zhiqiang <B48286@freescale.com>

The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.

Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile     |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/ppa.c        | 196 +++++++++++++++++++++++++
 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S  |  37 +++++
 arch/arm/include/asm/arch-fsl-layerscape/ppa.h |  15 ++
 4 files changed, 249 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index cce7405..27bfeb1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -10,6 +10,7 @@ obj-y += soc.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_SPL) += spl.o
+obj-$(CONFIG_FSL_LS_PPA) += ppa.o ppa_entry.o
 
 ifneq ($(CONFIG_FSL_LSCH3),)
 obj-y += fsl_lsch3_speed.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
new file mode 100644
index 0000000..15e4f8b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <config.h>
+#include <errno.h>
+#include <malloc.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/macro.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/immap_lsch2.h>
+#include <asm/arch/ppa.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void c_runtime_cpu_setup(void);
+
+#define LS_PPA_FIT_FIRMWARE_IMAGE	"firmware"
+#define LS_PPA_FIT_CNF_NAME		"config at 1"
+#define PPA_MEM_SIZE_ENV_VAR		"ppamemsize"
+
+/*
+ * Return the actual size of the PPA private DRAM block.
+ */
+unsigned long ppa_get_dram_block_size(void)
+{
+	unsigned long dram_block_size = CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE;
+
+	char *dram_block_size_env_var = getenv(PPA_MEM_SIZE_ENV_VAR);
+
+	if (dram_block_size_env_var) {
+		dram_block_size = simple_strtoul(dram_block_size_env_var, NULL,
+						 10);
+
+		if (dram_block_size < CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE) {
+			printf("fsl-ppa: WARNING: Invalid value for \'"
+			       PPA_MEM_SIZE_ENV_VAR
+			       "\' environment variable: %lu\n",
+			       dram_block_size);
+
+			dram_block_size = CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE;
+		}
+	}
+
+	return dram_block_size;
+}
+
+/*
+ * PPA firmware FIT image parser checks if the image is in FIT
+ * format, verifies integrity of the image and calculates raw
+ * image address and size values.
+ *
+ * Returns 0 on success and a negative errno on error task fail.
+ */
+static int parse_ppa_firmware_fit_image(const void **raw_image_addr,
+				size_t *raw_image_size)
+{
+	const void *ppa_data;
+	size_t ppa_size;
+	void *fit_hdr;
+	int conf_node_off, fw_node_off;
+	char *conf_node_name = NULL;
+
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+	fit_hdr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
+#else
+#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined"
+#endif
+
+	conf_node_name = LS_PPA_FIT_CNF_NAME;
+
+	if (fdt_check_header(fit_hdr)) {
+		printf("fsl-ppa: Bad firmware image (not a FIT image)\n");
+		return -EINVAL;
+	}
+
+	if (!fit_check_format(fit_hdr)) {
+		printf("fsl-ppa: Bad firmware image (bad FIT header)\n");
+		return -EINVAL;
+	}
+
+	conf_node_off = fit_conf_get_node(fit_hdr, conf_node_name);
+	if (conf_node_off < 0) {
+		printf("fsl-ppa: %s: no such config\n", conf_node_name);
+		return -ENOENT;
+	}
+
+	fw_node_off = fit_conf_get_prop_node(fit_hdr, conf_node_off,
+			LS_PPA_FIT_FIRMWARE_IMAGE);
+	if (fw_node_off < 0) {
+		printf("fsl-ppa: No '%s' in config\n",
+				LS_PPA_FIT_FIRMWARE_IMAGE);
+		return -ENOLINK;
+	}
+
+	/* Verify PPA firmware image */
+	if (!(fit_image_verify(fit_hdr, fw_node_off))) {
+		printf("fsl-ppa: Bad firmware image (bad CRC)\n");
+		return -EINVAL;
+	}
+
+	if (fit_image_get_data(fit_hdr, fw_node_off, &ppa_data, &ppa_size)) {
+		printf("fsl-ppa: Can't get %s subimage data/size",
+				LS_PPA_FIT_FIRMWARE_IMAGE);
+		return -ENOENT;
+	}
+
+	debug("fsl-ppa: raw_image_addr = %p, raw_image_size = 0x%lx\n",
+			ppa_data, ppa_size);
+	*raw_image_addr = ppa_data;
+	*raw_image_size = ppa_size;
+
+	return 0;
+}
+
+static int ppa_copy_image(const char *title,
+			 u64 image_addr, u32 image_size, u64 ppa_ram_addr)
+{
+	debug("%s copied to address %p\n", title, (void *)ppa_ram_addr);
+	memcpy((void *)ppa_ram_addr, (void *)image_addr, image_size);
+	flush_dcache_range(ppa_ram_addr, ppa_ram_addr + image_size);
+
+	return 0;
+}
+
+int ppa_init_pre(u64 *entry)
+{
+	u64 ppa_ram_addr;
+	const void *raw_image_addr;
+	size_t raw_image_size = 0;
+	size_t ppa_ram_size = ppa_get_dram_block_size();
+	int ret;
+
+	debug("fsl-ppa: ppa size(0x%lx)\n", ppa_ram_size);
+
+	/*
+	 * The PPA must be stored in secure memory.
+	 * Append PPA to secure mmu table.
+	 */
+	ppa_ram_addr = (gd->secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) +
+			gd->arch.tlb_size;
+
+	/* Align PPA base address to 4K */
+	ppa_ram_addr = (ppa_ram_addr + 0xfff) & ~0xfff;
+	debug("fsl-ppa: PPA load address (0x%llx)\n", ppa_ram_addr);
+
+	ret = parse_ppa_firmware_fit_image(&raw_image_addr, &raw_image_size);
+	if (ret < 0)
+		goto out;
+
+	if (ppa_ram_size < raw_image_size) {
+		ret = -ENOSPC;
+		goto out;
+	}
+
+	ppa_copy_image("PPA firmware", (u64)raw_image_addr,
+			raw_image_size, ppa_ram_addr);
+
+	debug("fsl-ppa: PPA entry: 0x%llx\n", ppa_ram_addr);
+	*entry = ppa_ram_addr;
+
+	return 0;
+
+out:
+	printf("fsl-ppa: error (%d)\n", ret);
+	*entry = 0;
+
+	return ret;
+}
+
+int ppa_init_entry(void *ppa_entry)
+{
+	int ret;
+
+	ret = ppa_init(ppa_entry);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * The PE will be turned into EL2 when run out of PPA.
+	 * First, set vector for EL2
+	 */
+	c_runtime_cpu_setup();
+
+	/*
+	 * Setup MMU for EL2
+	 */
+#ifndef CONFIG_SYS_DCACHE_OFF
+	mmu_init();
+#endif
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S b/arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
new file mode 100644
index 0000000..a143371
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/macro.h>
+
+ADDR_BASE_SCFG:
+        .long  0x01570000
+
+ENTRY(ppa_init)
+/* Save stack pointer for EL2 */
+        mov x1, sp
+        msr     sp_el2, x1
+
+/* Set boot loc pointer */
+        adr  x4, 1f
+        adr  x1, ADDR_BASE_SCFG
+        ldr  w2, [x1]
+        mov  x1, x4
+        rev  w3, w1
+        str  w3, [x2, #0x604]
+        lsr  x1, x4, #32
+        rev  w3, w1
+        str  w3, [x2, #0x600]
+
+/* Call PPA monitor */
+        br      x0
+
+1:
+        mov x0, #0
+        ret
+ENDPROC(ppa_init)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
new file mode 100644
index 0000000..e6c45c6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_PPA_H_
+#define __FSL_PPA_H_
+
+int ppa_init_pre(u64 *);
+int ppa_init_entry(void *);
+int ppa_init(void *);
+unsigned long ppa_get_dram_block_size(void);
+
+#endif
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Zhiqiang Hou [mailto:Zhiqiang.Hou at freescale.com]
> Sent: Tuesday, January 19, 2016 6:10 PM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net;
> Mingkai.hu at freescale.com; yorksun at freescale.com
> Cc: leoli at freescale.com; prabhakar at freescale.com;
> bhupesh.sharma at freescale.com; sjg at chromium.org;
> bmeng.cn at gmail.com; hs at denx.de; joe.hershberger at ni.com;
> marex at denx.de; Zhiqiang Hou <zhiqiang.hou@nxp.com>; Hou Zhiqiang
> <B48286@freescale.com>
> Subject: [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support
> 
> From: Hou Zhiqiang <B48286@freescale.com>
> 
> The FSL Primary Protected Application (PPA) is a software component loaded
> during boot which runs in TrustZone and remains resident after boot.
> 
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Makefile     |   1 +
>  arch/arm/cpu/armv8/fsl-layerscape/ppa.c        | 196
> +++++++++++++++++++++++++
>  arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S  |  37 +++++
> arch/arm/include/asm/arch-fsl-layerscape/ppa.h |  15 ++
>  4 files changed, 249 insertions(+)
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
>  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index cce7405..27bfeb1 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -10,6 +10,7 @@ obj-y += soc.o
>  obj-$(CONFIG_MP) += mp.o
>  obj-$(CONFIG_OF_LIBFDT) += fdt.o
>  obj-$(CONFIG_SPL) += spl.o
> +obj-$(CONFIG_FSL_LS_PPA) += ppa.o ppa_entry.o
> 
>  ifneq ($(CONFIG_FSL_LSCH3),)
>  obj-y += fsl_lsch3_speed.o
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> new file mode 100644
> index 0000000..15e4f8b
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> @@ -0,0 +1,196 @@
> +/*
> + * Copyright 2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +#include <common.h>
> +#include <config.h>
> +#include <errno.h>
> +#include <malloc.h>
> +#include <asm/system.h>
> +#include <asm/io.h>
> +#include <asm/types.h>
> +#include <asm/macro.h>
> +#include <asm/arch/soc.h>
> +#include <asm/arch/immap_lsch2.h>
> +#include <asm/arch/ppa.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +extern void c_runtime_cpu_setup(void);
> +
> +#define LS_PPA_FIT_FIRMWARE_IMAGE	"firmware"
> +#define LS_PPA_FIT_CNF_NAME		"config at 1"
> +#define PPA_MEM_SIZE_ENV_VAR		"ppamemsize"
> +
> +/*


<snip>

> +#include <config.h>
> +#include <linux/linkage.h>
> +#include <asm/system.h>
> +#include <asm/macro.h>
> +
> +ADDR_BASE_SCFG:
> +        .long  0x01570000

If I am correct it is address of BOOLPTR. This address looks to be specific to LS1043. 
For other SoC it may change


> +
> +ENTRY(ppa_init)
> +/* Save stack pointer for EL2 */
> +        mov x1, sp
> +        msr     sp_el2, x1
> +
> +/* Set boot loc pointer */
> +        adr  x4, 1f
> +        adr  x1, ADDR_BASE_SCFG
> +        ldr  w2, [x1]
> +        mov  x1, x4
> +        rev  w3, w1
> +        str  w3, [x2, #0x604]

It is LS1043 specific


> +        lsr  x1, x4, #32
> +        rev  w3, w1
> +        str  w3, [x2, #0x600]
Same as above

--prabhakar

[U-Boot] [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support

[Zhiqiang Hou]

Hi Prabhakar,

Thanks for your feedback!

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?1?19? 22:07
> To: Zhiqiang Hou <Zhiqiang.Hou@freescale.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; Mingkai.hu at freescale.com; yorksun at freescale.com
> Cc: leoli at freescale.com; prabhakar at freescale.com;
> bhupesh.sharma at freescale.com; sjg at chromium.org; bmeng.cn at gmail.com;
> hs at denx.de; joe.hershberger at ni.com; marex at denx.de; Zhiqiang Hou
> <zhiqiang.hou@nxp.com>; Hou Zhiqiang <B48286@freescale.com>
> Subject: RE: [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support
> 
> > -----Original Message-----
> > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at freescale.com]
> > Sent: Tuesday, January 19, 2016 6:10 PM
> > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net;
> > Mingkai.hu at freescale.com; yorksun at freescale.com
> > Cc: leoli at freescale.com; prabhakar at freescale.com;
> > bhupesh.sharma at freescale.com; sjg at chromium.org; bmeng.cn at gmail.com;
> > hs at denx.de; joe.hershberger at ni.com; marex at denx.de; Zhiqiang Hou
> > <zhiqiang.hou@nxp.com>; Hou Zhiqiang <B48286@freescale.com>
> > Subject: [PATCH 2/3] ARMv8/layerscape: Add FSL PPA support
> >
> > From: Hou Zhiqiang <B48286@freescale.com>
> >
> > The FSL Primary Protected Application (PPA) is a software component
> > loaded during boot which runs in TrustZone and remains resident after boot.
> >
> > Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/Makefile     |   1 +
> >  arch/arm/cpu/armv8/fsl-layerscape/ppa.c        | 196
> > +++++++++++++++++++++++++
> >  arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S  |  37 +++++
> > arch/arm/include/asm/arch-fsl-layerscape/ppa.h |  15 ++
> >  4 files changed, 249 insertions(+)
> >  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> >  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ppa_entry.S
> >  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/ppa.h
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> > b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> > index cce7405..27bfeb1 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> > @@ -10,6 +10,7 @@ obj-y += soc.o
> >  obj-$(CONFIG_MP) += mp.o
> >  obj-$(CONFIG_OF_LIBFDT) += fdt.o
> >  obj-$(CONFIG_SPL) += spl.o
> > +obj-$(CONFIG_FSL_LS_PPA) += ppa.o ppa_entry.o
> >
> >  ifneq ($(CONFIG_FSL_LSCH3),)
> >  obj-y += fsl_lsch3_speed.o
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> > new file mode 100644
> > index 0000000..15e4f8b
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
> > @@ -0,0 +1,196 @@
> > +/*
> > + * Copyright 2015 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0+
> > + */
> > +#include <common.h>
> > +#include <config.h>
> > +#include <errno.h>
> > +#include <malloc.h>
> > +#include <asm/system.h>
> > +#include <asm/io.h>
> > +#include <asm/types.h>
> > +#include <asm/macro.h>
> > +#include <asm/arch/soc.h>
> > +#include <asm/arch/immap_lsch2.h>
> > +#include <asm/arch/ppa.h>
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +extern void c_runtime_cpu_setup(void);
> > +
> > +#define LS_PPA_FIT_FIRMWARE_IMAGE	"firmware"
> > +#define LS_PPA_FIT_CNF_NAME		"config at 1"
> > +#define PPA_MEM_SIZE_ENV_VAR		"ppamemsize"
> > +
> > +/*
> 
> 
> <snip>
> 
> > +#include <config.h>
> > +#include <linux/linkage.h>
> > +#include <asm/system.h>
> > +#include <asm/macro.h>
> > +
> > +ADDR_BASE_SCFG:
> > +        .long  0x01570000
> 
> If I am correct it is address of BOOLPTR. This address looks to be specific to
> LS1043.
> For other SoC it may change
> 

Yes, I will make it a common interface for ARMv8 Layerscape platform in next version.

> 
> > +
> > +ENTRY(ppa_init)
> > +/* Save stack pointer for EL2 */
> > +        mov x1, sp
> > +        msr     sp_el2, x1
> > +
> > +/* Set boot loc pointer */
> > +        adr  x4, 1f
> > +        adr  x1, ADDR_BASE_SCFG
> > +        ldr  w2, [x1]
> > +        mov  x1, x4
> > +        rev  w3, w1
> > +        str  w3, [x2, #0x604]
> 
> It is LS1043 specific
> 
> 
> > +        lsr  x1, x4, #32
> > +        rev  w3, w1
> > +        str  w3, [x2, #0x600]
> Same as above
> 

Thanks,
Zhiqiang

[U-Boot] [PATCH 3/3] ARMv8/ls1043ardb: Integrate FSL PPA

[Zhiqiang Hou]

From: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
---
 board/freescale/ls1043ardb/ls1043ardb.c | 11 +++++++++++
 include/configs/ls1043ardb.h            |  9 +++++++++
 2 files changed, 20 insertions(+)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index c8f723a..eff09aa 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -9,6 +9,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
 #include <ahci.h>
@@ -94,6 +95,9 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+#ifdef CONFIG_FSL_LS_PPA
+	u64 ppa_entry;
+#endif
 
 	/*
 	 * Set CCI-400 control override register to enable barrier
@@ -113,6 +117,13 @@ int board_init(void)
 	enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+	ppa_init_pre(&ppa_entry);
+
+	if (ppa_entry)
+		ppa_init_entry((void *)ppa_entry);
+#endif
+
 	return 0;
 }
 
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 585114f..fd28814 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -9,6 +9,15 @@
 
 #include "ls1043a_common.h"
 
+#if defined(CONFIG_FSL_LS_PPA)
+#define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE		(1UL * 1024 * 1024)
+
+#define CONFIG_SYS_LS_PPA_FW_IN_NOR
+#ifdef CONFIG_SYS_LS_PPA_FW_IN_NOR
+#define	CONFIG_SYS_LS_PPA_FW_ADDR	0x60500000
+#endif
+#endif
+
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
2.1.0.27.g96db324

[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[Prabhakar Kushwaha]

> -----Original Message-----
> From: Zhiqiang Hou [mailto:Zhiqiang.Hou at freescale.com]
> Sent: Tuesday, January 19, 2016 6:10 PM
> To: u-boot at lists.denx.de; albert.u.boot at aribaud.net;
> Mingkai.hu at freescale.com; yorksun at freescale.com
> Cc: leoli at freescale.com; prabhakar at freescale.com;
> bhupesh.sharma at freescale.com; sjg at chromium.org;
> bmeng.cn at gmail.com; hs at denx.de; joe.hershberger at ni.com;
> marex at denx.de; Zhiqiang Hou <zhiqiang.hou@nxp.com>; Hou Zhiqiang
> <B48286@freescale.com>
> Subject: [PATCH 1/3] ARMv8/layerscape: Add mmu_init API
> 
> From: Hou Zhiqiang <B48286@freescale.com>
> 
> Expose this API to make it reuseable when u-boot turn into other EL from
> EL3.
> 
> Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 24
> ++++++++++++++++++++++++
>  include/common.h                        |  1 +
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 6ea28ed..df5670f 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -403,6 +403,30 @@ void enable_caches(void)
>  	final_mmu_setup();
>  	__asm_invalidate_tlb_all();
>  }
> +
> +static void mmu_disable(void)
> +{
> +	if (get_sctlr() & CR_M)
> +		set_sctlr(get_sctlr() & ~CR_M);
> +}
> +
> +static void mmu_enable(void)
> +{
> +	if (!(get_sctlr() & CR_M))
> +		set_sctlr(get_sctlr() | CR_M);
> +}
> +
> +void mmu_init(void)

Name of function is not mapping about what it is doing. 
This function assume MMU is already enabled with early_table and it will setup final_mmu_setup.

> +{
> +	mmu_disable();
> +	dcache_disable();
> +	icache_disable();
> +	final_mmu_setup();
> +	__asm_invalidate_tlb_all();
> +	mmu_enable();
> +	icache_enable();
> +	set_sctlr(get_sctlr() | CR_C);
> +}
>  #endif

If I am correct board_init_r deploy final_mmu_setup via enable_caches(). 
Why cannot existing framework be used.

> 
>  static inline u32 initiator_type(u32 cluster, int init_id) diff --git
> a/include/common.h b/include/common.h index 75c78d5..57a9b30 100644
> --- a/include/common.h
> +++ b/include/common.h
> @@ -757,6 +757,7 @@ void	flush_dcache_range(unsigned long start,
> unsigned long stop);
>  void	invalidate_dcache_range(unsigned long start, unsigned long stop);
>  void	invalidate_dcache_all(void);
>  void	invalidate_icache_all(void);
> +void	mmu_init(void);
> 
>  enum {
>  	/* Disable caches (else flush caches but leave them active) */
> --
> 2.1.0.27.g96db324

[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[Zhiqiang Hou]

Hi Prabhakar,

Thanks for your feedback!

> -----Original Message-----
> From: Prabhakar Kushwaha
> Sent: 2016?1?19? 21:54
> To: Zhiqiang Hou <Zhiqiang.Hou@freescale.com>; u-boot at lists.denx.de;
> albert.u.boot at aribaud.net; Mingkai.hu at freescale.com; yorksun at freescale.com
> Cc: leoli at freescale.com; prabhakar at freescale.com;
> bhupesh.sharma at freescale.com; sjg at chromium.org; bmeng.cn at gmail.com;
> hs at denx.de; joe.hershberger at ni.com; marex at denx.de; Zhiqiang Hou
> <zhiqiang.hou@nxp.com>; Hou Zhiqiang <B48286@freescale.com>
> Subject: RE: [PATCH 1/3] ARMv8/layerscape: Add mmu_init API
> 
> > -----Original Message-----
> > From: Zhiqiang Hou [mailto:Zhiqiang.Hou at freescale.com]
> > Sent: Tuesday, January 19, 2016 6:10 PM
> > To: u-boot at lists.denx.de; albert.u.boot at aribaud.net;
> > Mingkai.hu at freescale.com; yorksun at freescale.com
> > Cc: leoli at freescale.com; prabhakar at freescale.com;
> > bhupesh.sharma at freescale.com; sjg at chromium.org; bmeng.cn at gmail.com;
> > hs at denx.de; joe.hershberger at ni.com; marex at denx.de; Zhiqiang Hou
> > <zhiqiang.hou@nxp.com>; Hou Zhiqiang <B48286@freescale.com>
> > Subject: [PATCH 1/3] ARMv8/layerscape: Add mmu_init API
> >
> > From: Hou Zhiqiang <B48286@freescale.com>
> >
> > Expose this API to make it reuseable when u-boot turn into other EL
> > from EL3.
> >
> > Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 24
> > ++++++++++++++++++++++++
> >  include/common.h                        |  1 +
> >  2 files changed, 25 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index 6ea28ed..df5670f 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -403,6 +403,30 @@ void enable_caches(void)
> >  	final_mmu_setup();
> >  	__asm_invalidate_tlb_all();
> >  }
> > +
> > +static void mmu_disable(void)
> > +{
> > +	if (get_sctlr() & CR_M)
> > +		set_sctlr(get_sctlr() & ~CR_M);
> > +}
> > +
> > +static void mmu_enable(void)
> > +{
> > +	if (!(get_sctlr() & CR_M))
> > +		set_sctlr(get_sctlr() | CR_M);
> > +}
> > +
> > +void mmu_init(void)
> 
> Name of function is not mapping about what it is doing.
> This function assume MMU is already enabled with early_table and it will setup
> final_mmu_setup.
> 

This function map basically with what it is doing except some I-cache operations
that will be remove from this func, and not assume the early_mmu_setup.
It assumes the relocation has been done. 

> > +{
> > +	mmu_disable();
> > +	dcache_disable();
> > +	icache_disable();
> > +	final_mmu_setup();
> > +	__asm_invalidate_tlb_all();
> > +	mmu_enable();
> > +	icache_enable();
> > +	set_sctlr(get_sctlr() | CR_C);
> > +}
> >  #endif
> 
> If I am correct board_init_r deploy final_mmu_setup via enable_caches().
> Why cannot existing framework be used.
> 

This patch aims to make final_mmu_setup() can be called flexibly in case as
When it return from PPA and execute at EL2, the MMU must be initialized
for the current EL.
Yes, the enable_caches() will call the __weak__ mmu_setup() if MMU wasn't
enabled. But for fsl layerscape platforms, the MMU has been enabled by early
mmu setup, so the __weak__ mmu_setup won't be called.

I am not know cache and mmu so much, and have some question:
For ARM:
Why there isn't a isolate API for mmu_setup, but invoke it from dcache_enable()?
If data cache won't be used, the MMU also cannot be used?

> >
> >  static inline u32 initiator_type(u32 cluster, int init_id) diff --git
> > a/include/common.h b/include/common.h index 75c78d5..57a9b30 100644
> > --- a/include/common.h
> > +++ b/include/common.h
> > @@ -757,6 +757,7 @@ void	flush_dcache_range(unsigned long start,
> > unsigned long stop);
> >  void	invalidate_dcache_range(unsigned long start, unsigned long stop);
> >  void	invalidate_dcache_all(void);
> >  void	invalidate_icache_all(void);
> > +void	mmu_init(void);
> >
> >  enum {
> >  	/* Disable caches (else flush caches but leave them active) */
> > --
> > 2.1.0.27.g96db324

Thanks,
Zhiqiang

[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[york sun]

On 01/20/2016 04:06 AM, Zhiqiang Hou wrote:

<snip>

> I am not know cache and mmu so much, and have some question:
> For ARM:
> Why there isn't a isolate API for mmu_setup, but invoke it from dcache_enable()?
> If data cache won't be used, the MMU also cannot be used?

No. If MMU is not enabled, cacheability cannot be set.

York

[U-Boot] [PATCH 1/3] ARMv8/layerscape: Add mmu_init API

[Zhiqiang Hou]

Hi York,

> -----Original Message-----
> From: york sun
> Sent: 2016?1?20? 23:55
> To: Zhiqiang Hou <zhiqiang.hou@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; Zhiqiang Hou <Zhiqiang.Hou@freescale.com>;
> u-boot at lists.denx.de; albert.u.boot at aribaud.net; Mingkai.hu at freescale.com;
> yorksun at freescale.com
> Cc: leoli at freescale.com; prabhakar at freescale.com;
> bhupesh.sharma at freescale.com; sjg at chromium.org; bmeng.cn at gmail.com;
> hs at denx.de; joe.hershberger at ni.com; marex at denx.de; Hou Zhiqiang
> <B48286@freescale.com>
> Subject: Re: [PATCH 1/3] ARMv8/layerscape: Add mmu_init API
> 
> On 01/20/2016 04:06 AM, Zhiqiang Hou wrote:
> 
> <snip>
> 
> > I am not know cache and mmu so much, and have some question:
> > For ARM:
> > Why there isn't a isolate API for mmu_setup, but invoke it from dcache_enable()?
> > If data cache won't be used, the MMU also cannot be used?
> 
> No. If MMU is not enabled, cacheability cannot be set.

Thanks for your clarification!

- Zhiqiang