[U-Boot] [PATCH v2] armv8/ls1088a: configure PMU's PCTBENR to enable WDT

[U-Boot] [PATCH v2] armv8/ls1088a: configure PMU's PCTBENR to enable WDT

[ying.zhang22455 at nxp.com]

From: Zhang Ying-22455 <ying.zhang22455@nxp.com>

The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d082629..05c0137 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -574,7 +574,7 @@ int timer_init(void)
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 	u32 svr_dev_id;
 #endif
@@ -593,7 +593,7 @@ int timer_init(void)
 	out_le32(cltbenr, 0xf);
 #endif
 
-#ifdef CONFIG_ARCH_LS2080A
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
 	/*
 	 * In certain Layerscape SoCs, the clock for each core's
 	 * has an enable bit in the PMU Physical Core Time Base Enable
-- 
1.7.1

[U-Boot] [PATCH v2] armv8/ls1088a: configure PMU's PCTBENR to enable WDT

[York Sun]

On 01/09/2018 12:45 AM, ying.zhang22455 at nxp.com wrote:
> From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> 
> The SP805-WDT module on LS1088A requires configuration of PMU's
> PCTBENR register to enable watchdog counter decrement and reset
> signal generation. The watchdog clock needs to be enabled first.
> 
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>


Applied to fsl-qoriq master. Thanks.

York