* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
@ 2018-02-15 14:17 Calvin Johnson
2018-02-15 14:17 ` [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM Calvin Johnson
` (14 more replies)
0 siblings, 15 replies; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
Hi,
This patch series introduces U-Boot support for NXP's LS1012A Packet
Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
engine to provide high performance Ethernet interfaces. The device
includes two Ethernet ports.
Changes in v2 series:
1. PFE patches submitted on top of this base patch are now merged to
this patch.
2. Platform changes are segregated into different patches.
3. Network enabled on 2g5rdb platform
4. Moved from legacy to new driver model.
Calvin Johnson (12):
drivers: net: phy: Fix aquantia compilation with DM
drivers: net: pfe_eth: LS1012A PFE driver introduction
drivers: net: pfe_eth: provide pfe commands
drivers: net: pfe_eth: LS1012A PFE headers
board: freescale: ls1012aqds: enable network support on ls1012aqds
board: freescale: ls1012afrdm: enable network support on ls1012afrdm
board: freescale: ls1012ardb: enable network support on ls1012ardb
board: freescale: ls1012a2g5rdb: enable network support on
ls1012a2g5rdb
armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
armv8: layerscape: csu: enable ns access to PFE registers
configs: ls1012a: add pfe configuration for LS1012A
Prabhakar Kushwaha (1):
armv8: fsl-layerscape: Add support of GPIO structure
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 +
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 63 +-
.../include/asm/arch-fsl-layerscape/ns_access.h | 2 +
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +
board/freescale/ls1012afrdm/Kconfig | 14 +
board/freescale/ls1012afrdm/Makefile | 1 +
board/freescale/ls1012afrdm/eth.c | 122 +++
board/freescale/ls1012afrdm/ls1012afrdm.c | 5 -
board/freescale/ls1012aqds/Kconfig | 14 +
board/freescale/ls1012aqds/Makefile | 1 +
board/freescale/ls1012aqds/eth.c | 304 +++++++
board/freescale/ls1012aqds/ls1012aqds.c | 97 +-
board/freescale/ls1012aqds/ls1012aqds_pfe.h | 48 +
board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
board/freescale/ls1012ardb/Kconfig | 28 +
board/freescale/ls1012ardb/Makefile | 1 +
board/freescale/ls1012ardb/eth.c | 131 +++
board/freescale/ls1012ardb/ls1012ardb.c | 4 -
configs/ls1012a2g5rdb_qspi_defconfig | 2 +
configs/ls1012afrdm_qspi_defconfig | 2 +
configs/ls1012aqds_qspi_defconfig | 2 +
configs/ls1012ardb_qspi_defconfig | 2 +
drivers/net/Kconfig | 1 +
drivers/net/Makefile | 1 +
drivers/net/pfe_eth/Kconfig | 17 +
drivers/net/pfe_eth/Makefile | 12 +
drivers/net/pfe_eth/pfe_cmd.c | 497 ++++++++++
drivers/net/pfe_eth/pfe_driver.c | 643 +++++++++++++
drivers/net/pfe_eth/pfe_eth.c | 297 ++++++
drivers/net/pfe_eth/pfe_firmware.c | 230 +++++
drivers/net/pfe_eth/pfe_hw.c | 999 +++++++++++++++++++++
drivers/net/pfe_eth/pfe_mdio.c | 291 ++++++
drivers/net/phy/aquantia.c | 1 +
include/configs/ls1012a2g5rdb.h | 2 +-
include/configs/ls1012a_common.h | 6 +-
include/configs/ls1012afrdm.h | 9 +-
include/configs/ls1012aqds.h | 14 +
include/configs/ls1012ardb.h | 14 +-
include/dm/platform_data/pfe_dm_eth.h | 21 +
include/pfe_eth/pfe/cbus.h | 77 ++
include/pfe_eth/pfe/cbus/bmu.h | 40 +
include/pfe_eth/pfe/cbus/class_csr.h | 180 ++++
include/pfe_eth/pfe/cbus/emac.h | 140 +++
include/pfe_eth/pfe/cbus/gpi.h | 62 ++
include/pfe_eth/pfe/cbus/hif.h | 68 ++
include/pfe_eth/pfe/cbus/hif_nocpy.h | 40 +
include/pfe_eth/pfe/cbus/tmu_csr.h | 148 +++
include/pfe_eth/pfe/cbus/util_csr.h | 47 +
include/pfe_eth/pfe/pfe_hw.h | 163 ++++
include/pfe_eth/pfe_driver.h | 59 ++
include/pfe_eth/pfe_eth.h | 104 +++
include/pfe_eth/pfe_firmware.h | 17 +
include/pfe_eth/pfe_mdio.h | 13 +
53 files changed, 5060 insertions(+), 24 deletions(-)
create mode 100644 board/freescale/ls1012afrdm/eth.c
create mode 100644 board/freescale/ls1012aqds/eth.c
create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
create mode 100644 board/freescale/ls1012ardb/eth.c
create mode 100644 drivers/net/pfe_eth/Kconfig
create mode 100644 drivers/net/pfe_eth/Makefile
create mode 100644 drivers/net/pfe_eth/pfe_cmd.c
create mode 100644 drivers/net/pfe_eth/pfe_driver.c
create mode 100644 drivers/net/pfe_eth/pfe_eth.c
create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
create mode 100644 drivers/net/pfe_eth/pfe_hw.c
create mode 100644 drivers/net/pfe_eth/pfe_mdio.c
create mode 100644 include/dm/platform_data/pfe_dm_eth.h
create mode 100644 include/pfe_eth/pfe/cbus.h
create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
create mode 100644 include/pfe_eth/pfe/cbus/emac.h
create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
create mode 100644 include/pfe_eth/pfe/cbus/hif.h
create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
create mode 100644 include/pfe_eth/pfe/pfe_hw.h
create mode 100644 include/pfe_eth/pfe_driver.h
create mode 100644 include/pfe_eth/pfe_eth.h
create mode 100644 include/pfe_eth/pfe_firmware.h
create mode 100644 include/pfe_eth/pfe_mdio.h
--
2.7.4
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 16:58 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure Calvin Johnson
` (13 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
---
Changes in v2: None
---
drivers/net/phy/aquantia.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c
index ad12f6d..6678147 100644
--- a/drivers/net/phy/aquantia.c
+++ b/drivers/net/phy/aquantia.c
@@ -7,6 +7,7 @@
*/
#include <config.h>
#include <common.h>
+#include <dm.h>
#include <phy.h>
#ifndef CONFIG_PHYLIB_10G
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
2018-02-15 14:17 ` [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 17:01 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction Calvin Johnson
` (12 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Layerscape Gen2 SoC supports GPIO registers to control GPIO
signals. Adding support of GPIO structure to access GPIO
registers.
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---
Changes in v2: None
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 1ff5cac..b195005 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -82,6 +82,11 @@
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
+#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000)
+#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000)
+#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
+#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
+
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
@@ -591,6 +596,16 @@ struct ccsr_serdes {
u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */
};
+struct ccsr_gpio {
+ u32 gpdir;
+ u32 gpodr;
+ u32 gpdat;
+ u32 gpier;
+ u32 gpimr;
+ u32 gpicr;
+ u32 gpibe;
+};
+
/* MMU 500 */
#define SMMU_SCR0 (SMMU_BASE + 0x0)
#define SMMU_SCR1 (SMMU_BASE + 0x4)
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
2018-02-15 14:17 ` [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM Calvin Johnson
2018-02-15 14:17 ` [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:12 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands Calvin Johnson
` (11 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
This patch adds PFE driver to U-Boot
Following are the main driver files:-
pfe_hw.c: provides low level helper functions to initialize PFE
internal processor engines and other hardware blocks
pfe_driver.c: provides initialization functions
and packet send and receive functions
pfe_eth.c: provides high level gemac initialization functions
pfe_firmware.c: provides functions to load firmware into PFE
internal processor engines.
pfe_mdio.c: provides functions to initialize phy and mdio.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-fix RGMII TX-delay issue
-add pfe_rx_done to clear bd after packet processing
-use writel/readl to access hw bds
-cleanup typos and indent
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Consolidate code in pfe_lib_init
-Corrected typo receive
-Magic numbers replaced with proper definitions
-File names pfe.c renamed to pfe_hw.c to be more clear as it contains
low level functions that directly access pfe hardware block.
-MDIO related code is also moved from pfe_eth.c to a new file
pfe_mdio.c.
---
drivers/net/pfe_eth/pfe_driver.c | 643 ++++++++++++++++++++++++
drivers/net/pfe_eth/pfe_eth.c | 297 +++++++++++
drivers/net/pfe_eth/pfe_firmware.c | 230 +++++++++
drivers/net/pfe_eth/pfe_hw.c | 999 +++++++++++++++++++++++++++++++++++++
drivers/net/pfe_eth/pfe_mdio.c | 291 +++++++++++
5 files changed, 2460 insertions(+)
create mode 100644 drivers/net/pfe_eth/pfe_driver.c
create mode 100644 drivers/net/pfe_eth/pfe_eth.c
create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
create mode 100644 drivers/net/pfe_eth/pfe_hw.c
create mode 100644 drivers/net/pfe_eth/pfe_mdio.c
diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
new file mode 100644
index 0000000..3122d5a
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_driver.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <pfe_eth/pfe_eth.h>
+#include <pfe_eth/pfe_firmware.h>
+
+static struct tx_desc_s *g_tx_desc;
+static struct rx_desc_s *g_rx_desc;
+
+/*
+ * HIF Rx interface function
+ * Reads the rx descriptor from the current location (rx_to_read).
+ * - If the descriptor has a valid data/pkt, then get the data pointer
+ * - check for the input rx phy number
+ * - increment the rx data pointer by pkt_head_room_size
+ * - decrement the data length by pkt_head_room_size
+ * - handover the packet to caller.
+ *
+ * @param[out] pkt_ptr - Pointer to store rx packet
+ * @param[out] phy_port - Pointer to store recv phy port
+ *
+ * @return -1 if no packet, else return length of packet.
+ */
+int pfe_recv(uchar **pkt_ptr, int *phy_port)
+{
+ struct rx_desc_s *rx_desc = g_rx_desc;
+ struct buf_desc *bd;
+ int len = 0;
+
+ struct hif_header_s *hif_header;
+
+ bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return len; /* No pending Rx packet */
+
+ /* this len include hif_header(8 bytes) */
+ len = readl(&bd->ctrl) & 0xFFFF;
+
+ hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
+
+ /* Get the receive port info from the packet */
+ debug("Pkt received:");
+ debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
+ hif_header, len, hif_header->port_no, readl(&bd->status));
+#ifdef DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)hif_header;
+
+ for (i = 0; i < len; i++) {
+ if (!(i % 16))
+ printf("\n");
+ printf(" %02x", p[i]);
+ }
+ printf("\n");
+ }
+#endif
+
+ *pkt_ptr = (uchar *)(hif_header + 1);
+ *phy_port = hif_header->port_no;
+ len -= sizeof(struct hif_header_s);
+
+ return len;
+}
+
+/*
+ * HIF function to check the Rx done
+ * This function will check the rx done indication of the current rx_to_read
+ * locations
+ * if success, moves the rx_to_read to next location.
+ */
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct rx_desc_s *rx_desc = g_rx_desc;
+ struct buf_desc *bd;
+
+ debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
+ rx_desc->rx_to_read);
+
+ bd = rx_desc->rx_base + rx_desc->rx_to_read;
+
+ /* reset the control field */
+ writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
+ | BD_CTRL_DIR), &bd->ctrl);
+ writel(0, &bd->status);
+
+ debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
+ * BDP need not wait for rx_poll_cycle time to fetch the descriptor,
+ * In idle state (ie., no rx pkt), BDP will not fetch
+ * the descriptor even if strobe is given.
+ */
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+ /* increment the rx_to_read index to next location */
+ rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
+ & (rx_desc->rx_ring_size - 1);
+
+ debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
+
+ return 0;
+}
+
+/*
+ * HIF Tx interface function
+ * This function sends a single packet to PFE from HIF interface.
+ * - No interrupt indication on tx completion.
+ * - Data is copied to tx buffers before tx descriptor is updated
+ * and TX DMA is enabled.
+ *
+ * @param[in] phy_port Phy port number to send out this packet
+ * @param[in] data Pointer to the data
+ * @param[in] length Length of the ethernet packet to be transferred.
+ *
+ * @return -1 if tx Q is full, else returns the tx location where the pkt is
+ * placed.
+ */
+int pfe_send(int phy_port, void *data, int length)
+{
+ struct tx_desc_s *tx_desc = g_tx_desc;
+ struct buf_desc *bd;
+ struct hif_header_s hif_header;
+ u8 *tx_buf_va;
+
+ debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
+ data, length, tx_desc->tx_base, tx_desc->tx_to_send);
+
+ bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+ /* check queue-full condition */
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return -1;
+
+ /* PFE checks for min pkt size */
+ if (length < MIN_PKT_SIZE)
+ length = MIN_PKT_SIZE;
+
+ tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
+ debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
+ readl(&bd->data));
+
+ /* Fill the gemac/phy port number to send this packet out */
+ memset(&hif_header, 0, sizeof(struct hif_header_s));
+ hif_header.port_no = phy_port;
+
+ memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
+ memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
+ length += sizeof(struct hif_header_s);
+
+#ifdef DEBUG
+ {
+ int i;
+ unsigned char *p = (unsigned char *)tx_buf_va;
+
+ for (i = 0; i < length; i++) {
+ if (!(i % 16))
+ printf("\n");
+ printf("%02x ", p[i]);
+ }
+ }
+#endif
+
+ debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* fill the tx desc */
+ writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
+ &bd->ctrl);
+ writel(0, &bd->status);
+
+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
+
+ udelay(100);
+
+ return tx_desc->tx_to_send;
+}
+
+/*
+ * HIF function to check the Tx done
+ * This function will check the tx done indication of the current tx_to_send
+ * locations
+ * if success, moves the tx_to_send to next location.
+ *
+ * @return -1 if TX ownership bit is not cleared by hw.
+ * else on success (tx done completion) return zero.
+ */
+int pfe_tx_done(void)
+{
+ struct tx_desc_s *tx_desc = g_tx_desc;
+ struct buf_desc *bd;
+
+ debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
+ tx_desc->tx_to_send);
+
+ bd = tx_desc->tx_base + tx_desc->tx_to_send;
+
+ /* check queue-full condition */
+ if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
+ return -1;
+
+ /* reset the control field */
+ writel(0, &bd->ctrl);
+ writel(0, &bd->status);
+
+ debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
+ readl(&bd->ctrl));
+
+ /* increment the txtosend index to next location */
+ tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
+ & (tx_desc->tx_ring_size - 1);
+
+ debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
+
+ return 0;
+}
+
+/*
+ * Helper function to dump Rx descriptors.
+ */
+static inline void hif_rx_desc_dump(void)
+{
+ struct buf_desc *bd_va;
+ int i;
+ struct rx_desc_s *rx_desc;
+
+ if (!g_rx_desc) {
+ printf("%s: HIF Rx desc no init\n", __func__);
+ return;
+ }
+
+ rx_desc = g_rx_desc;
+ bd_va = rx_desc->rx_base;
+
+ debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
+ rx_desc->rx_base_pa);
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
+ readl(&bd_va->status),
+ readl(&bd_va->ctrl),
+ readl(&bd_va->data),
+ readl(&bd_va->next));
+ bd_va++;
+ }
+}
+
+/*
+ * This function mark all Rx descriptors as LAST_BD.
+ */
+void hif_rx_desc_disable(void)
+{
+ int i;
+ struct rx_desc_s *rx_desc;
+ struct buf_desc *bd_va;
+
+ if (!g_rx_desc) {
+ printf("%s: HIF Rx desc not initialized\n", __func__);
+ return;
+ }
+
+ rx_desc = g_rx_desc;
+ bd_va = rx_desc->rx_base;
+
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
+ bd_va++;
+ }
+}
+
+/*
+ * HIF Rx Desc initialization function.
+ */
+static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+ u32 ctrl;
+ struct buf_desc *bd_va;
+ struct buf_desc *bd_pa;
+ struct rx_desc_s *rx_desc;
+ u32 rx_buf_pa;
+ int i;
+
+ /* sanity check */
+ if (g_rx_desc) {
+ printf("%s: HIF Rx desc re-init request\n", __func__);
+ return 0;
+ }
+
+ rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
+ if (!rx_desc) {
+ printf("%s: Memory allocation failure\n", __func__);
+ return -ENOMEM;
+ }
+ memset(rx_desc, 0, sizeof(struct rx_desc_s));
+
+ /* init: Rx ring buffer */
+ rx_desc->rx_ring_size = HIF_RX_DESC_NT;
+
+ /* NOTE: must be 64bit aligned */
+ bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+ + RX_BD_BASEADDR);
+ bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+ + RX_BD_BASEADDR);
+
+ rx_desc->rx_base = bd_va;
+ rx_desc->rx_base_pa = (unsigned long)bd_pa;
+
+ rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
+
+ debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
+ __func__, rx_desc->rx_base, rx_desc->rx_base_pa,
+ rx_desc->rx_ring_size);
+
+ memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
+
+ ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
+
+ for (i = 0; i < rx_desc->rx_ring_size; i++) {
+ writel((unsigned long)(bd_pa + 1), &bd_va->next);
+ writel(ctrl, &bd_va->ctrl);
+ writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+ bd_va++;
+ bd_pa++;
+ }
+ --bd_va;
+ writel((u32)rx_desc->rx_base_pa, &bd_va->next);
+
+ writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
+ writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+
+ g_rx_desc = rx_desc;
+
+ return 0;
+}
+
+/*
+ * Helper function to dump Tx Descriptors.
+ */
+static inline void hif_tx_desc_dump(void)
+{
+ struct tx_desc_s *tx_desc;
+ int i;
+ struct buf_desc *bd_va;
+
+ if (!g_tx_desc) {
+ printf("%s: HIF Tx desc no init\n", __func__);
+ return;
+ }
+
+ tx_desc = g_tx_desc;
+ bd_va = tx_desc->tx_base;
+
+ debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
+ tx_desc->tx_base_pa);
+
+ for (i = 0; i < tx_desc->tx_ring_size; i++)
+ bd_va++;
+}
+
+/*
+ * HIF Tx descriptor initialization function.
+ */
+static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct buf_desc *bd_va;
+ struct buf_desc *bd_pa;
+ int i;
+ struct tx_desc_s *tx_desc;
+ u32 tx_buf_pa;
+
+ /* sanity check */
+ if (g_tx_desc) {
+ printf("%s: HIF Tx desc re-init request\n", __func__);
+ return 0;
+ }
+
+ tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
+ if (!tx_desc) {
+ printf("%s:%d:Memory allocation failure\n", __func__,
+ __LINE__);
+ return -ENOMEM;
+ }
+ memset(tx_desc, 0, sizeof(struct tx_desc_s));
+
+ /* init: Tx ring buffer */
+ tx_desc->tx_ring_size = HIF_TX_DESC_NT;
+
+ /* NOTE: must be 64bit aligned */
+ bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
+ + TX_BD_BASEADDR);
+ bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
+ + TX_BD_BASEADDR);
+
+ tx_desc->tx_base_pa = (unsigned long)bd_pa;
+ tx_desc->tx_base = bd_va;
+
+ debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
+ __func__, tx_desc->tx_base, tx_desc->tx_base_pa,
+ tx_desc->tx_ring_size);
+
+ memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
+
+ tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
+
+ for (i = 0; i < tx_desc->tx_ring_size; i++) {
+ writel((unsigned long)(bd_pa + 1), &bd_va->next);
+ writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
+ bd_va++;
+ bd_pa++;
+ }
+ --bd_va;
+ writel((u32)tx_desc->tx_base_pa, &bd_va->next);
+
+ writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
+
+ g_tx_desc = tx_desc;
+
+ return 0;
+}
+
+/*
+ * PFE/Class initialization.
+ */
+static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct class_cfg class_cfg = {
+ .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
+ ROUTE_TABLE_BASEADDR,
+ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
+ };
+
+ class_init(&class_cfg);
+
+ debug("class init complete\n");
+}
+
+/*
+ * PFE/TMU initialization.
+ */
+static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct tmu_cfg tmu_cfg = {
+ .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
+ + TMU_LLM_BASEADDR,
+ .llm_queue_len = TMU_LLM_QUEUE_LEN,
+ };
+
+ tmu_init(&tmu_cfg);
+
+ debug("tmu init complete\n");
+}
+
+/*
+ * PFE/BMU (both BMU1 & BMU2) initialization.
+ */
+static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct bmu_cfg bmu1_cfg = {
+ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
+ BMU1_LMEM_BASEADDR),
+ .count = BMU1_BUF_COUNT,
+ .size = BMU1_BUF_SIZE,
+ };
+
+ struct bmu_cfg bmu2_cfg = {
+ .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
+ .count = BMU2_BUF_COUNT,
+ .size = BMU2_BUF_SIZE,
+ };
+
+ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
+ debug("bmu1 init: done\n");
+
+ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
+ debug("bmu2 init: done\n");
+}
+
+/*
+ * PFE/GPI initialization function.
+ * - egpi1, egpi2, egpi3, hgpi
+ */
+static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
+{
+ struct gpi_cfg egpi1_cfg = {
+ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
+ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
+ .aseq_len = EGPI1_ASEQ_LEN,
+ };
+
+ struct gpi_cfg egpi2_cfg = {
+ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
+ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
+ .aseq_len = EGPI2_ASEQ_LEN,
+ };
+
+ struct gpi_cfg hgpi_cfg = {
+ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
+ .tmlf_txthres = HGPI_TMLF_TXTHRES,
+ .aseq_len = HGPI_ASEQ_LEN,
+ };
+
+ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
+ debug("GPI1 init complete\n");
+
+ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
+ debug("GPI2 init complete\n");
+
+ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
+ debug("HGPI init complete\n");
+}
+
+/*
+ * PFE/HIF initialization function.
+ */
+static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ hif_tx_disable();
+ hif_rx_disable();
+
+ ret = hif_tx_desc_init(pfe_addr);
+ if (ret)
+ return ret;
+ ret = hif_rx_desc_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ hif_init();
+
+ hif_tx_enable();
+ hif_rx_enable();
+
+ hif_rx_desc_dump();
+ hif_tx_desc_dump();
+
+ debug("HIF init complete\n");
+ return ret;
+}
+
+/*
+ * PFE initialization
+ * - Firmware loading (CLASS-PE and TMU-PE)
+ * - BMU1 and BMU2 init
+ * - GEMAC init
+ * - GPI init
+ * - CLASS-PE init
+ * - TMU-PE init
+ * - HIF tx and rx descriptors init
+ *
+ * @param[in] edev Pointer to eth device structure.
+ *
+ * @return 0, on success.
+ */
+static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ debug("%s: start\n", __func__);
+
+ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
+ writel(0x3, TMU_PE_SYS_CLK_RATIO);
+ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
+ udelay(10);
+
+ pfe_class_init(pfe_addr);
+
+ pfe_tmu_init(pfe_addr);
+
+ pfe_bmu_init(pfe_addr);
+
+ pfe_gpi_init(pfe_addr);
+
+ ret = pfe_hif_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ bmu_enable(BMU1_BASE_ADDR);
+ debug("bmu1 enabled\n");
+
+ bmu_enable(BMU2_BASE_ADDR);
+ debug("bmu2 enabled\n");
+
+ debug("%s: done\n", __func__);
+
+ return ret;
+}
+
+/*
+ * PFE driver init function.
+ * - Initializes pfe_lib
+ * - pfe hw init
+ * - fw loading and enables PEs
+ * - should be executed once.
+ *
+ * @param[in] pfe Pointer the pfe control block
+ */
+int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
+{
+ int ret = 0;
+
+ pfe_lib_init();
+
+ ret = pfe_hw_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ /* Load the class,TM, Util fw.
+ * By now pfe is:
+ * - out of reset + disabled + configured.
+ * Fw loading should be done after pfe_hw_init()
+ */
+ /* It loads default inbuilt sbl firmware */
+ pfe_firmware_init();
+
+ return ret;
+}
+
+/*
+ * PFE remove function
+ * - stops PEs
+ * - frees tx/rx descriptor resources
+ * - should be called once.
+ *
+ * @param[in] pfe Pointer to pfe control block.
+ */
+int pfe_eth_remove(struct udevice *dev)
+{
+ if (g_tx_desc)
+ free(g_tx_desc);
+
+ if (g_rx_desc)
+ free(g_rx_desc);
+
+ pfe_firmware_exit();
+
+ return 0;
+}
diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
new file mode 100644
index 0000000..067343a
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_eth.c
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <pfe_eth/pfe_eth.h>
+#include <pfe_eth/pfe_mdio.h>
+
+struct gemac_s gem_info[] = {
+ /* PORT_0 configuration */
+ {
+ /* GEMAC config */
+ .gemac_speed = PFE_MAC_SPEED_1000M,
+ .gemac_duplex = DUPLEX_FULL,
+
+ /* phy iface */
+ .phy_address = EMAC1_PHY_ADDR,
+ .phy_mode = PHY_INTERFACE_MODE_SGMII,
+ },
+ /* PORT_1 configuration */
+ {
+ /* GEMAC config */
+ .gemac_speed = PFE_MAC_SPEED_1000M,
+ .gemac_duplex = DUPLEX_FULL,
+
+ /* phy iface */
+ .phy_address = EMAC2_PHY_ADDR,
+ .phy_mode = PHY_INTERFACE_MODE_RGMII_TXID,
+ },
+};
+
+static inline void pfe_gemac_enable(void *gemac_base)
+{
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) |
+ EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_disable(void *gemac_base)
+{
+ writel(readl(gemac_base + EMAC_ECNTRL_REG) &
+ ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
+}
+
+static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
+ u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
+ u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
+ ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
+
+ if (speed == _1000BASET) {
+ ecr |= EMAC_ECNTRL_SPEED;
+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
+ } else if (speed != _100BASET) {
+ rcr |= EMAC_RCNTRL_RMII_10T;
+ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
+ }
+
+ writel(ecr, gemac_base + EMAC_ECNTRL_REG);
+ out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
+
+ /* remove loop back */
+ rcr &= ~EMAC_RCNTRL_LOOP;
+ /* enable flow control */
+ rcr |= EMAC_RCNTRL_FCE;
+
+ /* Enable MII mode */
+ rcr |= EMAC_RCNTRL_MII_MODE;
+
+ writel(rcr, gemac_base + EMAC_RCNTRL_REG);
+
+ /* Enable Tx full duplex */
+ writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
+ gemac_base + EMAC_TCNTRL_REG);
+}
+
+static int pfe_eth_write_hwaddr(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct gemac_s *gem = priv->gem;
+ struct eth_pdata *pdata = dev_get_platdata(dev);
+ uchar *mac = pdata->enetaddr;
+
+ writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
+ gem->gemac_base + EMAC_PHY_ADDR_LOW);
+ writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
+ EMAC_PHY_ADDR_HIGH);
+ return 0;
+}
+
+/** Stops or Disables GEMAC pointing to this eth iface.
+ *
+ * @param[in] edev Pointer to eth device structure.
+ *
+ * @return none
+ */
+static inline void pfe_eth_stop(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ pfe_gemac_disable(priv->gem->gemac_base);
+
+ gpi_disable(priv->gem->egpi_base);
+}
+
+static int pfe_eth_start(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct gemac_s *gem = priv->gem;
+ int speed;
+
+ /* set ethernet mac address */
+ pfe_eth_write_hwaddr(dev);
+
+ writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
+ writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
+ writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
+ writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
+ + EMAC_TX_SECTION_EMPTY);
+ writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
+ + EMAC_MIB_CTRL_STS_REG);
+
+#ifdef CONFIG_PHYLIB
+ /* Start up the PHY */
+ if (phy_startup(priv->phydev)) {
+ printf("Could not initialize PHY %s\n",
+ priv->phydev->dev->name);
+ return -1;
+ }
+ speed = priv->phydev->speed;
+ printf("Speed detected %x\n", speed);
+ if (priv->phydev->duplex == DUPLEX_HALF) {
+ printf("Half duplex not supported\n");
+ return -1;
+ }
+#endif
+
+ pfe_gemac_set_speed(gem->gemac_base, speed);
+
+ /* Enable GPI */
+ gpi_enable(gem->egpi_base);
+
+ /* Enable GEMAC */
+ pfe_gemac_enable(gem->gemac_base);
+
+ return 0;
+}
+
+static int pfe_eth_send(struct udevice *dev, void *packet, int length)
+{
+ struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev->priv;
+
+ int rc;
+ int i = 0;
+
+ rc = pfe_send(priv->gemac_port, packet, length);
+
+ if (rc < 0) {
+ printf("Tx Queue full\n");
+ return rc;
+ }
+
+ while (1) {
+ rc = pfe_tx_done();
+ if (rc == 0)
+ break;
+
+ udelay(100);
+ i++;
+ if (i == 30000)
+ printf("Tx timeout, send failed\n");
+ break;
+ }
+
+ return 0;
+}
+
+static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ uchar *pkt_buf;
+ int len;
+ int phy_port;
+
+ len = pfe_recv(&pkt_buf, &phy_port);
+
+ if (len == 0)
+ return -EAGAIN; /* no packet in rx */
+ else if (len < 0)
+ return -EAGAIN;
+
+ debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
+ phy_port, len);
+ if (phy_port != priv->gemac_port) {
+ printf("Rx pkt not on expected port\n");
+ return -EAGAIN;
+ }
+
+ *packetp = pkt_buf;
+
+ return len;
+}
+
+static int pfe_eth_probe(struct udevice *dev)
+{
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct pfe_ddr_address *pfe_addr;
+ struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ int ret = 0;
+ static int init_done;
+
+ if (!init_done) {
+ pfe_addr = (struct pfe_ddr_address *)malloc(sizeof
+ (struct pfe_ddr_address));
+ if (!pfe_addr)
+ return -ENOMEM;
+
+ pfe_addr->ddr_pfe_baseaddr =
+ (void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
+ pfe_addr->ddr_pfe_phys_baseaddr =
+ (unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
+
+ debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
+ pfe_addr->ddr_pfe_baseaddr,
+ (u32)pfe_addr->ddr_pfe_phys_baseaddr);
+
+ ret = pfe_drv_init(pfe_addr);
+ if (ret)
+ return ret;
+
+ init_pfe_scfg_dcfg_regs();
+ init_done = 1;
+ }
+
+ priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
+ priv->gem = &gem_info[priv->gemac_port];
+ priv->dev = dev;
+
+ switch (priv->gemac_port) {
+ case EMAC_PORT_0:
+ default:
+ priv->gem->gemac_base = EMAC1_BASE_ADDR;
+ priv->gem->egpi_base = EGPI1_BASE_ADDR;
+ break;
+ case EMAC_PORT_1:
+ priv->gem->gemac_base = EMAC2_BASE_ADDR;
+ priv->gem->egpi_base = EGPI2_BASE_ADDR;
+ break;
+ }
+
+ ret = pfe_eth_board_init(dev);
+ if (ret)
+ return ret;
+
+#if defined(CONFIG_PHYLIB)
+ ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
+ gem_info[priv->gemac_port].phy_address);
+#endif
+ return ret;
+}
+
+static int pfe_eth_bind(struct udevice *dev)
+{
+ struct pfe_eth_pdata *pdata = dev_get_platdata(dev);
+ char name[20];
+
+ sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
+
+ return device_set_name(dev, name);
+}
+
+static const struct eth_ops pfe_eth_ops = {
+ .start = pfe_eth_start,
+ .send = pfe_eth_send,
+ .recv = pfe_eth_recv,
+ .free_pkt = pfe_eth_free_pkt,
+ .stop = pfe_eth_stop,
+ .write_hwaddr = pfe_eth_write_hwaddr,
+};
+
+U_BOOT_DRIVER(pfe_eth) = {
+ .name = "pfe_eth",
+ .id = UCLASS_ETH,
+ .bind = pfe_eth_bind,
+ .probe = pfe_eth_probe,
+ .remove = pfe_eth_remove,
+ .ops = &pfe_eth_ops,
+ .priv_auto_alloc_size = sizeof(struct pfe_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct pfe_eth_pdata)
+};
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
new file mode 100644
index 0000000..c5c6b98
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * @file
+ * Contains all the functions to handle parsing and loading of PE firmware
+ * files.
+ */
+
+#include <pfe_eth/pfe_eth.h>
+#include <pfe_eth/pfe_firmware.h>
+
+#define PFE_FIRMEWARE_FIT_CNF_NAME "config at 1"
+
+static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR;
+
+/*
+ * PFE elf firmware loader.
+ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
+ *
+ * @param pe_mask Mask of PE id's to load firmware to
+ * @param pfe_firmware Pointer to the firmware image
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_load_elf(int pe_mask, uint8_t *pfe_firmware)
+{
+ Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)pfe_firmware;
+ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
+ Elf32_Shdr *shdr = (Elf32_Shdr *)(pfe_firmware +
+ be32_to_cpu(elf_hdr->e_shoff));
+ int id, section;
+ int ret;
+
+ debug("%s: no of sections: %d\n", __func__, sections);
+
+ /* Some sanity checks */
+ if (strncmp((char *)&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
+ printf("%s: incorrect elf magic number\n", __func__);
+ return -1;
+ }
+
+ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
+ printf("%s: incorrect elf class(%x)\n", __func__,
+ elf_hdr->e_ident[EI_CLASS]);
+ return -1;
+ }
+
+ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
+ printf("%s: incorrect elf data(%x)\n", __func__,
+ elf_hdr->e_ident[EI_DATA]);
+ return -1;
+ }
+
+ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
+ printf("%s: incorrect elf file type(%x)\n", __func__,
+ be16_to_cpu(elf_hdr->e_type));
+ return -1;
+ }
+
+ for (section = 0; section < sections; section++, shdr++) {
+ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
+ SHF_EXECINSTR)))
+ continue;
+ for (id = 0; id < MAX_PE; id++)
+ if (pe_mask & BIT(id)) {
+ ret = pe_load_elf_section(id,
+ pfe_firmware, shdr);
+ if (ret < 0)
+ goto err;
+ }
+ }
+ return 0;
+
+err:
+ return ret;
+}
+
+/*
+ * Get PFE firmware from FIT image
+ *
+ * @param data pointer to PFE firmware
+ * @param size pointer to size of the firmware
+ * @param fw_name pfe firmware name, either class or tmu
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_get_fw(const void **data,
+ size_t *size, char *fw_name)
+{
+ int conf_node_off, fw_node_off;
+ char *conf_node_name = NULL;
+ char *desc;
+ int ret = 0;
+
+ conf_node_name = PFE_FIRMEWARE_FIT_CNF_NAME;
+
+ conf_node_off = fit_conf_get_node(pfe_fit_addr, conf_node_name);
+ if (conf_node_off < 0) {
+ printf("PFE Firmware: %s: no such config\n", conf_node_name);
+ return -ENOENT;
+ }
+
+ fw_node_off = fit_conf_get_prop_node(pfe_fit_addr, conf_node_off,
+ fw_name);
+ if (fw_node_off < 0) {
+ printf("PFE Firmware: No '%s' in config\n",
+ fw_name);
+ return -ENOLINK;
+ }
+
+ if (!(fit_image_verify(pfe_fit_addr, fw_node_off))) {
+ printf("PFE Firmware: Bad firmware image (bad CRC)\n");
+ return -EINVAL;
+ }
+
+ if (fit_image_get_data(pfe_fit_addr, fw_node_off, data, size)) {
+ printf("PFE Firmware: Can't get %s subimage data/size",
+ fw_name);
+ return -ENOENT;
+ }
+
+ ret = fit_get_desc(pfe_fit_addr, fw_node_off, &desc);
+ if (ret)
+ printf("PFE Firmware: Can't get description\n");
+ else
+ printf("%s\n", desc);
+
+ return ret;
+}
+
+/*
+ * Check PFE FIT image
+ *
+ * @return 0 on success, a negative value on error
+ */
+static int pfe_fit_check(void)
+{
+ int ret = 0;
+
+ ret = fdt_check_header(pfe_fit_addr);
+ if (ret) {
+ printf("PFE Firmware: Bad firmware image (not a FIT image)\n");
+ return ret;
+ }
+
+ if (!fit_check_format(pfe_fit_addr)) {
+ printf("PFE Firmware: Bad firmware image (bad FIT header)\n");
+ ret = -1;
+ return ret;
+ }
+
+ return ret;
+}
+
+/*
+ * PFE firmware initialization.
+ * Loads different firmware files from FIT image.
+ * Initializes PE IMEM/DMEM and UTIL-PE DDR
+ * Initializes control path symbol addresses (by looking them up in the elf
+ * firmware files
+ * Takes PE's out of reset
+ *
+ * @return 0 on success, a negative value on error
+ */
+int pfe_firmware_init(void)
+{
+ char *pfe_firmware_name;
+ const void *raw_image_addr;
+ size_t raw_image_size = 0;
+ u8 *pfe_firmware;
+ int ret = 0;
+ int fw_count;
+
+ ret = pfe_fit_check();
+ if (ret)
+ goto err;
+
+ for (fw_count = 0; fw_count < 2; fw_count++) {
+ if (fw_count == 0)
+ pfe_firmware_name = "class";
+ else if (fw_count == 1)
+ pfe_firmware_name = "tmu";
+
+ pfe_get_fw(&raw_image_addr, &raw_image_size, pfe_firmware_name);
+ pfe_firmware = malloc(raw_image_size);
+ if (!pfe_firmware)
+ return -ENOMEM;
+ memcpy((void *)pfe_firmware, (void *)raw_image_addr,
+ raw_image_size);
+
+ if (fw_count == 0)
+ ret = pfe_load_elf(CLASS_MASK, pfe_firmware);
+ else if (fw_count == 1)
+ ret = pfe_load_elf(TMU_MASK, pfe_firmware);
+
+ if (ret < 0) {
+ printf("%s: %s firmware load failed\n", __func__,
+ pfe_firmware_name);
+ goto err;
+ }
+ debug("%s: %s firmware loaded\n", __func__, pfe_firmware_name);
+ free(pfe_firmware);
+ }
+
+ tmu_enable(0xb);
+ class_enable();
+ gpi_enable(HGPI_BASE_ADDR);
+
+err:
+ return ret;
+}
+
+/*
+ * PFE firmware cleanup
+ * Puts PE's in reset
+ */
+void pfe_firmware_exit(void)
+{
+ debug("%s\n", __func__);
+
+ class_disable();
+ tmu_disable(0xf);
+ hif_tx_disable();
+ hif_rx_disable();
+}
diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c
new file mode 100644
index 0000000..42513f6
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_hw.c
@@ -0,0 +1,999 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include <pfe_eth/pfe_eth.h>
+#include <pfe_eth/pfe/pfe_hw.h>
+
+static struct pe_info pe[MAX_PE];
+
+/*
+ * Initializes the PFE library.
+ * Must be called before using any of the library functions.
+ */
+void pfe_lib_init(void)
+{
+ int pfe_pe_id;
+
+ for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+ pe[pfe_pe_id].dmem_base_addr =
+ (u32)CLASS_DMEM_BASE_ADDR(pfe_pe_id);
+ pe[pfe_pe_id].pmem_base_addr =
+ (u32)CLASS_IMEM_BASE_ADDR(pfe_pe_id);
+ pe[pfe_pe_id].pmem_size = (u32)CLASS_IMEM_SIZE;
+ pe[pfe_pe_id].mem_access_wdata =
+ (void *)CLASS_MEM_ACCESS_WDATA;
+ pe[pfe_pe_id].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
+ pe[pfe_pe_id].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
+ }
+
+ for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+ if (pfe_pe_id == TMU2_ID)
+ continue;
+ pe[pfe_pe_id].dmem_base_addr =
+ (u32)TMU_DMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+ pe[pfe_pe_id].pmem_base_addr =
+ (u32)TMU_IMEM_BASE_ADDR(pfe_pe_id - TMU0_ID);
+ pe[pfe_pe_id].pmem_size = (u32)TMU_IMEM_SIZE;
+ pe[pfe_pe_id].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
+ pe[pfe_pe_id].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
+ pe[pfe_pe_id].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
+ }
+}
+
+/*
+ * Writes a buffer to PE internal memory from the host
+ * through indirect access registers.
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] mem_access_addr DMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src,
+ unsigned int len)
+{
+ u32 offset = 0, val, addr;
+ unsigned int len32 = len >> 2;
+ int i;
+
+ addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
+
+ for (i = 0; i < len32; i++, offset += 4, src += 4) {
+ val = *(u32 *)src;
+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+ writel(addr + offset, pe[id].mem_access_addr);
+ }
+
+ len = (len & 0x3);
+ if (len) {
+ val = 0;
+
+ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
+
+ for (i = 0; i < len; i++, src++)
+ val |= (*(u8 *)src) << (8 * i);
+
+ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
+ writel(addr, pe[id].mem_access_addr);
+ }
+}
+
+/*
+ * Writes a buffer to PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] dst DMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_dmem_memcpy_to32(int id, u32 dst, const void *src,
+ unsigned int len)
+{
+ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM,
+ src, len);
+}
+
+/*
+ * Writes a buffer to PE internal program memory (PMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., TMU3_ID)
+ * @param[in] dst PMEM destination address (must be 32bit
+ * aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void pe_pmem_memcpy_to32(int id, u32 dst, const void *src,
+ unsigned int len)
+{
+ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
+ - 1)) | PE_MEM_ACCESS_IMEM, src, len);
+}
+
+/*
+ * Reads PE internal program memory (IMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., TMU3_ID)
+ * @param[in] addr PMEM read address (must be aligned on size)
+ * @param[in] size Number of bytes to read (maximum 4, must not
+ * cross 32bit boundaries)
+ * @return the data read (in PE endianness, i.e BE).
+ */
+u32 pe_pmem_read(int id, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
+ | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM |
+ PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ writel(addr, pe[id].mem_access_addr);
+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] val Value to write (in PE endianness, i.e BE)
+ * @param[in] addr DMEM write address (must be aligned on size)
+ * @param[in] size Number of bytes to write (maximum 4, must not
+ * cross 32bit boundaries)
+ */
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+
+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
+ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ /* Indirect access interface is byte swapping data being written */
+ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
+ writel(addr, pe[id].mem_access_addr);
+}
+
+/*
+ * Reads PE internal data memory (DMEM) from the host
+ * through indirect access registers.
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] addr DMEM read address (must be aligned on size)
+ * @param[in] size Number of bytes to read (maximum 4, must not
+ * cross 32bit boundaries)
+ * @return the data read (in PE endianness, i.e BE).
+ */
+u32 pe_dmem_read(int id, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ |
+ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
+
+ writel(addr, pe[id].mem_access_addr);
+
+ /* Indirect access interface is byte swapping data being read */
+ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * This function is used to write to CLASS internal bus peripherals (ccu,
+ * pe-lem) from the host
+ * through indirect access registers.
+ * @param[in] val value to write
+ * @param[in] addr Address to write to (must be aligned on size)
+ * @param[in] size Number of bytes to write (1, 2 or 4)
+ *
+ */
+static void class_bus_write(u32 val, u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+
+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
+ (size << 24);
+
+ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
+ writel(addr, CLASS_BUS_ACCESS_ADDR);
+}
+
+/*
+ * Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
+ * through indirect access registers.
+ * @param[in] addr Address to read from (must be aligned on size)
+ * @param[in] size Number of bytes to read (1, 2 or 4)
+ * @return the read data
+ */
+static u32 class_bus_read(u32 addr, u8 size)
+{
+ u32 offset = addr & 0x3;
+ u32 mask = 0xffffffff >> ((4 - size) << 3);
+ u32 val;
+
+ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
+
+ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
+
+ writel(addr, CLASS_BUS_ACCESS_ADDR);
+ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
+
+ return (val >> (offset << 3)) & mask;
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
+ * @param[in] src Buffer source address
+ * @param[in] len Number of bytes to copy
+ */
+static void class_pe_lmem_memcpy_to32(u32 dst, const void *src,
+ unsigned int len)
+{
+ u32 len32 = len >> 2;
+ int i;
+
+ for (i = 0; i < len32; i++, src += 4, dst += 4)
+ class_bus_write(*(u32 *)src, dst, 4);
+
+ if (len & 0x2) {
+ class_bus_write(*(u16 *)src, dst, 2);
+ src += 2;
+ dst += 2;
+ }
+
+ if (len & 0x1) {
+ class_bus_write(*(u8 *)src, dst, 1);
+ src++;
+ dst++;
+ }
+}
+
+/*
+ * Writes value to the cluster memory (PE_LMEM)
+ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
+ * @param[in] val Value to write
+ * @param[in] len Number of bytes to write
+ */
+static void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
+{
+ u32 len32 = len >> 2;
+ int i;
+
+ val = val | (val << 8) | (val << 16) | (val << 24);
+
+ for (i = 0; i < len32; i++, dst += 4)
+ class_bus_write(val, dst, 4);
+
+ if (len & 0x2) {
+ class_bus_write(val, dst, 2);
+ dst += 2;
+ }
+
+ if (len & 0x1) {
+ class_bus_write(val, dst, 1);
+ dst++;
+ }
+}
+
+/*
+ * Reads data from the cluster memory (PE_LMEM)
+ * @param[out] dst pointer to the source buffer data are copied to
+ * @param[in] len length in bytes of the amount of data to read
+ * from cluster memory
+ * @param[in] offset offset in bytes in the cluster memory where data are
+ * read from
+ */
+void pe_lmem_read(u32 *dst, u32 len, u32 offset)
+{
+ u32 len32 = len >> 2;
+ int i = 0;
+
+ for (i = 0; i < len32; dst++, i++, offset += 4)
+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
+
+ if (len & 0x03)
+ *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
+}
+
+/*
+ * Writes data to the cluster memory (PE_LMEM)
+ * @param[in] src pointer to the source buffer data are copied from
+ * @param[in] len length in bytes of the amount of data to write to the
+ * cluster memory
+ * @param[in] offset offset in bytes in the cluster memory where data are
+ * written to
+ */
+void pe_lmem_write(u32 *src, u32 len, u32 offset)
+{
+ u32 len32 = len >> 2;
+ int i = 0;
+
+ for (i = 0; i < len32; src++, i++, offset += 4)
+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
+
+ if (len & 0x03)
+ class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len &
+ 0x03));
+}
+
+/*
+ * Loads an elf section into pmem
+ * Code needs to be@least 16bit aligned and only PROGBITS sections are
+ * supported
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ...,
+ * TMU3_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x1) {
+ printf("%s: load address(%x) is not 16bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ if (size & 0x1) {
+ printf("%s: load size(%x) is not 16bit aligned\n", __func__,
+ size);
+ return -1;
+ }
+
+ debug("pmem pe%d @%x len %d\n", id, addr, size);
+ switch (type) {
+ case SHT_PROGBITS:
+ pe_pmem_memcpy_to32(id, addr, data + offset, size);
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into dmem
+ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+ u32 size32 = size >> 2;
+ int i;
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x3) {
+ printf("%s: load address(%x) is not 32bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ switch (type) {
+ case SHT_PROGBITS:
+ debug("dmem pe%d @%x len %d\n", id, addr, size);
+ pe_dmem_memcpy_to32(id, addr, data + offset, size);
+ break;
+
+ case SHT_NOBITS:
+ debug("dmem zero pe%d @%x len %d\n", id, addr, size);
+ for (i = 0; i < size32; i++, addr += 4)
+ pe_dmem_write(id, 0, addr, 4);
+
+ if (size & 0x3)
+ pe_dmem_write(id, 0, addr, size & 0x3);
+
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into DDR
+ * Data needs to be@least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+ u32 flags = be32_to_cpu(shdr->sh_flags);
+
+ switch (type) {
+ case SHT_PROGBITS:
+ debug("ddr pe%d @%x len %d\n", id, addr, size);
+ if (flags & SHF_EXECINSTR) {
+ if (id <= CLASS_MAX_ID) {
+ /* DO the loading only once in DDR */
+ if (id == CLASS0_ID) {
+ debug(
+ "%s: load address(%x) and elf file address(%lx) rcvd\n"
+ , __func__, addr,
+ (unsigned long)data + offset);
+ if (((unsigned long)(data + offset)
+ & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr,
+ (unsigned long)data +
+ offset);
+
+ return -1;
+ }
+
+ if (addr & 0x1) {
+ printf(
+ "%s: load address(%x) is not 16bit aligned\n"
+ , __func__, addr);
+ return -1;
+ }
+
+ if (size & 0x1) {
+ printf(
+ "%s: load length(%x) is not 16bit aligned\n"
+ , __func__, size);
+ return -1;
+ }
+
+ memcpy((void *)DDR_PFE_TO_VIRT(addr),
+ data + offset, size);
+ }
+ } else {
+ printf(
+ "%s: unsupported ddr section type(%x) for PE(%d)\n"
+ , __func__, type, id);
+ return -1;
+ }
+
+ } else {
+ memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset,
+ size);
+ }
+
+ break;
+
+ case SHT_NOBITS:
+ debug("ddr zero pe%d @%x len %d\n", id, addr, size);
+ memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
+
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into pe lmem
+ * Data needs to be@least 32bit aligned, NOBITS sections are correctly
+ * initialized to 0
+ *
+ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 offset = be32_to_cpu(shdr->sh_offset);
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+ u32 type = be32_to_cpu(shdr->sh_type);
+
+ if (id > CLASS_MAX_ID) {
+ printf("%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
+ __func__, type, id);
+ return -1;
+ }
+
+ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
+ printf(
+ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
+ __func__, addr, (unsigned long)data + offset);
+
+ return -1;
+ }
+
+ if (addr & 0x3) {
+ printf("%s: load address(%x) is not 32bit aligned\n",
+ __func__, addr);
+ return -1;
+ }
+
+ debug("lmem pe%d @%x len %d\n", id, addr, size);
+
+ switch (type) {
+ case SHT_PROGBITS:
+ class_pe_lmem_memcpy_to32(addr, data + offset, size);
+ break;
+
+ case SHT_NOBITS:
+ class_pe_lmem_memset(addr, 0, size);
+ break;
+
+ default:
+ printf("%s: unsupported section type(%x)\n", __func__, type);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Loads an elf section into a PE
+ * For now only supports loading a section to dmem (all PE's), pmem (class and
+ * tmu PE's), DDDR (util PE code)
+ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
+ * ..., UTIL_ID)
+ * @param[in] data pointer to the elf firmware
+ * @param[in] shdr pointer to the elf section header
+ */
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
+{
+ u32 addr = be32_to_cpu(shdr->sh_addr);
+ u32 size = be32_to_cpu(shdr->sh_size);
+
+ if (IS_DMEM(addr, size))
+ return pe_load_dmem_section(id, data, shdr);
+ else if (IS_PMEM(addr, size))
+ return pe_load_pmem_section(id, data, shdr);
+ else if (IS_PFE_LMEM(addr, size))
+ return 0;
+ else if (IS_PHYS_DDR(addr, size))
+ return pe_load_ddr_section(id, data, shdr);
+ else if (IS_PE_LMEM(addr, size))
+ return pe_load_pe_lmem_section(id, data, shdr);
+
+ printf("%s: unsupported memory range(%x)\n", __func__, addr);
+
+ return 0;
+}
+
+/**************************** BMU ***************************/
+/*
+ * Resets a BMU block.
+ * @param[in] base BMU block base address
+ */
+static inline void bmu_reset(void *base)
+{
+ writel(CORE_SW_RESET, base + BMU_CTRL);
+
+ /* Wait for self clear */
+ while (readl(base + BMU_CTRL) & CORE_SW_RESET)
+ ;
+}
+
+/*
+ * Enabled a BMU block.
+ * @param[in] base BMU block base address
+ */
+void bmu_enable(void *base)
+{
+ writel(CORE_ENABLE, base + BMU_CTRL);
+}
+
+/*
+ * Disables a BMU block.
+ * @param[in] base BMU block base address
+ */
+static inline void bmu_disable(void *base)
+{
+ writel(CORE_DISABLE, base + BMU_CTRL);
+}
+
+/*
+ * Sets the configuration of a BMU block.
+ * @param[in] base BMU block base address
+ * @param[in] cfg BMU configuration
+ */
+static inline void bmu_set_config(void *base, struct bmu_cfg *cfg)
+{
+ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
+ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
+ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
+
+ /* Interrupts are never used */
+ writel(0x0, base + BMU_INT_ENABLE);
+}
+
+/*
+ * Initializes a BMU block.
+ * @param[in] base BMU block base address
+ * @param[in] cfg BMU configuration
+ */
+void bmu_init(void *base, struct bmu_cfg *cfg)
+{
+ bmu_disable(base);
+
+ bmu_set_config(base, cfg);
+
+ bmu_reset(base);
+}
+
+/**************************** GPI ***************************/
+/*
+ * Resets a GPI block.
+ * @param[in] base GPI base address
+ */
+static inline void gpi_reset(void *base)
+{
+ writel(CORE_SW_RESET, base + GPI_CTRL);
+}
+
+/*
+ * Enables a GPI block.
+ * @param[in] base GPI base address
+ */
+void gpi_enable(void *base)
+{
+ writel(CORE_ENABLE, base + GPI_CTRL);
+}
+
+/*
+ * Disables a GPI block.
+ * @param[in] base GPI base address
+ */
+void gpi_disable(void *base)
+{
+ writel(CORE_DISABLE, base + GPI_CTRL);
+}
+
+/*
+ * Sets the configuration of a GPI block.
+ * @param[in] base GPI base address
+ * @param[in] cfg GPI configuration
+ */
+static inline void gpi_set_config(void *base, struct gpi_cfg *cfg)
+{
+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base
+ + GPI_LMEM_ALLOC_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base
+ + GPI_LMEM_FREE_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base
+ + GPI_DDR_ALLOC_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base
+ + GPI_DDR_FREE_ADDR);
+ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
+ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
+ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
+ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
+ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
+ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
+
+ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
+ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
+ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
+ writel(cfg->aseq_len, base + GPI_DTX_ASEQ);
+
+ /*Make GPI AXI transactions non-bufferable */
+ writel(0x1, base + GPI_AXI_CTRL);
+}
+
+/*
+ * Initializes a GPI block.
+ * @param[in] base GPI base address
+ * @param[in] cfg GPI configuration
+ */
+void gpi_init(void *base, struct gpi_cfg *cfg)
+{
+ gpi_reset(base);
+
+ gpi_disable(base);
+
+ gpi_set_config(base, cfg);
+}
+
+/**************************** CLASSIFIER ***************************/
+/*
+ * Resets CLASSIFIER block.
+ */
+static inline void class_reset(void)
+{
+ writel(CORE_SW_RESET, CLASS_TX_CTRL);
+}
+
+/*
+ * Enables all CLASS-PE's cores.
+ */
+void class_enable(void)
+{
+ writel(CORE_ENABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Disables all CLASS-PE's cores.
+ */
+void class_disable(void)
+{
+ writel(CORE_DISABLE, CLASS_TX_CTRL);
+}
+
+/*
+ * Sets the configuration of the CLASSIFIER block.
+ * @param[in] cfg CLASSIFIER configuration
+ */
+static inline void class_set_config(struct class_cfg *cfg)
+{
+ if (PLL_CLK_EN == 0) {
+ /* Clock ratio: for 1:1 the value is 0 */
+ writel(0x0, CLASS_PE_SYS_CLK_RATIO);
+ } else {
+ /* Clock ratio: for 1:2 the value is 1 */
+ writel(0x1, CLASS_PE_SYS_CLK_RATIO);
+ }
+ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
+ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
+ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
+ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
+ CLASS_ROUTE_HASH_ENTRY_SIZE);
+ writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
+
+ writel(cfg->route_table_baseaddr, CLASS_ROUTE_TABLE_BASE);
+ memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0,
+ ROUTE_TABLE_SIZE);
+
+ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
+ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
+ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
+ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
+ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
+
+ writel(23, CLASS_AFULL_THRES);
+ writel(23, CLASS_TSQ_FIFO_THRES);
+
+ writel(24, CLASS_MAX_BUF_CNT);
+ writel(24, CLASS_TSQ_MAX_CNT);
+
+ /*Make Class AXI transactions non-bufferable */
+ writel(0x1, CLASS_AXI_CTRL);
+
+ /*Make Util AXI transactions non-bufferable */
+ /*Util is disabled in U-boot, do it from here */
+ writel(0x1, UTIL_AXI_CTRL);
+}
+
+/*
+ * Initializes CLASSIFIER block.
+ * @param[in] cfg CLASSIFIER configuration
+ */
+void class_init(struct class_cfg *cfg)
+{
+ class_reset();
+
+ class_disable();
+
+ class_set_config(cfg);
+}
+
+/**************************** TMU ***************************/
+/*
+ * Enables TMU-PE cores.
+ * @param[in] pe_mask TMU PE mask
+ */
+void tmu_enable(u32 pe_mask)
+{
+ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Disables TMU cores.
+ * @param[in] pe_mask TMU PE mask
+ */
+void tmu_disable(u32 pe_mask)
+{
+ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
+}
+
+/*
+ * Initializes TMU block.
+ * @param[in] cfg TMU configuration
+ */
+void tmu_init(struct tmu_cfg *cfg)
+{
+ int q, phyno;
+
+ /* keep in soft reset */
+ writel(SW_RESET, TMU_CTRL);
+
+ /*Make Class AXI transactions non-bufferable */
+ writel(0x1, TMU_AXI_CTRL);
+
+ /* enable EMAC PHY ports */
+ writel(0x3, TMU_SYS_GENERIC_CONTROL);
+
+ writel(750, TMU_INQ_WATERMARK);
+
+ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY0_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY1_INQ_ADDR);
+
+ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),
+ TMU_PHY3_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
+ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
+ TMU_BMU_INQ_ADDR);
+
+ /* enabling all 10 schedulers [9:0] of each TDQ */
+ writel(0x3FF, TMU_TDQ0_SCH_CTRL);
+ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
+ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
+
+ if (PLL_CLK_EN == 0) {
+ /* Clock ratio: for 1:1 the value is 0 */
+ writel(0x0, TMU_PE_SYS_CLK_RATIO);
+ } else {
+ /* Clock ratio: for 1:2 the value is 1 */
+ writel(0x1, TMU_PE_SYS_CLK_RATIO);
+ }
+
+ /* Extra packet pointers will be stored from this address onwards */
+ debug("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
+ writel(cfg->llm_base_addr, TMU_LLM_BASE_ADDR);
+
+ debug("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
+ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
+
+ writel(5, TMU_TDQ_IIFG_CFG);
+ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
+
+ writel(0x0, TMU_CTRL);
+
+ /* MEM init */
+ writel(MEM_INIT, TMU_CTRL);
+
+ while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
+ ;
+
+ /* LLM init */
+ writel(LLM_INIT, TMU_CTRL);
+
+ while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
+ ;
+
+ /* set up each queue for tail drop */
+ for (phyno = 0; phyno < 4; phyno++) {
+ if (phyno == 2)
+ continue;
+ for (q = 0; q < 16; q++) {
+ u32 qmax;
+
+ writel((phyno << 8) | q, TMU_TEQ_CTRL);
+ writel(BIT(22), TMU_TEQ_QCFG);
+
+ if (phyno == 3)
+ qmax = DEFAULT_TMU3_QDEPTH;
+ else
+ qmax = (q == 0) ? DEFAULT_Q0_QDEPTH :
+ DEFAULT_MAX_QDEPTH;
+
+ writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
+ writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
+ }
+ }
+ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
+ writel(0, TMU_CTRL);
+}
+
+/**************************** HIF ***************************/
+/*
+ * Enable hif tx DMA and interrupt
+ */
+void hif_tx_enable(void)
+{
+ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
+}
+
+/*
+ * Disable hif tx DMA and interrupt
+ */
+void hif_tx_disable(void)
+{
+ u32 hif_int;
+
+ writel(0, HIF_TX_CTRL);
+
+ hif_int = readl(HIF_INT_ENABLE);
+ hif_int &= HIF_TXPKT_INT_EN;
+ writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Enable hif rx DMA and interrupt
+ */
+void hif_rx_enable(void)
+{
+ writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
+}
+
+/*
+ * Disable hif rx DMA and interrupt
+ */
+void hif_rx_disable(void)
+{
+ u32 hif_int;
+
+ writel(0, HIF_RX_CTRL);
+
+ hif_int = readl(HIF_INT_ENABLE);
+ hif_int &= HIF_RXPKT_INT_EN;
+ writel(hif_int, HIF_INT_ENABLE);
+}
+
+/*
+ * Initializes HIF copy block.
+ */
+void hif_init(void)
+{
+ /* Initialize HIF registers */
+ writel(HIF_RX_POLL_CTRL_CYCLE << 16 | HIF_TX_POLL_CTRL_CYCLE,
+ HIF_POLL_CTRL);
+ /* Make HIF AXI transactions non-bufferable */
+ writel(0x1, HIF_AXI_CTRL);
+}
diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c
new file mode 100644
index 0000000..14c31cd
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_mdio.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <net.h>
+#include <pfe_eth/pfe_eth.h>
+
+extern struct gemac_s gem_info[];
+#if defined(CONFIG_PHYLIB)
+
+#define MDIO_TIMEOUT 5000
+static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ void *reg_base = bus->priv;
+ u32 devadr;
+ u32 phy;
+ u32 reg_data;
+ int timeout = MDIO_TIMEOUT;
+
+ devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ return 0;
+}
+
+static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ void *reg_base = bus->priv;
+ u32 reg;
+ u32 phy;
+ u32 reg_data;
+ u16 val;
+ int timeout = MDIO_TIMEOUT;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ } else {
+ pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+ reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ }
+
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ if (dev_addr == MDIO_DEVAD_NONE)
+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
+ EMAC_MII_DATA_TA | phy | reg);
+ else
+ reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA |
+ phy | reg);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ /*
+ * it's now safe to read the PHY's register
+ */
+ val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
+ debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
+ phy_addr, reg_addr, val);
+
+ return val;
+}
+
+static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr, u16 data)
+{
+ void *reg_base = bus->priv;
+ u32 reg;
+ u32 phy;
+ u32 reg_data;
+ int timeout = MDIO_TIMEOUT;
+ int val;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ } else {
+ pfe_write_addr(bus, phy_addr, dev_addr, reg_addr);
+ reg = ((dev_addr & EMAC_MII_DATA_RA_MASK) <<
+ EMAC_MII_DATA_RA_SHIFT);
+ }
+
+ phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
+
+ if (dev_addr == MDIO_DEVAD_NONE)
+ reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
+ EMAC_MII_DATA_TA | phy | reg | data);
+ else
+ reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA |
+ phy | reg | data);
+
+ writel(reg_data, reg_base + EMAC_MII_DATA_REG);
+
+ /*
+ * wait for the MII interrupt
+ */
+ while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
+ if (timeout-- <= 0) {
+ printf("Phy MDIO read/write timeout\n");
+ return -1;
+ }
+ }
+
+ /*
+ * clear MII interrupt
+ */
+ writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
+
+ debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr,
+ reg_addr, data);
+
+ return val;
+}
+
+static void pfe_configure_serdes(struct pfe_eth_dev *priv)
+{
+ struct mii_dev bus;
+ int value, sgmii_2500 = 0;
+ struct gemac_s *gem = priv->gem;
+
+ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
+ sgmii_2500 = 1;
+
+ printf("%s %d\n", __func__, priv->gemac_port);
+
+ /* PCS configuration done with corresponding GEMAC */
+ bus.priv = gem_info[priv->gemac_port].gemac_base;
+
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
+ pfe_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
+
+ /* Reset serdes */
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
+
+ /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
+ value = PHY_SGMII_IF_MODE_SGMII;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_IF_MODE_AN;
+ else
+ value |= PHY_SGMII_IF_MODE_SGMII_GBT;
+
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+
+ /* Dev ability according to SGMII specification */
+ value = PHY_SGMII_DEV_ABILITY_SGMII;
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+
+ /* These values taken from validation team */
+ if (!sgmii_2500) {
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
+ } else {
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x7);
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xa120);
+ }
+
+ /* Restart AN */
+ value = PHY_SGMII_CR_DEF_VAL;
+ if (!sgmii_2500)
+ value |= PHY_SGMII_CR_RESET_AN;
+ /* Disable Auto neg for 2.5G SGMII as it doesn't support auto neg*/
+ if (sgmii_2500)
+ value &= ~PHY_SGMII_ENABLE_AN;
+ pfe_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+}
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id)
+{
+ struct phy_device *phydev = NULL;
+ struct udevice *dev = priv->dev;
+ struct gemac_s *gem = priv->gem;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+ if (!gem->bus)
+ return -1;
+
+ /* Configure SGMII PCS */
+ if (gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
+ gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500) {
+ out_be32(&scfg->mdioselcr, 0x00000000);
+ pfe_configure_serdes(priv);
+ }
+
+ mdelay(100);
+
+ /* By this time on-chip SGMII initialization is done
+ * we can switch mdio interface to external PHYs
+ */
+ out_be32(&scfg->mdioselcr, 0x80000000);
+
+ phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
+ if (!phydev) {
+ printf("phy_connect failed\n");
+ return -ENODEV;
+ }
+
+ phy_config(phydev);
+
+ priv->phydev = phydev;
+
+ return 0;
+}
+#endif
+
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info)
+{
+ struct mii_dev *bus;
+ int ret;
+ u32 mdio_speed;
+ u32 pclk = 250000000;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf("mdio_alloc failed\n");
+ return NULL;
+ }
+ bus->read = pfe_phy_read;
+ bus->write = pfe_phy_write;
+
+ /* MAC1 MDIO used to communicate with external PHYS */
+ bus->priv = mdio_info->reg_base;
+ sprintf(bus->name, mdio_info->name);
+
+ /* configure mdio speed */
+ mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
+ mdio_speed |= EMAC_HOLDTIME(0x5);
+ writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
+
+ ret = mdio_register(bus);
+ if (ret) {
+ printf("mdio_register failed\n");
+ free(bus);
+ return NULL;
+ }
+ return bus;
+}
+
+void pfe_set_mdio(int dev_id, struct mii_dev *bus)
+{
+ gem_info[dev_id].bus = bus;
+}
+
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
+{
+ gem_info[dev_id].phy_address = phy_id;
+ gem_info[dev_id].phy_mode = phy_mode;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (2 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:21 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers Calvin Johnson
` (10 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
pfe_command provides command line support for several features that
support pfe, like starting or stopping the pfe, checking the health
of the processor engines and checking status of different units inside
pfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-remove unused code under CONFIG_UTIL_PE_DISABLED
-remove unused code under CONFIG_PFE_WARN_WA
---
drivers/net/pfe_eth/pfe_cmd.c | 497 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 497 insertions(+)
create mode 100644 drivers/net/pfe_eth/pfe_cmd.c
diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
new file mode 100644
index 0000000..41c9c9b
--- /dev/null
+++ b/drivers/net/pfe_eth/pfe_cmd.c
@@ -0,0 +1,497 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
+ * @file
+ * @brief PFE utility commands
+ */
+
+#include <pfe_eth/pfe_eth.h>
+
+static inline void pfe_command_help(void)
+{
+ printf("Usage: pfe [pe | status | expt ] <options>\n");
+}
+
+static void pfe_command_pe(int argc, char * const argv[])
+{
+ if (argc >= 3 && strcmp(argv[2], "pmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ int id;
+ u32 addr;
+ u32 size;
+ u32 val;
+
+ if (argc == 7) {
+ num = simple_strtoul(argv[6], NULL, 0);
+ } else if (argc == 6) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ addr = simple_strtoul(argv[5], NULL, 16);
+ size = 4;
+
+ for (i = 0; i < num; i++, addr += 4) {
+ val = pe_pmem_read(id, addr, size);
+ val = be32_to_cpu(val);
+ if (!(i & 3))
+ printf("%08x: ", addr);
+ printf("%08x%s", val, i == num - 1 || (i & 3)
+ == 3 ? "\n" : " ");
+ }
+
+ } else {
+ printf("Usage: pfe pe pmem read <parameters>\n");
+ }
+ } else if (argc >= 3 && strcmp(argv[2], "dmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ int id;
+ u32 addr;
+ u32 size;
+ u32 val;
+
+ if (argc == 7) {
+ num = simple_strtoul(argv[6], NULL, 0);
+ } else if (argc == 6) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ addr = simple_strtoul(argv[5], NULL, 16);
+ size = 4;
+
+ for (i = 0; i < num; i++, addr += 4) {
+ val = pe_dmem_read(id, addr, size);
+ val = be32_to_cpu(val);
+ if (!(i & 3))
+ printf("%08x: ", addr);
+ printf("%08x%s", val, i == num - 1 || (i & 3)
+ == 3 ? "\n" : " ");
+ }
+
+ } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+ int id;
+ u32 val;
+ u32 addr;
+ u32 size;
+
+ if (argc != 7) {
+ printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
+ return;
+ }
+
+ id = simple_strtoul(argv[4], NULL, 0);
+ val = simple_strtoul(argv[5], NULL, 16);
+ val = cpu_to_be32(val);
+ addr = simple_strtoul(argv[6], NULL, 16);
+ size = 4;
+ pe_dmem_write(id, val, addr, size);
+ } else {
+ printf("Usage: pfe pe dmem [read | write] <parameters>\n");
+ }
+ } else if (argc >= 3 && strcmp(argv[2], "lmem") == 0) {
+ if (argc >= 4 && strcmp(argv[3], "read") == 0) {
+ int i;
+ int num;
+ u32 val;
+ u32 offset;
+
+ if (argc == 6) {
+ num = simple_strtoul(argv[5], NULL, 0);
+ } else if (argc == 5) {
+ num = 1;
+ } else {
+ printf("Usage: pfe pe lmem read <offset> [<num>]\n");
+ return;
+ }
+
+ offset = simple_strtoul(argv[4], NULL, 16);
+
+ for (i = 0; i < num; i++, offset += 4) {
+ pe_lmem_read(&val, 4, offset);
+ val = be32_to_cpu(val);
+ printf("%08x%s", val, i == num - 1 || (i & 7)
+ == 7 ? "\n" : " ");
+ }
+
+ } else if (argc >= 4 && strcmp(argv[3], "write") == 0) {
+ u32 val;
+ u32 offset;
+
+ if (argc != 6) {
+ printf("Usage: pfe pe lmem write <val> <offset>\n");
+ return;
+ }
+
+ val = simple_strtoul(argv[4], NULL, 16);
+ val = cpu_to_be32(val);
+ offset = simple_strtoul(argv[5], NULL, 16);
+ pe_lmem_write(&val, 4, offset);
+ } else {
+ printf("Usage: pfe pe lmem [read | write] <parameters>\n");
+ }
+ } else {
+ if (strcmp(argv[2], "help") != 0)
+ printf("Unknown option: %s\n", argv[2]);
+
+ printf("Usage: pfe pe <parameters>\n");
+ }
+}
+
+#define NUM_QUEUES 16
+
+/*
+ * qm_read_drop_stat
+ * This function is used to read the drop statistics from the TMU
+ * hw drop counter. Since the hw counter is always cleared afer
+ * reading, this function maintains the previous drop count, and
+ * adds the new value to it. That value can be retrieved by
+ * passing a pointer to it with the total_drops arg.
+ *
+ * @param tmu TMU number (0 - 3)
+ * @param queue queue number (0 - 15)
+ * @param total_drops pointer to location to store total drops (or NULL)
+ * @param do_reset if TRUE, clear total drops after updating
+ *
+ */
+u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
+{
+ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
+ u32 val;
+
+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
+ val = readl(TMU_TEQ_DROP_STAT);
+ qtotal[tmu][queue] += val;
+ if (total_drops)
+ *total_drops = qtotal[tmu][queue];
+ if (do_reset)
+ qtotal[tmu][queue] = 0;
+ return val;
+}
+
+static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
+{
+ ssize_t len = 0;
+ u32 drops;
+
+ printf("%d-%02d, ", tmu, queue);
+
+ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
+
+ /* Select queue */
+ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
+ writel((tmu << 8) | queue, TMU_LLM_CTRL);
+
+ printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
+ drops, readl(TMU_TEQ_TRANS_STAT),
+ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
+ readl(TMU_LLM_QUE_DROPCNT));
+
+ return len;
+}
+
+static ssize_t tmu_queues(char *buf, int tmu)
+{
+ ssize_t len = 0;
+ int queue;
+
+ for (queue = 0; queue < 16; queue++)
+ len += tmu_queue_stats(buf + len, tmu, queue);
+
+ return len;
+}
+
+static inline void hif_status(void)
+{
+ printf("hif:\n");
+
+ printf(" tx curr bd: %x\n", readl(HIF_TX_CURR_BD_ADDR));
+ printf(" tx status: %x\n", readl(HIF_TX_STATUS));
+ printf(" tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
+
+ printf(" rx curr bd: %x\n", readl(HIF_RX_CURR_BD_ADDR));
+ printf(" rx status: %x\n", readl(HIF_RX_STATUS));
+ printf(" rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
+
+ printf("hif nocopy:\n");
+
+ printf(" tx curr bd: %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
+ printf(" tx status: %x\n", readl(HIF_NOCPY_TX_STATUS));
+ printf(" tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
+
+ printf(" rx curr bd: %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
+ printf(" rx status: %x\n", readl(HIF_NOCPY_RX_STATUS));
+ printf(" rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
+}
+
+static void gpi(int id, void *base)
+{
+ u32 val;
+
+ printf("%s%d:\n", __func__, id);
+
+ printf(" tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
+ val = readl(base + GPI_FIFO_DEBUG);
+ printf(" tx pkts: %x\n", (val >> 23) & 0x3f);
+ printf(" rx pkts: %x\n", (val >> 18) & 0x3f);
+ printf(" tx bytes: %x\n", (val >> 9) & 0x1ff);
+ printf(" rx bytes: %x\n", (val >> 0) & 0x1ff);
+ printf(" overrun: %x\n", readl(base + GPI_OVERRUN_DROPCNT));
+}
+
+static void bmu(int id, void *base)
+{
+ printf("%s%d:\n", __func__, id);
+
+ printf(" buf size: %x\n", (1 << readl(base + BMU_BUF_SIZE)));
+ printf(" buf count: %x\n", readl(base + BMU_BUF_CNT));
+ printf(" buf rem: %x\n", readl(base + BMU_REM_BUF_CNT));
+ printf(" buf curr: %x\n", readl(base + BMU_CURR_BUF_CNT));
+ printf(" free err: %x\n", readl(base + BMU_FREE_ERR_ADDR));
+}
+
+#define PESTATUS_ADDR_CLASS 0x800
+#define PEMBOX_ADDR_CLASS 0x890
+#define PESTATUS_ADDR_TMU 0x80
+#define PEMBOX_ADDR_TMU 0x290
+#define PESTATUS_ADDR_UTIL 0x0
+
+static void pfe_pe_status(int argc, char * const argv[])
+{
+ int do_clear = 0;
+ u32 id;
+ u32 dmem_addr;
+ u32 cpu_state;
+ u32 activity_counter;
+ u32 rx;
+ u32 tx;
+ u32 drop;
+ char statebuf[5];
+ u32 class_debug_reg = 0;
+
+ if (argc == 4 && strcmp(argv[3], "clear") == 0)
+ do_clear = 1;
+
+ for (id = CLASS0_ID; id < MAX_PE; id++) {
+ if (id >= TMU0_ID) {
+ if (id == TMU2_ID)
+ continue;
+ if (id == TMU0_ID)
+ printf("tmu:\n");
+ dmem_addr = PESTATUS_ADDR_TMU;
+ } else {
+ if (id == CLASS0_ID)
+ printf("class:\n");
+ dmem_addr = PESTATUS_ADDR_CLASS;
+ class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
+ }
+
+ cpu_state = pe_dmem_read(id, dmem_addr, 4);
+ dmem_addr += 4;
+ memcpy(statebuf, (char *)&cpu_state, 4);
+ statebuf[4] = '\0';
+ activity_counter = pe_dmem_read(id, dmem_addr, 4);
+ dmem_addr += 4;
+ rx = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+ tx = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+ drop = pe_dmem_read(id, dmem_addr, 4);
+ if (do_clear)
+ pe_dmem_write(id, 0, dmem_addr, 4);
+ dmem_addr += 4;
+
+ if (id >= TMU0_ID) {
+ printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
+ id - TMU0_ID, statebuf,
+ cpu_to_be32(activity_counter),
+ cpu_to_be32(rx), cpu_to_be32(tx));
+ } else {
+ printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
+ id - CLASS0_ID, class_debug_reg & 0xFFFF,
+ class_debug_reg >> 16,
+ statebuf, cpu_to_be32(activity_counter),
+ cpu_to_be32(rx), cpu_to_be32(tx),
+ cpu_to_be32(drop));
+ }
+ }
+}
+
+static void pfe_command_status(int argc, char * const argv[])
+{
+ if (argc >= 3 && strcmp(argv[2], "pe") == 0) {
+ pfe_pe_status(argc, argv);
+ } else if (argc == 3 && strcmp(argv[2], "bmu") == 0) {
+ bmu(1, BMU1_BASE_ADDR);
+ bmu(2, BMU2_BASE_ADDR);
+ } else if (argc == 3 && strcmp(argv[2], "hif") == 0) {
+ hif_status();
+ } else if (argc == 3 && strcmp(argv[2], "gpi") == 0) {
+ gpi(0, EGPI1_BASE_ADDR);
+ gpi(1, EGPI2_BASE_ADDR);
+ gpi(3, HGPI_BASE_ADDR);
+ } else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0) {
+ tmu_queues(NULL, 0);
+ } else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0) {
+ tmu_queues(NULL, 1);
+ } else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0) {
+ tmu_queues(NULL, 3);
+ } else {
+ printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
+ }
+}
+
+#define EXPT_DUMP_ADDR 0x1fa8
+#define EXPT_REG_COUNT 20
+static const char *register_names[EXPT_REG_COUNT] = {
+ " pc", "ECAS", " EID", " ED",
+ " sp", " r1", " r2", " r3",
+ " r4", " r5", " r6", " r7",
+ " r8", " r9", " r10", " r11",
+ " r12", " r13", " r14", " r15"
+};
+
+static void pfe_command_expt(int argc, char * const argv[])
+{
+ unsigned int id, i, val, addr;
+
+ if (argc == 3) {
+ id = simple_strtoul(argv[2], NULL, 0);
+ addr = EXPT_DUMP_ADDR;
+ printf("Exception information for PE %d:\n", id);
+ for (i = 0; i < EXPT_REG_COUNT; i++) {
+ val = pe_dmem_read(id, addr, 4);
+ val = be32_to_cpu(val);
+ printf("%s:%08x%s", register_names[i], val,
+ (i & 3) == 3 ? "\n" : " ");
+ addr += 4;
+ }
+ } else {
+ printf("Usage: pfe expt <id>\n");
+ }
+}
+
+#ifdef PFE_RESET_WA
+/*This function sends a dummy packet to HIF through TMU3 */
+static void send_dummy_pkt_to_hif(void)
+{
+ u32 buf;
+ static u32 dummy_pkt[] = {
+ 0x4200800a, 0x01000003, 0x00018100, 0x00000000,
+ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
+ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
+
+ /*Allocate BMU2 buffer */
+ buf = readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL);
+
+ debug("Sending a dummy pkt to HIF %x\n", buf);
+ buf += 0x80;
+ memcpy((void *)DDR_PFE_TO_VIRT(buf), dummy_pkt, sizeof(dummy_pkt));
+
+ /*Write length and pkt to TMU*/
+ writel(0x03000042, TMU_PHY_INQ_PKTPTR);
+ writel(buf, TMU_PHY_INQ_PKTINFO);
+}
+
+static void pfe_command_stop(int argc, char * const argv[])
+{
+ int pfe_pe_id, hif_stop_loop = 10;
+ u32 rx_status;
+
+ printf("Stopping PFE...\n");
+
+ /*Mark all descriptors as LAST_BD */
+ hif_rx_desc_disable();
+
+ /*If HIF Rx BDP is busy send a dummy packet */
+ do {
+ rx_status = readl(HIF_RX_STATUS);
+ if (rx_status & BDP_CSR_RX_DMA_ACTV)
+ send_dummy_pkt_to_hif();
+ udelay(10);
+ } while (hif_stop_loop--);
+
+ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
+ printf("Unable to stop HIF\n");
+
+ /*Disable Class PEs */
+ for (pfe_pe_id = CLASS0_ID; pfe_pe_id <= CLASS_MAX_ID; pfe_pe_id++) {
+ /*Inform PE to stop */
+ pe_dmem_write(pfe_pe_id, cpu_to_be32(1), PEMBOX_ADDR_CLASS, 4);
+ udelay(10);
+
+ /*Read status */
+ if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_CLASS + 4, 4))
+ printf("Failed to stop PE%d\n", pfe_pe_id);
+ }
+
+ /*Disable TMU PEs */
+ for (pfe_pe_id = TMU0_ID; pfe_pe_id <= TMU_MAX_ID; pfe_pe_id++) {
+ if (pfe_pe_id == TMU2_ID)
+ continue;
+
+ /*Inform PE to stop */
+ pe_dmem_write(pfe_pe_id, 1, PEMBOX_ADDR_TMU, 4);
+ udelay(10);
+
+ /*Read status */
+ if (!pe_dmem_read(pfe_pe_id, PEMBOX_ADDR_TMU + 4, 4))
+ printf("Failed to stop PE%d\n", pfe_pe_id);
+ }
+}
+#endif
+
+static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc == 1 || strcmp(argv[1], "help") == 0) {
+ pfe_command_help();
+ return CMD_RET_SUCCESS;
+ }
+
+ if (strcmp(argv[1], "pe") == 0) {
+ pfe_command_pe(argc, argv);
+ } else if (strcmp(argv[1], "status") == 0) {
+ pfe_command_status(argc, argv);
+ } else if (strcmp(argv[1], "expt") == 0) {
+ pfe_command_expt(argc, argv);
+#ifdef PFE_RESET_WA
+ } else if (strcmp(argv[1], "stop") == 0) {
+ pfe_command_stop(argc, argv);
+#endif
+ } else {
+ printf("Unknown option: %s\n", argv[1]);
+ pfe_command_help();
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ pfe, 7, 1, pfe_command,
+ "Performs PFE lib utility functions",
+ "Usage:\n"
+ "pfe <options>"
+);
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (3 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:29 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds Calvin Johnson
` (9 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
Contains all the pfe header files.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-Add pfe_rx_done to clear bd after packet processing
-remove unused code under CONFIG_UTIL_PE_DISABLED
-Used BIT and GENMASK macros wherever applicable
-Removed generic definitions that pollutes namespace
-File names pfe.h renamed to pfe_hw.h to be more clear as it contains
low level functions that directly access pfe hardware block
-Added pfe_dm_eth.h for new driver model
---
include/dm/platform_data/pfe_dm_eth.h | 21 ++++
include/pfe_eth/pfe/cbus.h | 77 +++++++++++++++
include/pfe_eth/pfe/cbus/bmu.h | 40 ++++++++
include/pfe_eth/pfe/cbus/class_csr.h | 180 ++++++++++++++++++++++++++++++++++
include/pfe_eth/pfe/cbus/emac.h | 140 ++++++++++++++++++++++++++
include/pfe_eth/pfe/cbus/gpi.h | 62 ++++++++++++
include/pfe_eth/pfe/cbus/hif.h | 68 +++++++++++++
include/pfe_eth/pfe/cbus/hif_nocpy.h | 40 ++++++++
include/pfe_eth/pfe/cbus/tmu_csr.h | 148 ++++++++++++++++++++++++++++
include/pfe_eth/pfe/cbus/util_csr.h | 47 +++++++++
include/pfe_eth/pfe/pfe_hw.h | 163 ++++++++++++++++++++++++++++++
include/pfe_eth/pfe_driver.h | 59 +++++++++++
include/pfe_eth/pfe_eth.h | 104 ++++++++++++++++++++
include/pfe_eth/pfe_firmware.h | 17 ++++
include/pfe_eth/pfe_mdio.h | 13 +++
15 files changed, 1179 insertions(+)
create mode 100644 include/dm/platform_data/pfe_dm_eth.h
create mode 100644 include/pfe_eth/pfe/cbus.h
create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
create mode 100644 include/pfe_eth/pfe/cbus/emac.h
create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
create mode 100644 include/pfe_eth/pfe/cbus/hif.h
create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
create mode 100644 include/pfe_eth/pfe/pfe_hw.h
create mode 100644 include/pfe_eth/pfe_driver.h
create mode 100644 include/pfe_eth/pfe_eth.h
create mode 100644 include/pfe_eth/pfe_firmware.h
create mode 100644 include/pfe_eth/pfe_mdio.h
diff --git a/include/dm/platform_data/pfe_dm_eth.h b/include/dm/platform_data/pfe_dm_eth.h
new file mode 100644
index 0000000..7943c67
--- /dev/null
+++ b/include/dm/platform_data/pfe_dm_eth.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_DM_ETH_H__
+#define __PFE_DM_ETH_H__
+#include <net.h>
+
+struct pfe_ddr_address {
+ void *ddr_pfe_baseaddr;
+ unsigned long ddr_pfe_phys_baseaddr;
+};
+
+struct pfe_eth_pdata {
+ struct eth_pdata pfe_eth_pdata_mac;
+ struct pfe_ddr_address pfe_ddr_addr;
+};
+#endif /* __PFE_DM_ETH_H__ */
diff --git a/include/pfe_eth/pfe/cbus.h b/include/pfe_eth/pfe/cbus.h
new file mode 100644
index 0000000..002041c
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CBUS_H_
+#define _CBUS_H_
+
+#include "cbus/emac.h"
+#include "cbus/gpi.h"
+#include "cbus/bmu.h"
+#include "cbus/hif.h"
+#include "cbus/tmu_csr.h"
+#include "cbus/class_csr.h"
+#include "cbus/hif_nocpy.h"
+#include "cbus/util_csr.h"
+
+#define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR)
+
+/* PFE Control and Status Register Desciption */
+#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
+#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
+#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
+#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
+#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
+#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
+#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
+#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
+#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
+#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
+#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
+#define LMEM_SIZE 0x10000
+#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
+#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
+#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
+#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
+#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
+#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
+
+/*
+ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
+ * XXX_MEM_ACCESS_ADDR register bit definitions.
+ */
+/* Internal Memory Write. */
+#define PE_MEM_ACCESS_WRITE BIT(31)
+/* Internal Memory Read. */
+#define PE_MEM_ACCESS_READ (0 << 31)
+
+#define PE_MEM_ACCESS_IMEM BIT(15)
+#define PE_MEM_ACCESS_DMEM BIT(16)
+
+/* Byte Enables of the Internal memory access. These are interpred in BE */
+#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \
+ - (offset) - (size)))\
+ & 0xf) << 24)
+
+/* PFE cores states */
+#define CORE_DISABLE 0x00000000
+#define CORE_ENABLE 0x00000001
+#define CORE_SW_RESET 0x00000002
+
+/* LMEM defines */
+#define LMEM_HDR_SIZE 0x0010
+#define LMEM_BUF_SIZE_LN2 0x7
+#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
+
+/* DDR defines */
+#define DDR_HDR_SIZE 0x0100
+#define DDR_BUF_SIZE_LN2 0xb
+#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
+
+/* Clock generation through PLL */
+#define PLL_CLK_EN 1
+
+#endif /* _CBUS_H_ */
diff --git a/include/pfe_eth/pfe/cbus/bmu.h b/include/pfe_eth/pfe/cbus/bmu.h
new file mode 100644
index 0000000..f707cc3
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/bmu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BMU_H_
+#define _BMU_H_
+
+#define BMU_VERSION 0x000
+#define BMU_CTRL 0x004
+#define BMU_UCAST_CONFIG 0x008
+#define BMU_UCAST_BASE_ADDR 0x00c
+#define BMU_BUF_SIZE 0x010
+#define BMU_BUF_CNT 0x014
+#define BMU_THRES 0x018
+#define BMU_INT_SRC 0x020
+#define BMU_INT_ENABLE 0x024
+#define BMU_ALLOC_CTRL 0x030
+#define BMU_FREE_CTRL 0x034
+#define BMU_FREE_ERR_ADDR 0x038
+#define BMU_CURR_BUF_CNT 0x03c
+#define BMU_MCAST_CNT 0x040
+#define BMU_MCAST_ALLOC_CTRL 0x044
+#define BMU_REM_BUF_CNT 0x048
+#define BMU_LOW_WATERMARK 0x050
+#define BMU_HIGH_WATERMARK 0x054
+#define BMU_INT_MEM_ACCESS 0x100
+
+struct bmu_cfg {
+ u32 baseaddr;
+ u32 count;
+ u32 size;
+};
+
+#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
+#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
+
+#endif /* _BMU_H_ */
diff --git a/include/pfe_eth/pfe/cbus/class_csr.h b/include/pfe_eth/pfe/cbus/class_csr.h
new file mode 100644
index 0000000..eeca751
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/class_csr.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLASS_CSR_H_
+#define _CLASS_CSR_H_
+
+/*
+ * @file class_csr.h.
+ * class_csr - block containing all the classifier control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
+#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
+#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
+/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
+#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
+/* LMEM header size for the Classifier block.
+ * Data in the LMEM is written from this offset.
+ */
+#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
+/* DDR header size for the Classifier block.
+ * Data in the DDR is written from this offset.
+ */
+#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
+#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
+
+/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
+/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
+#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
+
+/*
+ * @name Class PE memory access. Allows external PE's and HOST to
+ * read/write PMEM/DMEM memory ranges for each classifier PE.
+ */
+#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
+/* Internal Memory Access Write Data [31:0] */
+#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
+/* Internal Memory Access Read Data [31:0] */
+#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
+#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
+#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
+
+#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
+#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
+#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
+#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
+#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
+#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
+#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
+#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
+#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
+#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
+
+#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
+/* bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR */
+#define CLASS_BUS_ACCESS_ADDR_MASK (0x0001FFFF)
+
+#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
+#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
+
+/*
+ * (route_entry_size[9:0], route_hash_size[23:16]
+ * (this is actually ln2(size)))
+ */
+#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
+#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
+#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
+
+#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
+#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
+#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
+#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
+#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
+#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
+#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
+#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
+
+#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
+/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
+#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
+
+#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
+
+#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
+#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
+#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
+#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
+#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
+#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
+#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
+#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
+#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
+#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
+#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
+#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
+
+#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
+#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
+
+#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
+#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
+
+#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
+
+#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
+#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
+#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
+#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
+#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
+#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
+
+#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
+#define CLASS_AXI_CTRL (CLASS_CSR_BASE_ADDR + 0x2d0)
+
+/* CLASS defines */
+#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
+#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
+
+#define CLASS_PBUF0_BASE_ADDR 0x000 /* Can be configured */
+/* Can be configured */
+#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
+/* Can be configured */
+#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
+
+#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR +\
+ CLASS_PBUF_HEADER_OFFSET)
+
+#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) |\
+ CLASS_PBUF0_BASE_ADDR)
+#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) |\
+ CLASS_PBUF2_BASE_ADDR)
+
+#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16)\
+ | CLASS_PBUF0_HEADER_BASE_ADDR)
+#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16)\
+ | CLASS_PBUF2_HEADER_BASE_ADDR)
+
+#define CLASS_ROUTE_SIZE 128
+#define CLASS_ROUTE_HASH_BITS 20
+#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
+
+#define TWO_LEVEL_ROUTE BIT(0)
+#define PHYNO_IN_HASH BIT(1)
+#define HW_ROUTE_FETCH BIT(3)
+#define HW_BRIDGE_FETCH BIT(5)
+#define IP_ALIGNED BIT(6)
+#define ARC_HIT_CHECK_EN BIT(7)
+#define CLASS_TOE BIT(11)
+#define HASH_CRC_PORT BIT(12)
+#define HASH_CRC_IP BIT(13)
+#define HASH_CRC_PORT_IP GENMASK(13, 12)
+#define QB2BUS_LE BIT(15)
+
+#define TCP_CHKSUM_DROP BIT(0)
+#define UDP_CHKSUM_DROP BIT(1)
+#define IPV4_CHKSUM_DROP BIT(9)
+
+struct class_cfg {
+ u32 route_table_baseaddr;
+ u32 route_table_hash_bits;
+};
+
+#endif /* _CLASS_CSR_H_ */
diff --git a/include/pfe_eth/pfe/cbus/emac.h b/include/pfe_eth/pfe/cbus/emac.h
new file mode 100644
index 0000000..15c160d
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/emac.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+#define EMAC_IEVENT_REG 0x004
+#define EMAC_IMASK_REG 0x008
+#define EMAC_R_DES_ACTIVE_REG 0x010
+#define EMAC_X_DES_ACTIVE_REG 0x014
+#define EMAC_ECNTRL_REG 0x024
+#define EMAC_MII_DATA_REG 0x040
+#define EMAC_MII_CTRL_REG 0x044
+#define EMAC_MIB_CTRL_STS_REG 0x064
+#define EMAC_RCNTRL_REG 0x084
+#define EMAC_TCNTRL_REG 0x0C4
+#define EMAC_PHY_ADDR_LOW 0x0E4
+#define EMAC_PHY_ADDR_HIGH 0x0E8
+#define EMAC_TFWR_STR_FWD 0x144
+#define EMAC_RX_SECTIOM_FULL 0x190
+#define EMAC_TX_SECTION_EMPTY 0x1A0
+#define EMAC_TRUNC_FL 0x1B0
+
+/* GEMAC definitions and settings */
+#define EMAC_PORT_0 0
+#define EMAC_PORT_1 1
+
+/* GEMAC Bit definitions */
+#define EMAC_IEVENT_HBERR 0x80000000
+#define EMAC_IEVENT_BABR 0x40000000
+#define EMAC_IEVENT_BABT 0x20000000
+#define EMAC_IEVENT_GRA 0x10000000
+#define EMAC_IEVENT_TXF 0x08000000
+#define EMAC_IEVENT_TXB 0x04000000
+#define EMAC_IEVENT_RXF 0x02000000
+#define EMAC_IEVENT_RXB 0x01000000
+#define EMAC_IEVENT_MII 0x00800000
+#define EMAC_IEVENT_EBERR 0x00400000
+#define EMAC_IEVENT_LC 0x00200000
+#define EMAC_IEVENT_RL 0x00100000
+#define EMAC_IEVENT_UN 0x00080000
+
+#define EMAC_IMASK_HBERR 0x80000000
+#define EMAC_IMASK_BABR 0x40000000
+#define EMAC_IMASKT_BABT 0x20000000
+#define EMAC_IMASK_GRA 0x10000000
+#define EMAC_IMASKT_TXF 0x08000000
+#define EMAC_IMASK_TXB 0x04000000
+#define EMAC_IMASKT_RXF 0x02000000
+#define EMAC_IMASK_RXB 0x01000000
+#define EMAC_IMASK_MII 0x00800000
+#define EMAC_IMASK_EBERR 0x00400000
+#define EMAC_IMASK_LC 0x00200000
+#define EMAC_IMASKT_RL 0x00100000
+#define EMAC_IMASK_UN 0x00080000
+
+#define EMAC_RCNTRL_MAX_FL_SHIFT 16
+#define EMAC_RCNTRL_LOOP 0x00000001
+#define EMAC_RCNTRL_DRT 0x00000002
+#define EMAC_RCNTRL_MII_MODE 0x00000004
+#define EMAC_RCNTRL_PROM 0x00000008
+#define EMAC_RCNTRL_BC_REJ 0x00000010
+#define EMAC_RCNTRL_FCE 0x00000020
+#define EMAC_RCNTRL_RGMII 0x00000040
+#define EMAC_RCNTRL_SGMII 0x00000080
+#define EMAC_RCNTRL_RMII 0x00000100
+#define EMAC_RCNTRL_RMII_10T 0x00000200
+#define EMAC_RCNTRL_CRC_FWD 0x00004000
+
+#define EMAC_TCNTRL_GTS 0x00000001
+#define EMAC_TCNTRL_HBC 0x00000002
+#define EMAC_TCNTRL_FDEN 0x00000004
+#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
+#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
+
+#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
+#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
+#define EMAC_ECNTRL_SPEED 0x00000020
+#define EMAC_ECNTRL_DBSWAP 0x00000100
+
+#define EMAC_X_WMRK_STRFWD 0x00000100
+
+#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
+#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
+
+#define EMAC_TFWR (0x4)
+#define EMAC_RX_SECTION_FULL_32 (0x5)
+#define EMAC_TRUNC_FL_16K (0x3FFF)
+#define EMAC_TX_SECTION_EMPTY_30 (0x30)
+#define EMAC_MIBC_NO_CLR_NO_DIS (0x0)
+
+/*
+ * The possible operating speeds of the MAC, currently supporting 10, 100 and
+ * 1000Mb modes.
+ */
+enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
+ PFE_MAC_SPEED_1000M_PCS};
+
+/* MII-related definitios */
+#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
+#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
+#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
+#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
+#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
+#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
+#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
+
+#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
+#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
+#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
+#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
+
+#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+ EMAC_MII_DATA_RA_SHIFT)
+#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
+ EMAC_MII_DATA_PA_SHIFT)
+#define EMAC_MII_DATA(v) (v & 0xffff)
+
+#define EMAC_MII_SPEED_SHIFT 1
+#define EMAC_HOLDTIME_SHIFT 8
+#define EMAC_HOLDTIME_MASK 0x7
+#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET 0x8000
+#define PHY_SGMII_CR_RESET_AN 0x0200
+#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN 0x0002
+#define PHY_SGMII_IF_MODE_SGMII 0x0001
+#define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
+#define PHY_SGMII_ENABLE_AN 0x1000
+
+#endif /* _EMAC_H_ */
diff --git a/include/pfe_eth/pfe/cbus/gpi.h b/include/pfe_eth/pfe/cbus/gpi.h
new file mode 100644
index 0000000..f86f3f9
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/gpi.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GPI_H_
+#define _GPI_H_
+
+#define GPI_VERSION 0x00
+#define GPI_CTRL 0x04
+#define GPI_RX_CONFIG 0x08
+#define GPI_HDR_SIZE 0x0c
+#define GPI_BUF_SIZE 0x10
+#define GPI_LMEM_ALLOC_ADDR 0x14
+#define GPI_LMEM_FREE_ADDR 0x18
+#define GPI_DDR_ALLOC_ADDR 0x1c
+#define GPI_DDR_FREE_ADDR 0x20
+#define GPI_CLASS_ADDR 0x24
+#define GPI_DRX_FIFO 0x28
+#define GPI_TRX_FIFO 0x2c
+#define GPI_INQ_PKTPTR 0x30
+#define GPI_DDR_DATA_OFFSET 0x34
+#define GPI_LMEM_DATA_OFFSET 0x38
+#define GPI_TMLF_TX 0x4c
+#define GPI_DTX_ASEQ 0x50
+#define GPI_FIFO_STATUS 0x54
+#define GPI_FIFO_DEBUG 0x58
+#define GPI_TX_PAUSE_TIME 0x5c
+#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
+#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
+#define GPI_TOE_CHKSUM_EN 0x68
+#define GPI_OVERRUN_DROPCNT 0x6c
+#define GPI_AXI_CTRL 0x70
+
+struct gpi_cfg {
+ u32 lmem_rtry_cnt;
+ u32 tmlf_txthres;
+ u32 aseq_len;
+};
+
+/* GPI commons defines */
+#define GPI_LMEM_BUF_EN 0x1
+#define GPI_DDR_BUF_EN 0x1
+
+/* EGPI 1 defines */
+#define EGPI1_LMEM_RTRY_CNT 0x40
+#define EGPI1_TMLF_TXTHRES 0xBC
+#define EGPI1_ASEQ_LEN 0x50
+
+/* EGPI 2 defines */
+#define EGPI2_LMEM_RTRY_CNT 0x40
+#define EGPI2_TMLF_TXTHRES 0xBC
+#define EGPI2_ASEQ_LEN 0x40
+
+/* HGPI defines */
+#define HGPI_LMEM_RTRY_CNT 0x40
+#define HGPI_TMLF_TXTHRES 0xBC
+#define HGPI_ASEQ_LEN 0x40
+
+#endif /* _GPI_H_ */
diff --git a/include/pfe_eth/pfe/cbus/hif.h b/include/pfe_eth/pfe/cbus/hif.h
new file mode 100644
index 0000000..4b5cb3c
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/hif.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HIF_H_
+#define _HIF_H_
+
+/*
+ * @file hif.h.
+ * hif - PFE hif block control and status register.
+ * Mapped on CBUS and accessible from all PE's and ARM.
+ */
+#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
+#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
+#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
+#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
+#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
+#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
+#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
+#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
+#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
+#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
+#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
+#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
+#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
+#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
+#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
+#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
+#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
+#define HIF_AXI_CTRL (HIF_BASE_ADDR + 0x54)
+
+/* HIF_TX_CTRL bits */
+#define HIF_CTRL_DMA_EN BIT(0)
+#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
+#define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
+
+/* HIF_RX_STATUS bits */
+#define BDP_CSR_RX_DMA_ACTV BIT(16)
+
+/* HIF_INT_ENABLE bits */
+#define HIF_INT_EN BIT(0)
+#define HIF_RXBD_INT_EN BIT(1)
+#define HIF_RXPKT_INT_EN BIT(2)
+#define HIF_TXBD_INT_EN BIT(3)
+#define HIF_TXPKT_INT_EN BIT(4)
+
+/* HIF_POLL_CTRL bits*/
+#define HIF_RX_POLL_CTRL_CYCLE 0x0400
+#define HIF_TX_POLL_CTRL_CYCLE 0x0400
+
+/* Buffer descriptor control bits */
+#define BD_CTRL_BUFLEN_MASK (0xffff)
+#define BD_BUF_LEN(x) (x & BD_CTRL_BUFLEN_MASK)
+#define BD_CTRL_CBD_INT_EN BIT(16)
+#define BD_CTRL_PKT_INT_EN BIT(17)
+#define BD_CTRL_LIFM BIT(18)
+#define BD_CTRL_LAST_BD BIT(19)
+#define BD_CTRL_DIR BIT(20)
+#define BD_CTRL_PKT_XFER BIT(24)
+#define BD_CTRL_DESC_EN BIT(31)
+#define BD_CTRL_PARSE_DISABLE BIT(25)
+#define BD_CTRL_BRFETCH_DISABLE BIT(26)
+#define BD_CTRL_RTFETCH_DISABLE BIT(27)
+
+#endif /* _HIF_H_ */
diff --git a/include/pfe_eth/pfe/cbus/hif_nocpy.h b/include/pfe_eth/pfe/cbus/hif_nocpy.h
new file mode 100644
index 0000000..c2d6f6d
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/hif_nocpy.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _HIF_NOCPY_H_
+#define _HIF_NOCPY_H_
+
+#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
+#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
+#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
+#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
+#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
+#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
+#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
+#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
+#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
+#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
+#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
+#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
+#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
+#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
+#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
+#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
+#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
+#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
+#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
+#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
+#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
+#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
+#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
+#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
+#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
+#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
+#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
+#define HIF_NOCPY_AXI_CTRL (HIF_NOCPY_BASE_ADDR + 0x94)
+
+#endif /* _HIF_NOCPY_H_ */
diff --git a/include/pfe_eth/pfe/cbus/tmu_csr.h b/include/pfe_eth/pfe/cbus/tmu_csr.h
new file mode 100644
index 0000000..e810b79
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/tmu_csr.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TMU_CSR_H_
+#define _TMU_CSR_H_
+
+#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
+#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
+#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
+#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
+#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
+#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
+#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
+#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
+#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
+#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
+#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
+#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
+#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
+#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
+#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
+#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
+#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
+#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
+#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
+#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
+#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
+#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
+#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
+#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
+#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
+#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
+#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
+#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
+#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
+#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
+#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
+#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
+#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
+#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
+#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
+#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
+#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
+#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
+#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
+#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
+#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
+#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
+#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
+#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
+#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
+#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
+ * This is a global Enable for all schedulers in PHY0
+ */
+#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
+#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
+#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
+#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
+#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
+#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
+#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
+#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
+#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
+#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
+#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
+
+/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
+ * memory Write [27:24] Byte Enables of the Internal memory access [23:0]
+ * Address of the internal memory. This address is used to access both the
+ * PM and DM of all the PE's
+ */
+#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
+
+/* Internal Memory Access Write Data */
+#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
+/* Internal Memory Access Read Data. The commands are blocked@the
+ * mem_access only
+ */
+#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
+
+/* [31:0] PHY0 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
+/* [31:0] PHY1 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
+/* [31:0] PHY3 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
+#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
+#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
+
+#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
+#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
+#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
+
+/* [31:0] PHY4 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
+
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY1
+ */
+#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
+/* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
+ * is a global Enable for all schedulers in PHY3
+ */
+#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
+
+#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
+/* [31:0] PHY5 in queue address (must be initialized with one of the
+ * xxx_INQ_PKTPTR cbus addresses)
+ */
+#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
+
+#define TMU_AXI_CTRL (TMU_CSR_BASE_ADDR + 0x17c)
+
+#define SW_RESET BIT(0) /* Global software reset */
+#define INQ_RESET BIT(2)
+#define TEQ_RESET BIT(3)
+#define TDQ_RESET BIT(4)
+#define PE_RESET BIT(5)
+#define MEM_INIT BIT(6)
+#define MEM_INIT_DONE BIT(7)
+#define LLM_INIT BIT(8)
+#define LLM_INIT_DONE BIT(9)
+#define ECC_MEM_INIT_DONE BIT(10)
+
+struct tmu_cfg {
+ u32 llm_base_addr;
+ u32 llm_queue_len;
+};
+
+/* Not HW related for pfe_ctrl/pfe common defines */
+#define DEFAULT_MAX_QDEPTH 80
+#define DEFAULT_Q0_QDEPTH 511 /* We keep 1 large queue for host tx qos */
+#define DEFAULT_TMU3_QDEPTH 127
+
+#endif /* _TMU_CSR_H_ */
diff --git a/include/pfe_eth/pfe/cbus/util_csr.h b/include/pfe_eth/pfe/cbus/util_csr.h
new file mode 100644
index 0000000..bac4114
--- /dev/null
+++ b/include/pfe_eth/pfe/cbus/util_csr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _UTIL_CSR_H_
+#define _UTIL_CSR_H_
+
+#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
+#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
+#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
+
+#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
+
+#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
+#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
+#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
+#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
+
+#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
+#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
+#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
+
+#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
+#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
+
+#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
+#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
+#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
+#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
+#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
+#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
+#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
+#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
+#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
+#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
+
+#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
+#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
+#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
+
+#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
+#define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240)
+
+#endif /* _UTIL_CSR_H_ */
diff --git a/include/pfe_eth/pfe/pfe_hw.h b/include/pfe_eth/pfe/pfe_hw.h
new file mode 100644
index 0000000..992454f
--- /dev/null
+++ b/include/pfe_eth/pfe/pfe_hw.h
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PFE_H_
+#define _PFE_H_
+
+#include <elf.h>
+#include "cbus.h"
+
+#define PFE_RESET_WA
+
+#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+/* Only valid for mem access register interface */
+#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
+#define CLASS_DMEM_SIZE 0x00002000
+#define CLASS_IMEM_SIZE 0x00008000
+
+#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+/* Only valid for mem access register interface */
+#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
+#define TMU_DMEM_SIZE 0x00000800
+#define TMU_IMEM_SIZE 0x00002000
+
+#define UTIL_DMEM_BASE_ADDR 0x00000000
+#define UTIL_DMEM_SIZE 0x00002000
+
+#define PE_LMEM_BASE_ADDR 0xc3010000
+#define PE_LMEM_SIZE 0x8000
+#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
+
+#define DMEM_BASE_ADDR 0x00000000
+#define DMEM_SIZE 0x2000 /* TMU has less... */
+#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
+
+#define PMEM_BASE_ADDR 0x00010000
+#define PMEM_SIZE 0x8000 /* TMU has less... */
+#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
+
+/* Memory ranges check from PE point of view/memory map */
+#define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
+ (((unsigned long)(addr) +\
+ (len)) <= DMEM_END))
+#define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
+ (((unsigned long)(addr) +\
+ (len)) <= PMEM_END))
+#define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
+ ) && (((unsigned long)(addr)\
+ + (len)) <= PE_LMEM_END))
+
+#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
+ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
+ (((unsigned long)(addr) + (len)) <=\
+ CBUS_VIRT_TO_PFE(LMEM_END)))
+#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
+ PFE_DDR_PHYS_BASE_ADDR) &&\
+ (((unsigned long)(addr) + (len)) <=\
+ PFE_DDR_PHYS_END))
+
+/* Host View Address */
+extern void *ddr_pfe_base_addr;
+
+/* PFE View Address */
+/* DDR physical base address as seen by PE's. */
+#define PFE_DDR_PHYS_BASE_ADDR 0x03800000
+#define PFE_DDR_PHYS_SIZE 0xC000000
+#define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
+/* CBUS physical base address as seen by PE's. */
+#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
+
+/* Host<->PFE Mapping */
+#define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
+#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
+ PFE_CBUS_PHYS_BASE_ADDR)
+#define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
+ CBUS_BASE_ADDR)
+
+enum {
+ CLASS0_ID = 0,
+ CLASS1_ID,
+ CLASS2_ID,
+ CLASS3_ID,
+ CLASS4_ID,
+ CLASS5_ID,
+
+ TMU0_ID,
+ TMU1_ID,
+ TMU2_ID,
+ TMU3_ID,
+ MAX_PE
+};
+
+#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
+ | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
+ BIT(CLASS5_ID))
+#define CLASS_MAX_ID CLASS5_ID
+
+#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
+#define TMU_MAX_ID TMU3_ID
+
+/*
+ * PE information.
+ * Structure containing PE's specific information. It is used to create
+ * generic C functions common to all PEs.
+ * Before using the library functions this structure needs to be
+ * initialized with the different registers virtual addresses
+ * (according to the ARM MMU mmaping). The default initialization supports a
+ * virtual == physical mapping.
+ *
+ */
+struct pe_info {
+ u32 dmem_base_addr; /* PE's dmem base address */
+ u32 pmem_base_addr; /* PE's pmem base address */
+ u32 pmem_size; /* PE's pmem size */
+
+ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
+ * register address
+ */
+ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
+ * register address
+ */
+ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
+ * register address
+ */
+};
+
+void pe_lmem_read(u32 *dst, u32 len, u32 offset);
+void pe_lmem_write(u32 *src, u32 len, u32 offset);
+
+u32 pe_pmem_read(int id, u32 addr, u8 size);
+void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
+u32 pe_dmem_read(int id, u32 addr, u8 size);
+
+int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
+
+void pfe_lib_init(void);
+
+void bmu_init(void *base, struct bmu_cfg *cfg);
+void bmu_enable(void *base);
+
+void gpi_init(void *base, struct gpi_cfg *cfg);
+void gpi_enable(void *base);
+void gpi_disable(void *base);
+
+void class_init(struct class_cfg *cfg);
+void class_enable(void);
+void class_disable(void);
+
+void tmu_init(struct tmu_cfg *cfg);
+void tmu_enable(u32 pe_mask);
+void tmu_disable(u32 pe_mask);
+
+void hif_init(void);
+void hif_tx_enable(void);
+void hif_tx_disable(void);
+void hif_rx_enable(void);
+void hif_rx_disable(void);
+void hif_rx_desc_disable(void);
+
+#endif /* _PFE_H_ */
diff --git a/include/pfe_eth/pfe_driver.h b/include/pfe_eth/pfe_driver.h
new file mode 100644
index 0000000..b2aebf8
--- /dev/null
+++ b/include/pfe_eth/pfe_driver.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_DRIVER_H__
+#define __PFE_DRIVER_H__
+
+#include <pfe_eth/pfe/pfe_hw.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define HIF_RX_DESC_NT 64
+#define HIF_TX_DESC_NT 64
+
+#define RX_BD_BASEADDR (HIF_DESC_BASEADDR)
+#define TX_BD_BASEADDR (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
+
+#define MIN_PKT_SIZE 56
+#define MAX_FRAME_SIZE 2048
+
+struct __packed hif_header_s {
+ u8 port_no; /* Carries input port no for host rx packets and
+ * output port no for tx pkts
+ */
+ u8 reserved0;
+ u32 reserved2;
+};
+
+struct __packed buf_desc {
+ u32 ctrl;
+ u32 status;
+ u32 data;
+ u32 next;
+};
+
+struct rx_desc_s {
+ struct buf_desc *rx_base;
+ unsigned int rx_base_pa;
+ int rx_to_read;
+ int rx_ring_size;
+};
+
+struct tx_desc_s {
+ struct buf_desc *tx_base;
+ unsigned int tx_base_pa;
+ int tx_to_send;
+ int tx_ring_size;
+};
+
+int pfe_send(int phy_port, void *data, int length);
+int pfe_recv(uchar **pkt_ptr, int *phy_port);
+int pfe_tx_done(void);
+int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length);
+int pfe_drv_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_remove(struct udevice *dev);
+
+#endif
diff --git a/include/pfe_eth/pfe_eth.h b/include/pfe_eth/pfe_eth.h
new file mode 100644
index 0000000..f319365
--- /dev/null
+++ b/include/pfe_eth/pfe_eth.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PFE_ETH_H__
+#define __PFE_ETH_H__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include "pfe_driver.h"
+
+#define BMU2_DDR_BASEADDR 0
+#define BMU2_BUF_COUNT (3 * SZ_1K)
+#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
+
+#define HIF_RX_PKT_DDR_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
+#define HIF_RX_PKT_DDR_SIZE (HIF_RX_DESC_NT * DDR_BUF_SIZE)
+#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
+#define HIF_TX_PKT_DDR_SIZE (HIF_TX_DESC_NT * DDR_BUF_SIZE)
+
+#define HIF_DESC_BASEADDR (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
+#define HIF_RX_DESC_SIZE (16 * HIF_RX_DESC_NT)
+#define HIF_TX_DESC_SIZE (16 * HIF_TX_DESC_NT)
+
+#define UTIL_CODE_BASEADDR 0x780000
+#define UTIL_CODE_SIZE (128 * SZ_1K)
+
+#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
+#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
+
+#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
+#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
+
+#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
+#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
+
+#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
+#define TMU_LLM_QUEUE_LEN (16 * 256)
+ /* Must be power of two and at least 16 * 8 = 128 bytes */
+#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN)
+ /* (4 TMU's x 16 queues x queue_len) */
+
+#define ROUTE_TABLE_BASEADDR 0x800000
+#define ROUTE_TABLE_HASH_BITS_MAX 15 /* 32K entries */
+#define ROUTE_TABLE_HASH_BITS 8 /* 256 entries */
+#define ROUTE_TABLE_SIZE (BIT(ROUTE_TABLE_HASH_BITS_MAX) \
+ * CLASS_ROUTE_SIZE)
+
+#define PFE_TOTAL_DATA_SIZE (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
+
+#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
+#error DDR mapping above 12MiB
+#endif
+
+/* LMEM Mapping */
+#define BMU1_LMEM_BASEADDR 0
+#define BMU1_BUF_COUNT 256
+#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
+
+struct gemac_s {
+ void *gemac_base;
+ void *egpi_base;
+
+ /* GEMAC config */
+ int gemac_mode;
+ int gemac_speed;
+ int gemac_duplex;
+ int flags;
+ /* phy iface */
+ int phy_address;
+ int phy_mode;
+ struct mii_dev *bus;
+
+};
+
+struct pfe_mdio_info {
+ void *reg_base;
+ char *name;
+};
+
+struct pfe_eth_dev {
+ int gemac_port;
+ struct gemac_s *gem;
+ struct pfe_ddr_address pfe_addr;
+ struct udevice *dev;
+#ifdef CONFIG_PHYLIB
+ struct phy_device *phydev;
+#endif
+};
+
+int pfe_remove(struct pfe_ddr_address *pfe_addr);
+struct mii_dev *pfe_mdio_init(struct pfe_mdio_info *mdio_info);
+void pfe_set_mdio(int dev_id, struct mii_dev *bus);
+void pfe_set_phy_address_mode(int dev_id, int phy_id, int phy_mode);
+int gemac_initialize(bd_t *bis, int dev_id, char *devname);
+int pfe_init(struct pfe_ddr_address *pfe_addr);
+int pfe_eth_board_init(struct udevice *dev);
+
+#endif /* __PFE_ETH_H__ */
diff --git a/include/pfe_eth/pfe_firmware.h b/include/pfe_eth/pfe_firmware.h
new file mode 100644
index 0000000..588b2ae
--- /dev/null
+++ b/include/pfe_eth/pfe_firmware.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/** @file
+ * Contains all the defines to handle parsing and loading of PE firmware files.
+ */
+#ifndef __PFE_FIRMWARE_H__
+#define __PFE_FIRMWARE_H__
+
+int pfe_firmware_init(void);
+void pfe_firmware_exit(void);
+
+#endif
diff --git a/include/pfe_eth/pfe_mdio.h b/include/pfe_eth/pfe_mdio.h
new file mode 100644
index 0000000..ab27ec3
--- /dev/null
+++ b/include/pfe_eth/pfe_mdio.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PFE_MDIO_H_
+#define _PFE_MDIO_H_
+
+int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id);
+
+#endif /* _PFE_MDIO_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (4 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:42 ` Joe Hershberger
2018-02-27 23:46 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm Calvin Johnson
` (8 subsequent siblings)
14 siblings, 2 replies; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
This patch enables ethernet support for ls1012aqds.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
board/freescale/ls1012aqds/Kconfig | 14 ++
board/freescale/ls1012aqds/Makefile | 1 +
board/freescale/ls1012aqds/eth.c | 304 ++++++++++++++++++++++++++
board/freescale/ls1012aqds/ls1012aqds.c | 97 +++++++-
board/freescale/ls1012aqds/ls1012aqds_pfe.h | 48 ++++
board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
6 files changed, 459 insertions(+), 7 deletions(-)
create mode 100644 board/freescale/ls1012aqds/eth.c
create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index fc9250b..e6c2aa2 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012aqds"
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
index 0b813f9..b18494a 100644
--- a/board/freescale/ls1012aqds/Makefile
+++ b/board/freescale/ls1012aqds/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012aqds.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
new file mode 100644
index 0000000..41d077a
--- /dev/null
+++ b/board/freescale/ls1012aqds/eth.c
@@ -0,0 +1,304 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include "../common/qixis.h"
+#include <pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include "ls1012aqds_qixis.h"
+
+#define EMI_NONE 0xFF
+#define EMI1_RGMII 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 3
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+static const char * const mdio_names[] = {
+ "NULL",
+ "LS1012AQDS_MDIO_RGMII",
+ "LS1012AQDS_MDIO_SLOT1",
+ "LS1012AQDS_MDIO_SLOT2",
+ "NULL",
+};
+
+static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct ls1012aqds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void ls1012aqds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ ls1012aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ ls1012aqds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int ls1012aqds_mdio_reset(struct mii_dev *bus)
+{
+ struct ls1012aqds_mdio *priv = bus->priv;
+
+ if (priv->realbus->reset)
+ return priv->realbus->reset(priv->realbus);
+ else
+ return -1;
+}
+
+static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct ls1012aqds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate ls1012aqds MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate ls1012aqds private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = ls1012aqds_mdio_read;
+ bus->write = ls1012aqds_mdio_write;
+ bus->reset = ls1012aqds_mdio_reset;
+ sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+ return mdio_register(bus);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ static const char *mdio_name;
+ struct pfe_mdio_info mac_mdio_info;
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u8 data8;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ ls1012aqds_mux_mdio(EMI1_SLOT1);
+
+ if (!init_done) {
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ init_done = 1;
+ }
+
+ if (priv->gemac_port) {
+ mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ }
+
+ switch (srds_s1) {
+ case 0x3508:
+ printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+#ifdef RGMII_RESET_WA
+ /* Work around for FPGA registers initialization
+ * This is needed for RGMII to work.
+ */
+ printf("Reset RGMII WA....\n");
+ data8 = QIXIS_READ(rst_frc[0]);
+ data8 |= 0x2;
+ QIXIS_WRITE(rst_frc[0], data8);
+ data8 = QIXIS_READ(rst_frc[0]);
+
+ data8 = QIXIS_READ(res8[6]);
+ data8 |= 0xff;
+ QIXIS_WRITE(res8[6], data8);
+ data8 = QIXIS_READ(res8[6]);
+#endif
+ if (priv->gemac_port) {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC2*/
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_RGMII);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(priv->gemac_port, bus);
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII);
+
+ } else {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC1*/
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(priv->gemac_port, bus);
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ }
+
+ break;
+
+ case 0x2205:
+ printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
+ /* Work around for FPGA registers initialization
+ * This is needed for RGMII to work.
+ */
+ printf("Reset SLOT1 SLOT2....\n");
+ data8 = QIXIS_READ(rst_frc[2]);
+ data8 |= 0xc0;
+ QIXIS_WRITE(rst_frc[2], data8);
+ mdelay(100);
+ data8 = QIXIS_READ(rst_frc[2]);
+ data8 &= 0x3f;
+ QIXIS_WRITE(rst_frc[2], data8);
+
+ if (priv->gemac_port) {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT2)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+ /* MAC2*/
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT2);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(1, bus);
+ pfe_set_phy_address_mode(1, SGMII_2500_PHY2_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+
+ data8 = QIXIS_READ(brdcfg[12]);
+ data8 |= 0x20;
+ QIXIS_WRITE(brdcfg[12], data8);
+
+ } else {
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ if (ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1)
+ < 0) {
+ printf("Failed to register mdio for %s\n", mdio_name);
+ }
+
+ /* MAC1*/
+ mdio_name = ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1);
+ bus = miiphy_get_dev_by_name(mdio_name);
+ pfe_set_mdio(0, bus);
+ pfe_set_phy_address_mode(0, SGMII_2500_PHY1_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ }
+ break;
+
+ default:
+ printf("ls1012aqds:unsupported SerDes PRCTL= %d\n", srds_s1);
+ break;
+ }
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 406194d..4577917 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -25,9 +25,9 @@
#include <fsl_mmdc.h>
#include <spl.h>
#include <netdev.h>
-
#include "../common/qixis.h"
#include "ls1012aqds_qixis.h"
+#include "ls1012aqds_pfe.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -128,11 +128,6 @@ int board_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
int esdhc_status_fixup(void *blob, const char *compat)
{
char esdhc0_path[] = "/soc/esdhc at 1560000";
@@ -161,12 +156,102 @@ int esdhc_status_fixup(void *blob, const char *compat)
return 0;
}
+static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
+ char *enet_path, char *mdio_path)
+{
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
+ &prop_val.busid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
+ &prop_val.phyid, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
+ &prop_val.mux_val, PFE_PROP_LEN, 1);
+ do_fixup_by_path(set_blob, enet_path, "phy-mode",
+ prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
+ do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
+ &prop_val.phy_mask, PFE_PROP_LEN, 1);
+ return 0;
+}
+
+static void fdt_fsl_fixup_of_pfe(void *blob)
+{
+ int i = 0;
+ struct pfe_prop_val prop_val;
+ void *l_blob = blob;
+
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ for (i = 0; i < NUM_ETH_NODE; i++) {
+ switch (srds_s1) {
+ case SERDES_1_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_1G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_1G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_1G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_1G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "rgmii";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ case SERDES_2_5_G_PROTOCOL:
+ if (i == 0) {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_1_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_1_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_1_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
+ ETH_1_MDIO);
+ } else {
+ prop_val.busid = cpu_to_fdt32(
+ ETH_2_2_5G_BUS_ID);
+ prop_val.phyid = cpu_to_fdt32(
+ ETH_2_2_5G_PHY_ID);
+ prop_val.mux_val = cpu_to_fdt32(
+ ETH_2_2_5G_MDIO_MUX);
+ prop_val.phy_mask = cpu_to_fdt32(
+ ETH_2_5G_MDIO_PHY_MASK);
+ prop_val.phy_mode = "sgmii-2500";
+ pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
+ ETH_2_MDIO);
+ }
+ break;
+ default:
+ printf("serdes:[%d]\n", srds_s1);
+ }
+ }
+}
+
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
arch_fixup_fdt(blob);
ft_cpu_setup(blob, bd);
+ fdt_fsl_fixup_of_pfe(blob);
return 0;
}
diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
new file mode 100644
index 0000000..c279ef3
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define ETH_1_1G_BUS_ID 0x1
+#define ETH_1_1G_PHY_ID 0x1e
+#define ETH_1_1G_MDIO_MUX 0x2
+#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD
+#define ETH_1_1G_PHY_MODE "sgmii"
+#define ETH_2_1G_BUS_ID 0x1
+#define ETH_2_1G_PHY_ID 0x1
+#define ETH_2_1G_MDIO_MUX 0x1
+#define ETH_2_1G_PHY_MODE "rgmii"
+
+#define ETH_1_2_5G_BUS_ID 0x0
+#define ETH_1_2_5G_PHY_ID 0x1
+#define ETH_1_2_5G_MDIO_MUX 0x2
+#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
+#define ETH_2_5G_PHY_MODE "sgmii-2500"
+#define ETH_2_2_5G_BUS_ID 0x1
+#define ETH_2_2_5G_PHY_ID 0x2
+#define ETH_2_2_5G_MDIO_MUX 0x3
+
+#define SERDES_1_G_PROTOCOL 0x3508
+#define SERDES_2_5_G_PROTOCOL 0x2205
+
+#define PFE_PROP_LEN 4
+
+#define ETH_1_SOC_PATH "/soc/pfe at 04000000/ethernet at 0"
+#define ETH_1_PATH "/pfe at 04000000/ethernet at 0"
+#define ETH_2_SOC_PATH "/soc/pfe at 04000000/ethernet at 1"
+#define ETH_2_PATH "/pfe at 04000000/ethernet at 1"
+
+#define ETH_1_MDIO_SOC_PATH "/soc/pfe at 04000000/ethernet at 0/mdio at 0"
+#define ETH_1_MDIO "/pfe at 04000000/ethernet at 0/mdio at 0"
+#define ETH_2_MDIO_SOC_PATH "/soc/pfe at 04000000/ethernet at 1/mdio at 0"
+#define ETH_2_MDIO "/pfe at 04000000/ethernet at 1/mdio@0"
+
+#define NUM_ETH_NODE 2
+struct pfe_prop_val {
+ int busid;
+ int phyid;
+ int mux_val;
+ int phy_mask;
+ char *phy_mode;
+};
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
index 584f604..7a1ba3d 100644
--- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -11,7 +11,7 @@
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xe0
-#define BRDCFG4_EMISEL_SHIFT 5
+#define BRDCFG4_EMISEL_SHIFT 6
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (5 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:44 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb Calvin Johnson
` (7 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
This patch enables ethernet support for ls1012afrdm.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
board/freescale/ls1012afrdm/Kconfig | 14 ++++
board/freescale/ls1012afrdm/Makefile | 1 +
board/freescale/ls1012afrdm/eth.c | 122 ++++++++++++++++++++++++++++++
board/freescale/ls1012afrdm/ls1012afrdm.c | 5 --
4 files changed, 137 insertions(+), 5 deletions(-)
create mode 100644 board/freescale/ls1012afrdm/eth.c
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 38bd91b..ad6666b 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012afrdm"
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
index dbfa2ce..1364f22 100644
--- a/board/freescale/ls1012afrdm/Makefile
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012afrdm.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
new file mode 100644
index 0000000..4f4fff8
--- /dev/null
+++ b/board/freescale/ls1012afrdm/eth.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
+
+#define MASK_ETH_PHY_RST 0x00000100
+
+static inline void ls1012afrdm_reset_phy(void)
+{
+ unsigned int val;
+ struct ccsr_gpio *pgpio = (void *)(GPIO1_BASE_ADDR);
+
+ setbits_be32(&pgpio->gpdir, MASK_ETH_PHY_RST);
+
+ val = in_be32(&pgpio->gpdat);
+ setbits_be32(&pgpio->gpdat, val & ~MASK_ETH_PHY_RST);
+ mdelay(10);
+
+ val = in_be32(&pgpio->gpdat);
+ setbits_be32(&pgpio->gpdat, val | MASK_ETH_PHY_RST);
+ mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ struct pfe_mdio_info mac_mdio_info;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ if (!init_done) {
+ ls1012afrdm_reset_phy();
+
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+
+ init_done = 1;
+ }
+
+ if (priv->gemac_port) {
+ mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ }
+
+ pfe_set_mdio(priv->gemac_port,
+ miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ if (!priv->gemac_port)
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ else
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 9afd1c4..0145886 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -57,11 +57,6 @@ int dram_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (6 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 19:45 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb Calvin Johnson
` (6 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
This patch enables ethernet support for ls1012ardb.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-split from original patch "board: freescale: ls1012a: enable network
support on ls1012a platforms"
---
board/freescale/ls1012ardb/Kconfig | 14 +++++
board/freescale/ls1012ardb/Makefile | 1 +
board/freescale/ls1012ardb/eth.c | 106 ++++++++++++++++++++++++++++++++
board/freescale/ls1012ardb/ls1012ardb.c | 4 --
include/configs/ls1012ardb.h | 4 ++
5 files changed, 125 insertions(+), 4 deletions(-)
create mode 100644 board/freescale/ls1012ardb/eth.c
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index d13b08e..6e6197a 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -12,6 +12,20 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012ardb"
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
index 05fa9d9..bd80ce5 100644
--- a/board/freescale/ls1012ardb/Makefile
+++ b/board/freescale/ls1012ardb/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1012ardb.o
+obj-y += eth.o
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
new file mode 100644
index 0000000..bf67590
--- /dev/null
+++ b/board/freescale/ls1012ardb/eth.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <asm/types.h>
+#include <fsl_dtsec.h>
+#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch/fsl_serdes.h>
+#include <pfe_eth/pfe_eth.h>
+#include <dm/platform_data/pfe_dm_eth.h>
+#include <i2c.h>
+
+#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
+
+static inline void ls1012ardb_reset_phy(void)
+{
+ /* Through reset IO expander reset both RGMII and SGMII PHYs */
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH1_MASK);
+ mdelay(10);
+ i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
+ mdelay(50);
+}
+
+int pfe_eth_board_init(struct udevice *dev)
+{
+ static int init_done;
+ struct mii_dev *bus;
+ struct pfe_mdio_info mac_mdio_info;
+ struct pfe_eth_dev *priv = dev_get_priv(dev);
+
+ if (!init_done) {
+ ls1012ardb_reset_phy();
+ mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
+ mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
+
+ bus = pfe_mdio_init(&mac_mdio_info);
+ if (!bus) {
+ printf("Failed to register mdio\n");
+ return -1;
+ }
+ init_done = 1;
+ }
+
+ pfe_set_mdio(priv->gemac_port,
+ miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII_TXID);
+ }
+ return 0;
+}
+
+static struct pfe_eth_pdata pfe_pdata0 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC1_BASE_ADDR,
+ .phy_interface = 0,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+static struct pfe_eth_pdata pfe_pdata1 = {
+ .pfe_eth_pdata_mac = {
+ .iobase = (phys_addr_t)EMAC2_BASE_ADDR,
+ .phy_interface = 1,
+ },
+
+ .pfe_ddr_addr = {
+ .ddr_pfe_baseaddr = (void *)CONFIG_DDR_PFE_BASEADDR,
+ .ddr_pfe_phys_baseaddr = CONFIG_DDR_PFE_PHYS_BASEADDR,
+ },
+};
+
+U_BOOT_DEVICE(ls1012a_pfe0) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata0,
+};
+
+U_BOOT_DEVICE(ls1012a_pfe1) = {
+ .name = "pfe_eth",
+ .platdata = &pfe_pdata1,
+};
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index c9557bb..ed5a8e6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -114,10 +114,6 @@ int dram_init(void)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
int board_early_init_f(void)
{
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 438b5a6..ced6c5e 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -25,6 +25,7 @@
*/
#define I2C_MUX_IO_ADDR 0x24
+#define I2C_MUX_IO2_ADDR 0x25
#define I2C_MUX_IO_0 0
#define I2C_MUX_IO_1 1
#define SW_BOOT_MASK 0x03
@@ -39,6 +40,9 @@
#define SW_REV_C2 0xD8
#define SW_REV_D 0xD0
#define SW_REV_E 0xC8
+#define __PHY_MASK 0xF9
+#define __PHY_ETH2_MASK 0xFB
+#define __PHY_ETH1_MASK 0xFD
/* MMC */
#ifdef CONFIG_MMC
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (7 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 20:03 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure Calvin Johnson
` (5 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
This patch enables ethernet support for ls1012a2g5rdb.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
---
Changes in v2:
-New patch added to series to enable ethernet support for
ls1012a2g5rdb
---
board/freescale/ls1012ardb/Kconfig | 14 ++++++++++++++
board/freescale/ls1012ardb/eth.c | 25 +++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index 6e6197a..4bb672c 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -44,6 +44,20 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012a2g5rdb"
+if FSL_PFE
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index bf67590..fc062cf 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -26,6 +26,7 @@
static inline void ls1012ardb_reset_phy(void)
{
+#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50);
+#endif
}
int pfe_eth_board_init(struct udevice *dev)
@@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
if (!init_done) {
ls1012ardb_reset_phy();
@@ -59,6 +66,8 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port,
miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
+ switch (srds_s1) {
+ case 0x3508:
if (!priv->gemac_port) {
/* MAC1 */
pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
@@ -68,6 +77,22 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
PHY_INTERFACE_MODE_RGMII_TXID);
}
+ break;
+ case 0x2208:
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ }
+ break;
+ default:
+ printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+ break;
+ }
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (8 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 20:05 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC Calvin Johnson
` (4 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
SoC specific PFE macros are defined and structure ccsr_scfg
is updated with members defined for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2: None
---
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 38 ++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b195005..e1a57de 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -395,6 +395,21 @@ struct ccsr_gur {
#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
+/* RGMIIPCR bit definitions*/
+#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
+#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
+#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
+#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
+#define SCFG_RGMIIPCR_SETFD (0x00000001)
+
+/*PFEASBCR bit definitions */
+#define SCFG_PFEASBCR_ARCACHE0 (0x80000000)
+#define SCFG_PFEASBCR_AWCACHE0 (0x40000000)
+#define SCFG_PFEASBCR_ARCACHE1 (0x20000000)
+#define SCFG_PFEASBCR_AWCACHE1 (0x10000000)
+#define SCFG_PFEASBCR_ARSNP (0x08000000)
+#define SCFG_PFEASBCR_AWSNP (0x04000000)
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u8 res_000[0x100-0x000];
@@ -412,7 +427,12 @@ struct ccsr_scfg {
u8 res_140[0x158-0x140];
u32 altcbar;
u32 qspi_cfg;
- u8 res_160[0x180-0x160];
+ u8 res_160[0x164 - 0x160];
+ u32 wr_qos1;
+ u32 wr_qos2;
+ u32 rd_qos1;
+ u32 rd_qos2;
+ u8 res_174[0x180 - 0x174];
u32 dmamcr;
u8 res_184[0x188-0x184];
u32 gic_align;
@@ -443,7 +463,21 @@ struct ccsr_scfg {
u32 usb_refclk_selcr1;
u32 usb_refclk_selcr2;
u32 usb_refclk_selcr3;
- u8 res_424[0x600-0x424];
+ u8 res_424[0x434 - 0x424];
+ u32 rgmiipcr;
+ u32 res_438;
+ u32 rgmiipsr;
+ u32 pfepfcssr1;
+ u32 pfeintencr1;
+ u32 pfepfcssr2;
+ u32 pfeintencr2;
+ u32 pfeerrcr;
+ u32 pfeeerrintencr;
+ u32 pfeasbcr;
+ u32 pfebsbcr;
+ u8 res_460[0x484 - 0x460];
+ u32 mdioselcr;
+ u8 res_468[0x600 - 0x488];
u32 scratchrw[4];
u8 res_610[0x680-0x610];
u32 corebcr;
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (9 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 20:06 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers Calvin Johnson
` (3 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
to bufferable.
2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
3. Disable ECC detection for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-Improved commit message to provide more description
-Replaced magic numbers with proper definitions
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 ++++++++++++++++++++++
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 12 ++++++++++-
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index b9f837d..18fb937 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -612,6 +612,29 @@ int setup_chip_volt(void)
return 0;
}
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void)
+{
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ u32 ecccr2;
+
+ out_be32(&scfg->pfeasbcr,
+ in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
+ out_be32(&scfg->pfebsbcr,
+ in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
+
+ /* CCI-400 QoS settings for PFE */
+ out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
+ | SCFG_WR_QOS1_PFE2_QOS));
+ out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
+ | SCFG_RD_QOS1_PFE2_QOS));
+
+ ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
+ out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
+ ecccr2 | (unsigned int)DISABLE_PFE_ECC);
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index e1a57de..11cf35c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -205,6 +205,8 @@ struct sys_info {
/* Device Configuration and Pin Control */
#define DCFG_DCSR_PORCR1 0x0
+#define DCFG_DCSR_ECCCR2 0x524
+#define DISABLE_PFE_ECC BIT(13)
struct ccsr_gur {
u32 porsr1; /* POR status 1 */
@@ -402,7 +404,7 @@ struct ccsr_gur {
#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
#define SCFG_RGMIIPCR_SETFD (0x00000001)
-/*PFEASBCR bit definitions */
+/* PFEASBCR bit definitions */
#define SCFG_PFEASBCR_ARCACHE0 (0x80000000)
#define SCFG_PFEASBCR_AWCACHE0 (0x40000000)
#define SCFG_PFEASBCR_ARCACHE1 (0x20000000)
@@ -410,6 +412,14 @@ struct ccsr_gur {
#define SCFG_PFEASBCR_ARSNP (0x08000000)
#define SCFG_PFEASBCR_AWSNP (0x04000000)
+/* WR_QoS1 PFE bit definitions */
+#define SCFG_WR_QOS1_PFE1_QOS GENMASK(27, 24)
+#define SCFG_WR_QOS1_PFE2_QOS GENMASK(23, 20)
+
+/* RD_QoS1 PFE bit definitions */
+#define SCFG_RD_QOS1_PFE1_QOS GENMASK(27, 24)
+#define SCFG_RD_QOS1_PFE2_QOS GENMASK(23, 20)
+
/* Supplemental Configuration Unit */
struct ccsr_scfg {
u8 res_000[0x100-0x000];
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index cb760b5..d9bfddb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -127,6 +127,9 @@ void fsl_lsch2_early_init_f(void);
int setup_chip_volt(void);
/* Setup core vdd in unit mV */
int board_setup_core_volt(u32 vdd);
+#ifdef CONFIG_FSL_PFE
+void init_pfe_scfg_dcfg_regs(void);
+#endif
#endif
void cpu_name(char *name);
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (10 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 20:06 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A Calvin Johnson
` (2 subsequent siblings)
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
Enable all types of non-secure access to PFE block registers.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-Improved commit message to provide more description
---
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+ CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (11 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers Calvin Johnson
@ 2018-02-15 14:17 ` Calvin Johnson
2018-02-27 20:16 ` Joe Hershberger
2018-02-27 23:49 ` Joe Hershberger
2018-02-15 15:48 ` [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series York Sun
2018-02-22 4:32 ` Calvin Johnson
14 siblings, 2 replies; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 14:17 UTC (permalink / raw)
To: u-boot
Add configurations for PFE.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
---
Changes in v2:
-Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
-Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
---
configs/ls1012a2g5rdb_qspi_defconfig | 2 ++
configs/ls1012afrdm_qspi_defconfig | 2 ++
configs/ls1012aqds_qspi_defconfig | 2 ++
configs/ls1012ardb_qspi_defconfig | 2 ++
drivers/net/Kconfig | 1 +
drivers/net/Makefile | 1 +
drivers/net/pfe_eth/Kconfig | 17 +++++++++++++++++
drivers/net/pfe_eth/Makefile | 12 ++++++++++++
include/configs/ls1012a2g5rdb.h | 2 +-
include/configs/ls1012a_common.h | 6 +++---
include/configs/ls1012afrdm.h | 9 ++++++++-
include/configs/ls1012aqds.h | 14 ++++++++++++++
include/configs/ls1012ardb.h | 10 +++++++++-
13 files changed, 74 insertions(+), 6 deletions(-)
create mode 100644 drivers/net/pfe_eth/Kconfig
create mode 100644 drivers/net/pfe_eth/Makefile
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 140a4e1..a979211 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -30,7 +30,9 @@ CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
+CONFIG_FSL_PFE=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_USB=y
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
index 060f073..d0bf081 100644
--- a/configs/ls1012afrdm_qspi_defconfig
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -28,8 +28,10 @@ CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_FSL_PFE=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 0435d51..40fbdd8 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -39,8 +39,10 @@ CONFIG_SCSI_AHCI=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_FSL_PFE=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index ea28953..6262351 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -31,8 +31,10 @@ CONFIG_DM=y
CONFIG_DM_MMC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
+CONFIG_FSL_PFE=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index de1947c..f589978 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1,4 +1,5 @@
source "drivers/net/phy/Kconfig"
+source "drivers/net/pfe_eth/Kconfig"
config DM_ETH
bool "Enable Driver Model for Ethernet drivers"
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index ac5443c..102e65a 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_FSL_PFE) += pfe_eth/
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
new file mode 100644
index 0000000..6f99710
--- /dev/null
+++ b/drivers/net/pfe_eth/Kconfig
@@ -0,0 +1,17 @@
+menuconfig FSL_PFE
+ bool "Freescale PFE driver"
+ help
+ This driver provides support for Freescale PFE.
+
+if FSL_PFE
+
+config UTIL_PE_DISABLED
+ bool
+ help
+ Disable UTIL processor engine of PFE
+
+config SYS_FSL_PFE_ADDR
+ hex "PFE base address"
+ default 0x04000000
+
+endif
diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
new file mode 100644
index 0000000..6b5248f
--- /dev/null
+++ b/drivers/net/pfe_eth/Makefile
@@ -0,0 +1,12 @@
+# Copyright 2015-2016 Freescale Semiconductor, Inc.
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:GPL-2.0+
+
+# Layerscape PFE driver
+obj-y += pfe_cmd.o \
+ pfe_driver.o \
+ pfe_eth.o \
+ pfe_firmware.o \
+ pfe_hw.o \
+ pfe_mdio.o
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 25df103..2d18f3c 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -110,7 +110,7 @@
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
#endif
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 7dbe231..b590d7a 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -118,9 +118,9 @@
"kernel_size=0x2800000\0" \
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
- "$kernel_start $kernel_size && "\
- "bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
+ "$kernel_start $kernel_size && "\
+ "bootm $kernel_load"
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index 297c057..f54021e 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -9,6 +9,13 @@
#include "ls1012a_common.h"
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x2
+#define EMAC2_PHY_ADDR 0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_REALTEK
+#endif
+
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
@@ -68,7 +75,7 @@
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
+#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
#define CONFIG_CMD_MEMINFO
#define CONFIG_CMD_MEMTEST
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index e1767ef..f6c2650 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -9,6 +9,20 @@
#include "ls1012a_common.h"
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x1e
+#define EMAC2_PHY_ADDR 0x1
+#define SGMII_2500_PHY1_ADDR 0x1
+#define SGMII_2500_PHY2_ADDR 0x2
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_REALTEK
+#define CONFIG_PHY_AQUANTIA
+#define CONFIG_PHYLIB_10G
+#define RGMII_RESET_WA
+#endif
+
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index ced6c5e..3054ba1 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -9,6 +9,14 @@
#include "ls1012a_common.h"
+/* PFE Ethernet */
+#ifdef CONFIG_FSL_PFE
+#define EMAC1_PHY_ADDR 0x2
+#define EMAC2_PHY_ADDR 0x1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_REALTEK
+#endif
+
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
@@ -102,7 +110,7 @@
"$kernel_addr $kernel_size && bootm $load_addr#$board\0"
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
+#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd;run qspi_bootcmd"
#include <asm/fsl_secure_boot.h>
--
2.7.4
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (12 preceding siblings ...)
2018-02-15 14:17 ` [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A Calvin Johnson
@ 2018-02-15 15:48 ` York Sun
2018-02-15 16:44 ` Calvin Johnson
2018-02-22 4:32 ` Calvin Johnson
14 siblings, 1 reply; 38+ messages in thread
From: York Sun @ 2018-02-15 15:48 UTC (permalink / raw)
To: u-boot
On 02/15/2018 06:10 AM, Calvin Johnson wrote:
> Hi,
>
> This patch series introduces U-Boot support for NXP's LS1012A Packet
> Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
> engine to provide high performance Ethernet interfaces. The device
> includes two Ethernet ports.
>
> Changes in v2 series:
> 1. PFE patches submitted on top of this base patch are now merged to
> this patch.
> 2. Platform changes are segregated into different patches.
> 3. Network enabled on 2g5rdb platform
> 4. Moved from legacy to new driver model.
>
> Calvin Johnson (12):
> drivers: net: phy: Fix aquantia compilation with DM
> drivers: net: pfe_eth: LS1012A PFE driver introduction
> drivers: net: pfe_eth: provide pfe commands
> drivers: net: pfe_eth: LS1012A PFE headers
> board: freescale: ls1012aqds: enable network support on ls1012aqds
> board: freescale: ls1012afrdm: enable network support on ls1012afrdm
> board: freescale: ls1012ardb: enable network support on ls1012ardb
> board: freescale: ls1012a2g5rdb: enable network support on
> ls1012a2g5rdb
> armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
> armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
> armv8: layerscape: csu: enable ns access to PFE registers
> configs: ls1012a: add pfe configuration for LS1012A
>
> Prabhakar Kushwaha (1):
> armv8: fsl-layerscape: Add support of GPIO structure
Calvin,
I think you should update your copyright year. Is it right to add
2015-2016 copyright year? Did you have these files then?
York
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-15 15:48 ` [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series York Sun
@ 2018-02-15 16:44 ` Calvin Johnson
2018-02-16 14:24 ` Anji Jagarlmudi
0 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-15 16:44 UTC (permalink / raw)
To: u-boot
Hi York,
> -----Original Message-----
> From: York Sun
> Sent: Thursday, February 15, 2018 9:19 PM
> To: Calvin Johnson <calvin.johnson@nxp.com>; u-boot at lists.denx.de
> Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
> Subject: Re: [PATCH v2 00/13] LS1012A PFE driver patch series
>
> On 02/15/2018 06:10 AM, Calvin Johnson wrote:
> > Hi,
> >
> > This patch series introduces U-Boot support for NXP's LS1012A Packet
> > Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
> > engine to provide high performance Ethernet interfaces. The device
> > includes two Ethernet ports.
> >
> > Changes in v2 series:
> > 1. PFE patches submitted on top of this base patch are now merged to
> > this patch.
> > 2. Platform changes are segregated into different patches.
> > 3. Network enabled on 2g5rdb platform
> > 4. Moved from legacy to new driver model.
> >
> > Calvin Johnson (12):
> > drivers: net: phy: Fix aquantia compilation with DM
> > drivers: net: pfe_eth: LS1012A PFE driver introduction
> > drivers: net: pfe_eth: provide pfe commands
> > drivers: net: pfe_eth: LS1012A PFE headers
> > board: freescale: ls1012aqds: enable network support on ls1012aqds
> > board: freescale: ls1012afrdm: enable network support on ls1012afrdm
> > board: freescale: ls1012ardb: enable network support on ls1012ardb
> > board: freescale: ls1012a2g5rdb: enable network support on
> > ls1012a2g5rdb
> > armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
> > armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
> > armv8: layerscape: csu: enable ns access to PFE registers
> > configs: ls1012a: add pfe configuration for LS1012A
> >
> > Prabhakar Kushwaha (1):
> > armv8: fsl-layerscape: Add support of GPIO structure
>
> Calvin,
>
> I think you should update your copyright year. Is it right to add
> 2015-2016 copyright year? Did you have these files then?
I think most of the pfe driver files, except for board files were present
during that period.
However, I would wait for Anji to respond on this. Based on his response
I can update copyright year if required.
Thanks
Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-15 16:44 ` Calvin Johnson
@ 2018-02-16 14:24 ` Anji Jagarlmudi
0 siblings, 0 replies; 38+ messages in thread
From: Anji Jagarlmudi @ 2018-02-16 14:24 UTC (permalink / raw)
To: u-boot
Hi York,
> > I think you should update your copyright year. Is it right to add
> > 2015-2016 copyright year? Did you have these files then?
Yes, these files were exit during that time. In fact these files were exist since 2011 with Mindspeed copyright.
We did modifications for LS1012A and using them since 2015, I think during cleanup Mindspeed copyright has been removed.
Regards,
Anji
> -----Original Message-----
> From: Calvin Johnson
> Sent: Thursday, February 15, 2018 10:14 PM
> To: York Sun <york.sun@nxp.com>; u-boot at lists.denx.de
> Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
> Subject: RE: [PATCH v2 00/13] LS1012A PFE driver patch series
>
> Hi York,
>
> > -----Original Message-----
> > From: York Sun
> > Sent: Thursday, February 15, 2018 9:19 PM
> > To: Calvin Johnson <calvin.johnson@nxp.com>; u-boot at lists.denx.de
> > Cc: joe.hershberger at ni.com; Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
> > Subject: Re: [PATCH v2 00/13] LS1012A PFE driver patch series
> >
> > On 02/15/2018 06:10 AM, Calvin Johnson wrote:
> > > Hi,
> > >
> > > This patch series introduces U-Boot support for NXP's LS1012A Packet
> > > Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
> > > engine to provide high performance Ethernet interfaces. The device
> > > includes two Ethernet ports.
> > >
> > > Changes in v2 series:
> > > 1. PFE patches submitted on top of this base patch are now merged to
> > > this patch.
> > > 2. Platform changes are segregated into different patches.
> > > 3. Network enabled on 2g5rdb platform 4. Moved from legacy to new
> > > driver model.
> > >
> > > Calvin Johnson (12):
> > > drivers: net: phy: Fix aquantia compilation with DM
> > > drivers: net: pfe_eth: LS1012A PFE driver introduction
> > > drivers: net: pfe_eth: provide pfe commands
> > > drivers: net: pfe_eth: LS1012A PFE headers
> > > board: freescale: ls1012aqds: enable network support on ls1012aqds
> > > board: freescale: ls1012afrdm: enable network support on ls1012afrdm
> > > board: freescale: ls1012ardb: enable network support on ls1012ardb
> > > board: freescale: ls1012a2g5rdb: enable network support on
> > > ls1012a2g5rdb
> > > armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
> > > armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
> > > armv8: layerscape: csu: enable ns access to PFE registers
> > > configs: ls1012a: add pfe configuration for LS1012A
> > >
> > > Prabhakar Kushwaha (1):
> > > armv8: fsl-layerscape: Add support of GPIO structure
> >
> > Calvin,
> >
> > I think you should update your copyright year. Is it right to add
> > 2015-2016 copyright year? Did you have these files then?
>
> I think most of the pfe driver files, except for board files were present during
> that period.
>
> However, I would wait for Anji to respond on this. Based on his response I
> can update copyright year if required.
>
> Thanks
> Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
` (13 preceding siblings ...)
2018-02-15 15:48 ` [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series York Sun
@ 2018-02-22 4:32 ` Calvin Johnson
2018-02-26 20:00 ` Joe Hershberger
14 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-22 4:32 UTC (permalink / raw)
To: u-boot
Hi Joe,
> -----Original Message-----
> From: Calvin Johnson [mailto:calvin.johnson at nxp.com]
> Sent: Thursday, February 15, 2018 7:47 PM
> To: u-boot at lists.denx.de
> Cc: joe.hershberger at ni.com; York Sun <york.sun@nxp.com>; Anji Jagarlmudi
> <anji.jagarlmudi@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
>
<snip>
> Changes in v2 series:
> 1. PFE patches submitted on top of this base patch are now merged to
> this patch.
> 2. Platform changes are segregated into different patches.
> 3. Network enabled on 2g5rdb platform
> 4. Moved from legacy to new driver model.
Gentle reminder. Hope the PFE patches didn't miss your sight.
Thanks & Regards
Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-22 4:32 ` Calvin Johnson
@ 2018-02-26 20:00 ` Joe Hershberger
2018-02-27 4:49 ` Calvin Johnson
0 siblings, 1 reply; 38+ messages in thread
From: Joe Hershberger @ 2018-02-26 20:00 UTC (permalink / raw)
To: u-boot
Hi Calvin,
On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Hi Joe,
>
>> -----Original Message-----
>> From: Calvin Johnson [mailto:calvin.johnson at nxp.com]
>> Sent: Thursday, February 15, 2018 7:47 PM
>> To: u-boot at lists.denx.de
>> Cc: joe.hershberger at ni.com; York Sun <york.sun@nxp.com>; Anji Jagarlmudi
>> <anji.jagarlmudi@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
>> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
>>
>
> <snip>
>
>> Changes in v2 series:
>> 1. PFE patches submitted on top of this base patch are now merged to
>> this patch.
>> 2. Platform changes are segregated into different patches.
>> 3. Network enabled on 2g5rdb platform
>> 4. Moved from legacy to new driver model.
>
> Gentle reminder. Hope the PFE patches didn't miss your sight.
I tried applying your series and it had many checkpatch issues. Please
resolve those and resend.
Thanks,
-Joe
-----------------
Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
(823206.mbox)
823206.mbox:46: WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?
823206.mbox:534: CHECK: Avoid CamelCase: <Elf32_Shdr>
823206.mbox:551: CHECK: No space is necessary after a cast
823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)
823206.mbox:728: CHECK: Unbalanced braces around else statement
823206.mbox:835: WARNING: else is not generally useful after a break or return
823206.mbox:1231: CHECK: Please use a blank line after
function/struct/union/enum declarations
823206.mbox:1237: CHECK: spaces preferred around that '<<' (ctx:VxV)
823206.mbox:1237: CHECK: spaces preferred around that '|' (ctx:VxV)
823206.mbox:1461: CHECK: Comparison to NULL could be written "!g_rx_desc"
823206.mbox:1487: CHECK: Comparison to NULL could be written "!g_rx_desc"
823206.mbox:1520: CHECK: Comparison to NULL could be written "!rx_desc"
823206.mbox:1573: CHECK: Comparison to NULL could be written "!g_tx_desc"
823206.mbox:1606: CHECK: Comparison to NULL could be written "!tx_desc"
823206.mbox:1891: WARNING: Statements should start on a tabstop
823206.mbox:1901: WARNING: Statements should start on a tabstop
823206.mbox:1937: CHECK: spaces preferred around that '|' (ctx:VxV)
823206.mbox:2100: CHECK: Please don't use multiple blank lines
823206.mbox:2118: CHECK: Please don't use multiple blank lines
823206.mbox:2132: WARNING: suspect code indent for conditional
statements (8, 24)
823206.mbox:2178: CHECK: Alignment should match open parenthesis
823206.mbox:2462: CHECK: Avoid CamelCase: <Elf32_Ehdr>
823206.mbox:2605: CHECK: Prefer kernel type 'u8' over 'uint8_t'
total: 0 errors, 5 warnings, 18 checks, 2580 lines checked
Checking patch drivers/net/pfe_eth/Kconfig...
Checking patch drivers/net/pfe_eth/Makefile...
Checking patch drivers/net/pfe_eth/pfe.c...
Checking patch drivers/net/pfe_eth/pfe_driver.c...
Checking patch drivers/net/pfe_eth/pfe_eth.c...
Checking patch drivers/net/pfe_eth/pfe_firmware.c...
Applied patch drivers/net/pfe_eth/Kconfig cleanly.
Applied patch drivers/net/pfe_eth/Makefile cleanly.
Applied patch drivers/net/pfe_eth/pfe.c cleanly.
Applied patch drivers/net/pfe_eth/pfe_driver.c cleanly.
Applied patch drivers/net/pfe_eth/pfe_eth.c cleanly.
Applied patch drivers/net/pfe_eth/pfe_firmware.c cleanly.
Applying: drivers: net: pfe_eth: LS1012A PFE driver introduction
Fetched U-Boot-2-9-drivers-net-pfe_eth-provide-pfe-commands (823207.mbox)
823207.mbox:43: WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?
823207.mbox:83: WARNING: line over 80 characters
823207.mbox:94: CHECK: spaces preferred around that '&' (ctx:VxV)
823207.mbox:117: WARNING: line over 80 characters
823207.mbox:128: CHECK: spaces preferred around that '&' (ctx:VxV)
823207.mbox:141: WARNING: line over 80 characters
823207.mbox:152: WARNING: line over 80 characters
823207.mbox:166: WARNING: line over 80 characters
823207.mbox:184: WARNING: line over 80 characters
823207.mbox:193: WARNING: line over 80 characters
823207.mbox:248: WARNING: line over 80 characters
823207.mbox:294: WARNING: Prefer using '"%s...", __func__' to using
'gpi', this function's name, in a string
823207.mbox:307: WARNING: Prefer using '"%s...", __func__' to using
'bmu', this function's name, in a string
823207.mbox:385: WARNING: suspect code indent for conditional
statements (16, 16)
823207.mbox:385: CHECK: Unbalanced braces around else statement
823207.mbox:393: WARNING: line over 80 characters
823207.mbox:405: WARNING: Missing a blank line after declarations
823207.mbox:444: WARNING: line over 80 characters
823207.mbox:448: WARNING: void function return statements are not
generally useful
823207.mbox:532: CHECK: spaces preferred around that '+' (ctx:VxV)
823207.mbox:546: CHECK: spaces preferred around that '+' (ctx:VxV)
823207.mbox:578: CHECK: Please don't use multiple blank lines
total: 0 errors, 16 warnings, 6 checks, 544 lines checked
Checking patch drivers/net/pfe_eth/Makefile...
Checking patch drivers/net/pfe_eth/pfe_cmd.c...
Applied patch drivers/net/pfe_eth/Makefile cleanly.
Applied patch drivers/net/pfe_eth/pfe_cmd.c cleanly.
Applying: drivers: net: pfe_eth: provide pfe commands
Fetched U-Boot-3-9-drivers-net-pfe_eth-LS1012A-PFE-headers (823209.mbox)
823209.mbox:50: WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?
823209.mbox:101: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:101: CHECK: Prefer using the BIT macro
823209.mbox:103: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:105: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:105: CHECK: Prefer using the BIT macro
823209.mbox:106: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:106: CHECK: Prefer using the BIT macro
823209.mbox:108: CHECK: Macro argument reuse 'size' - possible side-effects?
823209.mbox:119: CHECK: Prefer using the BIT macro
823209.mbox:124: CHECK: Prefer using the BIT macro
823209.mbox:340: CHECK: Prefer using the BIT macro
823209.mbox:341: CHECK: Prefer using the BIT macro
823209.mbox:342: CHECK: Prefer using the BIT macro
823209.mbox:343: CHECK: Prefer using the BIT macro
823209.mbox:344: CHECK: Prefer using the BIT macro
823209.mbox:345: CHECK: Prefer using the BIT macro
823209.mbox:346: CHECK: Prefer using the BIT macro
823209.mbox:348: CHECK: Prefer using the BIT macro
823209.mbox:351: CHECK: Prefer using the BIT macro
823209.mbox:353: CHECK: Prefer using the BIT macro
823209.mbox:354: CHECK: Prefer using the BIT macro
823209.mbox:355: CHECK: Prefer using the BIT macro
823209.mbox:628: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:628: CHECK: Prefer using the BIT macro
823209.mbox:629: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:629: CHECK: Prefer using the BIT macro
823209.mbox:630: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:630: CHECK: Prefer using the BIT macro
823209.mbox:633: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:633: CHECK: Prefer using the BIT macro
823209.mbox:636: CHECK: Prefer using the BIT macro
823209.mbox:637: CHECK: Prefer using the BIT macro
823209.mbox:638: CHECK: Prefer using the BIT macro
823209.mbox:639: CHECK: Prefer using the BIT macro
823209.mbox:640: CHECK: Prefer using the BIT macro
823209.mbox:649: CHECK: Prefer using the BIT macro
823209.mbox:650: CHECK: Prefer using the BIT macro
823209.mbox:651: CHECK: Prefer using the BIT macro
823209.mbox:652: CHECK: Prefer using the BIT macro
823209.mbox:653: CHECK: Prefer using the BIT macro
823209.mbox:654: CHECK: Prefer using the BIT macro
823209.mbox:655: CHECK: Prefer using the BIT macro
823209.mbox:656: CHECK: Prefer using the BIT macro
823209.mbox:657: CHECK: Prefer using the BIT macro
823209.mbox:658: CHECK: Prefer using the BIT macro
823209.mbox:839: CHECK: Prefer using the BIT macro
823209.mbox:840: CHECK: Prefer using the BIT macro
823209.mbox:841: CHECK: Prefer using the BIT macro
823209.mbox:842: CHECK: Prefer using the BIT macro
823209.mbox:843: CHECK: Prefer using the BIT macro
823209.mbox:844: CHECK: Prefer using the BIT macro
823209.mbox:845: CHECK: Prefer using the BIT macro
823209.mbox:846: CHECK: Prefer using the BIT macro
823209.mbox:847: CHECK: Prefer using the BIT macro
823209.mbox:848: CHECK: spaces preferred around that '<<' (ctx:VxV)
823209.mbox:848: CHECK: Prefer using the BIT macro
823209.mbox:964: CHECK: Macro argument reuse 'addr' - possible side-effects?
823209.mbox:967: CHECK: Macro argument reuse 'addr' - possible side-effects?
823209.mbox:970: CHECK: Macro argument reuse 'addr' - possible side-effects?
823209.mbox:974: CHECK: Macro argument reuse 'addr' - possible side-effects?
823209.mbox:978: CHECK: Macro argument reuse 'addr' - possible side-effects?
823209.mbox:1030: CHECK: Prefer using the BIT macro
823209.mbox:1071: CHECK: Avoid CamelCase: <Elf32_Shdr>
823209.mbox:1125: WARNING: Adding new packed members is to be done with care
823209.mbox:1133: WARNING: Adding new packed members is to be done with care
total: 0 errors, 3 warnings, 63 checks, 1172 lines checked
Checking patch include/pfe_eth/pfe/cbus.h...
Checking patch include/pfe_eth/pfe/cbus/bmu.h...
Checking patch include/pfe_eth/pfe/cbus/class_csr.h...
Checking patch include/pfe_eth/pfe/cbus/emac.h...
Checking patch include/pfe_eth/pfe/cbus/gpi.h...
Checking patch include/pfe_eth/pfe/cbus/hif.h...
Checking patch include/pfe_eth/pfe/cbus/hif_nocpy.h...
Checking patch include/pfe_eth/pfe/cbus/tmu_csr.h...
Checking patch include/pfe_eth/pfe/cbus/util_csr.h...
Checking patch include/pfe_eth/pfe/pfe.h...
Checking patch include/pfe_eth/pfe_driver.h...
Checking patch include/pfe_eth/pfe_eth.h...
Checking patch include/pfe_eth/pfe_firmware.h...
Applied patch include/pfe_eth/pfe/cbus.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/bmu.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/class_csr.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/emac.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/gpi.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/hif.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/hif_nocpy.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/tmu_csr.h cleanly.
Applied patch include/pfe_eth/pfe/cbus/util_csr.h cleanly.
Applied patch include/pfe_eth/pfe/pfe.h cleanly.
Applied patch include/pfe_eth/pfe_driver.h cleanly.
Applied patch include/pfe_eth/pfe_eth.h cleanly.
Applied patch include/pfe_eth/pfe_firmware.h cleanly.
Applying: drivers: net: pfe_eth: LS1012A PFE headers
Fetched U-Boot-4-9-board-freescale-ls1012a-enable-network-support-on-ls1012a-platforms
(823210.mbox)
823210.mbox:55: WARNING: added, moved or deleted file(s), does
MAINTAINERS need updating?
823210.mbox:122: WARNING: Block comments use a trailing */ on a separate line
823210.mbox:142: CHECK: Please don't use multiple blank lines
823210.mbox:239: CHECK: Alignment should match open parenthesis
823210.mbox:249: CHECK: Alignment should match open parenthesis
823210.mbox:344: WARNING: Block comments use a trailing */ on a separate line
823210.mbox:364: WARNING: suspect code indent for conditional
statements (16, 32)
823210.mbox:389: WARNING: Block comments use a trailing */ on a separate line
823210.mbox:400: WARNING: suspect code indent for conditional
statements (16, 32)
823210.mbox:511: WARNING: suspect code indent for conditional
statements (32, 32)
823210.mbox:538: WARNING: suspect code indent for conditional
statements (32, 32)
823210.mbox:674: CHECK: Please don't use multiple blank lines
total: 0 errors, 8 warnings, 4 checks, 640 lines checked
[ ... ]
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-26 20:00 ` Joe Hershberger
@ 2018-02-27 4:49 ` Calvin Johnson
2018-02-27 15:48 ` Joe Hershberger
0 siblings, 1 reply; 38+ messages in thread
From: Calvin Johnson @ 2018-02-27 4:49 UTC (permalink / raw)
To: u-boot
Hi Joe,
> -----Original Message-----
> From: Joe Hershberger [mailto:joe.hershberger at ni.com]
> Sent: Tuesday, February 27, 2018 1:31 AM
> To: Calvin Johnson <calvin.johnson@nxp.com>
> Cc: joe.hershberger at ni.com; u-boot at lists.denx.de; Anji Jagarlmudi
> <anji.jagarlmudi@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
>
> Hi Calvin,
>
> On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.johnson@nxp.com>
> wrote:
> > Hi Joe,
> >
> >> -----Original Message-----
> >> From: Calvin Johnson [mailto:calvin.johnson at nxp.com]
> >> Sent: Thursday, February 15, 2018 7:47 PM
> >> To: u-boot at lists.denx.de
> >> Cc: joe.hershberger at ni.com; York Sun <york.sun@nxp.com>; Anji Jagarlmudi
> >> <anji.jagarlmudi@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> >> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
> >>
> >
> > <snip>
> >
> >> Changes in v2 series:
> >> 1. PFE patches submitted on top of this base patch are now merged to
> >> this patch.
> >> 2. Platform changes are segregated into different patches.
> >> 3. Network enabled on 2g5rdb platform
> >> 4. Moved from legacy to new driver model.
> >
> > Gentle reminder. Hope the PFE patches didn't miss your sight.
>
> I tried applying your series and it had many checkpatch issues. Please
> resolve those and resend.
>
> Thanks,
> -Joe
>
> -----------------
>
>
> Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
> (823206.mbox)
> 823206.mbox:46: WARNING: added, moved or deleted file(s), does
> MAINTAINERS need updating?
> 823206.mbox:534: CHECK: Avoid CamelCase: <Elf32_Shdr>
> 823206.mbox:551: CHECK: No space is necessary after a cast
> 823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)
<snip>
Looks like you have run checkpatch on the v1 series (9 patches).
I had submitted the v2 series (13 patches).
However, in the v2 series, there are some checkpatch warnings like ' line over 80 characters'
which I had to ignore due to valid reasons. If there is any concern on these, I can work on them
after discussion.
Thanks
Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-27 4:49 ` Calvin Johnson
@ 2018-02-27 15:48 ` Joe Hershberger
2018-02-27 16:45 ` Calvin Johnson
0 siblings, 1 reply; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 15:48 UTC (permalink / raw)
To: u-boot
On Mon, Feb 26, 2018 at 10:49 PM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Hi Joe,
>
>> -----Original Message-----
>> From: Joe Hershberger [mailto:joe.hershberger at ni.com]
>> Sent: Tuesday, February 27, 2018 1:31 AM
>> To: Calvin Johnson <calvin.johnson@nxp.com>
>> Cc: joe.hershberger at ni.com; u-boot at lists.denx.de; Anji Jagarlmudi
>> <anji.jagarlmudi@nxp.com>
>> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
>>
>> Hi Calvin,
>>
>> On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.johnson@nxp.com>
>> wrote:
>> > Hi Joe,
>> >
>> >> -----Original Message-----
>> >> From: Calvin Johnson [mailto:calvin.johnson at nxp.com]
>> >> Sent: Thursday, February 15, 2018 7:47 PM
>> >> To: u-boot at lists.denx.de
>> >> Cc: joe.hershberger at ni.com; York Sun <york.sun@nxp.com>; Anji Jagarlmudi
>> >> <anji.jagarlmudi@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
>> >> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
>> >>
>> >
>> > <snip>
>> >
>> >> Changes in v2 series:
>> >> 1. PFE patches submitted on top of this base patch are now merged to
>> >> this patch.
>> >> 2. Platform changes are segregated into different patches.
>> >> 3. Network enabled on 2g5rdb platform
>> >> 4. Moved from legacy to new driver model.
>> >
>> > Gentle reminder. Hope the PFE patches didn't miss your sight.
>>
>> I tried applying your series and it had many checkpatch issues. Please
>> resolve those and resend.
>>
>> Thanks,
>> -Joe
>>
>> -----------------
>>
>>
>> Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
>> (823206.mbox)
>> 823206.mbox:46: WARNING: added, moved or deleted file(s), does
>> MAINTAINERS need updating?
>> 823206.mbox:534: CHECK: Avoid CamelCase: <Elf32_Shdr>
>> 823206.mbox:551: CHECK: No space is necessary after a cast
>> 823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)
>
> <snip>
>
> Looks like you have run checkpatch on the v1 series (9 patches).
> I had submitted the v2 series (13 patches).
>
> However, in the v2 series, there are some checkpatch warnings like ' line over 80 characters'
> which I had to ignore due to valid reasons. If there is any concern on these, I can work on them
> after discussion.
Sorry about that - Only your V1 was assigned to me in patchwork, so I missed it.
Looks like V2 is assigned to York at the moment, but I'm going to
assign it to myself since it is all about networking.
Cheers,
-Joe
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
2018-02-27 15:48 ` Joe Hershberger
@ 2018-02-27 16:45 ` Calvin Johnson
0 siblings, 0 replies; 38+ messages in thread
From: Calvin Johnson @ 2018-02-27 16:45 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Joe Hershberger [mailto:joe.hershberger at ni.com]
> Sent: Tuesday, February 27, 2018 9:18 PM
> To: Calvin Johnson <calvin.johnson@nxp.com>
> Cc: joe.hershberger at ni.com; u-boot at lists.denx.de; Anji Jagarlmudi
> <anji.jagarlmudi@nxp.com>; York Sun <york.sun@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
>
> On Mon, Feb 26, 2018 at 10:49 PM, Calvin Johnson <calvin.johnson@nxp.com>
> wrote:
> > Hi Joe,
> >
> >> -----Original Message-----
> >> From: Joe Hershberger [mailto:joe.hershberger at ni.com]
> >> Sent: Tuesday, February 27, 2018 1:31 AM
> >> To: Calvin Johnson <calvin.johnson@nxp.com>
> >> Cc: joe.hershberger at ni.com; u-boot at lists.denx.de; Anji Jagarlmudi
> >> <anji.jagarlmudi@nxp.com>
> >> Subject: Re: [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series
> >>
> >> Hi Calvin,
> >>
> >> On Wed, Feb 21, 2018 at 10:32 PM, Calvin Johnson <calvin.johnson@nxp.com>
> >> wrote:
> >> > Hi Joe,
> >> >
> >> >> -----Original Message-----
> >> >> From: Calvin Johnson [mailto:calvin.johnson at nxp.com]
> >> >> Sent: Thursday, February 15, 2018 7:47 PM
> >> >> To: u-boot at lists.denx.de
> >> >> Cc: joe.hershberger at ni.com; York Sun <york.sun@nxp.com>; Anji
> Jagarlmudi
> >> >> <anji.jagarlmudi@nxp.com>; Calvin Johnson <calvin.johnson@nxp.com>
> >> >> Subject: [PATCH v2 00/13] LS1012A PFE driver patch series
> >> >>
> >> >
> >> > <snip>
> >> >
> >> >> Changes in v2 series:
> >> >> 1. PFE patches submitted on top of this base patch are now merged to
> >> >> this patch.
> >> >> 2. Platform changes are segregated into different patches.
> >> >> 3. Network enabled on 2g5rdb platform
> >> >> 4. Moved from legacy to new driver model.
> >> >
> >> > Gentle reminder. Hope the PFE patches didn't miss your sight.
> >>
> >> I tried applying your series and it had many checkpatch issues. Please
> >> resolve those and resend.
> >>
> >> Thanks,
> >> -Joe
> >>
> >> -----------------
> >>
> >>
> >> Fetched U-Boot-1-9-drivers-net-pfe_eth-LS1012A-PFE-driver-introduction
> >> (823206.mbox)
> >> 823206.mbox:46: WARNING: added, moved or deleted file(s), does
> >> MAINTAINERS need updating?
> >> 823206.mbox:534: CHECK: Avoid CamelCase: <Elf32_Shdr>
> >> 823206.mbox:551: CHECK: No space is necessary after a cast
> >> 823206.mbox:669: CHECK: spaces preferred around that '&' (ctx:ExV)
> >
> > <snip>
> >
> > Looks like you have run checkpatch on the v1 series (9 patches).
> > I had submitted the v2 series (13 patches).
> >
> > However, in the v2 series, there are some checkpatch warnings like ' line over
> 80 characters'
> > which I had to ignore due to valid reasons. If there is any concern on these, I
> can work on them
> > after discussion.
>
> Sorry about that - Only your V1 was assigned to me in patchwork, so I missed it.
>
> Looks like V2 is assigned to York at the moment, but I'm going to
> assign it to myself since it is all about networking.
Not sure, how it got assigned to York. Thanks for taking up the patches.
Regards
Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM
2018-02-15 14:17 ` [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM Calvin Johnson
@ 2018-02-27 16:58 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 16:58 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
> below error. This patch fixes the issue by including dm.h.
>
> drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
> drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
> incomplete
> type ‘struct udevice’
> phydev->dev->name);
> ^~
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure
2018-02-15 14:17 ` [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure Calvin Johnson
@ 2018-02-27 17:01 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 17:01 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
>
> Layerscape Gen2 SoC supports GPIO registers to control GPIO
> signals. Adding support of GPIO structure to access GPIO
> registers.
>
> Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction
2018-02-15 14:17 ` [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction Calvin Johnson
@ 2018-02-27 19:12 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:12 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch adds PFE driver to U-Boot
>
> Following are the main driver files:-
> pfe_hw.c: provides low level helper functions to initialize PFE
> internal processor engines and other hardware blocks
> pfe_driver.c: provides initialization functions
> and packet send and receive functions
> pfe_eth.c: provides high level gemac initialization functions
> pfe_firmware.c: provides functions to load firmware into PFE
> internal processor engines.
> pfe_mdio.c: provides functions to initialize phy and mdio.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands
2018-02-15 14:17 ` [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands Calvin Johnson
@ 2018-02-27 19:21 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:21 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> pfe_command provides command line support for several features that
> support pfe, like starting or stopping the pfe, checking the health
> of the processor engines and checking status of different units inside
> pfe.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers
2018-02-15 14:17 ` [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers Calvin Johnson
@ 2018-02-27 19:29 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:29 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Contains all the pfe header files.
Looks good, but I'd like to move the files.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2:
> -Add pfe_rx_done to clear bd after packet processing
> -remove unused code under CONFIG_UTIL_PE_DISABLED
> -Used BIT and GENMASK macros wherever applicable
> -Removed generic definitions that pollutes namespace
> -File names pfe.h renamed to pfe_hw.h to be more clear as it contains
> low level functions that directly access pfe hardware block
> -Added pfe_dm_eth.h for new driver model
> ---
> include/dm/platform_data/pfe_dm_eth.h | 21 ++++
This is fine.
> include/pfe_eth/pfe/cbus.h | 77 +++++++++++++++
> include/pfe_eth/pfe/cbus/bmu.h | 40 ++++++++
> include/pfe_eth/pfe/cbus/class_csr.h | 180 ++++++++++++++++++++++++++++++++++
> include/pfe_eth/pfe/cbus/emac.h | 140 ++++++++++++++++++++++++++
> include/pfe_eth/pfe/cbus/gpi.h | 62 ++++++++++++
> include/pfe_eth/pfe/cbus/hif.h | 68 +++++++++++++
> include/pfe_eth/pfe/cbus/hif_nocpy.h | 40 ++++++++
> include/pfe_eth/pfe/cbus/tmu_csr.h | 148 ++++++++++++++++++++++++++++
> include/pfe_eth/pfe/cbus/util_csr.h | 47 +++++++++
> include/pfe_eth/pfe/pfe_hw.h | 163 ++++++++++++++++++++++++++++++
Please move these to include/net/pfe/*
> include/pfe_eth/pfe_driver.h | 59 +++++++++++
> include/pfe_eth/pfe_eth.h | 104 ++++++++++++++++++++
> include/pfe_eth/pfe_firmware.h | 17 ++++
> include/pfe_eth/pfe_mdio.h | 13 +++
Please move these to include/net/pfe/*
> 15 files changed, 1179 insertions(+)
> create mode 100644 include/dm/platform_data/pfe_dm_eth.h
> create mode 100644 include/pfe_eth/pfe/cbus.h
> create mode 100644 include/pfe_eth/pfe/cbus/bmu.h
> create mode 100644 include/pfe_eth/pfe/cbus/class_csr.h
> create mode 100644 include/pfe_eth/pfe/cbus/emac.h
> create mode 100644 include/pfe_eth/pfe/cbus/gpi.h
> create mode 100644 include/pfe_eth/pfe/cbus/hif.h
> create mode 100644 include/pfe_eth/pfe/cbus/hif_nocpy.h
> create mode 100644 include/pfe_eth/pfe/cbus/tmu_csr.h
> create mode 100644 include/pfe_eth/pfe/cbus/util_csr.h
> create mode 100644 include/pfe_eth/pfe/pfe_hw.h
> create mode 100644 include/pfe_eth/pfe_driver.h
> create mode 100644 include/pfe_eth/pfe_eth.h
> create mode 100644 include/pfe_eth/pfe_firmware.h
> create mode 100644 include/pfe_eth/pfe_mdio.h
>
Thanks,
-Joe
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds
2018-02-15 14:17 ` [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds Calvin Johnson
@ 2018-02-27 19:42 ` Joe Hershberger
2018-02-27 23:46 ` Joe Hershberger
1 sibling, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:42 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch enables ethernet support for ls1012aqds.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2:
> -split from original patch "board: freescale: ls1012a: enable network
> support on ls1012a platforms"
> ---
> board/freescale/ls1012aqds/Kconfig | 14 ++
> board/freescale/ls1012aqds/Makefile | 1 +
> board/freescale/ls1012aqds/eth.c | 304 ++++++++++++++++++++++++++
> board/freescale/ls1012aqds/ls1012aqds.c | 97 +++++++-
> board/freescale/ls1012aqds/ls1012aqds_pfe.h | 48 ++++
> board/freescale/ls1012aqds/ls1012aqds_qixis.h | 2 +-
> 6 files changed, 459 insertions(+), 7 deletions(-)
> create mode 100644 board/freescale/ls1012aqds/eth.c
> create mode 100644 board/freescale/ls1012aqds/ls1012aqds_pfe.h
>
[ ... ]
> diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
> new file mode 100644
> index 0000000..41d077a
> --- /dev/null
> +++ b/board/freescale/ls1012aqds/eth.c
[ ... ]
> +int pfe_eth_board_init(struct udevice *dev)
> +{
> + static int init_done;
> + struct mii_dev *bus;
> + static const char *mdio_name;
> + struct pfe_mdio_info mac_mdio_info;
> + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
> + u8 data8;
> + struct pfe_eth_dev *priv = dev_get_priv(dev);
> +
> + int srds_s1 = in_be32(&gur->rcwsr[4]) &
> + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
> + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
> +
> + ls1012aqds_mux_mdio(EMI1_SLOT1);
> +
> + if (!init_done) {
> + mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR;
> + mac_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
> +
> + bus = pfe_mdio_init(&mac_mdio_info);
> + if (!bus) {
> + printf("Failed to register mdio\n");
> + return -1;
> + }
> + init_done = 1;
> + }
> +
> + if (priv->gemac_port) {
> + mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR;
> + mac_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
> +
> + bus = pfe_mdio_init(&mac_mdio_info);
> + if (!bus) {
> + printf("Failed to register mdio\n");
> + return -1;
> + }
> + }
> +
> + switch (srds_s1) {
> + case 0x3508:
> + printf("ls1012aqds:supported SerDes PRCTL= %d\n", srds_s1);
> +#ifdef RGMII_RESET_WA
> + /* Work around for FPGA registers initialization
Please use the normal multi-line comment style where the first /* stands alone.
> + * This is needed for RGMII to work.
> + */
> + printf("Reset RGMII WA....\n");
> + data8 = QIXIS_READ(rst_frc[0]);
> + data8 |= 0x2;
> + QIXIS_WRITE(rst_frc[0], data8);
> + data8 = QIXIS_READ(rst_frc[0]);
> +
> + data8 = QIXIS_READ(res8[6]);
> + data8 |= 0xff;
> + QIXIS_WRITE(res8[6], data8);
> + data8 = QIXIS_READ(res8[6]);
> +#endif
[ ... ]
> diff --git a/board/freescale/ls1012aqds/ls1012aqds_pfe.h b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
> new file mode 100644
> index 0000000..c279ef3
> --- /dev/null
> +++ b/board/freescale/ls1012aqds/ls1012aqds_pfe.h
> @@ -0,0 +1,48 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#define ETH_1_1G_BUS_ID 0x1
> +#define ETH_1_1G_PHY_ID 0x1e
> +#define ETH_1_1G_MDIO_MUX 0x2
> +#define ETH_1G_MDIO_PHY_MASK 0xBFFFFFFD
> +#define ETH_1_1G_PHY_MODE "sgmii"
> +#define ETH_2_1G_BUS_ID 0x1
> +#define ETH_2_1G_PHY_ID 0x1
> +#define ETH_2_1G_MDIO_MUX 0x1
> +#define ETH_2_1G_PHY_MODE "rgmii"
> +
> +#define ETH_1_2_5G_BUS_ID 0x0
> +#define ETH_1_2_5G_PHY_ID 0x1
> +#define ETH_1_2_5G_MDIO_MUX 0x2
> +#define ETH_2_5G_MDIO_PHY_MASK 0xFFFFFFF9
> +#define ETH_2_5G_PHY_MODE "sgmii-2500"
> +#define ETH_2_2_5G_BUS_ID 0x1
> +#define ETH_2_2_5G_PHY_ID 0x2
> +#define ETH_2_2_5G_MDIO_MUX 0x3
> +
> +#define SERDES_1_G_PROTOCOL 0x3508
> +#define SERDES_2_5_G_PROTOCOL 0x2205
> +
> +#define PFE_PROP_LEN 4
> +
> +#define ETH_1_SOC_PATH "/soc/pfe at 04000000/ethernet at 0"
> +#define ETH_1_PATH "/pfe at 04000000/ethernet at 0"
> +#define ETH_2_SOC_PATH "/soc/pfe at 04000000/ethernet at 1"
> +#define ETH_2_PATH "/pfe at 04000000/ethernet at 1"
Seems like you could easily define *_SOC_PATH in terms of *_PATH
like:
#define ETH_1_PATH "/pfe at 04000000/ethernet at 0"
#define ETH_1_SOC_PATH "/soc" ETH_1_PATH
> +
> +#define ETH_1_MDIO_SOC_PATH "/soc/pfe at 04000000/ethernet at 0/mdio at 0"
> +#define ETH_1_MDIO "/pfe at 04000000/ethernet at 0/mdio at 0"
> +#define ETH_2_MDIO_SOC_PATH "/soc/pfe at 04000000/ethernet at 1/mdio at 0"
> +#define ETH_2_MDIO "/pfe at 04000000/ethernet at 1/mdio at 0"
> +
> +#define NUM_ETH_NODE 2
> +struct pfe_prop_val {
> + int busid;
> + int phyid;
> + int mux_val;
> + int phy_mask;
> + char *phy_mode;
> +};
> diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> index 584f604..7a1ba3d 100644
> --- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
> @@ -11,7 +11,7 @@
>
> /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
> #define BRDCFG4_EMISEL_MASK 0xe0
> -#define BRDCFG4_EMISEL_SHIFT 5
> +#define BRDCFG4_EMISEL_SHIFT 6
>
> /* SYSCLK */
> #define QIXIS_SYSCLK_66 0x0
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm
2018-02-15 14:17 ` [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm Calvin Johnson
@ 2018-02-27 19:44 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:44 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch enables ethernet support for ls1012afrdm.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb
2018-02-15 14:17 ` [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb Calvin Johnson
@ 2018-02-27 19:45 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 19:45 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch enables ethernet support for ls1012ardb.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb
2018-02-15 14:17 ` [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb Calvin Johnson
@ 2018-02-27 20:03 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 20:03 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch enables ethernet support for ls1012a2g5rdb.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> Changes in v2:
> -New patch added to series to enable ethernet support for
> ls1012a2g5rdb
> ---
> board/freescale/ls1012ardb/Kconfig | 14 ++++++++++++++
> board/freescale/ls1012ardb/eth.c | 25 +++++++++++++++++++++++++
> 2 files changed, 39 insertions(+)
>
> diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
> index 6e6197a..4bb672c 100644
> --- a/board/freescale/ls1012ardb/Kconfig
> +++ b/board/freescale/ls1012ardb/Kconfig
> @@ -44,6 +44,20 @@ config SYS_SOC
> config SYS_CONFIG_NAME
> default "ls1012a2g5rdb"
>
> +if FSL_PFE
> +config SYS_LS_PFE_FW_ADDR
> + hex "Flash address of PFE firmware"
> + default 0x40a00000
> +
> +config DDR_PFE_PHYS_BASEADDR
> + hex "PFE DDR physical base address"
> + default 0x03800000
> +
> +config DDR_PFE_BASEADDR
> + hex "PFE DDR base address"
> + default 0x83800000
> +endif
> +
> source "board/freescale/common/Kconfig"
>
> endif
> diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
> index bf67590..fc062cf 100644
> --- a/board/freescale/ls1012ardb/eth.c
> +++ b/board/freescale/ls1012ardb/eth.c
> @@ -26,6 +26,7 @@
>
> static inline void ls1012ardb_reset_phy(void)
> {
> +#ifdef CONFIG_TARGET_LS1012ARDB
> /* Through reset IO expander reset both RGMII and SGMII PHYs */
> i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
> i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
> @@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
> mdelay(10);
> i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
> mdelay(50);
> +#endif
> }
>
> int pfe_eth_board_init(struct udevice *dev)
> @@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
> struct mii_dev *bus;
> struct pfe_mdio_info mac_mdio_info;
> struct pfe_eth_dev *priv = dev_get_priv(dev);
> + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
> +
> + int srds_s1 = in_be32(&gur->rcwsr[4]) &
> + FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
> + srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
>
> if (!init_done) {
> ls1012ardb_reset_phy();
> @@ -59,6 +66,8 @@ int pfe_eth_board_init(struct udevice *dev)
> pfe_set_mdio(priv->gemac_port,
> miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
>
> + switch (srds_s1) {
> + case 0x3508:
> if (!priv->gemac_port) {
This needs to be indented.
> /* MAC1 */
> pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
> @@ -68,6 +77,22 @@ int pfe_eth_board_init(struct udevice *dev)
> pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
> PHY_INTERFACE_MODE_RGMII_TXID);
> }
> + break;
> + case 0x2208:
> + if (!priv->gemac_port) {
This indentation needs to be fixed.
> + /* MAC1 */
> + pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
> + PHY_INTERFACE_MODE_SGMII_2500);
> + } else {
> + /* MAC2 */
> + pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
> + PHY_INTERFACE_MODE_SGMII_2500);
> + }
> + break;
> + default:
> + printf("unsupported SerDes PRCTL= %d\n", srds_s1);
> + break;
> + }
> return 0;
> }
>
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure
2018-02-15 14:17 ` [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure Calvin Johnson
@ 2018-02-27 20:05 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 20:05 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> SoC specific PFE macros are defined and structure ccsr_scfg
> is updated with members defined for PFE.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2: None
> ---
> .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 38 ++++++++++++++++++++--
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index b195005..e1a57de 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -395,6 +395,21 @@ struct ccsr_gur {
> #define SCFG_SNPCNFGCR_SATARDSNP 0x00800000
> #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000
>
> +/* RGMIIPCR bit definitions*/
> +#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
> +#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
> +#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
> +#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
> +#define SCFG_RGMIIPCR_SETFD (0x00000001)
> +
> +/*PFEASBCR bit definitions */
> +#define SCFG_PFEASBCR_ARCACHE0 (0x80000000)
> +#define SCFG_PFEASBCR_AWCACHE0 (0x40000000)
> +#define SCFG_PFEASBCR_ARCACHE1 (0x20000000)
> +#define SCFG_PFEASBCR_AWCACHE1 (0x10000000)
> +#define SCFG_PFEASBCR_ARSNP (0x08000000)
> +#define SCFG_PFEASBCR_AWSNP (0x04000000)
I thought you were switching to using the BIT() macro.
> +
> /* Supplemental Configuration Unit */
> struct ccsr_scfg {
> u8 res_000[0x100-0x000];
> @@ -412,7 +427,12 @@ struct ccsr_scfg {
> u8 res_140[0x158-0x140];
> u32 altcbar;
> u32 qspi_cfg;
> - u8 res_160[0x180-0x160];
> + u8 res_160[0x164 - 0x160];
> + u32 wr_qos1;
> + u32 wr_qos2;
> + u32 rd_qos1;
> + u32 rd_qos2;
> + u8 res_174[0x180 - 0x174];
> u32 dmamcr;
> u8 res_184[0x188-0x184];
> u32 gic_align;
> @@ -443,7 +463,21 @@ struct ccsr_scfg {
> u32 usb_refclk_selcr1;
> u32 usb_refclk_selcr2;
> u32 usb_refclk_selcr3;
> - u8 res_424[0x600-0x424];
> + u8 res_424[0x434 - 0x424];
> + u32 rgmiipcr;
> + u32 res_438;
> + u32 rgmiipsr;
> + u32 pfepfcssr1;
> + u32 pfeintencr1;
> + u32 pfepfcssr2;
> + u32 pfeintencr2;
> + u32 pfeerrcr;
> + u32 pfeeerrintencr;
> + u32 pfeasbcr;
> + u32 pfebsbcr;
> + u8 res_460[0x484 - 0x460];
> + u32 mdioselcr;
> + u8 res_468[0x600 - 0x488];
> u32 scratchrw[4];
> u8 res_610[0x680-0x610];
> u32 corebcr;
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC
2018-02-15 14:17 ` [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC Calvin Johnson
@ 2018-02-27 20:06 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 20:06 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> 1. Set AWCACHE0 attribute of PFE DDR and HDBUS master interfaces
> to bufferable.
> 2. Set RD/WR QoS for PFE DDR and HDBUS AXI master interfaces.
> 3. Disable ECC detection for PFE.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers
2018-02-15 14:17 ` [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers Calvin Johnson
@ 2018-02-27 20:06 ` Joe Hershberger
0 siblings, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 20:06 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Enable all types of non-secure access to PFE block registers.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A
2018-02-15 14:17 ` [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A Calvin Johnson
@ 2018-02-27 20:16 ` Joe Hershberger
2018-03-01 5:45 ` Calvin Johnson
2018-02-27 23:49 ` Joe Hershberger
1 sibling, 1 reply; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 20:16 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Add configurations for PFE.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2:
> -Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
> -Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
> ---
> configs/ls1012a2g5rdb_qspi_defconfig | 2 ++
> configs/ls1012afrdm_qspi_defconfig | 2 ++
> configs/ls1012aqds_qspi_defconfig | 2 ++
> configs/ls1012ardb_qspi_defconfig | 2 ++
> drivers/net/Kconfig | 1 +
> drivers/net/Makefile | 1 +
> drivers/net/pfe_eth/Kconfig | 17 +++++++++++++++++
> drivers/net/pfe_eth/Makefile | 12 ++++++++++++
> include/configs/ls1012a2g5rdb.h | 2 +-
> include/configs/ls1012a_common.h | 6 +++---
> include/configs/ls1012afrdm.h | 9 ++++++++-
> include/configs/ls1012aqds.h | 14 ++++++++++++++
> include/configs/ls1012ardb.h | 10 +++++++++-
> 13 files changed, 74 insertions(+), 6 deletions(-)
> create mode 100644 drivers/net/pfe_eth/Kconfig
> create mode 100644 drivers/net/pfe_eth/Makefile
>
> diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
> index 140a4e1..a979211 100644
> --- a/configs/ls1012a2g5rdb_qspi_defconfig
> +++ b/configs/ls1012a2g5rdb_qspi_defconfig
> @@ -30,7 +30,9 @@ CONFIG_DM=y
> CONFIG_DM_MMC=y
> CONFIG_DM_SPI_FLASH=y
> CONFIG_SPI_FLASH=y
> +CONFIG_DM_ETH=y
> CONFIG_NETDEVICES=y
> +CONFIG_FSL_PFE=y
> CONFIG_SYS_NS16550=y
> CONFIG_DM_SPI=y
> CONFIG_USB=y
> diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
> index 060f073..d0bf081 100644
> --- a/configs/ls1012afrdm_qspi_defconfig
> +++ b/configs/ls1012afrdm_qspi_defconfig
> @@ -28,8 +28,10 @@ CONFIG_DM=y
> # CONFIG_MMC is not set
> CONFIG_DM_SPI_FLASH=y
> CONFIG_SPI_FLASH=y
> +CONFIG_DM_ETH=y
> CONFIG_NETDEVICES=y
> CONFIG_E1000=y
> +CONFIG_FSL_PFE=y
> CONFIG_PCI=y
> CONFIG_DM_PCI=y
> CONFIG_DM_PCI_COMPAT=y
> diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
> index 0435d51..40fbdd8 100644
> --- a/configs/ls1012aqds_qspi_defconfig
> +++ b/configs/ls1012aqds_qspi_defconfig
> @@ -39,8 +39,10 @@ CONFIG_SCSI_AHCI=y
> CONFIG_DM_MMC=y
> CONFIG_DM_SPI_FLASH=y
> CONFIG_SPI_FLASH=y
> +CONFIG_DM_ETH=y
> CONFIG_NETDEVICES=y
> CONFIG_E1000=y
> +CONFIG_FSL_PFE=y
> CONFIG_PCI=y
> CONFIG_DM_PCI=y
> CONFIG_DM_PCI_COMPAT=y
> diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
> index ea28953..6262351 100644
> --- a/configs/ls1012ardb_qspi_defconfig
> +++ b/configs/ls1012ardb_qspi_defconfig
> @@ -31,8 +31,10 @@ CONFIG_DM=y
> CONFIG_DM_MMC=y
> CONFIG_DM_SPI_FLASH=y
> CONFIG_SPI_FLASH=y
> +CONFIG_DM_ETH=y
> CONFIG_NETDEVICES=y
> CONFIG_E1000=y
> +CONFIG_FSL_PFE=y
> CONFIG_PCI=y
> CONFIG_DM_PCI=y
> CONFIG_DM_PCI_COMPAT=y
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index de1947c..f589978 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -1,4 +1,5 @@
> source "drivers/net/phy/Kconfig"
> +source "drivers/net/pfe_eth/Kconfig"
>
> config DM_ETH
> bool "Enable Driver Model for Ethernet drivers"
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index ac5443c..102e65a 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -75,3 +75,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
> obj-$(CONFIG_VSC9953) += vsc9953.o
> obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> +obj-$(CONFIG_FSL_PFE) += pfe_eth/
> diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
> new file mode 100644
> index 0000000..6f99710
> --- /dev/null
> +++ b/drivers/net/pfe_eth/Kconfig
> @@ -0,0 +1,17 @@
> +menuconfig FSL_PFE
> + bool "Freescale PFE driver"
Is NXP more appropriate at this point? Or Qualcomm? Or Broadcom? :D
Seriously, though, maybe it should include "Ethernet driver".
> + help
> + This driver provides support for Freescale PFE.
It probably makes sense here to spell out the acronym.
> +
> +if FSL_PFE
> +
> +config UTIL_PE_DISABLED
> + bool
> + help
> + Disable UTIL processor engine of PFE
> +
> +config SYS_FSL_PFE_ADDR
> + hex "PFE base address"
> + default 0x04000000
> +
> +endif
> diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
> new file mode 100644
> index 0000000..6b5248f
> --- /dev/null
> +++ b/drivers/net/pfe_eth/Makefile
> @@ -0,0 +1,12 @@
> +# Copyright 2015-2016 Freescale Semiconductor, Inc.
> +# Copyright 2017 NXP
> +#
> +# SPDX-License-Identifier:GPL-2.0+
> +
> +# Layerscape PFE driver
> +obj-y += pfe_cmd.o \
> + pfe_driver.o \
> + pfe_eth.o \
> + pfe_firmware.o \
> + pfe_hw.o \
> + pfe_mdio.o
> diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
> index 25df103..2d18f3c 100644
> --- a/include/configs/ls1012a2g5rdb.h
> +++ b/include/configs/ls1012a2g5rdb.h
> @@ -110,7 +110,7 @@
>
> #undef CONFIG_BOOTCOMMAND
> #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
> +#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \
> "env exists secureboot && esbc_halt;"
> #endif
>
> diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
> index 7dbe231..b590d7a 100644
> --- a/include/configs/ls1012a_common.h
> +++ b/include/configs/ls1012a_common.h
> @@ -118,9 +118,9 @@
> "kernel_size=0x2800000\0" \
>
> #undef CONFIG_BOOTCOMMAND
> -#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
> - "$kernel_start $kernel_size && "\
> - "bootm $kernel_load"
> +#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\
> + "$kernel_start $kernel_size && "\
> + "bootm $kernel_load"
>
> /* Monitor Command Prompt */
> #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
> diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
> index 297c057..f54021e 100644
> --- a/include/configs/ls1012afrdm.h
> +++ b/include/configs/ls1012afrdm.h
> @@ -9,6 +9,13 @@
>
> #include "ls1012a_common.h"
>
> +#ifdef CONFIG_FSL_PFE
> +#define EMAC1_PHY_ADDR 0x2
> +#define EMAC2_PHY_ADDR 0x1
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_REALTEK
> +#endif
> +
> /* DDR */
> #define CONFIG_DIMM_SLOTS_PER_CTLR 1
> #define CONFIG_CHIP_SELECTS_PER_CTRL 1
> @@ -68,7 +75,7 @@
> "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
>
> #undef CONFIG_BOOTCOMMAND
> -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
> +#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd"
>
> #define CONFIG_CMD_MEMINFO
> #define CONFIG_CMD_MEMTEST
> diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
> index e1767ef..f6c2650 100644
> --- a/include/configs/ls1012aqds.h
> +++ b/include/configs/ls1012aqds.h
> @@ -9,6 +9,20 @@
>
> #include "ls1012a_common.h"
>
> +/* PFE Ethernet */
> +#ifdef CONFIG_FSL_PFE
> +#define EMAC1_PHY_ADDR 0x1e
> +#define EMAC2_PHY_ADDR 0x1
> +#define SGMII_2500_PHY1_ADDR 0x1
> +#define SGMII_2500_PHY2_ADDR 0x2
Seems like these 4 could move to Kconfig for PFE, maybe prefixed with PFE.
> +#define CONFIG_PHYLIB
This is Kconfig. Select it.
> +#define CONFIG_PHY_VITESSE
> +#define CONFIG_PHY_REALTEK
> +#define CONFIG_PHY_AQUANTIA
> +#define CONFIG_PHYLIB_10G
These are all in Kconfig. Imply them?
> +#define RGMII_RESET_WA
> +#endif
> +
> /* DDR */
> #define CONFIG_DIMM_SLOTS_PER_CTLR 1
> #define CONFIG_CHIP_SELECTS_PER_CTRL 1
> diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
> index ced6c5e..3054ba1 100644
> --- a/include/configs/ls1012ardb.h
> +++ b/include/configs/ls1012ardb.h
> @@ -9,6 +9,14 @@
>
> #include "ls1012a_common.h"
>
> +/* PFE Ethernet */
> +#ifdef CONFIG_FSL_PFE
> +#define EMAC1_PHY_ADDR 0x2
> +#define EMAC2_PHY_ADDR 0x1
> +#define CONFIG_PHYLIB
> +#define CONFIG_PHY_REALTEK
> +#endif
> +
> /* DDR */
> #define CONFIG_DIMM_SLOTS_PER_CTLR 1
> #define CONFIG_CHIP_SELECTS_PER_CTRL 1
> @@ -102,7 +110,7 @@
> "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
>
> #undef CONFIG_BOOTCOMMAND
> -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
> +#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd;run qspi_bootcmd"
>
> #include <asm/fsl_secure_boot.h>
>
> --
> 2.7.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds
2018-02-15 14:17 ` [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds Calvin Johnson
2018-02-27 19:42 ` Joe Hershberger
@ 2018-02-27 23:46 ` Joe Hershberger
1 sibling, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 23:46 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> This patch enables ethernet support for ls1012aqds.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2:
> -split from original patch "board: freescale: ls1012a: enable network
> support on ls1012a platforms"
FYI, this doesn't apply cleanly as of today. Please be sure to rebase
the series before next version.
Thanks,
-Joe
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A
2018-02-15 14:17 ` [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A Calvin Johnson
2018-02-27 20:16 ` Joe Hershberger
@ 2018-02-27 23:49 ` Joe Hershberger
1 sibling, 0 replies; 38+ messages in thread
From: Joe Hershberger @ 2018-02-27 23:49 UTC (permalink / raw)
To: u-boot
On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com> wrote:
> Add configurations for PFE.
>
> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> ---
> Changes in v2:
> -Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
> -Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
This one also does not apply cleanly as of today. Please rebase.
Thanks!
-Joe
^ permalink raw reply [flat|nested] 38+ messages in thread
* [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A
2018-02-27 20:16 ` Joe Hershberger
@ 2018-03-01 5:45 ` Calvin Johnson
0 siblings, 0 replies; 38+ messages in thread
From: Calvin Johnson @ 2018-03-01 5:45 UTC (permalink / raw)
To: u-boot
Hi Joe,
> -----Original Message-----
> From: Joe Hershberger [mailto:joe.hershberger at ni.com]
> Sent: Wednesday, February 28, 2018 1:47 AM
> To: Calvin Johnson <calvin.johnson@nxp.com>
> Cc: u-boot <u-boot@lists.denx.de>; Joe Hershberger
> <joe.hershberger@ni.com>; Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
> Subject: Re: [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for
> LS1012A
>
> On Thu, Feb 15, 2018 at 8:17 AM, Calvin Johnson <calvin.johnson@nxp.com>
> wrote:
> > Add configurations for PFE.
> >
> > Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
> > Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
> > ---
> > Changes in v2:
> > -Moved SYS_LS_PFE_FW_ADDR from pfe Kconfig to board Kconfigs
> > -Add "pfe stop" to ls1012a rdb, frdm and 2g5rdb config files
> > ---
> > configs/ls1012a2g5rdb_qspi_defconfig | 2 ++
> > configs/ls1012afrdm_qspi_defconfig | 2 ++
> > configs/ls1012aqds_qspi_defconfig | 2 ++
> > configs/ls1012ardb_qspi_defconfig | 2 ++
> > drivers/net/Kconfig | 1 +
> > drivers/net/Makefile | 1 +
> > drivers/net/pfe_eth/Kconfig | 17 +++++++++++++++++
> > drivers/net/pfe_eth/Makefile | 12 ++++++++++++
> > include/configs/ls1012a2g5rdb.h | 2 +-
> > include/configs/ls1012a_common.h | 6 +++---
> > include/configs/ls1012afrdm.h | 9 ++++++++-
> > include/configs/ls1012aqds.h | 14 ++++++++++++++
> > include/configs/ls1012ardb.h | 10 +++++++++-
> > 13 files changed, 74 insertions(+), 6 deletions(-)
> > create mode 100644 drivers/net/pfe_eth/Kconfig
> > create mode 100644 drivers/net/pfe_eth/Makefile
> >
<snip>
> > diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
> > new file mode 100644
> > index 0000000..6f99710
> > --- /dev/null
> > +++ b/drivers/net/pfe_eth/Kconfig
> > @@ -0,0 +1,17 @@
> > +menuconfig FSL_PFE
> > + bool "Freescale PFE driver"
>
> Is NXP more appropriate at this point? Or Qualcomm? Or Broadcom? :D
Yes, I think NXP is more appropriate right now.
If required, we can change it later. 😊
>
> Seriously, though, maybe it should include "Ethernet driver".
>
> > + help
> > + This driver provides support for Freescale PFE.
>
> It probably makes sense here to spell out the acronym.
>
> > +
> > +if FSL_PFE
> > +
> > +config UTIL_PE_DISABLED
> > + bool
> > + help
> > + Disable UTIL processor engine of PFE
> > +
> > +config SYS_FSL_PFE_ADDR
> > + hex "PFE base address"
> > + default 0x04000000
> > +
> > +endif
> > diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
> > new file mode 100644
> > index 0000000..6b5248f
> > --- /dev/null
> > +++ b/drivers/net/pfe_eth/Makefile
> > @@ -0,0 +1,12 @@
> > +# Copyright 2015-2016 Freescale Semiconductor, Inc.
> > +# Copyright 2017 NXP
> > +#
> > +# SPDX-License-Identifier:GPL-2.0+
> > +
> > +# Layerscape PFE driver
> > +obj-y += pfe_cmd.o \
> > + pfe_driver.o \
> > + pfe_eth.o \
> > + pfe_firmware.o \
> > + pfe_hw.o \
> > + pfe_mdio.o
> > diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
> > index 25df103..2d18f3c 100644
> > --- a/include/configs/ls1012a2g5rdb.h
> > +++ b/include/configs/ls1012a2g5rdb.h
> > @@ -110,7 +110,7 @@
> >
> > #undef CONFIG_BOOTCOMMAND
> > #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
> > -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "
> \
> > +#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run
> qspi_bootcmd; " \
> > "env exists secureboot && esbc_halt;"
> > #endif
> >
> > diff --git a/include/configs/ls1012a_common.h
> b/include/configs/ls1012a_common.h
> > index 7dbe231..b590d7a 100644
> > --- a/include/configs/ls1012a_common.h
> > +++ b/include/configs/ls1012a_common.h
> > @@ -118,9 +118,9 @@
> > "kernel_size=0x2800000\0" \
> >
> > #undef CONFIG_BOOTCOMMAND
> > -#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
> > - "$kernel_start $kernel_size && "\
> > - "bootm $kernel_load"
> > +#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read
> $kernel_load "\
> > + "$kernel_start $kernel_size && "\
> > + "bootm $kernel_load"
> >
> > /* Monitor Command Prompt */
> > #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
> > diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
> > index 297c057..f54021e 100644
> > --- a/include/configs/ls1012afrdm.h
> > +++ b/include/configs/ls1012afrdm.h
> > @@ -9,6 +9,13 @@
> >
> > #include "ls1012a_common.h"
> >
> > +#ifdef CONFIG_FSL_PFE
> > +#define EMAC1_PHY_ADDR 0x2
> > +#define EMAC2_PHY_ADDR 0x1
> > +#define CONFIG_PHYLIB
> > +#define CONFIG_PHY_REALTEK
> > +#endif
> > +
> > /* DDR */
> > #define CONFIG_DIMM_SLOTS_PER_CTLR 1
> > #define CONFIG_CHIP_SELECTS_PER_CTRL 1
> > @@ -68,7 +75,7 @@
> > "$kernel_addr $kernel_size && bootm $load_addr#$board\0"
> >
> > #undef CONFIG_BOOTCOMMAND
> > -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run qspi_bootcmd"
> > +#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run
> qspi_bootcmd"
> >
> > #define CONFIG_CMD_MEMINFO
> > #define CONFIG_CMD_MEMTEST
> > diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
> > index e1767ef..f6c2650 100644
> > --- a/include/configs/ls1012aqds.h
> > +++ b/include/configs/ls1012aqds.h
> > @@ -9,6 +9,20 @@
> >
> > #include "ls1012a_common.h"
> >
> > +/* PFE Ethernet */
> > +#ifdef CONFIG_FSL_PFE
> > +#define EMAC1_PHY_ADDR 0x1e
> > +#define EMAC2_PHY_ADDR 0x1
> > +#define SGMII_2500_PHY1_ADDR 0x1
> > +#define SGMII_2500_PHY2_ADDR 0x2
>
> Seems like these 4 could move to Kconfig for PFE, maybe prefixed with PFE.
>
> > +#define CONFIG_PHYLIB
>
> This is Kconfig. Select it.
>
> > +#define CONFIG_PHY_VITESSE
> > +#define CONFIG_PHY_REALTEK
> > +#define CONFIG_PHY_AQUANTIA
> > +#define CONFIG_PHYLIB_10G
>
> These are all in Kconfig. Imply them?
Agree with your comments. Will work on them and submit v3.
Thanks
Calvin
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2018-03-01 5:45 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-15 14:17 [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series Calvin Johnson
2018-02-15 14:17 ` [U-Boot] [PATCH v2 01/13] drivers: net: phy: Fix aquantia compilation with DM Calvin Johnson
2018-02-27 16:58 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 02/13] armv8: fsl-layerscape: Add support of GPIO structure Calvin Johnson
2018-02-27 17:01 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 03/13] drivers: net: pfe_eth: LS1012A PFE driver introduction Calvin Johnson
2018-02-27 19:12 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 04/13] drivers: net: pfe_eth: provide pfe commands Calvin Johnson
2018-02-27 19:21 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 05/13] drivers: net: pfe_eth: LS1012A PFE headers Calvin Johnson
2018-02-27 19:29 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 06/13] board: freescale: ls1012aqds: enable network support on ls1012aqds Calvin Johnson
2018-02-27 19:42 ` Joe Hershberger
2018-02-27 23:46 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 07/13] board: freescale: ls1012afrdm: enable network support on ls1012afrdm Calvin Johnson
2018-02-27 19:44 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 08/13] board: freescale: ls1012ardb: enable network support on ls1012ardb Calvin Johnson
2018-02-27 19:45 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 09/13] board: freescale: ls1012a2g5rdb: enable network support on ls1012a2g5rdb Calvin Johnson
2018-02-27 20:03 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 10/13] armv8: fsl-lsch2: add pfe macros and update ccsr_scfg structure Calvin Johnson
2018-02-27 20:05 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 11/13] armv8: fsl-lsch2: configure pfe's DDR and HDBUS interfaces and ECC Calvin Johnson
2018-02-27 20:06 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 12/13] armv8: layerscape: csu: enable ns access to PFE registers Calvin Johnson
2018-02-27 20:06 ` Joe Hershberger
2018-02-15 14:17 ` [U-Boot] [PATCH v2 13/13] configs: ls1012a: add pfe configuration for LS1012A Calvin Johnson
2018-02-27 20:16 ` Joe Hershberger
2018-03-01 5:45 ` Calvin Johnson
2018-02-27 23:49 ` Joe Hershberger
2018-02-15 15:48 ` [U-Boot] [PATCH v2 00/13] LS1012A PFE driver patch series York Sun
2018-02-15 16:44 ` Calvin Johnson
2018-02-16 14:24 ` Anji Jagarlmudi
2018-02-22 4:32 ` Calvin Johnson
2018-02-26 20:00 ` Joe Hershberger
2018-02-27 4:49 ` Calvin Johnson
2018-02-27 15:48 ` Joe Hershberger
2018-02-27 16:45 ` Calvin Johnson
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