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* [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
@ 2022-04-13  5:34 Billy Tsai
  2022-04-14  6:40 ` Ryan Chen
  2022-04-20 13:12 ` Tom Rini
  0 siblings, 2 replies; 3+ messages in thread
From: Billy Tsai @ 2022-04-13  5:34 UTC (permalink / raw)
  To: ryan_chen, chiawei_wang, BMC-SW, andrew, billy_tsai, u-boot

The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.

Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
---
 drivers/gpio/gpio-aspeed.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index a8a2afcb5c..2c5415c671 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset
 	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
 	const struct aspeed_gpio_bank *bank = to_bank(offset);
 	u32 dir = readl(bank_reg(priv, bank, reg_dir));
-	u32 output = readl(bank_reg(priv, bank, reg_val));
+	u32 output = readl(bank_reg(priv, bank, reg_rdata));
 
 	dir |= GPIO_BIT(offset);
 	writel(dir, bank_reg(priv, bank, reg_dir));
@@ -239,7 +239,7 @@ aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
 {
 	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
 	const struct aspeed_gpio_bank *bank = to_bank(offset);
-	u32 data = readl(bank_reg(priv, bank, reg_val));
+	u32 data = readl(bank_reg(priv, bank, reg_rdata));
 
 	if (value)
 		data |= GPIO_BIT(offset);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* RE: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
  2022-04-13  5:34 [PATCH] gpio: aspeed: Fix incorrect offset of read back register Billy Tsai
@ 2022-04-14  6:40 ` Ryan Chen
  2022-04-20 13:12 ` Tom Rini
  1 sibling, 0 replies; 3+ messages in thread
From: Ryan Chen @ 2022-04-14  6:40 UTC (permalink / raw)
  To: Billy Tsai, ChiaWei Wang, BMC-SW, andrew, u-boot

> -----Original Message-----
> From: Billy Tsai <billy_tsai@aspeedtech.com>
> Sent: Wednesday, April 13, 2022 1:35 PM
> To: Ryan Chen <ryan_chen@aspeedtech.com>; ChiaWei Wang
> <chiawei_wang@aspeedtech.com>; BMC-SW <BMC-SW@aspeedtech.com>;
> andrew@aj.id.au; Billy Tsai <billy_tsai@aspeedtech.com>;
> u-boot@lists.denx.de
> Subject: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
> 
> The offset of the current read back register is the value of the gpio pin, not the
> value written for the gpio output.
> This patch fix it to avoid the other gpio output value controlled by the same
> register being set incorrectly.
> 
> Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>

Review-by: ryan_chen <ryan_chen@aspeedtech.com>

> ---
>  drivers/gpio/gpio-aspeed.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index
> a8a2afcb5c..2c5415c671 100644
> --- a/drivers/gpio/gpio-aspeed.c
> +++ b/drivers/gpio/gpio-aspeed.c
> @@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice
> *dev, unsigned int offset
>  	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
>  	const struct aspeed_gpio_bank *bank = to_bank(offset);
>  	u32 dir = readl(bank_reg(priv, bank, reg_dir));
> -	u32 output = readl(bank_reg(priv, bank, reg_val));
> +	u32 output = readl(bank_reg(priv, bank, reg_rdata));
> 
>  	dir |= GPIO_BIT(offset);
>  	writel(dir, bank_reg(priv, bank, reg_dir)); @@ -239,7 +239,7 @@
> aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)  {
>  	struct aspeed_gpio_priv *priv = dev_get_priv(dev);
>  	const struct aspeed_gpio_bank *bank = to_bank(offset);
> -	u32 data = readl(bank_reg(priv, bank, reg_val));
> +	u32 data = readl(bank_reg(priv, bank, reg_rdata));
> 
>  	if (value)
>  		data |= GPIO_BIT(offset);
> --
> 2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] gpio: aspeed: Fix incorrect offset of read back register.
  2022-04-13  5:34 [PATCH] gpio: aspeed: Fix incorrect offset of read back register Billy Tsai
  2022-04-14  6:40 ` Ryan Chen
@ 2022-04-20 13:12 ` Tom Rini
  1 sibling, 0 replies; 3+ messages in thread
From: Tom Rini @ 2022-04-20 13:12 UTC (permalink / raw)
  To: Billy Tsai; +Cc: ryan_chen, chiawei_wang, BMC-SW, andrew, u-boot

[-- Attachment #1: Type: text/plain, Size: 469 bytes --]

On Wed, Apr 13, 2022 at 01:34:51PM +0800, Billy Tsai wrote:

> The offset of the current read back register is the value of the gpio pin,
> not the value written for the gpio output.
> This patch fix it to avoid the other gpio output value controlled by the
> same register being set incorrectly.
> 
> Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>

Applied to u-boot/master, thanks!

-- 
Tom

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2022-04-20 13:12 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-13  5:34 [PATCH] gpio: aspeed: Fix incorrect offset of read back register Billy Tsai
2022-04-14  6:40 ` Ryan Chen
2022-04-20 13:12 ` Tom Rini

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