[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Ley Foon Tan]

Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation.

After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.

This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.

Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)

After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
index 7d9874cafa0b..d24f621cd669 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
@@ -68,3 +68,7 @@
 &portc {
 	bank-name = "portc";
 };
+
+&i2c0 {
+	i2c-scl-falling-time-ns = <300>;
+};
-- 
2.19.0

[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Marek Vasut]

On 6/5/20 10:21 AM, Ley Foon Tan wrote:
> Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation")
> change the hcnt and lcnt timing calculation.
> 
> After this new timing calculation, hcnt will have negative value
> with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
Shouldn't either the driver or the calculation be fixed instead ?

[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Friday, June 5, 2020 8:52 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>; u-boot at lists.denx.de
> Cc: Ley Foon Tan <lftan.linux@gmail.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>
> Subject: Re: [PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-
> time-ns
> 
> On 6/5/20 10:21 AM, Ley Foon Tan wrote:
> > Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing
> > calculation") change the hcnt and lcnt timing calculation.
> >
> > After this new timing calculation, hcnt will have negative value with
> > i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
> Shouldn't either the driver or the calculation be fixed instead ?
The original timing calculation in driver doesn't take fall time or rise time into calculation.
The new i2c timing calculation is based on calculation from Designware i2c databook. So, I don't think need fix in driver.

Regards
Ley Foon

[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Marek Vasut]

On 6/9/20 8:33 AM, Tan, Ley Foon wrote:
[...]
>>> Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing
>>> calculation") change the hcnt and lcnt timing calculation.
>>>
>>> After this new timing calculation, hcnt will have negative value with
>>> i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
>> Shouldn't either the driver or the calculation be fixed instead ?
> The original timing calculation in driver doesn't take fall time or rise time into calculation.
> The new i2c timing calculation is based on calculation from Designware i2c databook. So, I don't think need fix in driver.

Then just mention it in the commit message that it's from the databook
please.

[PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

[Tan, Ley Foon]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, June 9, 2020 5:53 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>; u-boot at lists.denx.de
> Cc: Ley Foon Tan <lftan.linux@gmail.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>
> Subject: Re: [PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-
> time-ns
> 
> On 6/9/20 8:33 AM, Tan, Ley Foon wrote:
> [...]
> >>> Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing
> >>> calculation") change the hcnt and lcnt timing calculation.
> >>>
> >>> After this new timing calculation, hcnt will have negative value
> >>> with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
> >> Shouldn't either the driver or the calculation be fixed instead ?
> > The original timing calculation in driver doesn't take fall time or rise time
> into calculation.
> > The new i2c timing calculation is based on calculation from Designware i2c
> databook. So, I don't think need fix in driver.
> 
> Then just mention it in the commit message that it's from the databook
> please.
Okay.

Regards
Ley Foon