* [PATCH] drm/amdgpu: Hardcode reg access using L1 security
@ 2019-06-03 11:43 Trigger Huang
[not found] ` <1559562183-29241-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Trigger Huang @ 2019-06-03 11:43 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Trigger.Huang-5C7GfCeVMHo
Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
default as the non-security VF will no longer be supported.
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 31030f8..235548c 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev)
{
- uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
- uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
-
adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY;
- if (rlc_fw_ver >= 0x5d)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
+ /* Enable L1 security reg access mode by defaul, as non-security VF
+ * will no longer be supported.
+ */
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
- if (sos_fw_ver >= 0x80455)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
- if (sos_fw_ver >= 0x8045b)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
}
const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu: Hardcode reg access using L1 security
[not found] ` <1559562183-29241-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
@ 2019-06-04 6:31 ` Deng, Emily
0 siblings, 0 replies; 2+ messages in thread
From: Deng, Emily @ 2019-06-04 6:31 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Huang, Trigger
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
>-----Original Message-----
>From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>Trigger Huang
>Sent: Monday, June 3, 2019 7:43 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Huang, Trigger <Trigger.Huang@amd.com>
>Subject: [PATCH] drm/amdgpu: Hardcode reg access using L1 security
>
>Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
>default as the non-security VF will no longer be supported.
>
>Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
>---
> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>index 31030f8..235548c 100644
>--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>@@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct
>amdgpu_device *adev)
>
> static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev) {
>- uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0,
>mmRLC_GPM_GENERAL_6);
>- uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0,
>mmMP0_SMN_C2PMSG_58);
>-
> adev->virt.reg_access_mode =
>AMDGPU_VIRT_REG_ACCESS_LEGACY;
>
>- if (rlc_fw_ver >= 0x5d)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_RLC;
>+ /* Enable L1 security reg access mode by defaul, as non-security VF
>+ * will no longer be supported.
>+ */
>+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
>
>- if (sos_fw_ver >= 0x80455)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
>+ adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
>
>- if (sos_fw_ver >= 0x8045b)
>- adev->virt.reg_access_mode |=
>AMDGPU_VIRT_REG_SKIP_SEETING;
>+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
> }
>
> const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
>--
>2.7.4
>
>_______________________________________________
>amd-gfx mailing list
>amd-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 2+ messages in thread
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2019-06-03 11:43 [PATCH] drm/amdgpu: Hardcode reg access using L1 security Trigger Huang
[not found] ` <1559562183-29241-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
2019-06-04 6:31 ` Deng, Emily
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