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* [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h
@ 2019-07-25  5:11 Wang, Kevin(Yang)
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  5:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

move some enum type (message, feature, clock) to smu_types.h.
these types is too long in amdgpu_smu.h, and not clearly.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 186 +---------------
 drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 210 ++++++++++++++++++
 2 files changed, 211 insertions(+), 185 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_types.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 33d2d75ba903..397040a4d1b4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -26,6 +26,7 @@
 #include "kgd_pp_interface.h"
 #include "dm_pp_interface.h"
 #include "dm_pp_smu.h"
+#include "smu_types.h"
 
 #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
@@ -150,134 +151,6 @@ struct smu_power_state {
 	struct smu_hw_power_state                     hardware;
 };
 
-enum smu_message_type
-{
-	SMU_MSG_TestMessage = 0,
-	SMU_MSG_GetSmuVersion,
-	SMU_MSG_GetDriverIfVersion,
-	SMU_MSG_SetAllowedFeaturesMaskLow,
-	SMU_MSG_SetAllowedFeaturesMaskHigh,
-	SMU_MSG_EnableAllSmuFeatures,
-	SMU_MSG_DisableAllSmuFeatures,
-	SMU_MSG_EnableSmuFeaturesLow,
-	SMU_MSG_EnableSmuFeaturesHigh,
-	SMU_MSG_DisableSmuFeaturesLow,
-	SMU_MSG_DisableSmuFeaturesHigh,
-	SMU_MSG_GetEnabledSmuFeaturesLow,
-	SMU_MSG_GetEnabledSmuFeaturesHigh,
-	SMU_MSG_SetWorkloadMask,
-	SMU_MSG_SetPptLimit,
-	SMU_MSG_SetDriverDramAddrHigh,
-	SMU_MSG_SetDriverDramAddrLow,
-	SMU_MSG_SetToolsDramAddrHigh,
-	SMU_MSG_SetToolsDramAddrLow,
-	SMU_MSG_TransferTableSmu2Dram,
-	SMU_MSG_TransferTableDram2Smu,
-	SMU_MSG_UseDefaultPPTable,
-	SMU_MSG_UseBackupPPTable,
-	SMU_MSG_RunBtc,
-	SMU_MSG_RequestI2CBus,
-	SMU_MSG_ReleaseI2CBus,
-	SMU_MSG_SetFloorSocVoltage,
-	SMU_MSG_SoftReset,
-	SMU_MSG_StartBacoMonitor,
-	SMU_MSG_CancelBacoMonitor,
-	SMU_MSG_EnterBaco,
-	SMU_MSG_SetSoftMinByFreq,
-	SMU_MSG_SetSoftMaxByFreq,
-	SMU_MSG_SetHardMinByFreq,
-	SMU_MSG_SetHardMaxByFreq,
-	SMU_MSG_GetMinDpmFreq,
-	SMU_MSG_GetMaxDpmFreq,
-	SMU_MSG_GetDpmFreqByIndex,
-	SMU_MSG_GetDpmClockFreq,
-	SMU_MSG_GetSsVoltageByDpm,
-	SMU_MSG_SetMemoryChannelConfig,
-	SMU_MSG_SetGeminiMode,
-	SMU_MSG_SetGeminiApertureHigh,
-	SMU_MSG_SetGeminiApertureLow,
-	SMU_MSG_SetMinLinkDpmByIndex,
-	SMU_MSG_OverridePcieParameters,
-	SMU_MSG_OverDriveSetPercentage,
-	SMU_MSG_SetMinDeepSleepDcefclk,
-	SMU_MSG_ReenableAcDcInterrupt,
-	SMU_MSG_NotifyPowerSource,
-	SMU_MSG_SetUclkFastSwitch,
-	SMU_MSG_SetUclkDownHyst,
-	SMU_MSG_GfxDeviceDriverReset,
-	SMU_MSG_GetCurrentRpm,
-	SMU_MSG_SetVideoFps,
-	SMU_MSG_SetTjMax,
-	SMU_MSG_SetFanTemperatureTarget,
-	SMU_MSG_PrepareMp1ForUnload,
-	SMU_MSG_DramLogSetDramAddrHigh,
-	SMU_MSG_DramLogSetDramAddrLow,
-	SMU_MSG_DramLogSetDramSize,
-	SMU_MSG_SetFanMaxRpm,
-	SMU_MSG_SetFanMinPwm,
-	SMU_MSG_ConfigureGfxDidt,
-	SMU_MSG_NumOfDisplays,
-	SMU_MSG_RemoveMargins,
-	SMU_MSG_ReadSerialNumTop32,
-	SMU_MSG_ReadSerialNumBottom32,
-	SMU_MSG_SetSystemVirtualDramAddrHigh,
-	SMU_MSG_SetSystemVirtualDramAddrLow,
-	SMU_MSG_WaflTest,
-	SMU_MSG_SetFclkGfxClkRatio,
-	SMU_MSG_AllowGfxOff,
-	SMU_MSG_DisallowGfxOff,
-	SMU_MSG_GetPptLimit,
-	SMU_MSG_GetDcModeMaxDpmFreq,
-	SMU_MSG_GetDebugData,
-	SMU_MSG_SetXgmiMode,
-	SMU_MSG_RunAfllBtc,
-	SMU_MSG_ExitBaco,
-	SMU_MSG_PrepareMp1ForReset,
-	SMU_MSG_PrepareMp1ForShutdown,
-	SMU_MSG_SetMGpuFanBoostLimitRpm,
-	SMU_MSG_GetAVFSVoltageByDpm,
-	SMU_MSG_PowerUpVcn,
-	SMU_MSG_PowerDownVcn,
-	SMU_MSG_PowerUpJpeg,
-	SMU_MSG_PowerDownJpeg,
-	SMU_MSG_BacoAudioD3PME,
-	SMU_MSG_ArmD3,
-	SMU_MSG_RunGfxDcBtc,
-	SMU_MSG_RunSocDcBtc,
-	SMU_MSG_SetMemoryChannelEnable,
-	SMU_MSG_SetDfSwitchType,
-	SMU_MSG_GetVoltageByDpm,
-	SMU_MSG_GetVoltageByDpmOverdrive,
-	SMU_MSG_PowerUpVcn0,
-	SMU_MSG_PowerDownVcn01,
-	SMU_MSG_PowerUpVcn1,
-	SMU_MSG_PowerDownVcn1,
-	SMU_MSG_MAX_COUNT,
-};
-
-enum smu_clk_type
-{
-	SMU_GFXCLK,
-	SMU_VCLK,
-	SMU_DCLK,
-	SMU_ECLK,
-	SMU_SOCCLK,
-	SMU_UCLK,
-	SMU_DCEFCLK,
-	SMU_DISPCLK,
-	SMU_PIXCLK,
-	SMU_PHYCLK,
-	SMU_FCLK,
-	SMU_SCLK,
-	SMU_MCLK,
-	SMU_PCIE,
-	SMU_OD_SCLK,
-	SMU_OD_MCLK,
-	SMU_OD_VDDC_CURVE,
-	SMU_OD_RANGE,
-	SMU_CLK_COUNT,
-};
-
 enum smu_power_src_type
 {
 	SMU_POWER_SOURCE_AC,
@@ -285,63 +158,6 @@ enum smu_power_src_type
 	SMU_POWER_SOURCE_COUNT,
 };
 
-enum smu_feature_mask
-{
-	SMU_FEATURE_DPM_PREFETCHER_BIT,
-	SMU_FEATURE_DPM_GFXCLK_BIT,
-	SMU_FEATURE_DPM_UCLK_BIT,
-	SMU_FEATURE_DPM_SOCCLK_BIT,
-	SMU_FEATURE_DPM_UVD_BIT,
-	SMU_FEATURE_DPM_VCE_BIT,
-	SMU_FEATURE_ULV_BIT,
-	SMU_FEATURE_DPM_MP0CLK_BIT,
-	SMU_FEATURE_DPM_LINK_BIT,
-	SMU_FEATURE_DPM_DCEFCLK_BIT,
-	SMU_FEATURE_DS_GFXCLK_BIT,
-	SMU_FEATURE_DS_SOCCLK_BIT,
-	SMU_FEATURE_DS_LCLK_BIT,
-	SMU_FEATURE_PPT_BIT,
-	SMU_FEATURE_TDC_BIT,
-	SMU_FEATURE_THERMAL_BIT,
-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
-	SMU_FEATURE_RM_BIT,
-	SMU_FEATURE_DS_DCEFCLK_BIT,
-	SMU_FEATURE_ACDC_BIT,
-	SMU_FEATURE_VR0HOT_BIT,
-	SMU_FEATURE_VR1HOT_BIT,
-	SMU_FEATURE_FW_CTF_BIT,
-	SMU_FEATURE_LED_DISPLAY_BIT,
-	SMU_FEATURE_FAN_CONTROL_BIT,
-	SMU_FEATURE_GFX_EDC_BIT,
-	SMU_FEATURE_GFXOFF_BIT,
-	SMU_FEATURE_CG_BIT,
-	SMU_FEATURE_DPM_FCLK_BIT,
-	SMU_FEATURE_DS_FCLK_BIT,
-	SMU_FEATURE_DS_MP1CLK_BIT,
-	SMU_FEATURE_DS_MP0CLK_BIT,
-	SMU_FEATURE_XGMI_BIT,
-	SMU_FEATURE_DPM_GFX_PACE_BIT,
-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
-	SMU_FEATURE_DS_UCLK_BIT,
-	SMU_FEATURE_GFX_ULV_BIT,
-	SMU_FEATURE_FW_DSTATE_BIT,
-	SMU_FEATURE_BACO_BIT,
-	SMU_FEATURE_VCN_PG_BIT,
-	SMU_FEATURE_JPEG_PG_BIT,
-	SMU_FEATURE_USB_PG_BIT,
-	SMU_FEATURE_RSMU_SMN_CG_BIT,
-	SMU_FEATURE_APCC_PLUS_BIT,
-	SMU_FEATURE_GTHR_BIT,
-	SMU_FEATURE_GFX_DCS_BIT,
-	SMU_FEATURE_GFX_SS_BIT,
-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
-	SMU_FEATURE_MMHUB_PG_BIT,
-	SMU_FEATURE_ATHUB_PG_BIT,
-	SMU_FEATURE_COUNT,
-};
-
 enum smu_memory_pool_size
 {
     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
new file mode 100644
index 000000000000..29d14c162417
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __SMU_TYPES_H__
+#define __SMU_TYPES_H__
+
+
+enum smu_message_type {
+	SMU_MSG_TestMessage = 0,
+	SMU_MSG_GetSmuVersion,
+	SMU_MSG_GetDriverIfVersion,
+	SMU_MSG_SetAllowedFeaturesMaskLow,
+	SMU_MSG_SetAllowedFeaturesMaskHigh,
+	SMU_MSG_EnableAllSmuFeatures,
+	SMU_MSG_DisableAllSmuFeatures,
+	SMU_MSG_EnableSmuFeaturesLow,
+	SMU_MSG_EnableSmuFeaturesHigh,
+	SMU_MSG_DisableSmuFeaturesLow,
+	SMU_MSG_DisableSmuFeaturesHigh,
+	SMU_MSG_GetEnabledSmuFeaturesLow,
+	SMU_MSG_GetEnabledSmuFeaturesHigh,
+	SMU_MSG_SetWorkloadMask,
+	SMU_MSG_SetPptLimit,
+	SMU_MSG_SetDriverDramAddrHigh,
+	SMU_MSG_SetDriverDramAddrLow,
+	SMU_MSG_SetToolsDramAddrHigh,
+	SMU_MSG_SetToolsDramAddrLow,
+	SMU_MSG_TransferTableSmu2Dram,
+	SMU_MSG_TransferTableDram2Smu,
+	SMU_MSG_UseDefaultPPTable,
+	SMU_MSG_UseBackupPPTable,
+	SMU_MSG_RunBtc,
+	SMU_MSG_RequestI2CBus,
+	SMU_MSG_ReleaseI2CBus,
+	SMU_MSG_SetFloorSocVoltage,
+	SMU_MSG_SoftReset,
+	SMU_MSG_StartBacoMonitor,
+	SMU_MSG_CancelBacoMonitor,
+	SMU_MSG_EnterBaco,
+	SMU_MSG_SetSoftMinByFreq,
+	SMU_MSG_SetSoftMaxByFreq,
+	SMU_MSG_SetHardMinByFreq,
+	SMU_MSG_SetHardMaxByFreq,
+	SMU_MSG_GetMinDpmFreq,
+	SMU_MSG_GetMaxDpmFreq,
+	SMU_MSG_GetDpmFreqByIndex,
+	SMU_MSG_GetDpmClockFreq,
+	SMU_MSG_GetSsVoltageByDpm,
+	SMU_MSG_SetMemoryChannelConfig,
+	SMU_MSG_SetGeminiMode,
+	SMU_MSG_SetGeminiApertureHigh,
+	SMU_MSG_SetGeminiApertureLow,
+	SMU_MSG_SetMinLinkDpmByIndex,
+	SMU_MSG_OverridePcieParameters,
+	SMU_MSG_OverDriveSetPercentage,
+	SMU_MSG_SetMinDeepSleepDcefclk,
+	SMU_MSG_ReenableAcDcInterrupt,
+	SMU_MSG_NotifyPowerSource,
+	SMU_MSG_SetUclkFastSwitch,
+	SMU_MSG_SetUclkDownHyst,
+	SMU_MSG_GfxDeviceDriverReset,
+	SMU_MSG_GetCurrentRpm,
+	SMU_MSG_SetVideoFps,
+	SMU_MSG_SetTjMax,
+	SMU_MSG_SetFanTemperatureTarget,
+	SMU_MSG_PrepareMp1ForUnload,
+	SMU_MSG_DramLogSetDramAddrHigh,
+	SMU_MSG_DramLogSetDramAddrLow,
+	SMU_MSG_DramLogSetDramSize,
+	SMU_MSG_SetFanMaxRpm,
+	SMU_MSG_SetFanMinPwm,
+	SMU_MSG_ConfigureGfxDidt,
+	SMU_MSG_NumOfDisplays,
+	SMU_MSG_RemoveMargins,
+	SMU_MSG_ReadSerialNumTop32,
+	SMU_MSG_ReadSerialNumBottom32,
+	SMU_MSG_SetSystemVirtualDramAddrHigh,
+	SMU_MSG_SetSystemVirtualDramAddrLow,
+	SMU_MSG_WaflTest,
+	SMU_MSG_SetFclkGfxClkRatio,
+	SMU_MSG_AllowGfxOff,
+	SMU_MSG_DisallowGfxOff,
+	SMU_MSG_GetPptLimit,
+	SMU_MSG_GetDcModeMaxDpmFreq,
+	SMU_MSG_GetDebugData,
+	SMU_MSG_SetXgmiMode,
+	SMU_MSG_RunAfllBtc,
+	SMU_MSG_ExitBaco,
+	SMU_MSG_PrepareMp1ForReset,
+	SMU_MSG_PrepareMp1ForShutdown,
+	SMU_MSG_SetMGpuFanBoostLimitRpm,
+	SMU_MSG_GetAVFSVoltageByDpm,
+	SMU_MSG_PowerUpVcn,
+	SMU_MSG_PowerDownVcn,
+	SMU_MSG_PowerUpJpeg,
+	SMU_MSG_PowerDownJpeg,
+	SMU_MSG_BacoAudioD3PME,
+	SMU_MSG_ArmD3,
+	SMU_MSG_RunGfxDcBtc,
+	SMU_MSG_RunSocDcBtc,
+	SMU_MSG_SetMemoryChannelEnable,
+	SMU_MSG_SetDfSwitchType,
+	SMU_MSG_GetVoltageByDpm,
+	SMU_MSG_GetVoltageByDpmOverdrive,
+	SMU_MSG_PowerUpVcn0,
+	SMU_MSG_PowerDownVcn01,
+	SMU_MSG_PowerUpVcn1,
+	SMU_MSG_PowerDownVcn1,
+	SMU_MSG_MAX_COUNT,
+};
+
+enum smu_clk_type {
+	SMU_GFXCLK,
+	SMU_VCLK,
+	SMU_DCLK,
+	SMU_ECLK,
+	SMU_SOCCLK,
+	SMU_UCLK,
+	SMU_DCEFCLK,
+	SMU_DISPCLK,
+	SMU_PIXCLK,
+	SMU_PHYCLK,
+	SMU_FCLK,
+	SMU_SCLK,
+	SMU_MCLK,
+	SMU_PCIE,
+	SMU_OD_SCLK,
+	SMU_OD_MCLK,
+	SMU_OD_VDDC_CURVE,
+	SMU_OD_RANGE,
+	SMU_CLK_COUNT,
+};
+
+enum smu_feature_mask {
+	SMU_FEATURE_DPM_PREFETCHER_BIT,
+	SMU_FEATURE_DPM_GFXCLK_BIT,
+	SMU_FEATURE_DPM_UCLK_BIT,
+	SMU_FEATURE_DPM_SOCCLK_BIT,
+	SMU_FEATURE_DPM_UVD_BIT,
+	SMU_FEATURE_DPM_VCE_BIT,
+	SMU_FEATURE_ULV_BIT,
+	SMU_FEATURE_DPM_MP0CLK_BIT,
+	SMU_FEATURE_DPM_LINK_BIT,
+	SMU_FEATURE_DPM_DCEFCLK_BIT,
+	SMU_FEATURE_DS_GFXCLK_BIT,
+	SMU_FEATURE_DS_SOCCLK_BIT,
+	SMU_FEATURE_DS_LCLK_BIT,
+	SMU_FEATURE_PPT_BIT,
+	SMU_FEATURE_TDC_BIT,
+	SMU_FEATURE_THERMAL_BIT,
+	SMU_FEATURE_GFX_PER_CU_CG_BIT,
+	SMU_FEATURE_RM_BIT,
+	SMU_FEATURE_DS_DCEFCLK_BIT,
+	SMU_FEATURE_ACDC_BIT,
+	SMU_FEATURE_VR0HOT_BIT,
+	SMU_FEATURE_VR1HOT_BIT,
+	SMU_FEATURE_FW_CTF_BIT,
+	SMU_FEATURE_LED_DISPLAY_BIT,
+	SMU_FEATURE_FAN_CONTROL_BIT,
+	SMU_FEATURE_GFX_EDC_BIT,
+	SMU_FEATURE_GFXOFF_BIT,
+	SMU_FEATURE_CG_BIT,
+	SMU_FEATURE_DPM_FCLK_BIT,
+	SMU_FEATURE_DS_FCLK_BIT,
+	SMU_FEATURE_DS_MP1CLK_BIT,
+	SMU_FEATURE_DS_MP0CLK_BIT,
+	SMU_FEATURE_XGMI_BIT,
+	SMU_FEATURE_DPM_GFX_PACE_BIT,
+	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
+	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
+	SMU_FEATURE_DS_UCLK_BIT,
+	SMU_FEATURE_GFX_ULV_BIT,
+	SMU_FEATURE_FW_DSTATE_BIT,
+	SMU_FEATURE_BACO_BIT,
+	SMU_FEATURE_VCN_PG_BIT,
+	SMU_FEATURE_JPEG_PG_BIT,
+	SMU_FEATURE_USB_PG_BIT,
+	SMU_FEATURE_RSMU_SMN_CG_BIT,
+	SMU_FEATURE_APCC_PLUS_BIT,
+	SMU_FEATURE_GTHR_BIT,
+	SMU_FEATURE_GFX_DCS_BIT,
+	SMU_FEATURE_GFX_SS_BIT,
+	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
+	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
+	SMU_FEATURE_MMHUB_PG_BIT,
+	SMU_FEATURE_ATHUB_PG_BIT,
+	SMU_FEATURE_COUNT,
+};
+
+#endif
+
-- 
2.22.0

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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 2/5] drm/amd/powerplay: add smu message name support
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  5:11   ` Wang, Kevin(Yang)
       [not found]     ` <20190725051057.28862-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  5:11   ` [PATCH 3/5] drm/amd/powerplay: add smu feature " Wang, Kevin(Yang)
                     ` (4 subsequent siblings)
  5 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  5:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

add smu_get_message_name support in smu.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 ++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
 drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 205 +++++++++---------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  12 +-
 4 files changed, 124 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..4604b6af56bb 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,19 @@
 #include "smu_v11_0.h"
 #include "atom.h"
 
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(type)	#type
+static const char* __smu_message_names[] = {
+	SMU_MESSAGE_TYPES
+};
+
+const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type)
+{
+	if (type < 0 || type > SMU_MSG_MAX_COUNT)
+		return "unknow smu message";
+	return __smu_message_names[type];
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
 	int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 397040a4d1b4..035f857922ec 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -804,5 +804,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index 29d14c162417..d42e3424e704 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -23,108 +23,112 @@
 #ifndef __SMU_TYPES_H__
 #define __SMU_TYPES_H__
 
+#define SMU_MESSAGE_TYPES			      \
+       __SMU_DUMMY_MAP(TestMessage),		      \
+       __SMU_DUMMY_MAP(GetSmuVersion),                \
+       __SMU_DUMMY_MAP(GetDriverIfVersion),           \
+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskLow),    \
+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskHigh),   \
+       __SMU_DUMMY_MAP(EnableAllSmuFeatures),         \
+       __SMU_DUMMY_MAP(DisableAllSmuFeatures),        \
+       __SMU_DUMMY_MAP(EnableSmuFeaturesLow),         \
+       __SMU_DUMMY_MAP(EnableSmuFeaturesHigh),        \
+       __SMU_DUMMY_MAP(DisableSmuFeaturesLow),        \
+       __SMU_DUMMY_MAP(DisableSmuFeaturesHigh),       \
+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow),     \
+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),    \
+       __SMU_DUMMY_MAP(SetWorkloadMask),              \
+       __SMU_DUMMY_MAP(SetPptLimit),                  \
+       __SMU_DUMMY_MAP(SetDriverDramAddrHigh),        \
+       __SMU_DUMMY_MAP(SetDriverDramAddrLow),         \
+       __SMU_DUMMY_MAP(SetToolsDramAddrHigh),         \
+       __SMU_DUMMY_MAP(SetToolsDramAddrLow),          \
+       __SMU_DUMMY_MAP(TransferTableSmu2Dram),        \
+       __SMU_DUMMY_MAP(TransferTableDram2Smu),        \
+       __SMU_DUMMY_MAP(UseDefaultPPTable),            \
+       __SMU_DUMMY_MAP(UseBackupPPTable),             \
+       __SMU_DUMMY_MAP(RunBtc),                       \
+       __SMU_DUMMY_MAP(RequestI2CBus),                \
+       __SMU_DUMMY_MAP(ReleaseI2CBus),                \
+       __SMU_DUMMY_MAP(SetFloorSocVoltage),           \
+       __SMU_DUMMY_MAP(SoftReset),                    \
+       __SMU_DUMMY_MAP(StartBacoMonitor),             \
+       __SMU_DUMMY_MAP(CancelBacoMonitor),            \
+       __SMU_DUMMY_MAP(EnterBaco),                    \
+       __SMU_DUMMY_MAP(SetSoftMinByFreq),             \
+       __SMU_DUMMY_MAP(SetSoftMaxByFreq),             \
+       __SMU_DUMMY_MAP(SetHardMinByFreq),             \
+       __SMU_DUMMY_MAP(SetHardMaxByFreq),             \
+       __SMU_DUMMY_MAP(GetMinDpmFreq),                \
+       __SMU_DUMMY_MAP(GetMaxDpmFreq),                \
+       __SMU_DUMMY_MAP(GetDpmFreqByIndex),            \
+       __SMU_DUMMY_MAP(GetDpmClockFreq),              \
+       __SMU_DUMMY_MAP(GetSsVoltageByDpm),            \
+       __SMU_DUMMY_MAP(SetMemoryChannelConfig),       \
+       __SMU_DUMMY_MAP(SetGeminiMode),                \
+       __SMU_DUMMY_MAP(SetGeminiApertureHigh),        \
+       __SMU_DUMMY_MAP(SetGeminiApertureLow),         \
+       __SMU_DUMMY_MAP(SetMinLinkDpmByIndex),         \
+       __SMU_DUMMY_MAP(OverridePcieParameters),       \
+       __SMU_DUMMY_MAP(OverDriveSetPercentage),       \
+       __SMU_DUMMY_MAP(SetMinDeepSleepDcefclk),       \
+       __SMU_DUMMY_MAP(ReenableAcDcInterrupt),        \
+       __SMU_DUMMY_MAP(NotifyPowerSource),            \
+       __SMU_DUMMY_MAP(SetUclkFastSwitch),            \
+       __SMU_DUMMY_MAP(SetUclkDownHyst),              \
+       __SMU_DUMMY_MAP(GfxDeviceDriverReset),         \
+       __SMU_DUMMY_MAP(GetCurrentRpm),                \
+       __SMU_DUMMY_MAP(SetVideoFps),                  \
+       __SMU_DUMMY_MAP(SetTjMax),                     \
+       __SMU_DUMMY_MAP(SetFanTemperatureTarget),      \
+       __SMU_DUMMY_MAP(PrepareMp1ForUnload),          \
+       __SMU_DUMMY_MAP(DramLogSetDramAddrHigh),       \
+       __SMU_DUMMY_MAP(DramLogSetDramAddrLow),        \
+       __SMU_DUMMY_MAP(DramLogSetDramSize),           \
+       __SMU_DUMMY_MAP(SetFanMaxRpm),                 \
+       __SMU_DUMMY_MAP(SetFanMinPwm),                 \
+       __SMU_DUMMY_MAP(ConfigureGfxDidt),             \
+       __SMU_DUMMY_MAP(NumOfDisplays),                \
+       __SMU_DUMMY_MAP(RemoveMargins),                \
+       __SMU_DUMMY_MAP(ReadSerialNumTop32),           \
+       __SMU_DUMMY_MAP(ReadSerialNumBottom32),        \
+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrHigh), \
+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrLow),  \
+       __SMU_DUMMY_MAP(WaflTest),                     \
+       __SMU_DUMMY_MAP(SetFclkGfxClkRatio),           \
+       __SMU_DUMMY_MAP(AllowGfxOff),                  \
+       __SMU_DUMMY_MAP(DisallowGfxOff),               \
+       __SMU_DUMMY_MAP(GetPptLimit),                  \
+       __SMU_DUMMY_MAP(GetDcModeMaxDpmFreq),          \
+       __SMU_DUMMY_MAP(GetDebugData),                 \
+       __SMU_DUMMY_MAP(SetXgmiMode),                  \
+       __SMU_DUMMY_MAP(RunAfllBtc),                   \
+       __SMU_DUMMY_MAP(ExitBaco),                     \
+       __SMU_DUMMY_MAP(PrepareMp1ForReset),           \
+       __SMU_DUMMY_MAP(PrepareMp1ForShutdown),        \
+       __SMU_DUMMY_MAP(SetMGpuFanBoostLimitRpm),      \
+       __SMU_DUMMY_MAP(GetAVFSVoltageByDpm),          \
+       __SMU_DUMMY_MAP(PowerUpVcn),                   \
+       __SMU_DUMMY_MAP(PowerDownVcn),                 \
+       __SMU_DUMMY_MAP(PowerUpJpeg),                  \
+       __SMU_DUMMY_MAP(PowerDownJpeg),                \
+       __SMU_DUMMY_MAP(BacoAudioD3PME),               \
+       __SMU_DUMMY_MAP(ArmD3),                        \
+       __SMU_DUMMY_MAP(RunGfxDcBtc),                  \
+       __SMU_DUMMY_MAP(RunSocDcBtc),                  \
+       __SMU_DUMMY_MAP(SetMemoryChannelEnable),       \
+       __SMU_DUMMY_MAP(SetDfSwitchType),              \
+       __SMU_DUMMY_MAP(GetVoltageByDpm),              \
+       __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
+       __SMU_DUMMY_MAP(PowerUpVcn0),                  \
+       __SMU_DUMMY_MAP(PowerDownVcn01),               \
+       __SMU_DUMMY_MAP(PowerUpVcn1),                  \
+       __SMU_DUMMY_MAP(PowerDownVcn1),                \
 
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
 enum smu_message_type {
-	SMU_MSG_TestMessage = 0,
-	SMU_MSG_GetSmuVersion,
-	SMU_MSG_GetDriverIfVersion,
-	SMU_MSG_SetAllowedFeaturesMaskLow,
-	SMU_MSG_SetAllowedFeaturesMaskHigh,
-	SMU_MSG_EnableAllSmuFeatures,
-	SMU_MSG_DisableAllSmuFeatures,
-	SMU_MSG_EnableSmuFeaturesLow,
-	SMU_MSG_EnableSmuFeaturesHigh,
-	SMU_MSG_DisableSmuFeaturesLow,
-	SMU_MSG_DisableSmuFeaturesHigh,
-	SMU_MSG_GetEnabledSmuFeaturesLow,
-	SMU_MSG_GetEnabledSmuFeaturesHigh,
-	SMU_MSG_SetWorkloadMask,
-	SMU_MSG_SetPptLimit,
-	SMU_MSG_SetDriverDramAddrHigh,
-	SMU_MSG_SetDriverDramAddrLow,
-	SMU_MSG_SetToolsDramAddrHigh,
-	SMU_MSG_SetToolsDramAddrLow,
-	SMU_MSG_TransferTableSmu2Dram,
-	SMU_MSG_TransferTableDram2Smu,
-	SMU_MSG_UseDefaultPPTable,
-	SMU_MSG_UseBackupPPTable,
-	SMU_MSG_RunBtc,
-	SMU_MSG_RequestI2CBus,
-	SMU_MSG_ReleaseI2CBus,
-	SMU_MSG_SetFloorSocVoltage,
-	SMU_MSG_SoftReset,
-	SMU_MSG_StartBacoMonitor,
-	SMU_MSG_CancelBacoMonitor,
-	SMU_MSG_EnterBaco,
-	SMU_MSG_SetSoftMinByFreq,
-	SMU_MSG_SetSoftMaxByFreq,
-	SMU_MSG_SetHardMinByFreq,
-	SMU_MSG_SetHardMaxByFreq,
-	SMU_MSG_GetMinDpmFreq,
-	SMU_MSG_GetMaxDpmFreq,
-	SMU_MSG_GetDpmFreqByIndex,
-	SMU_MSG_GetDpmClockFreq,
-	SMU_MSG_GetSsVoltageByDpm,
-	SMU_MSG_SetMemoryChannelConfig,
-	SMU_MSG_SetGeminiMode,
-	SMU_MSG_SetGeminiApertureHigh,
-	SMU_MSG_SetGeminiApertureLow,
-	SMU_MSG_SetMinLinkDpmByIndex,
-	SMU_MSG_OverridePcieParameters,
-	SMU_MSG_OverDriveSetPercentage,
-	SMU_MSG_SetMinDeepSleepDcefclk,
-	SMU_MSG_ReenableAcDcInterrupt,
-	SMU_MSG_NotifyPowerSource,
-	SMU_MSG_SetUclkFastSwitch,
-	SMU_MSG_SetUclkDownHyst,
-	SMU_MSG_GfxDeviceDriverReset,
-	SMU_MSG_GetCurrentRpm,
-	SMU_MSG_SetVideoFps,
-	SMU_MSG_SetTjMax,
-	SMU_MSG_SetFanTemperatureTarget,
-	SMU_MSG_PrepareMp1ForUnload,
-	SMU_MSG_DramLogSetDramAddrHigh,
-	SMU_MSG_DramLogSetDramAddrLow,
-	SMU_MSG_DramLogSetDramSize,
-	SMU_MSG_SetFanMaxRpm,
-	SMU_MSG_SetFanMinPwm,
-	SMU_MSG_ConfigureGfxDidt,
-	SMU_MSG_NumOfDisplays,
-	SMU_MSG_RemoveMargins,
-	SMU_MSG_ReadSerialNumTop32,
-	SMU_MSG_ReadSerialNumBottom32,
-	SMU_MSG_SetSystemVirtualDramAddrHigh,
-	SMU_MSG_SetSystemVirtualDramAddrLow,
-	SMU_MSG_WaflTest,
-	SMU_MSG_SetFclkGfxClkRatio,
-	SMU_MSG_AllowGfxOff,
-	SMU_MSG_DisallowGfxOff,
-	SMU_MSG_GetPptLimit,
-	SMU_MSG_GetDcModeMaxDpmFreq,
-	SMU_MSG_GetDebugData,
-	SMU_MSG_SetXgmiMode,
-	SMU_MSG_RunAfllBtc,
-	SMU_MSG_ExitBaco,
-	SMU_MSG_PrepareMp1ForReset,
-	SMU_MSG_PrepareMp1ForShutdown,
-	SMU_MSG_SetMGpuFanBoostLimitRpm,
-	SMU_MSG_GetAVFSVoltageByDpm,
-	SMU_MSG_PowerUpVcn,
-	SMU_MSG_PowerDownVcn,
-	SMU_MSG_PowerUpJpeg,
-	SMU_MSG_PowerDownJpeg,
-	SMU_MSG_BacoAudioD3PME,
-	SMU_MSG_ArmD3,
-	SMU_MSG_RunGfxDcBtc,
-	SMU_MSG_RunSocDcBtc,
-	SMU_MSG_SetMemoryChannelEnable,
-	SMU_MSG_SetDfSwitchType,
-	SMU_MSG_GetVoltageByDpm,
-	SMU_MSG_GetVoltageByDpmOverdrive,
-	SMU_MSG_PowerUpVcn0,
-	SMU_MSG_PowerDownVcn01,
-	SMU_MSG_PowerUpVcn1,
-	SMU_MSG_PowerDownVcn1,
+	SMU_MESSAGE_TYPES
 	SMU_MSG_MAX_COUNT,
 };
 
@@ -207,4 +211,3 @@ enum smu_feature_mask {
 };
 
 #endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 745b35a1600d..ccf6af055d03 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -102,8 +102,8 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
 	ret = smu_v11_0_wait_for_response(smu);
 
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
-		       ret);
+		pr_err("failed send message: %10s (%d) response %#x\n",
+		       smu_get_message_name(smu, msg), index, ret);
 
 	return ret;
 
@@ -123,8 +123,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
-		       index, ret, param);
+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+		       smu_get_message_name(smu, msg), index, param, ret);
 
 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
@@ -134,8 +134,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
-		       index, ret, param);
+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+		       smu_get_message_name(smu, msg), index, param, ret);
 
 	return ret;
 }
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 3/5] drm/amd/powerplay: add smu feature name support
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  5:11   ` [PATCH 2/5] drm/amd/powerplay: add smu message name support Wang, Kevin(Yang)
@ 2019-07-25  5:11   ` Wang, Kevin(Yang)
       [not found]     ` <20190725051057.28862-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  5:11   ` [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level Wang, Kevin(Yang)
                     ` (3 subsequent siblings)
  5 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  5:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

add smu_get_feature_name support in smu.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 +++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
 drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 109 +++++++++---------
 3 files changed, 71 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 4604b6af56bb..8563f9083f4e 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -42,6 +42,19 @@ const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type
 	return __smu_message_names[type];
 }
 
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(fea)	#fea
+static const char* __smu_feature_names[] = {
+	SMU_FEATURE_MASKS
+};
+
+const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature)
+{
+	if (feature < 0 || feature > SMU_FEATURE_COUNT)
+		return "unknow smu feature";
+	return __smu_feature_names[feature];
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
 	int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 035f857922ec..ba2385026b89 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -805,5 +805,6 @@ int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_lev
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
+const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index d42e3424e704..8793c8d0dc52 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -154,59 +154,64 @@ enum smu_clk_type {
 	SMU_CLK_COUNT,
 };
 
+#define SMU_FEATURE_MASKS				\
+       __SMU_DUMMY_MAP(DPM_PREFETCHER),			\
+       __SMU_DUMMY_MAP(DPM_GFXCLK),                    	\
+       __SMU_DUMMY_MAP(DPM_UCLK),                      	\
+       __SMU_DUMMY_MAP(DPM_SOCCLK),                    	\
+       __SMU_DUMMY_MAP(DPM_UVD),                       	\
+       __SMU_DUMMY_MAP(DPM_VCE),                       	\
+       __SMU_DUMMY_MAP(ULV),                           	\
+       __SMU_DUMMY_MAP(DPM_MP0CLK),                    	\
+       __SMU_DUMMY_MAP(DPM_LINK),                      	\
+       __SMU_DUMMY_MAP(DPM_DCEFCLK),                   	\
+       __SMU_DUMMY_MAP(DS_GFXCLK),                     	\
+       __SMU_DUMMY_MAP(DS_SOCCLK),                     	\
+       __SMU_DUMMY_MAP(DS_LCLK),                       	\
+       __SMU_DUMMY_MAP(PPT),                           	\
+       __SMU_DUMMY_MAP(TDC),                           	\
+       __SMU_DUMMY_MAP(THERMAL),                       	\
+       __SMU_DUMMY_MAP(GFX_PER_CU_CG),                 	\
+       __SMU_DUMMY_MAP(RM),                            	\
+       __SMU_DUMMY_MAP(DS_DCEFCLK),                    	\
+       __SMU_DUMMY_MAP(ACDC),                          	\
+       __SMU_DUMMY_MAP(VR0HOT),                        	\
+       __SMU_DUMMY_MAP(VR1HOT),                        	\
+       __SMU_DUMMY_MAP(FW_CTF),                        	\
+       __SMU_DUMMY_MAP(LED_DISPLAY),                   	\
+       __SMU_DUMMY_MAP(FAN_CONTROL),                   	\
+       __SMU_DUMMY_MAP(GFX_EDC),                       	\
+       __SMU_DUMMY_MAP(GFXOFF),                        	\
+       __SMU_DUMMY_MAP(CG),                            	\
+       __SMU_DUMMY_MAP(DPM_FCLK),                      	\
+       __SMU_DUMMY_MAP(DS_FCLK),                       	\
+       __SMU_DUMMY_MAP(DS_MP1CLK),                     	\
+       __SMU_DUMMY_MAP(DS_MP0CLK),                     	\
+       __SMU_DUMMY_MAP(XGMI),                          	\
+       __SMU_DUMMY_MAP(DPM_GFX_PACE),                  	\
+       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),             	\
+       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),              	\
+       __SMU_DUMMY_MAP(DS_UCLK),                       	\
+       __SMU_DUMMY_MAP(GFX_ULV),                       	\
+       __SMU_DUMMY_MAP(FW_DSTATE),                     	\
+       __SMU_DUMMY_MAP(BACO),                          	\
+       __SMU_DUMMY_MAP(VCN_PG),                        	\
+       __SMU_DUMMY_MAP(JPEG_PG),                       	\
+       __SMU_DUMMY_MAP(USB_PG),                        	\
+       __SMU_DUMMY_MAP(RSMU_SMN_CG),                   	\
+       __SMU_DUMMY_MAP(APCC_PLUS),                     	\
+       __SMU_DUMMY_MAP(GTHR),                          	\
+       __SMU_DUMMY_MAP(GFX_DCS),                       	\
+       __SMU_DUMMY_MAP(GFX_SS),                        	\
+       __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR),           	\
+       __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
+       __SMU_DUMMY_MAP(MMHUB_PG),                      	\
+       __SMU_DUMMY_MAP(ATHUB_PG),                      	\
+
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT
 enum smu_feature_mask {
-	SMU_FEATURE_DPM_PREFETCHER_BIT,
-	SMU_FEATURE_DPM_GFXCLK_BIT,
-	SMU_FEATURE_DPM_UCLK_BIT,
-	SMU_FEATURE_DPM_SOCCLK_BIT,
-	SMU_FEATURE_DPM_UVD_BIT,
-	SMU_FEATURE_DPM_VCE_BIT,
-	SMU_FEATURE_ULV_BIT,
-	SMU_FEATURE_DPM_MP0CLK_BIT,
-	SMU_FEATURE_DPM_LINK_BIT,
-	SMU_FEATURE_DPM_DCEFCLK_BIT,
-	SMU_FEATURE_DS_GFXCLK_BIT,
-	SMU_FEATURE_DS_SOCCLK_BIT,
-	SMU_FEATURE_DS_LCLK_BIT,
-	SMU_FEATURE_PPT_BIT,
-	SMU_FEATURE_TDC_BIT,
-	SMU_FEATURE_THERMAL_BIT,
-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
-	SMU_FEATURE_RM_BIT,
-	SMU_FEATURE_DS_DCEFCLK_BIT,
-	SMU_FEATURE_ACDC_BIT,
-	SMU_FEATURE_VR0HOT_BIT,
-	SMU_FEATURE_VR1HOT_BIT,
-	SMU_FEATURE_FW_CTF_BIT,
-	SMU_FEATURE_LED_DISPLAY_BIT,
-	SMU_FEATURE_FAN_CONTROL_BIT,
-	SMU_FEATURE_GFX_EDC_BIT,
-	SMU_FEATURE_GFXOFF_BIT,
-	SMU_FEATURE_CG_BIT,
-	SMU_FEATURE_DPM_FCLK_BIT,
-	SMU_FEATURE_DS_FCLK_BIT,
-	SMU_FEATURE_DS_MP1CLK_BIT,
-	SMU_FEATURE_DS_MP0CLK_BIT,
-	SMU_FEATURE_XGMI_BIT,
-	SMU_FEATURE_DPM_GFX_PACE_BIT,
-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
-	SMU_FEATURE_DS_UCLK_BIT,
-	SMU_FEATURE_GFX_ULV_BIT,
-	SMU_FEATURE_FW_DSTATE_BIT,
-	SMU_FEATURE_BACO_BIT,
-	SMU_FEATURE_VCN_PG_BIT,
-	SMU_FEATURE_JPEG_PG_BIT,
-	SMU_FEATURE_USB_PG_BIT,
-	SMU_FEATURE_RSMU_SMN_CG_BIT,
-	SMU_FEATURE_APCC_PLUS_BIT,
-	SMU_FEATURE_GTHR_BIT,
-	SMU_FEATURE_GFX_DCS_BIT,
-	SMU_FEATURE_GFX_SS_BIT,
-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
-	SMU_FEATURE_MMHUB_PG_BIT,
-	SMU_FEATURE_ATHUB_PG_BIT,
+	SMU_FEATURE_MASKS
 	SMU_FEATURE_COUNT,
 };
 
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  5:11   ` [PATCH 2/5] drm/amd/powerplay: add smu message name support Wang, Kevin(Yang)
  2019-07-25  5:11   ` [PATCH 3/5] drm/amd/powerplay: add smu feature " Wang, Kevin(Yang)
@ 2019-07-25  5:11   ` Wang, Kevin(Yang)
       [not found]     ` <20190725051057.28862-4-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  5:11   ` [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu Wang, Kevin(Yang)
                     ` (2 subsequent siblings)
  5 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  5:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

this function is not ip or asic related function,
so move it to top level as public api in smu.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40 ++++++++++++++++++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 ------------------
 3 files changed, 40 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 8563f9083f4e..e881de955388 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -507,6 +507,41 @@ int smu_feature_init_dpm(struct smu_context *smu)
 
 	return ret;
 }
+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
+{
+	uint32_t feature_low = 0, feature_high = 0;
+	int ret = 0;
+
+	if (!smu->pm_enabled)
+		return ret;
+
+	feature_low = (feature_mask >> 0 ) & 0xffffffff;
+	feature_high = (feature_mask >> 32) & 0xffffffff;
+
+	if (enabled) {
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+						  feature_low);
+		if (ret)
+			return ret;
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+						  feature_high);
+		if (ret)
+			return ret;
+
+	} else {
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+						  feature_low);
+		if (ret)
+			return ret;
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+						  feature_high);
+		if (ret)
+			return ret;
+
+	}
+
+	return ret;
+}
 
 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 {
@@ -532,6 +567,7 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 {
 	struct smu_feature *feature = &smu->smu_feature;
 	int feature_id;
+	uint64_t feature_mask = 0;
 	int ret = 0;
 
 	feature_id = smu_feature_get_index(smu, mask);
@@ -540,8 +576,10 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 
 	WARN_ON(feature_id > feature->feature_num);
 
+	feature_mask = 1UL << feature_id;
+
 	mutex_lock(&feature->mutex);
-	ret = smu_feature_update_enable_state(smu, feature_id, enable);
+	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
 	if (ret)
 		goto failed;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ba2385026b89..abc2644b4c07 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -479,7 +479,6 @@ struct smu_funcs
 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
 	int (*set_allowed_mask)(struct smu_context *smu);
 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
-	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
 	int (*notify_display_change)(struct smu_context *smu);
 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
@@ -595,8 +594,6 @@ struct smu_funcs
 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
 #define smu_is_dpm_running(smu) \
 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_feature_update_enable_state(smu, feature_id, enabled) \
-	((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
 #define smu_notify_display_change(smu) \
 	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
 #define smu_store_powerplay_table(smu) \
@@ -804,6 +801,7 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ccf6af055d03..93f3ffb8b471 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -795,44 +795,6 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 	return ret;
 }
 
-static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
-{
-	uint32_t feature_low = 0, feature_high = 0;
-	int ret = 0;
-
-	if (!smu->pm_enabled)
-		return ret;
-	if (feature_id >= 0 && feature_id < 31)
-		feature_low = (1 << feature_id);
-	else if (feature_id > 31 && feature_id < 63)
-		feature_high = (1 << feature_id);
-	else
-		return -EINVAL;
-
-	if (enabled) {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-
-	} else {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-
-	}
-
-	return ret;
-}
 
 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 {
@@ -1781,7 +1743,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
 	.system_features_control = smu_v11_0_system_features_control,
-	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
 	.notify_display_change = smu_v11_0_notify_display_change,
 	.get_power_limit = smu_v11_0_get_power_limit,
 	.set_power_limit = smu_v11_0_set_power_limit,
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2019-07-25  5:11   ` [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level Wang, Kevin(Yang)
@ 2019-07-25  5:11   ` Wang, Kevin(Yang)
       [not found]     ` <20190725051057.28862-5-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-25  6:36   ` [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h Feng, Kenneth
  2019-07-25  9:31   ` Quan, Evan
  5 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  5:11 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }
 
 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
 		struct device_attribute *attr,
 		const char *buf,
 		size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 	pr_debug("featuremask = 0x%llx\n", featuremask);
 
 	if (is_support_sw_smu(adev)) {
-		ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+		ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 		if (ret)
 			return -EINVAL;
 	} else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
 	return count;
 }
 
-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
 		struct device_attribute *attr,
 		char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
 	struct amdgpu_device *adev = ddev->dev_private;
 
 	if (is_support_sw_smu(adev)) {
-		return smu_get_ppfeature_status(&adev->smu, buf);
+		return smu_sys_get_pp_feature_mask(&adev->smu, buf);
 	} else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 		return amdgpu_dpm_get_ppfeature_status(adev, buf);
 
@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
 		amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-		amdgpu_get_ppfeature_status,
-		amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+		amdgpu_get_pp_feature_status,
+		amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
 
 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 	if ((adev->asic_type >= CHIP_VEGA10) &&
 	    !(adev->flags & AMD_IS_APU)) {
 		ret = device_create_file(adev->dev,
-				&dev_attr_ppfeatures);
+				&dev_attr_pp_features);
 		if (ret) {
 			DRM_ERROR("failed to create device file	"
-					"ppfeatures\n");
+					"pp_features\n");
 			return ret;
 		}
 	}
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 		device_remove_file(adev->dev, &dev_attr_unique_id);
 	if ((adev->asic_type >= CHIP_VEGA10) &&
 	    !(adev->flags & AMD_IS_APU))
-		device_remove_file(adev->dev, &dev_attr_ppfeatures);
+		device_remove_file(adev->dev, &dev_attr_pp_features);
 }
 
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
 	return __smu_feature_names[feature];
 }
 
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+	size_t size = 0;
+	int ret = 0, i = 0;
+	uint32_t feature_mask[2] = { 0 };
+	int32_t feature_index = 0;
+	uint32_t count = 0;
+
+	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+	if (ret)
+		goto failed;
+
+	size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+			feature_mask[1], feature_mask[0]);
+
+	for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+		feature_index = smu_feature_get_index(smu, i);
+		if (feature_index < 0)
+			continue;
+		size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+			       count++,
+			       smu_get_feature_name(smu, i),
+			       feature_index,
+			       !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+	}
+
+failed:
+	return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+	int ret = 0;
+	uint32_t feature_mask[2] = { 0 };
+	uint64_t feature_2_enabled = 0;
+	uint64_t feature_2_disabled = 0;
+	uint64_t feature_enables = 0;
+
+	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+	if (ret)
+		return ret;
+
+	feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+	feature_2_enabled  = ~feature_enables & new_mask;
+	feature_2_disabled = feature_enables & ~new_mask;
+
+	if (feature_2_enabled) {
+		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+		if (ret)
+			ret;
+	}
+	if (feature_2_disabled) {
+		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+		if (ret)
+			return ret;
+	}
+
+	return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
 	int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
 				      uint32_t *mclk_mask,
 				      uint32_t *soc_mask);
 	int (*set_cpu_power_state)(struct smu_context *smu);
-	int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-	int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
 	bool (*is_dpm_running)(struct smu_context *smu);
 	int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
 	int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
 	((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
 		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-	((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-	((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
 	((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
 	return 0;
 }
 
-static int navi10_get_ppfeature_status(struct smu_context *smu,
-				       char *buf)
-{
-	static const char *ppfeature_name[] = {
-				"DPM_PREFETCHER",
-				"DPM_GFXCLK",
-				"DPM_GFX_PACE",
-				"DPM_UCLK",
-				"DPM_SOCCLK",
-				"DPM_MP0CLK",
-				"DPM_LINK",
-				"DPM_DCEFCLK",
-				"MEM_VDDCI_SCALING",
-				"MEM_MVDD_SCALING",
-				"DS_GFXCLK",
-				"DS_SOCCLK",
-				"DS_LCLK",
-				"DS_DCEFCLK",
-				"DS_UCLK",
-				"GFX_ULV",
-				"FW_DSTATE",
-				"GFXOFF",
-				"BACO",
-				"VCN_PG",
-				"JPEG_PG",
-				"USB_PG",
-				"RSMU_SMN_CG",
-				"PPT",
-				"TDC",
-				"GFX_EDC",
-				"APCC_PLUS",
-				"GTHR",
-				"ACDC",
-				"VR0HOT",
-				"VR1HOT",
-				"FW_CTF",
-				"FAN_CONTROL",
-				"THERMAL",
-				"GFX_DCS",
-				"RM",
-				"LED_DISPLAY",
-				"GFX_SS",
-				"OUT_OF_BAND_MONITOR",
-				"TEMP_DEPENDENT_VMIN",
-				"MMHUB_PG",
-				"ATHUB_PG"};
-	static const char *output_title[] = {
-				"FEATURES",
-				"BITMASK",
-				"ENABLEMENT"};
-	uint64_t features_enabled;
-	uint32_t feature_mask[2];
-	int i;
-	int ret = 0;
-	int size = 0;
-
-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-	PP_ASSERT_WITH_CODE(!ret,
-			"[GetPPfeatureStatus] Failed to get enabled smc features!",
-			return ret);
-	features_enabled = (uint64_t)feature_mask[0] |
-			   (uint64_t)feature_mask[1] << 32;
-
-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-	size += sprintf(buf + size, "%-19s %-22s %s\n",
-				output_title[0],
-				output_title[1],
-				output_title[2]);
-	for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-					ppfeature_name[i],
-					1ULL << i,
-					(features_enabled & (1ULL << i)) ? "Y" : "N");
-	}
-
-	return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-				      bool enabled,
-				      uint64_t feature_masks)
-{
-	struct smu_feature *feature = &smu->smu_feature;
-	uint32_t feature_low, feature_high;
-	uint32_t feature_mask[2];
-	int ret = 0;
-
-	feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-	feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-	if (enabled) {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-	} else {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-	}
-
-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-	if (ret)
-		return ret;
-
-	mutex_lock(&feature->mutex);
-	bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-		    feature->feature_num);
-	mutex_unlock(&feature->mutex);
-
-	return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-				       uint64_t new_ppfeature_masks)
-{
-	uint64_t features_enabled;
-	uint32_t feature_mask[2];
-	uint64_t features_to_enable;
-	uint64_t features_to_disable;
-	int ret = 0;
-
-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-	PP_ASSERT_WITH_CODE(!ret,
-			"[SetPPfeatureStatus] Failed to get enabled smc features!",
-			return ret);
-	features_enabled = (uint64_t)feature_mask[0] |
-			   (uint64_t)feature_mask[1] << 32;
-
-	features_to_disable =
-		features_enabled & ~new_ppfeature_masks;
-	features_to_enable =
-		~features_enabled & new_ppfeature_masks;
-
-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-	if (features_to_disable) {
-		ret = navi10_enable_smc_features(smu, false, features_to_disable);
-		PP_ASSERT_WITH_CODE(!ret,
-				"[SetPPfeatureStatus] Failed to disable smc features!",
-				return ret);
-	}
-
-	if (features_to_enable) {
-		ret = navi10_enable_smc_features(smu, true, features_to_enable);
-		PP_ASSERT_WITH_CODE(!ret,
-				"[SetPPfeatureStatus] Failed to enable smc features!",
-				return ret);
-	}
-
-	return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
 	struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
 	.set_watermarks_table = navi10_set_watermarks_table,
 	.read_sensor = navi10_read_sensor,
 	.get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-	.get_ppfeature_status = navi10_get_ppfeature_status,
-	.set_ppfeature_status = navi10_set_ppfeature_status,
 	.set_performance_level = navi10_set_performance_level,
 	.get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
 	return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }
 
-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-		uint64_t *features_enabled)
-{
-	uint32_t feature_mask[2] = {0, 0};
-	int ret = 0;
-
-	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-	if (ret)
-		return ret;
-
-	*features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-			(((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-	return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-		bool enable, uint64_t feature_mask)
-{
-	uint32_t smu_features_low, smu_features_high;
-	int ret = 0;
-
-	smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-	smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-	if (enable) {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-						  smu_features_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-						  smu_features_high);
-		if (ret)
-			return ret;
-	} else {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-						  smu_features_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-						  smu_features_high);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-	static const char *ppfeature_name[] = {
-				"DPM_PREFETCHER",
-				"GFXCLK_DPM",
-				"UCLK_DPM",
-				"SOCCLK_DPM",
-				"UVD_DPM",
-				"VCE_DPM",
-				"ULV",
-				"MP0CLK_DPM",
-				"LINK_DPM",
-				"DCEFCLK_DPM",
-				"GFXCLK_DS",
-				"SOCCLK_DS",
-				"LCLK_DS",
-				"PPT",
-				"TDC",
-				"THERMAL",
-				"GFX_PER_CU_CG",
-				"RM",
-				"DCEFCLK_DS",
-				"ACDC",
-				"VR0HOT",
-				"VR1HOT",
-				"FW_CTF",
-				"LED_DISPLAY",
-				"FAN_CONTROL",
-				"GFX_EDC",
-				"GFXOFF",
-				"CG",
-				"FCLK_DPM",
-				"FCLK_DS",
-				"MP1CLK_DS",
-				"MP0CLK_DS",
-				"XGMI",
-				"ECC"};
-	static const char *output_title[] = {
-				"FEATURES",
-				"BITMASK",
-				"ENABLEMENT"};
-	uint64_t features_enabled;
-	int i;
-	int ret = 0;
-	int size = 0;
-
-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-	if (ret)
-		return ret;
-
-	size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-	size += sprintf(buf + size, "%-19s %-22s %s\n",
-				output_title[0],
-				output_title[1],
-				output_title[2]);
-	for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-		size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-					ppfeature_name[i],
-					1ULL << i,
-					(features_enabled & (1ULL << i)) ? "Y" : "N");
-	}
-
-	return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-	uint64_t features_enabled;
-	uint64_t features_to_enable;
-	uint64_t features_to_disable;
-	int ret = 0;
-
-	if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-		return -EINVAL;
-
-	ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-	if (ret)
-		return ret;
-
-	features_to_disable =
-		features_enabled & ~new_ppfeature_masks;
-	features_to_enable =
-		~features_enabled & new_ppfeature_masks;
-
-	pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-	pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-	if (features_to_disable) {
-		ret = vega20_enable_smc_features(smu, false, features_to_disable);
-		if (ret)
-			return ret;
-	}
-
-	if (features_to_enable) {
-		ret = vega20_enable_smc_features(smu, true, features_to_enable);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
 	int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
 	.force_dpm_limit_value = vega20_force_dpm_limit_value,
 	.unforce_dpm_levels = vega20_unforce_dpm_levels,
 	.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-	.set_ppfeature_status = vega20_set_ppfeature_status,
-	.get_ppfeature_status = vega20_get_ppfeature_status,
 	.is_dpm_running = vega20_is_dpm_running,
 	.set_thermal_fan_table = vega20_set_thermal_fan_table,
 	.get_fan_speed_percent = vega20_get_fan_speed_percent,
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2019-07-25  5:11   ` [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu Wang, Kevin(Yang)
@ 2019-07-25  6:36   ` Feng, Kenneth
  2019-07-25  9:31   ` Quan, Evan
  5 siblings, 0 replies; 23+ messages in thread
From: Feng, Kenneth @ 2019-07-25  6:36 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>



-----Original Message-----
From: Wang, Kevin(Yang) 
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
Subject: [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h

move some enum type (message, feature, clock) to smu_types.h.
these types is too long in amdgpu_smu.h, and not clearly.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 186 +---------------
 drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 210 ++++++++++++++++++
 2 files changed, 211 insertions(+), 185 deletions(-)  create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu_types.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 33d2d75ba903..397040a4d1b4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -26,6 +26,7 @@
 #include "kgd_pp_interface.h"
 #include "dm_pp_interface.h"
 #include "dm_pp_smu.h"
+#include "smu_types.h"
 
 #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
@@ -150,134 +151,6 @@ struct smu_power_state {
 	struct smu_hw_power_state                     hardware;
 };
 
-enum smu_message_type
-{
-	SMU_MSG_TestMessage = 0,
-	SMU_MSG_GetSmuVersion,
-	SMU_MSG_GetDriverIfVersion,
-	SMU_MSG_SetAllowedFeaturesMaskLow,
-	SMU_MSG_SetAllowedFeaturesMaskHigh,
-	SMU_MSG_EnableAllSmuFeatures,
-	SMU_MSG_DisableAllSmuFeatures,
-	SMU_MSG_EnableSmuFeaturesLow,
-	SMU_MSG_EnableSmuFeaturesHigh,
-	SMU_MSG_DisableSmuFeaturesLow,
-	SMU_MSG_DisableSmuFeaturesHigh,
-	SMU_MSG_GetEnabledSmuFeaturesLow,
-	SMU_MSG_GetEnabledSmuFeaturesHigh,
-	SMU_MSG_SetWorkloadMask,
-	SMU_MSG_SetPptLimit,
-	SMU_MSG_SetDriverDramAddrHigh,
-	SMU_MSG_SetDriverDramAddrLow,
-	SMU_MSG_SetToolsDramAddrHigh,
-	SMU_MSG_SetToolsDramAddrLow,
-	SMU_MSG_TransferTableSmu2Dram,
-	SMU_MSG_TransferTableDram2Smu,
-	SMU_MSG_UseDefaultPPTable,
-	SMU_MSG_UseBackupPPTable,
-	SMU_MSG_RunBtc,
-	SMU_MSG_RequestI2CBus,
-	SMU_MSG_ReleaseI2CBus,
-	SMU_MSG_SetFloorSocVoltage,
-	SMU_MSG_SoftReset,
-	SMU_MSG_StartBacoMonitor,
-	SMU_MSG_CancelBacoMonitor,
-	SMU_MSG_EnterBaco,
-	SMU_MSG_SetSoftMinByFreq,
-	SMU_MSG_SetSoftMaxByFreq,
-	SMU_MSG_SetHardMinByFreq,
-	SMU_MSG_SetHardMaxByFreq,
-	SMU_MSG_GetMinDpmFreq,
-	SMU_MSG_GetMaxDpmFreq,
-	SMU_MSG_GetDpmFreqByIndex,
-	SMU_MSG_GetDpmClockFreq,
-	SMU_MSG_GetSsVoltageByDpm,
-	SMU_MSG_SetMemoryChannelConfig,
-	SMU_MSG_SetGeminiMode,
-	SMU_MSG_SetGeminiApertureHigh,
-	SMU_MSG_SetGeminiApertureLow,
-	SMU_MSG_SetMinLinkDpmByIndex,
-	SMU_MSG_OverridePcieParameters,
-	SMU_MSG_OverDriveSetPercentage,
-	SMU_MSG_SetMinDeepSleepDcefclk,
-	SMU_MSG_ReenableAcDcInterrupt,
-	SMU_MSG_NotifyPowerSource,
-	SMU_MSG_SetUclkFastSwitch,
-	SMU_MSG_SetUclkDownHyst,
-	SMU_MSG_GfxDeviceDriverReset,
-	SMU_MSG_GetCurrentRpm,
-	SMU_MSG_SetVideoFps,
-	SMU_MSG_SetTjMax,
-	SMU_MSG_SetFanTemperatureTarget,
-	SMU_MSG_PrepareMp1ForUnload,
-	SMU_MSG_DramLogSetDramAddrHigh,
-	SMU_MSG_DramLogSetDramAddrLow,
-	SMU_MSG_DramLogSetDramSize,
-	SMU_MSG_SetFanMaxRpm,
-	SMU_MSG_SetFanMinPwm,
-	SMU_MSG_ConfigureGfxDidt,
-	SMU_MSG_NumOfDisplays,
-	SMU_MSG_RemoveMargins,
-	SMU_MSG_ReadSerialNumTop32,
-	SMU_MSG_ReadSerialNumBottom32,
-	SMU_MSG_SetSystemVirtualDramAddrHigh,
-	SMU_MSG_SetSystemVirtualDramAddrLow,
-	SMU_MSG_WaflTest,
-	SMU_MSG_SetFclkGfxClkRatio,
-	SMU_MSG_AllowGfxOff,
-	SMU_MSG_DisallowGfxOff,
-	SMU_MSG_GetPptLimit,
-	SMU_MSG_GetDcModeMaxDpmFreq,
-	SMU_MSG_GetDebugData,
-	SMU_MSG_SetXgmiMode,
-	SMU_MSG_RunAfllBtc,
-	SMU_MSG_ExitBaco,
-	SMU_MSG_PrepareMp1ForReset,
-	SMU_MSG_PrepareMp1ForShutdown,
-	SMU_MSG_SetMGpuFanBoostLimitRpm,
-	SMU_MSG_GetAVFSVoltageByDpm,
-	SMU_MSG_PowerUpVcn,
-	SMU_MSG_PowerDownVcn,
-	SMU_MSG_PowerUpJpeg,
-	SMU_MSG_PowerDownJpeg,
-	SMU_MSG_BacoAudioD3PME,
-	SMU_MSG_ArmD3,
-	SMU_MSG_RunGfxDcBtc,
-	SMU_MSG_RunSocDcBtc,
-	SMU_MSG_SetMemoryChannelEnable,
-	SMU_MSG_SetDfSwitchType,
-	SMU_MSG_GetVoltageByDpm,
-	SMU_MSG_GetVoltageByDpmOverdrive,
-	SMU_MSG_PowerUpVcn0,
-	SMU_MSG_PowerDownVcn01,
-	SMU_MSG_PowerUpVcn1,
-	SMU_MSG_PowerDownVcn1,
-	SMU_MSG_MAX_COUNT,
-};
-
-enum smu_clk_type
-{
-	SMU_GFXCLK,
-	SMU_VCLK,
-	SMU_DCLK,
-	SMU_ECLK,
-	SMU_SOCCLK,
-	SMU_UCLK,
-	SMU_DCEFCLK,
-	SMU_DISPCLK,
-	SMU_PIXCLK,
-	SMU_PHYCLK,
-	SMU_FCLK,
-	SMU_SCLK,
-	SMU_MCLK,
-	SMU_PCIE,
-	SMU_OD_SCLK,
-	SMU_OD_MCLK,
-	SMU_OD_VDDC_CURVE,
-	SMU_OD_RANGE,
-	SMU_CLK_COUNT,
-};
-
 enum smu_power_src_type
 {
 	SMU_POWER_SOURCE_AC,
@@ -285,63 +158,6 @@ enum smu_power_src_type
 	SMU_POWER_SOURCE_COUNT,
 };
 
-enum smu_feature_mask
-{
-	SMU_FEATURE_DPM_PREFETCHER_BIT,
-	SMU_FEATURE_DPM_GFXCLK_BIT,
-	SMU_FEATURE_DPM_UCLK_BIT,
-	SMU_FEATURE_DPM_SOCCLK_BIT,
-	SMU_FEATURE_DPM_UVD_BIT,
-	SMU_FEATURE_DPM_VCE_BIT,
-	SMU_FEATURE_ULV_BIT,
-	SMU_FEATURE_DPM_MP0CLK_BIT,
-	SMU_FEATURE_DPM_LINK_BIT,
-	SMU_FEATURE_DPM_DCEFCLK_BIT,
-	SMU_FEATURE_DS_GFXCLK_BIT,
-	SMU_FEATURE_DS_SOCCLK_BIT,
-	SMU_FEATURE_DS_LCLK_BIT,
-	SMU_FEATURE_PPT_BIT,
-	SMU_FEATURE_TDC_BIT,
-	SMU_FEATURE_THERMAL_BIT,
-	SMU_FEATURE_GFX_PER_CU_CG_BIT,
-	SMU_FEATURE_RM_BIT,
-	SMU_FEATURE_DS_DCEFCLK_BIT,
-	SMU_FEATURE_ACDC_BIT,
-	SMU_FEATURE_VR0HOT_BIT,
-	SMU_FEATURE_VR1HOT_BIT,
-	SMU_FEATURE_FW_CTF_BIT,
-	SMU_FEATURE_LED_DISPLAY_BIT,
-	SMU_FEATURE_FAN_CONTROL_BIT,
-	SMU_FEATURE_GFX_EDC_BIT,
-	SMU_FEATURE_GFXOFF_BIT,
-	SMU_FEATURE_CG_BIT,
-	SMU_FEATURE_DPM_FCLK_BIT,
-	SMU_FEATURE_DS_FCLK_BIT,
-	SMU_FEATURE_DS_MP1CLK_BIT,
-	SMU_FEATURE_DS_MP0CLK_BIT,
-	SMU_FEATURE_XGMI_BIT,
-	SMU_FEATURE_DPM_GFX_PACE_BIT,
-	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
-	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
-	SMU_FEATURE_DS_UCLK_BIT,
-	SMU_FEATURE_GFX_ULV_BIT,
-	SMU_FEATURE_FW_DSTATE_BIT,
-	SMU_FEATURE_BACO_BIT,
-	SMU_FEATURE_VCN_PG_BIT,
-	SMU_FEATURE_JPEG_PG_BIT,
-	SMU_FEATURE_USB_PG_BIT,
-	SMU_FEATURE_RSMU_SMN_CG_BIT,
-	SMU_FEATURE_APCC_PLUS_BIT,
-	SMU_FEATURE_GTHR_BIT,
-	SMU_FEATURE_GFX_DCS_BIT,
-	SMU_FEATURE_GFX_SS_BIT,
-	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
-	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
-	SMU_FEATURE_MMHUB_PG_BIT,
-	SMU_FEATURE_ATHUB_PG_BIT,
-	SMU_FEATURE_COUNT,
-};
-
 enum smu_memory_pool_size
 {
     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
new file mode 100644
index 000000000000..29d14c162417
--- /dev/null
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person 
+obtaining a
+ * copy of this software and associated documentation files (the 
+"Software"),
+ * to deal in the Software without restriction, including without 
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute, 
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom 
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be 
+included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT 
+SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, 
+DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 
+OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __SMU_TYPES_H__
+#define __SMU_TYPES_H__
+
+
+enum smu_message_type {
+	SMU_MSG_TestMessage = 0,
+	SMU_MSG_GetSmuVersion,
+	SMU_MSG_GetDriverIfVersion,
+	SMU_MSG_SetAllowedFeaturesMaskLow,
+	SMU_MSG_SetAllowedFeaturesMaskHigh,
+	SMU_MSG_EnableAllSmuFeatures,
+	SMU_MSG_DisableAllSmuFeatures,
+	SMU_MSG_EnableSmuFeaturesLow,
+	SMU_MSG_EnableSmuFeaturesHigh,
+	SMU_MSG_DisableSmuFeaturesLow,
+	SMU_MSG_DisableSmuFeaturesHigh,
+	SMU_MSG_GetEnabledSmuFeaturesLow,
+	SMU_MSG_GetEnabledSmuFeaturesHigh,
+	SMU_MSG_SetWorkloadMask,
+	SMU_MSG_SetPptLimit,
+	SMU_MSG_SetDriverDramAddrHigh,
+	SMU_MSG_SetDriverDramAddrLow,
+	SMU_MSG_SetToolsDramAddrHigh,
+	SMU_MSG_SetToolsDramAddrLow,
+	SMU_MSG_TransferTableSmu2Dram,
+	SMU_MSG_TransferTableDram2Smu,
+	SMU_MSG_UseDefaultPPTable,
+	SMU_MSG_UseBackupPPTable,
+	SMU_MSG_RunBtc,
+	SMU_MSG_RequestI2CBus,
+	SMU_MSG_ReleaseI2CBus,
+	SMU_MSG_SetFloorSocVoltage,
+	SMU_MSG_SoftReset,
+	SMU_MSG_StartBacoMonitor,
+	SMU_MSG_CancelBacoMonitor,
+	SMU_MSG_EnterBaco,
+	SMU_MSG_SetSoftMinByFreq,
+	SMU_MSG_SetSoftMaxByFreq,
+	SMU_MSG_SetHardMinByFreq,
+	SMU_MSG_SetHardMaxByFreq,
+	SMU_MSG_GetMinDpmFreq,
+	SMU_MSG_GetMaxDpmFreq,
+	SMU_MSG_GetDpmFreqByIndex,
+	SMU_MSG_GetDpmClockFreq,
+	SMU_MSG_GetSsVoltageByDpm,
+	SMU_MSG_SetMemoryChannelConfig,
+	SMU_MSG_SetGeminiMode,
+	SMU_MSG_SetGeminiApertureHigh,
+	SMU_MSG_SetGeminiApertureLow,
+	SMU_MSG_SetMinLinkDpmByIndex,
+	SMU_MSG_OverridePcieParameters,
+	SMU_MSG_OverDriveSetPercentage,
+	SMU_MSG_SetMinDeepSleepDcefclk,
+	SMU_MSG_ReenableAcDcInterrupt,
+	SMU_MSG_NotifyPowerSource,
+	SMU_MSG_SetUclkFastSwitch,
+	SMU_MSG_SetUclkDownHyst,
+	SMU_MSG_GfxDeviceDriverReset,
+	SMU_MSG_GetCurrentRpm,
+	SMU_MSG_SetVideoFps,
+	SMU_MSG_SetTjMax,
+	SMU_MSG_SetFanTemperatureTarget,
+	SMU_MSG_PrepareMp1ForUnload,
+	SMU_MSG_DramLogSetDramAddrHigh,
+	SMU_MSG_DramLogSetDramAddrLow,
+	SMU_MSG_DramLogSetDramSize,
+	SMU_MSG_SetFanMaxRpm,
+	SMU_MSG_SetFanMinPwm,
+	SMU_MSG_ConfigureGfxDidt,
+	SMU_MSG_NumOfDisplays,
+	SMU_MSG_RemoveMargins,
+	SMU_MSG_ReadSerialNumTop32,
+	SMU_MSG_ReadSerialNumBottom32,
+	SMU_MSG_SetSystemVirtualDramAddrHigh,
+	SMU_MSG_SetSystemVirtualDramAddrLow,
+	SMU_MSG_WaflTest,
+	SMU_MSG_SetFclkGfxClkRatio,
+	SMU_MSG_AllowGfxOff,
+	SMU_MSG_DisallowGfxOff,
+	SMU_MSG_GetPptLimit,
+	SMU_MSG_GetDcModeMaxDpmFreq,
+	SMU_MSG_GetDebugData,
+	SMU_MSG_SetXgmiMode,
+	SMU_MSG_RunAfllBtc,
+	SMU_MSG_ExitBaco,
+	SMU_MSG_PrepareMp1ForReset,
+	SMU_MSG_PrepareMp1ForShutdown,
+	SMU_MSG_SetMGpuFanBoostLimitRpm,
+	SMU_MSG_GetAVFSVoltageByDpm,
+	SMU_MSG_PowerUpVcn,
+	SMU_MSG_PowerDownVcn,
+	SMU_MSG_PowerUpJpeg,
+	SMU_MSG_PowerDownJpeg,
+	SMU_MSG_BacoAudioD3PME,
+	SMU_MSG_ArmD3,
+	SMU_MSG_RunGfxDcBtc,
+	SMU_MSG_RunSocDcBtc,
+	SMU_MSG_SetMemoryChannelEnable,
+	SMU_MSG_SetDfSwitchType,
+	SMU_MSG_GetVoltageByDpm,
+	SMU_MSG_GetVoltageByDpmOverdrive,
+	SMU_MSG_PowerUpVcn0,
+	SMU_MSG_PowerDownVcn01,
+	SMU_MSG_PowerUpVcn1,
+	SMU_MSG_PowerDownVcn1,
+	SMU_MSG_MAX_COUNT,
+};
+
+enum smu_clk_type {
+	SMU_GFXCLK,
+	SMU_VCLK,
+	SMU_DCLK,
+	SMU_ECLK,
+	SMU_SOCCLK,
+	SMU_UCLK,
+	SMU_DCEFCLK,
+	SMU_DISPCLK,
+	SMU_PIXCLK,
+	SMU_PHYCLK,
+	SMU_FCLK,
+	SMU_SCLK,
+	SMU_MCLK,
+	SMU_PCIE,
+	SMU_OD_SCLK,
+	SMU_OD_MCLK,
+	SMU_OD_VDDC_CURVE,
+	SMU_OD_RANGE,
+	SMU_CLK_COUNT,
+};
+
+enum smu_feature_mask {
+	SMU_FEATURE_DPM_PREFETCHER_BIT,
+	SMU_FEATURE_DPM_GFXCLK_BIT,
+	SMU_FEATURE_DPM_UCLK_BIT,
+	SMU_FEATURE_DPM_SOCCLK_BIT,
+	SMU_FEATURE_DPM_UVD_BIT,
+	SMU_FEATURE_DPM_VCE_BIT,
+	SMU_FEATURE_ULV_BIT,
+	SMU_FEATURE_DPM_MP0CLK_BIT,
+	SMU_FEATURE_DPM_LINK_BIT,
+	SMU_FEATURE_DPM_DCEFCLK_BIT,
+	SMU_FEATURE_DS_GFXCLK_BIT,
+	SMU_FEATURE_DS_SOCCLK_BIT,
+	SMU_FEATURE_DS_LCLK_BIT,
+	SMU_FEATURE_PPT_BIT,
+	SMU_FEATURE_TDC_BIT,
+	SMU_FEATURE_THERMAL_BIT,
+	SMU_FEATURE_GFX_PER_CU_CG_BIT,
+	SMU_FEATURE_RM_BIT,
+	SMU_FEATURE_DS_DCEFCLK_BIT,
+	SMU_FEATURE_ACDC_BIT,
+	SMU_FEATURE_VR0HOT_BIT,
+	SMU_FEATURE_VR1HOT_BIT,
+	SMU_FEATURE_FW_CTF_BIT,
+	SMU_FEATURE_LED_DISPLAY_BIT,
+	SMU_FEATURE_FAN_CONTROL_BIT,
+	SMU_FEATURE_GFX_EDC_BIT,
+	SMU_FEATURE_GFXOFF_BIT,
+	SMU_FEATURE_CG_BIT,
+	SMU_FEATURE_DPM_FCLK_BIT,
+	SMU_FEATURE_DS_FCLK_BIT,
+	SMU_FEATURE_DS_MP1CLK_BIT,
+	SMU_FEATURE_DS_MP0CLK_BIT,
+	SMU_FEATURE_XGMI_BIT,
+	SMU_FEATURE_DPM_GFX_PACE_BIT,
+	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
+	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
+	SMU_FEATURE_DS_UCLK_BIT,
+	SMU_FEATURE_GFX_ULV_BIT,
+	SMU_FEATURE_FW_DSTATE_BIT,
+	SMU_FEATURE_BACO_BIT,
+	SMU_FEATURE_VCN_PG_BIT,
+	SMU_FEATURE_JPEG_PG_BIT,
+	SMU_FEATURE_USB_PG_BIT,
+	SMU_FEATURE_RSMU_SMN_CG_BIT,
+	SMU_FEATURE_APCC_PLUS_BIT,
+	SMU_FEATURE_GTHR_BIT,
+	SMU_FEATURE_GFX_DCS_BIT,
+	SMU_FEATURE_GFX_SS_BIT,
+	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
+	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
+	SMU_FEATURE_MMHUB_PG_BIT,
+	SMU_FEATURE_ATHUB_PG_BIT,
+	SMU_FEATURE_COUNT,
+};
+
+#endif
+
--
2.22.0

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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 2/5] drm/amd/powerplay: add smu message name support
       [not found]     ` <20190725051057.28862-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  7:44       ` Feng, Kenneth
  0 siblings, 0 replies; 23+ messages in thread
From: Feng, Kenneth @ 2019-07-25  7:44 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray

A little difficult for me to understand, but the logic is ok.
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>

-----Original Message-----
From: Wang, Kevin(Yang) 
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
Subject: [PATCH 2/5] drm/amd/powerplay: add smu message name support

add smu_get_message_name support in smu.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 ++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
 drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 205 +++++++++---------
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     |  12 +-
 4 files changed, 124 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 6935a00cd389..4604b6af56bb 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -29,6 +29,19 @@
 #include "smu_v11_0.h"
 #include "atom.h"
 
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(type)	#type
+static const char* __smu_message_names[] = {
+	SMU_MESSAGE_TYPES
+};
+
+const char *smu_get_message_name(struct smu_context *smu, enum 
+smu_message_type type) {
+	if (type < 0 || type > SMU_MSG_MAX_COUNT)
+		return "unknow smu message";
+	return __smu_message_names[type];
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)  {
 	int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 397040a4d1b4..035f857922ec 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -804,5 +804,6 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);  int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);  int smu_set_display_count(struct smu_context *smu, uint32_t count);  bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+const char *smu_get_message_name(struct smu_context *smu, enum 
+smu_message_type type);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
index 29d14c162417..d42e3424e704 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
@@ -23,108 +23,112 @@
 #ifndef __SMU_TYPES_H__
 #define __SMU_TYPES_H__
 
+#define SMU_MESSAGE_TYPES			      \
+       __SMU_DUMMY_MAP(TestMessage),		      \
+       __SMU_DUMMY_MAP(GetSmuVersion),                \
+       __SMU_DUMMY_MAP(GetDriverIfVersion),           \
+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskLow),    \
+       __SMU_DUMMY_MAP(SetAllowedFeaturesMaskHigh),   \
+       __SMU_DUMMY_MAP(EnableAllSmuFeatures),         \
+       __SMU_DUMMY_MAP(DisableAllSmuFeatures),        \
+       __SMU_DUMMY_MAP(EnableSmuFeaturesLow),         \
+       __SMU_DUMMY_MAP(EnableSmuFeaturesHigh),        \
+       __SMU_DUMMY_MAP(DisableSmuFeaturesLow),        \
+       __SMU_DUMMY_MAP(DisableSmuFeaturesHigh),       \
+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesLow),     \
+       __SMU_DUMMY_MAP(GetEnabledSmuFeaturesHigh),    \
+       __SMU_DUMMY_MAP(SetWorkloadMask),              \
+       __SMU_DUMMY_MAP(SetPptLimit),                  \
+       __SMU_DUMMY_MAP(SetDriverDramAddrHigh),        \
+       __SMU_DUMMY_MAP(SetDriverDramAddrLow),         \
+       __SMU_DUMMY_MAP(SetToolsDramAddrHigh),         \
+       __SMU_DUMMY_MAP(SetToolsDramAddrLow),          \
+       __SMU_DUMMY_MAP(TransferTableSmu2Dram),        \
+       __SMU_DUMMY_MAP(TransferTableDram2Smu),        \
+       __SMU_DUMMY_MAP(UseDefaultPPTable),            \
+       __SMU_DUMMY_MAP(UseBackupPPTable),             \
+       __SMU_DUMMY_MAP(RunBtc),                       \
+       __SMU_DUMMY_MAP(RequestI2CBus),                \
+       __SMU_DUMMY_MAP(ReleaseI2CBus),                \
+       __SMU_DUMMY_MAP(SetFloorSocVoltage),           \
+       __SMU_DUMMY_MAP(SoftReset),                    \
+       __SMU_DUMMY_MAP(StartBacoMonitor),             \
+       __SMU_DUMMY_MAP(CancelBacoMonitor),            \
+       __SMU_DUMMY_MAP(EnterBaco),                    \
+       __SMU_DUMMY_MAP(SetSoftMinByFreq),             \
+       __SMU_DUMMY_MAP(SetSoftMaxByFreq),             \
+       __SMU_DUMMY_MAP(SetHardMinByFreq),             \
+       __SMU_DUMMY_MAP(SetHardMaxByFreq),             \
+       __SMU_DUMMY_MAP(GetMinDpmFreq),                \
+       __SMU_DUMMY_MAP(GetMaxDpmFreq),                \
+       __SMU_DUMMY_MAP(GetDpmFreqByIndex),            \
+       __SMU_DUMMY_MAP(GetDpmClockFreq),              \
+       __SMU_DUMMY_MAP(GetSsVoltageByDpm),            \
+       __SMU_DUMMY_MAP(SetMemoryChannelConfig),       \
+       __SMU_DUMMY_MAP(SetGeminiMode),                \
+       __SMU_DUMMY_MAP(SetGeminiApertureHigh),        \
+       __SMU_DUMMY_MAP(SetGeminiApertureLow),         \
+       __SMU_DUMMY_MAP(SetMinLinkDpmByIndex),         \
+       __SMU_DUMMY_MAP(OverridePcieParameters),       \
+       __SMU_DUMMY_MAP(OverDriveSetPercentage),       \
+       __SMU_DUMMY_MAP(SetMinDeepSleepDcefclk),       \
+       __SMU_DUMMY_MAP(ReenableAcDcInterrupt),        \
+       __SMU_DUMMY_MAP(NotifyPowerSource),            \
+       __SMU_DUMMY_MAP(SetUclkFastSwitch),            \
+       __SMU_DUMMY_MAP(SetUclkDownHyst),              \
+       __SMU_DUMMY_MAP(GfxDeviceDriverReset),         \
+       __SMU_DUMMY_MAP(GetCurrentRpm),                \
+       __SMU_DUMMY_MAP(SetVideoFps),                  \
+       __SMU_DUMMY_MAP(SetTjMax),                     \
+       __SMU_DUMMY_MAP(SetFanTemperatureTarget),      \
+       __SMU_DUMMY_MAP(PrepareMp1ForUnload),          \
+       __SMU_DUMMY_MAP(DramLogSetDramAddrHigh),       \
+       __SMU_DUMMY_MAP(DramLogSetDramAddrLow),        \
+       __SMU_DUMMY_MAP(DramLogSetDramSize),           \
+       __SMU_DUMMY_MAP(SetFanMaxRpm),                 \
+       __SMU_DUMMY_MAP(SetFanMinPwm),                 \
+       __SMU_DUMMY_MAP(ConfigureGfxDidt),             \
+       __SMU_DUMMY_MAP(NumOfDisplays),                \
+       __SMU_DUMMY_MAP(RemoveMargins),                \
+       __SMU_DUMMY_MAP(ReadSerialNumTop32),           \
+       __SMU_DUMMY_MAP(ReadSerialNumBottom32),        \
+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrHigh), \
+       __SMU_DUMMY_MAP(SetSystemVirtualDramAddrLow),  \
+       __SMU_DUMMY_MAP(WaflTest),                     \
+       __SMU_DUMMY_MAP(SetFclkGfxClkRatio),           \
+       __SMU_DUMMY_MAP(AllowGfxOff),                  \
+       __SMU_DUMMY_MAP(DisallowGfxOff),               \
+       __SMU_DUMMY_MAP(GetPptLimit),                  \
+       __SMU_DUMMY_MAP(GetDcModeMaxDpmFreq),          \
+       __SMU_DUMMY_MAP(GetDebugData),                 \
+       __SMU_DUMMY_MAP(SetXgmiMode),                  \
+       __SMU_DUMMY_MAP(RunAfllBtc),                   \
+       __SMU_DUMMY_MAP(ExitBaco),                     \
+       __SMU_DUMMY_MAP(PrepareMp1ForReset),           \
+       __SMU_DUMMY_MAP(PrepareMp1ForShutdown),        \
+       __SMU_DUMMY_MAP(SetMGpuFanBoostLimitRpm),      \
+       __SMU_DUMMY_MAP(GetAVFSVoltageByDpm),          \
+       __SMU_DUMMY_MAP(PowerUpVcn),                   \
+       __SMU_DUMMY_MAP(PowerDownVcn),                 \
+       __SMU_DUMMY_MAP(PowerUpJpeg),                  \
+       __SMU_DUMMY_MAP(PowerDownJpeg),                \
+       __SMU_DUMMY_MAP(BacoAudioD3PME),               \
+       __SMU_DUMMY_MAP(ArmD3),                        \
+       __SMU_DUMMY_MAP(RunGfxDcBtc),                  \
+       __SMU_DUMMY_MAP(RunSocDcBtc),                  \
+       __SMU_DUMMY_MAP(SetMemoryChannelEnable),       \
+       __SMU_DUMMY_MAP(SetDfSwitchType),              \
+       __SMU_DUMMY_MAP(GetVoltageByDpm),              \
+       __SMU_DUMMY_MAP(GetVoltageByDpmOverdrive),     \
+       __SMU_DUMMY_MAP(PowerUpVcn0),                  \
+       __SMU_DUMMY_MAP(PowerDownVcn01),               \
+       __SMU_DUMMY_MAP(PowerUpVcn1),                  \
+       __SMU_DUMMY_MAP(PowerDownVcn1),                \
 
+#undef __SMU_DUMMY_MAP
+#define __SMU_DUMMY_MAP(type)	SMU_MSG_##type
 enum smu_message_type {
-	SMU_MSG_TestMessage = 0,
-	SMU_MSG_GetSmuVersion,
-	SMU_MSG_GetDriverIfVersion,
-	SMU_MSG_SetAllowedFeaturesMaskLow,
-	SMU_MSG_SetAllowedFeaturesMaskHigh,
-	SMU_MSG_EnableAllSmuFeatures,
-	SMU_MSG_DisableAllSmuFeatures,
-	SMU_MSG_EnableSmuFeaturesLow,
-	SMU_MSG_EnableSmuFeaturesHigh,
-	SMU_MSG_DisableSmuFeaturesLow,
-	SMU_MSG_DisableSmuFeaturesHigh,
-	SMU_MSG_GetEnabledSmuFeaturesLow,
-	SMU_MSG_GetEnabledSmuFeaturesHigh,
-	SMU_MSG_SetWorkloadMask,
-	SMU_MSG_SetPptLimit,
-	SMU_MSG_SetDriverDramAddrHigh,
-	SMU_MSG_SetDriverDramAddrLow,
-	SMU_MSG_SetToolsDramAddrHigh,
-	SMU_MSG_SetToolsDramAddrLow,
-	SMU_MSG_TransferTableSmu2Dram,
-	SMU_MSG_TransferTableDram2Smu,
-	SMU_MSG_UseDefaultPPTable,
-	SMU_MSG_UseBackupPPTable,
-	SMU_MSG_RunBtc,
-	SMU_MSG_RequestI2CBus,
-	SMU_MSG_ReleaseI2CBus,
-	SMU_MSG_SetFloorSocVoltage,
-	SMU_MSG_SoftReset,
-	SMU_MSG_StartBacoMonitor,
-	SMU_MSG_CancelBacoMonitor,
-	SMU_MSG_EnterBaco,
-	SMU_MSG_SetSoftMinByFreq,
-	SMU_MSG_SetSoftMaxByFreq,
-	SMU_MSG_SetHardMinByFreq,
-	SMU_MSG_SetHardMaxByFreq,
-	SMU_MSG_GetMinDpmFreq,
-	SMU_MSG_GetMaxDpmFreq,
-	SMU_MSG_GetDpmFreqByIndex,
-	SMU_MSG_GetDpmClockFreq,
-	SMU_MSG_GetSsVoltageByDpm,
-	SMU_MSG_SetMemoryChannelConfig,
-	SMU_MSG_SetGeminiMode,
-	SMU_MSG_SetGeminiApertureHigh,
-	SMU_MSG_SetGeminiApertureLow,
-	SMU_MSG_SetMinLinkDpmByIndex,
-	SMU_MSG_OverridePcieParameters,
-	SMU_MSG_OverDriveSetPercentage,
-	SMU_MSG_SetMinDeepSleepDcefclk,
-	SMU_MSG_ReenableAcDcInterrupt,
-	SMU_MSG_NotifyPowerSource,
-	SMU_MSG_SetUclkFastSwitch,
-	SMU_MSG_SetUclkDownHyst,
-	SMU_MSG_GfxDeviceDriverReset,
-	SMU_MSG_GetCurrentRpm,
-	SMU_MSG_SetVideoFps,
-	SMU_MSG_SetTjMax,
-	SMU_MSG_SetFanTemperatureTarget,
-	SMU_MSG_PrepareMp1ForUnload,
-	SMU_MSG_DramLogSetDramAddrHigh,
-	SMU_MSG_DramLogSetDramAddrLow,
-	SMU_MSG_DramLogSetDramSize,
-	SMU_MSG_SetFanMaxRpm,
-	SMU_MSG_SetFanMinPwm,
-	SMU_MSG_ConfigureGfxDidt,
-	SMU_MSG_NumOfDisplays,
-	SMU_MSG_RemoveMargins,
-	SMU_MSG_ReadSerialNumTop32,
-	SMU_MSG_ReadSerialNumBottom32,
-	SMU_MSG_SetSystemVirtualDramAddrHigh,
-	SMU_MSG_SetSystemVirtualDramAddrLow,
-	SMU_MSG_WaflTest,
-	SMU_MSG_SetFclkGfxClkRatio,
-	SMU_MSG_AllowGfxOff,
-	SMU_MSG_DisallowGfxOff,
-	SMU_MSG_GetPptLimit,
-	SMU_MSG_GetDcModeMaxDpmFreq,
-	SMU_MSG_GetDebugData,
-	SMU_MSG_SetXgmiMode,
-	SMU_MSG_RunAfllBtc,
-	SMU_MSG_ExitBaco,
-	SMU_MSG_PrepareMp1ForReset,
-	SMU_MSG_PrepareMp1ForShutdown,
-	SMU_MSG_SetMGpuFanBoostLimitRpm,
-	SMU_MSG_GetAVFSVoltageByDpm,
-	SMU_MSG_PowerUpVcn,
-	SMU_MSG_PowerDownVcn,
-	SMU_MSG_PowerUpJpeg,
-	SMU_MSG_PowerDownJpeg,
-	SMU_MSG_BacoAudioD3PME,
-	SMU_MSG_ArmD3,
-	SMU_MSG_RunGfxDcBtc,
-	SMU_MSG_RunSocDcBtc,
-	SMU_MSG_SetMemoryChannelEnable,
-	SMU_MSG_SetDfSwitchType,
-	SMU_MSG_GetVoltageByDpm,
-	SMU_MSG_GetVoltageByDpmOverdrive,
-	SMU_MSG_PowerUpVcn0,
-	SMU_MSG_PowerDownVcn01,
-	SMU_MSG_PowerUpVcn1,
-	SMU_MSG_PowerDownVcn1,
+	SMU_MESSAGE_TYPES
 	SMU_MSG_MAX_COUNT,
 };
 
@@ -207,4 +211,3 @@ enum smu_feature_mask {  };
 
 #endif
-
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 745b35a1600d..ccf6af055d03 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -102,8 +102,8 @@ static int smu_v11_0_send_msg(struct smu_context *smu, uint16_t msg)
 	ret = smu_v11_0_wait_for_response(smu);
 
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x\n", index,
-		       ret);
+		pr_err("failed send message: %10s (%d) response %#x\n",
+		       smu_get_message_name(smu, msg), index, ret);
 
 	return ret;
 
@@ -123,8 +123,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x, param 0x%x\n",
-		       index, ret, param);
+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+		       smu_get_message_name(smu, msg), index, param, ret);
 
 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
 
@@ -134,8 +134,8 @@ smu_v11_0_send_msg_with_param(struct smu_context *smu, uint16_t msg,
 
 	ret = smu_v11_0_wait_for_response(smu);
 	if (ret)
-		pr_err("Failed to send message 0x%x, response 0x%x param 0x%x\n",
-		       index, ret, param);
+		pr_err("failed send message: %10s (%d) \tparam: 0x%08x response %#x\n",
+		       smu_get_message_name(smu, msg), index, param, ret);
 
 	return ret;
 }
--
2.22.0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]     ` <20190725051057.28862-5-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  8:10       ` Wang, Kevin(Yang)
       [not found]         ` <MN2PR12MB32966C19A3EF83A1E868B25CA2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  8:10 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 27035 bytes --]

add sample data from sysfs pp_features with this patch.

print format:
index. feature name (Hardware Message ID): state

sudo find /sys -name "pp_features" -exec cat {} \;
features high: 0x00000623 low: 0xb3cdaffb
00. DPM_PREFETCHER       ( 0) : enabeld
01. DPM_GFXCLK           ( 1) : enabeld
02. DPM_UCLK             ( 3) : enabeld
03. DPM_SOCCLK           ( 4) : enabeld
04. DPM_MP0CLK           ( 5) : enabeld
05. DPM_LINK             ( 6) : enabeld
06. DPM_DCEFCLK          ( 7) : enabeld
07. DS_GFXCLK            (10) : enabeld
08. DS_SOCCLK            (11) : enabeld
09. DS_LCLK              (12) : disabled
10. PPT                  (23) : enabeld
11. TDC                  (24) : enabeld
12. THERMAL              (33) : enabeld
13. RM                   (35) : disabled
14. DS_DCEFCLK           (13) : enabeld
15. ACDC                 (28) : enabeld
16. VR0HOT               (29) : enabeld
17. VR1HOT               (30) : disabled
18. FW_CTF               (31) : enabeld
19. LED_DISPLAY          (36) : disabled
20. FAN_CONTROL          (32) : enabeld
21. GFX_EDC              (25) : enabeld
22. GFXOFF               (17) : disabled
23. DPM_GFX_PACE         ( 2) : disabled
24. MEM_VDDCI_SCALING    ( 8) : enabeld
25. MEM_MVDD_SCALING     ( 9) : enabeld
26. DS_UCLK              (14) : disabled
27. GFX_ULV              (15) : enabeld
28. FW_DSTATE            (16) : enabeld
29. BACO                 (18) : enabeld
30. VCN_PG               (19) : enabeld
31. JPEG_PG              (20) : disabled
32. USB_PG               (21) : disabled
33. RSMU_SMN_CG          (22) : enabeld
34. APCC_PLUS            (26) : disabled
35. GTHR                 (27) : disabled
36. GFX_DCS              (34) : disabled
37. GFX_SS               (37) : enabeld
38. OUT_OF_BAND_MONITOR  (38) : disabled
39. TEMP_DEPENDENT_VMIN  (39) : disabled
40. MMHUB_PG             (40) : disabled
41. ATHUB_PG             (41) : enabeld

________________________________
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0


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_______________________________________________
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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]         ` <MN2PR12MB32966C19A3EF83A1E868B25CA2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25  8:21           ` Feng, Kenneth
  2019-07-25  8:30           ` Quan, Evan
  1 sibling, 0 replies; 23+ messages in thread
From: Feng, Kenneth @ 2019-07-25  8:21 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray


[-- Attachment #1.1: Type: text/plain, Size: 28005 bytes --]

Series are Reviewed-by: Kenneth Feng <kenneth.feng-5C7GfCeVMHo@public.gmane.org<mailto:kenneth.feng-5C7GfCeVMHo@public.gmane.org>>


From: Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

add sample data from sysfs pp_features with this patch.

print format:
index. feature name (Hardware Message ID): state

sudo find /sys -name "pp_features" -exec cat {} \;
features high: 0x00000623 low: 0xb3cdaffb
00. DPM_PREFETCHER       ( 0) : enabeld
01. DPM_GFXCLK           ( 1) : enabeld
02. DPM_UCLK             ( 3) : enabeld
03. DPM_SOCCLK           ( 4) : enabeld
04. DPM_MP0CLK           ( 5) : enabeld
05. DPM_LINK             ( 6) : enabeld
06. DPM_DCEFCLK          ( 7) : enabeld
07. DS_GFXCLK            (10) : enabeld
08. DS_SOCCLK            (11) : enabeld
09. DS_LCLK              (12) : disabled
10. PPT                  (23) : enabeld
11. TDC                  (24) : enabeld
12. THERMAL              (33) : enabeld
13. RM                   (35) : disabled
14. DS_DCEFCLK           (13) : enabeld
15. ACDC                 (28) : enabeld
16. VR0HOT               (29) : enabeld
17. VR1HOT               (30) : disabled
18. FW_CTF               (31) : enabeld
19. LED_DISPLAY          (36) : disabled
20. FAN_CONTROL          (32) : enabeld
21. GFX_EDC              (25) : enabeld
22. GFXOFF               (17) : disabled
23. DPM_GFX_PACE         ( 2) : disabled
24. MEM_VDDCI_SCALING    ( 8) : enabeld
25. MEM_MVDD_SCALING     ( 9) : enabeld
26. DS_UCLK              (14) : disabled
27. GFX_ULV              (15) : enabeld
28. FW_DSTATE            (16) : enabeld
29. BACO                 (18) : enabeld
30. VCN_PG               (19) : enabeld
31. JPEG_PG              (20) : disabled
32. USB_PG               (21) : disabled
33. RSMU_SMN_CG          (22) : enabeld
34. APCC_PLUS            (26) : disabled
35. GTHR                 (27) : disabled
36. GFX_DCS              (34) : disabled
37. GFX_SS               (37) : enabeld
38. OUT_OF_BAND_MONITOR  (38) : disabled
39. TEMP_DEPENDENT_VMIN  (39) : disabled
40. MMHUB_PG             (40) : disabled
41. ATHUB_PG             (41) : enabeld

________________________________
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]         ` <MN2PR12MB32966C19A3EF83A1E868B25CA2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  2019-07-25  8:21           ` Feng, Kenneth
@ 2019-07-25  8:30           ` Quan, Evan
       [not found]             ` <MN2PR12MB334476A964852FD3B092B385E4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  1 sibling, 1 reply; 23+ messages in thread
From: Quan, Evan @ 2019-07-25  8:30 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 28085 bytes --]

To keep backward compatibility, we cannot change the sysfs file naming.
But it's a good idea to summarize these as common APIs.

Regards,
Evan
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> On Behalf Of Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

add sample data from sysfs pp_features with this patch.

print format:
index. feature name (Hardware Message ID): state

sudo find /sys -name "pp_features" -exec cat {} \;
features high: 0x00000623 low: 0xb3cdaffb
00. DPM_PREFETCHER       ( 0) : enabeld
01. DPM_GFXCLK           ( 1) : enabeld
02. DPM_UCLK             ( 3) : enabeld
03. DPM_SOCCLK           ( 4) : enabeld
04. DPM_MP0CLK           ( 5) : enabeld
05. DPM_LINK             ( 6) : enabeld
06. DPM_DCEFCLK          ( 7) : enabeld
07. DS_GFXCLK            (10) : enabeld
08. DS_SOCCLK            (11) : enabeld
09. DS_LCLK              (12) : disabled
10. PPT                  (23) : enabeld
11. TDC                  (24) : enabeld
12. THERMAL              (33) : enabeld
13. RM                   (35) : disabled
14. DS_DCEFCLK           (13) : enabeld
15. ACDC                 (28) : enabeld
16. VR0HOT               (29) : enabeld
17. VR1HOT               (30) : disabled
18. FW_CTF               (31) : enabeld
19. LED_DISPLAY          (36) : disabled
20. FAN_CONTROL          (32) : enabeld
21. GFX_EDC              (25) : enabeld
22. GFXOFF               (17) : disabled
23. DPM_GFX_PACE         ( 2) : disabled
24. MEM_VDDCI_SCALING    ( 8) : enabeld
25. MEM_MVDD_SCALING     ( 9) : enabeld
26. DS_UCLK              (14) : disabled
27. GFX_ULV              (15) : enabeld
28. FW_DSTATE            (16) : enabeld
29. BACO                 (18) : enabeld
30. VCN_PG               (19) : enabeld
31. JPEG_PG              (20) : disabled
32. USB_PG               (21) : disabled
33. RSMU_SMN_CG          (22) : enabeld
34. APCC_PLUS            (26) : disabled
35. GTHR                 (27) : disabled
36. GFX_DCS              (34) : disabled
37. GFX_SS               (37) : enabeld
38. OUT_OF_BAND_MONITOR  (38) : disabled
39. TEMP_DEPENDENT_VMIN  (39) : disabled
40. MMHUB_PG             (40) : disabled
41. ATHUB_PG             (41) : enabeld

________________________________
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0

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_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]             ` <MN2PR12MB334476A964852FD3B092B385E4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25  8:44               ` Wang, Kevin(Yang)
       [not found]                 ` <MN2PR12MB32968D539CA68CCE3E4AFFB6A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  8:44 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang,
	Hawking, Deucher, Alexander
  Cc: Huang, Ray, Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 29485 bytes --]

in fact, i don't want to change this sysfs name from "ppfeatures" to "pp_features",
but it seems that don't have same name format with other pp sysfs node.
the other powerplay sysfs name have "pp_" prefix, i think we'd better to change it name to "pp_features"

eg:
pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk  pp_force_state  pp_num_states          pp_sclk_od
pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od      pp_power_profile_mode  pp_table

@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>

Could you give us some idea about it,
Thanks.

Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 4:30 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu


To keep backward compatibility, we cannot change the sysfs file naming.

But it’s a good idea to summarize these as common APIs.



Regards,

Evan

From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> On Behalf Of Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



add sample data from sysfs pp_features with this patch.



print format:

index. feature name (Hardware Message ID): state



sudo find /sys -name "pp_features" -exec cat {} \;

features high: 0x00000623 low: 0xb3cdaffb

00. DPM_PREFETCHER       ( 0) : enabeld

01. DPM_GFXCLK           ( 1) : enabeld

02. DPM_UCLK             ( 3) : enabeld

03. DPM_SOCCLK           ( 4) : enabeld

04. DPM_MP0CLK           ( 5) : enabeld

05. DPM_LINK             ( 6) : enabeld

06. DPM_DCEFCLK          ( 7) : enabeld

07. DS_GFXCLK            (10) : enabeld

08. DS_SOCCLK            (11) : enabeld

09. DS_LCLK              (12) : disabled

10. PPT                  (23) : enabeld

11. TDC                  (24) : enabeld

12. THERMAL              (33) : enabeld

13. RM                   (35) : disabled

14. DS_DCEFCLK           (13) : enabeld

15. ACDC                 (28) : enabeld

16. VR0HOT               (29) : enabeld

17. VR1HOT               (30) : disabled

18. FW_CTF               (31) : enabeld

19. LED_DISPLAY          (36) : disabled

20. FAN_CONTROL          (32) : enabeld

21. GFX_EDC              (25) : enabeld

22. GFXOFF               (17) : disabled

23. DPM_GFX_PACE         ( 2) : disabled

24. MEM_VDDCI_SCALING    ( 8) : enabeld

25. MEM_MVDD_SCALING     ( 9) : enabeld

26. DS_UCLK              (14) : disabled

27. GFX_ULV              (15) : enabeld

28. FW_DSTATE            (16) : enabeld

29. BACO                 (18) : enabeld

30. VCN_PG               (19) : enabeld

31. JPEG_PG              (20) : disabled

32. USB_PG               (21) : disabled

33. RSMU_SMN_CG          (22) : enabeld

34. APCC_PLUS            (26) : disabled

35. GTHR                 (27) : disabled

36. GFX_DCS              (34) : disabled

37. GFX_SS               (37) : enabeld

38. OUT_OF_BAND_MONITOR  (38) : disabled

39. TEMP_DEPENDENT_VMIN  (39) : disabled

40. MMHUB_PG             (40) : disabled

41. ATHUB_PG             (41) : enabeld



________________________________

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                 ` <MN2PR12MB32968D539CA68CCE3E4AFFB6A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25  8:49                   ` Huang, Ray
       [not found]                     ` <MN2PR12MB33098222156F946AA7EABB26ECC10-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Huang, Ray @ 2019-07-25  8:49 UTC (permalink / raw)
  To: Wang, Kevin(Yang),
	Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang,
	Hawking, Deucher, Alexander
  Cc: Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 30723 bytes --]

Any other user mode tool use the "ppfeature" sysfs interface?

Thanks,
Ray

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 4:44 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Cc: Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

in fact, i don't want to change this sysfs name from "ppfeatures" to "pp_features",
but it seems that don't have same name format with other pp sysfs node.
the other powerplay sysfs name have "pp_" prefix, i think we'd better to change it name to "pp_features"

eg:
pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk  pp_force_state  pp_num_states          pp_sclk_od
pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od      pp_power_profile_mode  pp_table

@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>

Could you give us some idea about it,
Thanks.

Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 4:30 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Subject: RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu


To keep backward compatibility, we cannot change the sysfs file naming.

But it's a good idea to summarize these as common APIs.



Regards,

Evan

From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> On Behalf Of Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



add sample data from sysfs pp_features with this patch.



print format:

index. feature name (Hardware Message ID): state



sudo find /sys -name "pp_features" -exec cat {} \;

features high: 0x00000623 low: 0xb3cdaffb

00. DPM_PREFETCHER       ( 0) : enabeld

01. DPM_GFXCLK           ( 1) : enabeld

02. DPM_UCLK             ( 3) : enabeld

03. DPM_SOCCLK           ( 4) : enabeld

04. DPM_MP0CLK           ( 5) : enabeld

05. DPM_LINK             ( 6) : enabeld

06. DPM_DCEFCLK          ( 7) : enabeld

07. DS_GFXCLK            (10) : enabeld

08. DS_SOCCLK            (11) : enabeld

09. DS_LCLK              (12) : disabled

10. PPT                  (23) : enabeld

11. TDC                  (24) : enabeld

12. THERMAL              (33) : enabeld

13. RM                   (35) : disabled

14. DS_DCEFCLK           (13) : enabeld

15. ACDC                 (28) : enabeld

16. VR0HOT               (29) : enabeld

17. VR1HOT               (30) : disabled

18. FW_CTF               (31) : enabeld

19. LED_DISPLAY          (36) : disabled

20. FAN_CONTROL          (32) : enabeld

21. GFX_EDC              (25) : enabeld

22. GFXOFF               (17) : disabled

23. DPM_GFX_PACE         ( 2) : disabled

24. MEM_VDDCI_SCALING    ( 8) : enabeld

25. MEM_MVDD_SCALING     ( 9) : enabeld

26. DS_UCLK              (14) : disabled

27. GFX_ULV              (15) : enabeld

28. FW_DSTATE            (16) : enabeld

29. BACO                 (18) : enabeld

30. VCN_PG               (19) : enabeld

31. JPEG_PG              (20) : disabled

32. USB_PG               (21) : disabled

33. RSMU_SMN_CG          (22) : enabeld

34. APCC_PLUS            (26) : disabled

35. GTHR                 (27) : disabled

36. GFX_DCS              (34) : disabled

37. GFX_SS               (37) : enabeld

38. OUT_OF_BAND_MONITOR  (38) : disabled

39. TEMP_DEPENDENT_VMIN  (39) : disabled

40. MMHUB_PG             (40) : disabled

41. ATHUB_PG             (41) : enabeld



________________________________

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0

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_______________________________________________
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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* RE: [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level
       [not found]     ` <20190725051057.28862-4-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  9:29       ` Quan, Evan
       [not found]         ` <MN2PR12MB334402CBE2CB315E0205EC3BE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Quan, Evan @ 2019-07-25  9:29 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

+	feature_mask = 1UL << feature_id;
Use "ULL" here. That can guard it to be 64bits long even on 32bits target.
With that fixed, reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray
> <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 4/5] drm/amd/powerplay: move
> smu_feature_update_enable_state to up level
> 
> this function is not ip or asic related function,
> so move it to top level as public api in smu.
> 
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40
> ++++++++++++++++++-
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 ------------------
>  3 files changed, 40 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 8563f9083f4e..e881de955388 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -507,6 +507,41 @@ int smu_feature_init_dpm(struct smu_context
> *smu)
> 
>  	return ret;
>  }
> +int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled)
> +{
> +	uint32_t feature_low = 0, feature_high = 0;
> +	int ret = 0;
> +
> +	if (!smu->pm_enabled)
> +		return ret;
> +
> +	feature_low = (feature_mask >> 0 ) & 0xffffffff;
> +	feature_high = (feature_mask >> 32) & 0xffffffff;
> +
> +	if (enabled) {
> +		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> +						  feature_low);
> +		if (ret)
> +			return ret;
> +		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> +						  feature_high);
> +		if (ret)
> +			return ret;
> +
> +	} else {
> +		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> +						  feature_low);
> +		if (ret)
> +			return ret;
> +		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> +						  feature_high);
> +		if (ret)
> +			return ret;
> +
> +	}
> +
> +	return ret;
> +}
> 
>  int smu_feature_is_enabled(struct smu_context *smu, enum
> smu_feature_mask mask)
>  {
> @@ -532,6 +567,7 @@ int smu_feature_set_enabled(struct smu_context
> *smu, enum smu_feature_mask mask,
>  {
>  	struct smu_feature *feature = &smu->smu_feature;
>  	int feature_id;
> +	uint64_t feature_mask = 0;
>  	int ret = 0;
> 
>  	feature_id = smu_feature_get_index(smu, mask);
> @@ -540,8 +576,10 @@ int smu_feature_set_enabled(struct smu_context
> *smu, enum smu_feature_mask mask,
> 
>  	WARN_ON(feature_id > feature->feature_num);
> 
> +	feature_mask = 1UL << feature_id;
> +
>  	mutex_lock(&feature->mutex);
> -	ret = smu_feature_update_enable_state(smu, feature_id, enable);
> +	ret = smu_feature_update_enable_state(smu, feature_mask,
> enable);
>  	if (ret)
>  		goto failed;
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ba2385026b89..abc2644b4c07 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -479,7 +479,6 @@ struct smu_funcs
>  	int (*init_display_count)(struct smu_context *smu, uint32_t count);
>  	int (*set_allowed_mask)(struct smu_context *smu);
>  	int (*get_enabled_mask)(struct smu_context *smu, uint32_t
> *feature_mask, uint32_t num);
> -	int (*update_feature_enable_state)(struct smu_context *smu,
> uint32_t feature_id, bool enabled);
>  	int (*notify_display_change)(struct smu_context *smu);
>  	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit,
> bool def);
>  	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
> @@ -595,8 +594,6 @@ struct smu_funcs
>  	((smu)->funcs->get_enabled_mask? (smu)->funcs-
> >get_enabled_mask((smu), (mask), (num)) : 0)
>  #define smu_is_dpm_running(smu) \
>  	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs-
> >is_dpm_running((smu)) : 0)
> -#define smu_feature_update_enable_state(smu, feature_id, enabled) \
> -	((smu)->funcs->update_feature_enable_state? (smu)->funcs-
> >update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
>  #define smu_notify_display_change(smu) \
>  	((smu)->funcs->notify_display_change? (smu)->funcs-
> >notify_display_change((smu)) : 0)
>  #define smu_store_powerplay_table(smu) \
> @@ -804,6 +801,7 @@ enum amd_dpm_forced_level
> smu_get_performance_level(struct smu_context *smu);
>  int smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level);
>  int smu_set_display_count(struct smu_context *smu, uint32_t count);
>  bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum
> smu_clk_type clk_type);
> +int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum
> smu_feature_mask feature);
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index ccf6af055d03..93f3ffb8b471 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -795,44 +795,6 @@ static int smu_v11_0_init_display_count(struct
> smu_context *smu, uint32_t count)
>  	return ret;
>  }
> 
> -static int smu_v11_0_update_feature_enable_state(struct smu_context
> *smu, uint32_t feature_id, bool enabled)
> -{
> -	uint32_t feature_low = 0, feature_high = 0;
> -	int ret = 0;
> -
> -	if (!smu->pm_enabled)
> -		return ret;
> -	if (feature_id >= 0 && feature_id < 31)
> -		feature_low = (1 << feature_id);
> -	else if (feature_id > 31 && feature_id < 63)
> -		feature_high = (1 << feature_id);
> -	else
> -		return -EINVAL;
> -
> -	if (enabled) {
> -		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -						  feature_low);
> -		if (ret)
> -			return ret;
> -		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -						  feature_high);
> -		if (ret)
> -			return ret;
> -
> -	} else {
> -		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -						  feature_low);
> -		if (ret)
> -			return ret;
> -		ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -						  feature_high);
> -		if (ret)
> -			return ret;
> -
> -	}
> -
> -	return ret;
> -}
> 
>  static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
>  {
> @@ -1781,7 +1743,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
>  	.set_allowed_mask = smu_v11_0_set_allowed_mask,
>  	.get_enabled_mask = smu_v11_0_get_enabled_mask,
>  	.system_features_control = smu_v11_0_system_features_control,
> -	.update_feature_enable_state =
> smu_v11_0_update_feature_enable_state,
>  	.notify_display_change = smu_v11_0_notify_display_change,
>  	.get_power_limit = smu_v11_0_get_power_limit,
>  	.set_power_limit = smu_v11_0_set_power_limit,
> --
> 2.22.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* RE: [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h
       [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
                     ` (4 preceding siblings ...)
  2019-07-25  6:36   ` [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h Feng, Kenneth
@ 2019-07-25  9:31   ` Quan, Evan
  5 siblings, 0 replies; 23+ messages in thread
From: Quan, Evan @ 2019-07-25  9:31 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray
> <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h
> 
> move some enum type (message, feature, clock) to smu_types.h.
> these types is too long in amdgpu_smu.h, and not clearly.
> 
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    | 186 +---------------
>  drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 210
> ++++++++++++++++++
>  2 files changed, 211 insertions(+), 185 deletions(-)  create mode 100644
> drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 33d2d75ba903..397040a4d1b4 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -26,6 +26,7 @@
>  #include "kgd_pp_interface.h"
>  #include "dm_pp_interface.h"
>  #include "dm_pp_smu.h"
> +#include "smu_types.h"
> 
>  #define SMU_THERMAL_MINIMUM_ALERT_TEMP		0
>  #define SMU_THERMAL_MAXIMUM_ALERT_TEMP		255
> @@ -150,134 +151,6 @@ struct smu_power_state {
>  	struct smu_hw_power_state                     hardware;
>  };
> 
> -enum smu_message_type
> -{
> -	SMU_MSG_TestMessage = 0,
> -	SMU_MSG_GetSmuVersion,
> -	SMU_MSG_GetDriverIfVersion,
> -	SMU_MSG_SetAllowedFeaturesMaskLow,
> -	SMU_MSG_SetAllowedFeaturesMaskHigh,
> -	SMU_MSG_EnableAllSmuFeatures,
> -	SMU_MSG_DisableAllSmuFeatures,
> -	SMU_MSG_EnableSmuFeaturesLow,
> -	SMU_MSG_EnableSmuFeaturesHigh,
> -	SMU_MSG_DisableSmuFeaturesLow,
> -	SMU_MSG_DisableSmuFeaturesHigh,
> -	SMU_MSG_GetEnabledSmuFeaturesLow,
> -	SMU_MSG_GetEnabledSmuFeaturesHigh,
> -	SMU_MSG_SetWorkloadMask,
> -	SMU_MSG_SetPptLimit,
> -	SMU_MSG_SetDriverDramAddrHigh,
> -	SMU_MSG_SetDriverDramAddrLow,
> -	SMU_MSG_SetToolsDramAddrHigh,
> -	SMU_MSG_SetToolsDramAddrLow,
> -	SMU_MSG_TransferTableSmu2Dram,
> -	SMU_MSG_TransferTableDram2Smu,
> -	SMU_MSG_UseDefaultPPTable,
> -	SMU_MSG_UseBackupPPTable,
> -	SMU_MSG_RunBtc,
> -	SMU_MSG_RequestI2CBus,
> -	SMU_MSG_ReleaseI2CBus,
> -	SMU_MSG_SetFloorSocVoltage,
> -	SMU_MSG_SoftReset,
> -	SMU_MSG_StartBacoMonitor,
> -	SMU_MSG_CancelBacoMonitor,
> -	SMU_MSG_EnterBaco,
> -	SMU_MSG_SetSoftMinByFreq,
> -	SMU_MSG_SetSoftMaxByFreq,
> -	SMU_MSG_SetHardMinByFreq,
> -	SMU_MSG_SetHardMaxByFreq,
> -	SMU_MSG_GetMinDpmFreq,
> -	SMU_MSG_GetMaxDpmFreq,
> -	SMU_MSG_GetDpmFreqByIndex,
> -	SMU_MSG_GetDpmClockFreq,
> -	SMU_MSG_GetSsVoltageByDpm,
> -	SMU_MSG_SetMemoryChannelConfig,
> -	SMU_MSG_SetGeminiMode,
> -	SMU_MSG_SetGeminiApertureHigh,
> -	SMU_MSG_SetGeminiApertureLow,
> -	SMU_MSG_SetMinLinkDpmByIndex,
> -	SMU_MSG_OverridePcieParameters,
> -	SMU_MSG_OverDriveSetPercentage,
> -	SMU_MSG_SetMinDeepSleepDcefclk,
> -	SMU_MSG_ReenableAcDcInterrupt,
> -	SMU_MSG_NotifyPowerSource,
> -	SMU_MSG_SetUclkFastSwitch,
> -	SMU_MSG_SetUclkDownHyst,
> -	SMU_MSG_GfxDeviceDriverReset,
> -	SMU_MSG_GetCurrentRpm,
> -	SMU_MSG_SetVideoFps,
> -	SMU_MSG_SetTjMax,
> -	SMU_MSG_SetFanTemperatureTarget,
> -	SMU_MSG_PrepareMp1ForUnload,
> -	SMU_MSG_DramLogSetDramAddrHigh,
> -	SMU_MSG_DramLogSetDramAddrLow,
> -	SMU_MSG_DramLogSetDramSize,
> -	SMU_MSG_SetFanMaxRpm,
> -	SMU_MSG_SetFanMinPwm,
> -	SMU_MSG_ConfigureGfxDidt,
> -	SMU_MSG_NumOfDisplays,
> -	SMU_MSG_RemoveMargins,
> -	SMU_MSG_ReadSerialNumTop32,
> -	SMU_MSG_ReadSerialNumBottom32,
> -	SMU_MSG_SetSystemVirtualDramAddrHigh,
> -	SMU_MSG_SetSystemVirtualDramAddrLow,
> -	SMU_MSG_WaflTest,
> -	SMU_MSG_SetFclkGfxClkRatio,
> -	SMU_MSG_AllowGfxOff,
> -	SMU_MSG_DisallowGfxOff,
> -	SMU_MSG_GetPptLimit,
> -	SMU_MSG_GetDcModeMaxDpmFreq,
> -	SMU_MSG_GetDebugData,
> -	SMU_MSG_SetXgmiMode,
> -	SMU_MSG_RunAfllBtc,
> -	SMU_MSG_ExitBaco,
> -	SMU_MSG_PrepareMp1ForReset,
> -	SMU_MSG_PrepareMp1ForShutdown,
> -	SMU_MSG_SetMGpuFanBoostLimitRpm,
> -	SMU_MSG_GetAVFSVoltageByDpm,
> -	SMU_MSG_PowerUpVcn,
> -	SMU_MSG_PowerDownVcn,
> -	SMU_MSG_PowerUpJpeg,
> -	SMU_MSG_PowerDownJpeg,
> -	SMU_MSG_BacoAudioD3PME,
> -	SMU_MSG_ArmD3,
> -	SMU_MSG_RunGfxDcBtc,
> -	SMU_MSG_RunSocDcBtc,
> -	SMU_MSG_SetMemoryChannelEnable,
> -	SMU_MSG_SetDfSwitchType,
> -	SMU_MSG_GetVoltageByDpm,
> -	SMU_MSG_GetVoltageByDpmOverdrive,
> -	SMU_MSG_PowerUpVcn0,
> -	SMU_MSG_PowerDownVcn01,
> -	SMU_MSG_PowerUpVcn1,
> -	SMU_MSG_PowerDownVcn1,
> -	SMU_MSG_MAX_COUNT,
> -};
> -
> -enum smu_clk_type
> -{
> -	SMU_GFXCLK,
> -	SMU_VCLK,
> -	SMU_DCLK,
> -	SMU_ECLK,
> -	SMU_SOCCLK,
> -	SMU_UCLK,
> -	SMU_DCEFCLK,
> -	SMU_DISPCLK,
> -	SMU_PIXCLK,
> -	SMU_PHYCLK,
> -	SMU_FCLK,
> -	SMU_SCLK,
> -	SMU_MCLK,
> -	SMU_PCIE,
> -	SMU_OD_SCLK,
> -	SMU_OD_MCLK,
> -	SMU_OD_VDDC_CURVE,
> -	SMU_OD_RANGE,
> -	SMU_CLK_COUNT,
> -};
> -
>  enum smu_power_src_type
>  {
>  	SMU_POWER_SOURCE_AC,
> @@ -285,63 +158,6 @@ enum smu_power_src_type
>  	SMU_POWER_SOURCE_COUNT,
>  };
> 
> -enum smu_feature_mask
> -{
> -	SMU_FEATURE_DPM_PREFETCHER_BIT,
> -	SMU_FEATURE_DPM_GFXCLK_BIT,
> -	SMU_FEATURE_DPM_UCLK_BIT,
> -	SMU_FEATURE_DPM_SOCCLK_BIT,
> -	SMU_FEATURE_DPM_UVD_BIT,
> -	SMU_FEATURE_DPM_VCE_BIT,
> -	SMU_FEATURE_ULV_BIT,
> -	SMU_FEATURE_DPM_MP0CLK_BIT,
> -	SMU_FEATURE_DPM_LINK_BIT,
> -	SMU_FEATURE_DPM_DCEFCLK_BIT,
> -	SMU_FEATURE_DS_GFXCLK_BIT,
> -	SMU_FEATURE_DS_SOCCLK_BIT,
> -	SMU_FEATURE_DS_LCLK_BIT,
> -	SMU_FEATURE_PPT_BIT,
> -	SMU_FEATURE_TDC_BIT,
> -	SMU_FEATURE_THERMAL_BIT,
> -	SMU_FEATURE_GFX_PER_CU_CG_BIT,
> -	SMU_FEATURE_RM_BIT,
> -	SMU_FEATURE_DS_DCEFCLK_BIT,
> -	SMU_FEATURE_ACDC_BIT,
> -	SMU_FEATURE_VR0HOT_BIT,
> -	SMU_FEATURE_VR1HOT_BIT,
> -	SMU_FEATURE_FW_CTF_BIT,
> -	SMU_FEATURE_LED_DISPLAY_BIT,
> -	SMU_FEATURE_FAN_CONTROL_BIT,
> -	SMU_FEATURE_GFX_EDC_BIT,
> -	SMU_FEATURE_GFXOFF_BIT,
> -	SMU_FEATURE_CG_BIT,
> -	SMU_FEATURE_DPM_FCLK_BIT,
> -	SMU_FEATURE_DS_FCLK_BIT,
> -	SMU_FEATURE_DS_MP1CLK_BIT,
> -	SMU_FEATURE_DS_MP0CLK_BIT,
> -	SMU_FEATURE_XGMI_BIT,
> -	SMU_FEATURE_DPM_GFX_PACE_BIT,
> -	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
> -	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
> -	SMU_FEATURE_DS_UCLK_BIT,
> -	SMU_FEATURE_GFX_ULV_BIT,
> -	SMU_FEATURE_FW_DSTATE_BIT,
> -	SMU_FEATURE_BACO_BIT,
> -	SMU_FEATURE_VCN_PG_BIT,
> -	SMU_FEATURE_JPEG_PG_BIT,
> -	SMU_FEATURE_USB_PG_BIT,
> -	SMU_FEATURE_RSMU_SMN_CG_BIT,
> -	SMU_FEATURE_APCC_PLUS_BIT,
> -	SMU_FEATURE_GTHR_BIT,
> -	SMU_FEATURE_GFX_DCS_BIT,
> -	SMU_FEATURE_GFX_SS_BIT,
> -	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
> -	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
> -	SMU_FEATURE_MMHUB_PG_BIT,
> -	SMU_FEATURE_ATHUB_PG_BIT,
> -	SMU_FEATURE_COUNT,
> -};
> -
>  enum smu_memory_pool_size
>  {
>      SMU_MEMORY_POOL_SIZE_ZERO   = 0,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> new file mode 100644
> index 000000000000..29d14c162417
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> @@ -0,0 +1,210 @@
> +/*
> + * Copyright 2019 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> +included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> +SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> +DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> +OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE
> +OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __SMU_TYPES_H__
> +#define __SMU_TYPES_H__
> +
> +
> +enum smu_message_type {
> +	SMU_MSG_TestMessage = 0,
> +	SMU_MSG_GetSmuVersion,
> +	SMU_MSG_GetDriverIfVersion,
> +	SMU_MSG_SetAllowedFeaturesMaskLow,
> +	SMU_MSG_SetAllowedFeaturesMaskHigh,
> +	SMU_MSG_EnableAllSmuFeatures,
> +	SMU_MSG_DisableAllSmuFeatures,
> +	SMU_MSG_EnableSmuFeaturesLow,
> +	SMU_MSG_EnableSmuFeaturesHigh,
> +	SMU_MSG_DisableSmuFeaturesLow,
> +	SMU_MSG_DisableSmuFeaturesHigh,
> +	SMU_MSG_GetEnabledSmuFeaturesLow,
> +	SMU_MSG_GetEnabledSmuFeaturesHigh,
> +	SMU_MSG_SetWorkloadMask,
> +	SMU_MSG_SetPptLimit,
> +	SMU_MSG_SetDriverDramAddrHigh,
> +	SMU_MSG_SetDriverDramAddrLow,
> +	SMU_MSG_SetToolsDramAddrHigh,
> +	SMU_MSG_SetToolsDramAddrLow,
> +	SMU_MSG_TransferTableSmu2Dram,
> +	SMU_MSG_TransferTableDram2Smu,
> +	SMU_MSG_UseDefaultPPTable,
> +	SMU_MSG_UseBackupPPTable,
> +	SMU_MSG_RunBtc,
> +	SMU_MSG_RequestI2CBus,
> +	SMU_MSG_ReleaseI2CBus,
> +	SMU_MSG_SetFloorSocVoltage,
> +	SMU_MSG_SoftReset,
> +	SMU_MSG_StartBacoMonitor,
> +	SMU_MSG_CancelBacoMonitor,
> +	SMU_MSG_EnterBaco,
> +	SMU_MSG_SetSoftMinByFreq,
> +	SMU_MSG_SetSoftMaxByFreq,
> +	SMU_MSG_SetHardMinByFreq,
> +	SMU_MSG_SetHardMaxByFreq,
> +	SMU_MSG_GetMinDpmFreq,
> +	SMU_MSG_GetMaxDpmFreq,
> +	SMU_MSG_GetDpmFreqByIndex,
> +	SMU_MSG_GetDpmClockFreq,
> +	SMU_MSG_GetSsVoltageByDpm,
> +	SMU_MSG_SetMemoryChannelConfig,
> +	SMU_MSG_SetGeminiMode,
> +	SMU_MSG_SetGeminiApertureHigh,
> +	SMU_MSG_SetGeminiApertureLow,
> +	SMU_MSG_SetMinLinkDpmByIndex,
> +	SMU_MSG_OverridePcieParameters,
> +	SMU_MSG_OverDriveSetPercentage,
> +	SMU_MSG_SetMinDeepSleepDcefclk,
> +	SMU_MSG_ReenableAcDcInterrupt,
> +	SMU_MSG_NotifyPowerSource,
> +	SMU_MSG_SetUclkFastSwitch,
> +	SMU_MSG_SetUclkDownHyst,
> +	SMU_MSG_GfxDeviceDriverReset,
> +	SMU_MSG_GetCurrentRpm,
> +	SMU_MSG_SetVideoFps,
> +	SMU_MSG_SetTjMax,
> +	SMU_MSG_SetFanTemperatureTarget,
> +	SMU_MSG_PrepareMp1ForUnload,
> +	SMU_MSG_DramLogSetDramAddrHigh,
> +	SMU_MSG_DramLogSetDramAddrLow,
> +	SMU_MSG_DramLogSetDramSize,
> +	SMU_MSG_SetFanMaxRpm,
> +	SMU_MSG_SetFanMinPwm,
> +	SMU_MSG_ConfigureGfxDidt,
> +	SMU_MSG_NumOfDisplays,
> +	SMU_MSG_RemoveMargins,
> +	SMU_MSG_ReadSerialNumTop32,
> +	SMU_MSG_ReadSerialNumBottom32,
> +	SMU_MSG_SetSystemVirtualDramAddrHigh,
> +	SMU_MSG_SetSystemVirtualDramAddrLow,
> +	SMU_MSG_WaflTest,
> +	SMU_MSG_SetFclkGfxClkRatio,
> +	SMU_MSG_AllowGfxOff,
> +	SMU_MSG_DisallowGfxOff,
> +	SMU_MSG_GetPptLimit,
> +	SMU_MSG_GetDcModeMaxDpmFreq,
> +	SMU_MSG_GetDebugData,
> +	SMU_MSG_SetXgmiMode,
> +	SMU_MSG_RunAfllBtc,
> +	SMU_MSG_ExitBaco,
> +	SMU_MSG_PrepareMp1ForReset,
> +	SMU_MSG_PrepareMp1ForShutdown,
> +	SMU_MSG_SetMGpuFanBoostLimitRpm,
> +	SMU_MSG_GetAVFSVoltageByDpm,
> +	SMU_MSG_PowerUpVcn,
> +	SMU_MSG_PowerDownVcn,
> +	SMU_MSG_PowerUpJpeg,
> +	SMU_MSG_PowerDownJpeg,
> +	SMU_MSG_BacoAudioD3PME,
> +	SMU_MSG_ArmD3,
> +	SMU_MSG_RunGfxDcBtc,
> +	SMU_MSG_RunSocDcBtc,
> +	SMU_MSG_SetMemoryChannelEnable,
> +	SMU_MSG_SetDfSwitchType,
> +	SMU_MSG_GetVoltageByDpm,
> +	SMU_MSG_GetVoltageByDpmOverdrive,
> +	SMU_MSG_PowerUpVcn0,
> +	SMU_MSG_PowerDownVcn01,
> +	SMU_MSG_PowerUpVcn1,
> +	SMU_MSG_PowerDownVcn1,
> +	SMU_MSG_MAX_COUNT,
> +};
> +
> +enum smu_clk_type {
> +	SMU_GFXCLK,
> +	SMU_VCLK,
> +	SMU_DCLK,
> +	SMU_ECLK,
> +	SMU_SOCCLK,
> +	SMU_UCLK,
> +	SMU_DCEFCLK,
> +	SMU_DISPCLK,
> +	SMU_PIXCLK,
> +	SMU_PHYCLK,
> +	SMU_FCLK,
> +	SMU_SCLK,
> +	SMU_MCLK,
> +	SMU_PCIE,
> +	SMU_OD_SCLK,
> +	SMU_OD_MCLK,
> +	SMU_OD_VDDC_CURVE,
> +	SMU_OD_RANGE,
> +	SMU_CLK_COUNT,
> +};
> +
> +enum smu_feature_mask {
> +	SMU_FEATURE_DPM_PREFETCHER_BIT,
> +	SMU_FEATURE_DPM_GFXCLK_BIT,
> +	SMU_FEATURE_DPM_UCLK_BIT,
> +	SMU_FEATURE_DPM_SOCCLK_BIT,
> +	SMU_FEATURE_DPM_UVD_BIT,
> +	SMU_FEATURE_DPM_VCE_BIT,
> +	SMU_FEATURE_ULV_BIT,
> +	SMU_FEATURE_DPM_MP0CLK_BIT,
> +	SMU_FEATURE_DPM_LINK_BIT,
> +	SMU_FEATURE_DPM_DCEFCLK_BIT,
> +	SMU_FEATURE_DS_GFXCLK_BIT,
> +	SMU_FEATURE_DS_SOCCLK_BIT,
> +	SMU_FEATURE_DS_LCLK_BIT,
> +	SMU_FEATURE_PPT_BIT,
> +	SMU_FEATURE_TDC_BIT,
> +	SMU_FEATURE_THERMAL_BIT,
> +	SMU_FEATURE_GFX_PER_CU_CG_BIT,
> +	SMU_FEATURE_RM_BIT,
> +	SMU_FEATURE_DS_DCEFCLK_BIT,
> +	SMU_FEATURE_ACDC_BIT,
> +	SMU_FEATURE_VR0HOT_BIT,
> +	SMU_FEATURE_VR1HOT_BIT,
> +	SMU_FEATURE_FW_CTF_BIT,
> +	SMU_FEATURE_LED_DISPLAY_BIT,
> +	SMU_FEATURE_FAN_CONTROL_BIT,
> +	SMU_FEATURE_GFX_EDC_BIT,
> +	SMU_FEATURE_GFXOFF_BIT,
> +	SMU_FEATURE_CG_BIT,
> +	SMU_FEATURE_DPM_FCLK_BIT,
> +	SMU_FEATURE_DS_FCLK_BIT,
> +	SMU_FEATURE_DS_MP1CLK_BIT,
> +	SMU_FEATURE_DS_MP0CLK_BIT,
> +	SMU_FEATURE_XGMI_BIT,
> +	SMU_FEATURE_DPM_GFX_PACE_BIT,
> +	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
> +	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
> +	SMU_FEATURE_DS_UCLK_BIT,
> +	SMU_FEATURE_GFX_ULV_BIT,
> +	SMU_FEATURE_FW_DSTATE_BIT,
> +	SMU_FEATURE_BACO_BIT,
> +	SMU_FEATURE_VCN_PG_BIT,
> +	SMU_FEATURE_JPEG_PG_BIT,
> +	SMU_FEATURE_USB_PG_BIT,
> +	SMU_FEATURE_RSMU_SMN_CG_BIT,
> +	SMU_FEATURE_APCC_PLUS_BIT,
> +	SMU_FEATURE_GTHR_BIT,
> +	SMU_FEATURE_GFX_DCS_BIT,
> +	SMU_FEATURE_GFX_SS_BIT,
> +	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
> +	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
> +	SMU_FEATURE_MMHUB_PG_BIT,
> +	SMU_FEATURE_ATHUB_PG_BIT,
> +	SMU_FEATURE_COUNT,
> +};
> +
> +#endif
> +
> --
> 2.22.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* RE: [PATCH 3/5] drm/amd/powerplay: add smu feature name support
       [not found]     ` <20190725051057.28862-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  9:35       ` Quan, Evan
       [not found]         ` <MN2PR12MB3344FF4A8126C0263C3D2E7CE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Quan, Evan @ 2019-07-25  9:35 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

For patch2 and patch3, __SMU_DUMMY_MAP has several different defines.
It's not sure what it is defined as and that's why you need "#undef __SMU_DUMMY_MAP" before each use.
Please give them separate names and avoid this confusing.

Regards,
Evan
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray
> <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 3/5] drm/amd/powerplay: add smu feature name support
> 
> add smu_get_feature_name support in smu.
> 
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 +++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
>  drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 109 +++++++++--------
> -
>  3 files changed, 71 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 4604b6af56bb..8563f9083f4e 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -42,6 +42,19 @@ const char *smu_get_message_name(struct
> smu_context *smu, enum smu_message_type
>  	return __smu_message_names[type];
>  }
> 
> +#undef __SMU_DUMMY_MAP
> +#define __SMU_DUMMY_MAP(fea)	#fea
> +static const char* __smu_feature_names[] = {
> +	SMU_FEATURE_MASKS
> +};
> +
> +const char *smu_get_feature_name(struct smu_context *smu, enum
> +smu_feature_mask feature) {
> +	if (feature < 0 || feature > SMU_FEATURE_COUNT)
> +		return "unknow smu feature";
> +	return __smu_feature_names[feature];
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version,
> uint32_t *smu_version)  {
>  	int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 035f857922ec..ba2385026b89 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -805,5 +805,6 @@ int smu_force_performance_level(struct
> smu_context *smu, enum amd_dpm_forced_lev  int
> smu_set_display_count(struct smu_context *smu, uint32_t count);  bool
> smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type
> clk_type);  const char *smu_get_message_name(struct smu_context *smu,
> enum smu_message_type type);
> +const char *smu_get_feature_name(struct smu_context *smu, enum
> +smu_feature_mask feature);
> 
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> index d42e3424e704..8793c8d0dc52 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> @@ -154,59 +154,64 @@ enum smu_clk_type {
>  	SMU_CLK_COUNT,
>  };
> 
> +#define SMU_FEATURE_MASKS				\
> +       __SMU_DUMMY_MAP(DPM_PREFETCHER),			\
> +       __SMU_DUMMY_MAP(DPM_GFXCLK),                    	\
> +       __SMU_DUMMY_MAP(DPM_UCLK),                      	\
> +       __SMU_DUMMY_MAP(DPM_SOCCLK),                    	\
> +       __SMU_DUMMY_MAP(DPM_UVD),                       	\
> +       __SMU_DUMMY_MAP(DPM_VCE),                       	\
> +       __SMU_DUMMY_MAP(ULV),                           	\
> +       __SMU_DUMMY_MAP(DPM_MP0CLK),                    	\
> +       __SMU_DUMMY_MAP(DPM_LINK),                      	\
> +       __SMU_DUMMY_MAP(DPM_DCEFCLK),                   	\
> +       __SMU_DUMMY_MAP(DS_GFXCLK),                     	\
> +       __SMU_DUMMY_MAP(DS_SOCCLK),                     	\
> +       __SMU_DUMMY_MAP(DS_LCLK),                       	\
> +       __SMU_DUMMY_MAP(PPT),                           	\
> +       __SMU_DUMMY_MAP(TDC),                           	\
> +       __SMU_DUMMY_MAP(THERMAL),                       	\
> +       __SMU_DUMMY_MAP(GFX_PER_CU_CG),                 	\
> +       __SMU_DUMMY_MAP(RM),                            	\
> +       __SMU_DUMMY_MAP(DS_DCEFCLK),                    	\
> +       __SMU_DUMMY_MAP(ACDC),                          	\
> +       __SMU_DUMMY_MAP(VR0HOT),                        	\
> +       __SMU_DUMMY_MAP(VR1HOT),                        	\
> +       __SMU_DUMMY_MAP(FW_CTF),                        	\
> +       __SMU_DUMMY_MAP(LED_DISPLAY),                   	\
> +       __SMU_DUMMY_MAP(FAN_CONTROL),                   	\
> +       __SMU_DUMMY_MAP(GFX_EDC),                       	\
> +       __SMU_DUMMY_MAP(GFXOFF),                        	\
> +       __SMU_DUMMY_MAP(CG),                            	\
> +       __SMU_DUMMY_MAP(DPM_FCLK),                      	\
> +       __SMU_DUMMY_MAP(DS_FCLK),                       	\
> +       __SMU_DUMMY_MAP(DS_MP1CLK),                     	\
> +       __SMU_DUMMY_MAP(DS_MP0CLK),                     	\
> +       __SMU_DUMMY_MAP(XGMI),                          	\
> +       __SMU_DUMMY_MAP(DPM_GFX_PACE),                  	\
> +       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),             	\
> +       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),              	\
> +       __SMU_DUMMY_MAP(DS_UCLK),                       	\
> +       __SMU_DUMMY_MAP(GFX_ULV),                       	\
> +       __SMU_DUMMY_MAP(FW_DSTATE),                     	\
> +       __SMU_DUMMY_MAP(BACO),                          	\
> +       __SMU_DUMMY_MAP(VCN_PG),                        	\
> +       __SMU_DUMMY_MAP(JPEG_PG),                       	\
> +       __SMU_DUMMY_MAP(USB_PG),                        	\
> +       __SMU_DUMMY_MAP(RSMU_SMN_CG),                   	\
> +       __SMU_DUMMY_MAP(APCC_PLUS),                     	\
> +       __SMU_DUMMY_MAP(GTHR),                          	\
> +       __SMU_DUMMY_MAP(GFX_DCS),                       	\
> +       __SMU_DUMMY_MAP(GFX_SS),                        	\
> +       __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR),           	\
> +       __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),           	\
> +       __SMU_DUMMY_MAP(MMHUB_PG),                      	\
> +       __SMU_DUMMY_MAP(ATHUB_PG),                      	\
> +
> +#undef __SMU_DUMMY_MAP
> +#define __SMU_DUMMY_MAP(feature)
> 	SMU_FEATURE_##feature##_BIT
>  enum smu_feature_mask {
> -	SMU_FEATURE_DPM_PREFETCHER_BIT,
> -	SMU_FEATURE_DPM_GFXCLK_BIT,
> -	SMU_FEATURE_DPM_UCLK_BIT,
> -	SMU_FEATURE_DPM_SOCCLK_BIT,
> -	SMU_FEATURE_DPM_UVD_BIT,
> -	SMU_FEATURE_DPM_VCE_BIT,
> -	SMU_FEATURE_ULV_BIT,
> -	SMU_FEATURE_DPM_MP0CLK_BIT,
> -	SMU_FEATURE_DPM_LINK_BIT,
> -	SMU_FEATURE_DPM_DCEFCLK_BIT,
> -	SMU_FEATURE_DS_GFXCLK_BIT,
> -	SMU_FEATURE_DS_SOCCLK_BIT,
> -	SMU_FEATURE_DS_LCLK_BIT,
> -	SMU_FEATURE_PPT_BIT,
> -	SMU_FEATURE_TDC_BIT,
> -	SMU_FEATURE_THERMAL_BIT,
> -	SMU_FEATURE_GFX_PER_CU_CG_BIT,
> -	SMU_FEATURE_RM_BIT,
> -	SMU_FEATURE_DS_DCEFCLK_BIT,
> -	SMU_FEATURE_ACDC_BIT,
> -	SMU_FEATURE_VR0HOT_BIT,
> -	SMU_FEATURE_VR1HOT_BIT,
> -	SMU_FEATURE_FW_CTF_BIT,
> -	SMU_FEATURE_LED_DISPLAY_BIT,
> -	SMU_FEATURE_FAN_CONTROL_BIT,
> -	SMU_FEATURE_GFX_EDC_BIT,
> -	SMU_FEATURE_GFXOFF_BIT,
> -	SMU_FEATURE_CG_BIT,
> -	SMU_FEATURE_DPM_FCLK_BIT,
> -	SMU_FEATURE_DS_FCLK_BIT,
> -	SMU_FEATURE_DS_MP1CLK_BIT,
> -	SMU_FEATURE_DS_MP0CLK_BIT,
> -	SMU_FEATURE_XGMI_BIT,
> -	SMU_FEATURE_DPM_GFX_PACE_BIT,
> -	SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
> -	SMU_FEATURE_MEM_MVDD_SCALING_BIT,
> -	SMU_FEATURE_DS_UCLK_BIT,
> -	SMU_FEATURE_GFX_ULV_BIT,
> -	SMU_FEATURE_FW_DSTATE_BIT,
> -	SMU_FEATURE_BACO_BIT,
> -	SMU_FEATURE_VCN_PG_BIT,
> -	SMU_FEATURE_JPEG_PG_BIT,
> -	SMU_FEATURE_USB_PG_BIT,
> -	SMU_FEATURE_RSMU_SMN_CG_BIT,
> -	SMU_FEATURE_APCC_PLUS_BIT,
> -	SMU_FEATURE_GTHR_BIT,
> -	SMU_FEATURE_GFX_DCS_BIT,
> -	SMU_FEATURE_GFX_SS_BIT,
> -	SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
> -	SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
> -	SMU_FEATURE_MMHUB_PG_BIT,
> -	SMU_FEATURE_ATHUB_PG_BIT,
> +	SMU_FEATURE_MASKS
>  	SMU_FEATURE_COUNT,
>  };
> 
> --
> 2.22.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 3/5] drm/amd/powerplay: add smu feature name support
       [not found]         ` <MN2PR12MB3344FF4A8126C0263C3D2E7CE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25  9:47           ` Wang, Kevin(Yang)
  0 siblings, 0 replies; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  9:47 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 9978 bytes --]

this is my intention,
i think we should to keep the  macro name of __SMU_DUMMY_MAP.
the smu driver code will use macro SMU_MESSAGE_TYPES and SMU_FEATURE_MASKS.
the __SMU_DUMMY_MAP just a placeholder, the driver shouldn't add more one.

Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 5:35 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 3/5] drm/amd/powerplay: add smu feature name support

For patch2 and patch3, __SMU_DUMMY_MAP has several different defines.
It's not sure what it is defined as and that's why you need "#undef __SMU_DUMMY_MAP" before each use.
Please give them separate names and avoid this confusing.

Regards,
Evan
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray
> <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Wang,
> Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
> Subject: [PATCH 3/5] drm/amd/powerplay: add smu feature name support
>
> add smu_get_feature_name support in smu.
>
> Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  13 +++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   1 +
>  drivers/gpu/drm/amd/powerplay/inc/smu_types.h | 109 +++++++++--------
> -
>  3 files changed, 71 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 4604b6af56bb..8563f9083f4e 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -42,6 +42,19 @@ const char *smu_get_message_name(struct
> smu_context *smu, enum smu_message_type
>        return __smu_message_names[type];
>  }
>
> +#undef __SMU_DUMMY_MAP
> +#define __SMU_DUMMY_MAP(fea) #fea
> +static const char* __smu_feature_names[] = {
> +     SMU_FEATURE_MASKS
> +};
> +
> +const char *smu_get_feature_name(struct smu_context *smu, enum
> +smu_feature_mask feature) {
> +     if (feature < 0 || feature > SMU_FEATURE_COUNT)
> +             return "unknow smu feature";
> +     return __smu_feature_names[feature];
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version,
> uint32_t *smu_version)  {
>        int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index 035f857922ec..ba2385026b89 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -805,5 +805,6 @@ int smu_force_performance_level(struct
> smu_context *smu, enum amd_dpm_forced_lev  int
> smu_set_display_count(struct smu_context *smu, uint32_t count);  bool
> smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type
> clk_type);  const char *smu_get_message_name(struct smu_context *smu,
> enum smu_message_type type);
> +const char *smu_get_feature_name(struct smu_context *smu, enum
> +smu_feature_mask feature);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> index d42e3424e704..8793c8d0dc52 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_types.h
> @@ -154,59 +154,64 @@ enum smu_clk_type {
>        SMU_CLK_COUNT,
>  };
>
> +#define SMU_FEATURE_MASKS                            \
> +       __SMU_DUMMY_MAP(DPM_PREFETCHER),                      \
> +       __SMU_DUMMY_MAP(DPM_GFXCLK),                           \
> +       __SMU_DUMMY_MAP(DPM_UCLK),                             \
> +       __SMU_DUMMY_MAP(DPM_SOCCLK),                           \
> +       __SMU_DUMMY_MAP(DPM_UVD),                              \
> +       __SMU_DUMMY_MAP(DPM_VCE),                              \
> +       __SMU_DUMMY_MAP(ULV),                                  \
> +       __SMU_DUMMY_MAP(DPM_MP0CLK),                           \
> +       __SMU_DUMMY_MAP(DPM_LINK),                             \
> +       __SMU_DUMMY_MAP(DPM_DCEFCLK),                          \
> +       __SMU_DUMMY_MAP(DS_GFXCLK),                            \
> +       __SMU_DUMMY_MAP(DS_SOCCLK),                            \
> +       __SMU_DUMMY_MAP(DS_LCLK),                              \
> +       __SMU_DUMMY_MAP(PPT),                                  \
> +       __SMU_DUMMY_MAP(TDC),                                  \
> +       __SMU_DUMMY_MAP(THERMAL),                              \
> +       __SMU_DUMMY_MAP(GFX_PER_CU_CG),                        \
> +       __SMU_DUMMY_MAP(RM),                                   \
> +       __SMU_DUMMY_MAP(DS_DCEFCLK),                           \
> +       __SMU_DUMMY_MAP(ACDC),                                 \
> +       __SMU_DUMMY_MAP(VR0HOT),                               \
> +       __SMU_DUMMY_MAP(VR1HOT),                               \
> +       __SMU_DUMMY_MAP(FW_CTF),                               \
> +       __SMU_DUMMY_MAP(LED_DISPLAY),                          \
> +       __SMU_DUMMY_MAP(FAN_CONTROL),                          \
> +       __SMU_DUMMY_MAP(GFX_EDC),                              \
> +       __SMU_DUMMY_MAP(GFXOFF),                               \
> +       __SMU_DUMMY_MAP(CG),                                   \
> +       __SMU_DUMMY_MAP(DPM_FCLK),                             \
> +       __SMU_DUMMY_MAP(DS_FCLK),                              \
> +       __SMU_DUMMY_MAP(DS_MP1CLK),                            \
> +       __SMU_DUMMY_MAP(DS_MP0CLK),                            \
> +       __SMU_DUMMY_MAP(XGMI),                                 \
> +       __SMU_DUMMY_MAP(DPM_GFX_PACE),                         \
> +       __SMU_DUMMY_MAP(MEM_VDDCI_SCALING),                    \
> +       __SMU_DUMMY_MAP(MEM_MVDD_SCALING),                     \
> +       __SMU_DUMMY_MAP(DS_UCLK),                              \
> +       __SMU_DUMMY_MAP(GFX_ULV),                              \
> +       __SMU_DUMMY_MAP(FW_DSTATE),                            \
> +       __SMU_DUMMY_MAP(BACO),                                 \
> +       __SMU_DUMMY_MAP(VCN_PG),                               \
> +       __SMU_DUMMY_MAP(JPEG_PG),                              \
> +       __SMU_DUMMY_MAP(USB_PG),                               \
> +       __SMU_DUMMY_MAP(RSMU_SMN_CG),                          \
> +       __SMU_DUMMY_MAP(APCC_PLUS),                            \
> +       __SMU_DUMMY_MAP(GTHR),                                 \
> +       __SMU_DUMMY_MAP(GFX_DCS),                              \
> +       __SMU_DUMMY_MAP(GFX_SS),                               \
> +       __SMU_DUMMY_MAP(OUT_OF_BAND_MONITOR),                  \
> +       __SMU_DUMMY_MAP(TEMP_DEPENDENT_VMIN),                  \
> +       __SMU_DUMMY_MAP(MMHUB_PG),                             \
> +       __SMU_DUMMY_MAP(ATHUB_PG),                             \
> +
> +#undef __SMU_DUMMY_MAP
> +#define __SMU_DUMMY_MAP(feature)
>        SMU_FEATURE_##feature##_BIT
>  enum smu_feature_mask {
> -     SMU_FEATURE_DPM_PREFETCHER_BIT,
> -     SMU_FEATURE_DPM_GFXCLK_BIT,
> -     SMU_FEATURE_DPM_UCLK_BIT,
> -     SMU_FEATURE_DPM_SOCCLK_BIT,
> -     SMU_FEATURE_DPM_UVD_BIT,
> -     SMU_FEATURE_DPM_VCE_BIT,
> -     SMU_FEATURE_ULV_BIT,
> -     SMU_FEATURE_DPM_MP0CLK_BIT,
> -     SMU_FEATURE_DPM_LINK_BIT,
> -     SMU_FEATURE_DPM_DCEFCLK_BIT,
> -     SMU_FEATURE_DS_GFXCLK_BIT,
> -     SMU_FEATURE_DS_SOCCLK_BIT,
> -     SMU_FEATURE_DS_LCLK_BIT,
> -     SMU_FEATURE_PPT_BIT,
> -     SMU_FEATURE_TDC_BIT,
> -     SMU_FEATURE_THERMAL_BIT,
> -     SMU_FEATURE_GFX_PER_CU_CG_BIT,
> -     SMU_FEATURE_RM_BIT,
> -     SMU_FEATURE_DS_DCEFCLK_BIT,
> -     SMU_FEATURE_ACDC_BIT,
> -     SMU_FEATURE_VR0HOT_BIT,
> -     SMU_FEATURE_VR1HOT_BIT,
> -     SMU_FEATURE_FW_CTF_BIT,
> -     SMU_FEATURE_LED_DISPLAY_BIT,
> -     SMU_FEATURE_FAN_CONTROL_BIT,
> -     SMU_FEATURE_GFX_EDC_BIT,
> -     SMU_FEATURE_GFXOFF_BIT,
> -     SMU_FEATURE_CG_BIT,
> -     SMU_FEATURE_DPM_FCLK_BIT,
> -     SMU_FEATURE_DS_FCLK_BIT,
> -     SMU_FEATURE_DS_MP1CLK_BIT,
> -     SMU_FEATURE_DS_MP0CLK_BIT,
> -     SMU_FEATURE_XGMI_BIT,
> -     SMU_FEATURE_DPM_GFX_PACE_BIT,
> -     SMU_FEATURE_MEM_VDDCI_SCALING_BIT,
> -     SMU_FEATURE_MEM_MVDD_SCALING_BIT,
> -     SMU_FEATURE_DS_UCLK_BIT,
> -     SMU_FEATURE_GFX_ULV_BIT,
> -     SMU_FEATURE_FW_DSTATE_BIT,
> -     SMU_FEATURE_BACO_BIT,
> -     SMU_FEATURE_VCN_PG_BIT,
> -     SMU_FEATURE_JPEG_PG_BIT,
> -     SMU_FEATURE_USB_PG_BIT,
> -     SMU_FEATURE_RSMU_SMN_CG_BIT,
> -     SMU_FEATURE_APCC_PLUS_BIT,
> -     SMU_FEATURE_GTHR_BIT,
> -     SMU_FEATURE_GFX_DCS_BIT,
> -     SMU_FEATURE_GFX_SS_BIT,
> -     SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,
> -     SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT,
> -     SMU_FEATURE_MMHUB_PG_BIT,
> -     SMU_FEATURE_ATHUB_PG_BIT,
> +     SMU_FEATURE_MASKS
>        SMU_FEATURE_COUNT,
>  };
>
> --
> 2.22.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level
       [not found]         ` <MN2PR12MB334402CBE2CB315E0205EC3BE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25  9:50           ` Wang, Kevin(Yang)
  0 siblings, 0 replies; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  9:50 UTC (permalink / raw)
  To: Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 9469 bytes --]

i will addressed it before submit patch.
thanks.

Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 5:29 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level

+       feature_mask = 1UL << feature_id;
Use "ULL" here. That can guard it to be 64bits long even on 32bits target.
With that fixed, reviewed-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> On Behalf Of
> Wang, Kevin(Yang)
> Sent: Thursday, July 25, 2019 1:11 PM
> To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray
> <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Wang,
> Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
> Subject: [PATCH 4/5] drm/amd/powerplay: move
> smu_feature_update_enable_state to up level
>
> this function is not ip or asic related function,
> so move it to top level as public api in smu.
>
> Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40
> ++++++++++++++++++-
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 ------------------
>  3 files changed, 40 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 8563f9083f4e..e881de955388 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -507,6 +507,41 @@ int smu_feature_init_dpm(struct smu_context
> *smu)
>
>        return ret;
>  }
> +int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled)
> +{
> +     uint32_t feature_low = 0, feature_high = 0;
> +     int ret = 0;
> +
> +     if (!smu->pm_enabled)
> +             return ret;
> +
> +     feature_low = (feature_mask >> 0 ) & 0xffffffff;
> +     feature_high = (feature_mask >> 32) & 0xffffffff;
> +
> +     if (enabled) {
> +             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> +                                               feature_low);
> +             if (ret)
> +                     return ret;
> +             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> +                                               feature_high);
> +             if (ret)
> +                     return ret;
> +
> +     } else {
> +             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> +                                               feature_low);
> +             if (ret)
> +                     return ret;
> +             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> +                                               feature_high);
> +             if (ret)
> +                     return ret;
> +
> +     }
> +
> +     return ret;
> +}
>
>  int smu_feature_is_enabled(struct smu_context *smu, enum
> smu_feature_mask mask)
>  {
> @@ -532,6 +567,7 @@ int smu_feature_set_enabled(struct smu_context
> *smu, enum smu_feature_mask mask,
>  {
>        struct smu_feature *feature = &smu->smu_feature;
>        int feature_id;
> +     uint64_t feature_mask = 0;
>        int ret = 0;
>
>        feature_id = smu_feature_get_index(smu, mask);
> @@ -540,8 +576,10 @@ int smu_feature_set_enabled(struct smu_context
> *smu, enum smu_feature_mask mask,
>
>        WARN_ON(feature_id > feature->feature_num);
>
> +     feature_mask = 1UL << feature_id;
> +
>        mutex_lock(&feature->mutex);
> -     ret = smu_feature_update_enable_state(smu, feature_id, enable);
> +     ret = smu_feature_update_enable_state(smu, feature_mask,
> enable);
>        if (ret)
>                goto failed;
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ba2385026b89..abc2644b4c07 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -479,7 +479,6 @@ struct smu_funcs
>        int (*init_display_count)(struct smu_context *smu, uint32_t count);
>        int (*set_allowed_mask)(struct smu_context *smu);
>        int (*get_enabled_mask)(struct smu_context *smu, uint32_t
> *feature_mask, uint32_t num);
> -     int (*update_feature_enable_state)(struct smu_context *smu,
> uint32_t feature_id, bool enabled);
>        int (*notify_display_change)(struct smu_context *smu);
>        int (*get_power_limit)(struct smu_context *smu, uint32_t *limit,
> bool def);
>        int (*set_power_limit)(struct smu_context *smu, uint32_t n);
> @@ -595,8 +594,6 @@ struct smu_funcs
>        ((smu)->funcs->get_enabled_mask? (smu)->funcs-
> >get_enabled_mask((smu), (mask), (num)) : 0)
>  #define smu_is_dpm_running(smu) \
>        ((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs-
> >is_dpm_running((smu)) : 0)
> -#define smu_feature_update_enable_state(smu, feature_id, enabled) \
> -     ((smu)->funcs->update_feature_enable_state? (smu)->funcs-
> >update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
>  #define smu_notify_display_change(smu) \
>        ((smu)->funcs->notify_display_change? (smu)->funcs-
> >notify_display_change((smu)) : 0)
>  #define smu_store_powerplay_table(smu) \
> @@ -804,6 +801,7 @@ enum amd_dpm_forced_level
> smu_get_performance_level(struct smu_context *smu);
>  int smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level);
>  int smu_set_display_count(struct smu_context *smu, uint32_t count);
>  bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum
> smu_clk_type clk_type);
> +int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum
> smu_feature_mask feature);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> index ccf6af055d03..93f3ffb8b471 100644
> --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
> @@ -795,44 +795,6 @@ static int smu_v11_0_init_display_count(struct
> smu_context *smu, uint32_t count)
>        return ret;
>  }
>
> -static int smu_v11_0_update_feature_enable_state(struct smu_context
> *smu, uint32_t feature_id, bool enabled)
> -{
> -     uint32_t feature_low = 0, feature_high = 0;
> -     int ret = 0;
> -
> -     if (!smu->pm_enabled)
> -             return ret;
> -     if (feature_id >= 0 && feature_id < 31)
> -             feature_low = (1 << feature_id);
> -     else if (feature_id > 31 && feature_id < 63)
> -             feature_high = (1 << feature_id);
> -     else
> -             return -EINVAL;
> -
> -     if (enabled) {
> -             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                               feature_low);
> -             if (ret)
> -                     return ret;
> -             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                               feature_high);
> -             if (ret)
> -                     return ret;
> -
> -     } else {
> -             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                               feature_low);
> -             if (ret)
> -                     return ret;
> -             ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                               feature_high);
> -             if (ret)
> -                     return ret;
> -
> -     }
> -
> -     return ret;
> -}
>
>  static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
>  {
> @@ -1781,7 +1743,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
>        .set_allowed_mask = smu_v11_0_set_allowed_mask,
>        .get_enabled_mask = smu_v11_0_get_enabled_mask,
>        .system_features_control = smu_v11_0_system_features_control,
> -     .update_feature_enable_state =
> smu_v11_0_update_feature_enable_state,
>        .notify_display_change = smu_v11_0_notify_display_change,
>        .get_power_limit = smu_v11_0_get_power_limit,
>        .set_power_limit = smu_v11_0_set_power_limit,
> --
> 2.22.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                     ` <MN2PR12MB33098222156F946AA7EABB26ECC10-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25 13:01                       ` Deucher, Alexander
       [not found]                         ` <BN6PR12MB1809E62D6BFE3224637F25D9F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Deucher, Alexander @ 2019-07-25 13:01 UTC (permalink / raw)
  To: Huang, Ray, Wang, Kevin(Yang),
	Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang,
	Hawking, StDenis, Tom
  Cc: Feng, Kenneth


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Tom, does umr use it?

Alex
________________________________
From: Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 4:49 AM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu


Any other user mode tool use the “ppfeature” sysfs interface?



Thanks,

Ray



From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 4:44 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Cc: Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



in fact, i don't want to change this sysfs name from "ppfeatures" to "pp_features",

but it seems that don't have same name format with other pp sysfs node.

the other powerplay sysfs name have "pp_" prefix, i think we'd better to change it name to "pp_features"



eg:

pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk  pp_force_state  pp_num_states          pp_sclk_od
pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od      pp_power_profile_mode  pp_table



@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>



Could you give us some idea about it,

Thanks.



Best Regards,
Kevin

________________________________

From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 4:30 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Subject: RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



To keep backward compatibility, we cannot change the sysfs file naming.

But it’s a good idea to summarize these as common APIs.



Regards,

Evan

From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> On Behalf Of Wang, Kevin(Yang)
Sent: Thursday, July 25, 2019 4:10 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



add sample data from sysfs pp_features with this patch.



print format:

index. feature name (Hardware Message ID): state



sudo find /sys -name "pp_features" -exec cat {} \;

features high: 0x00000623 low: 0xb3cdaffb

00. DPM_PREFETCHER       ( 0) : enabeld

01. DPM_GFXCLK           ( 1) : enabeld

02. DPM_UCLK             ( 3) : enabeld

03. DPM_SOCCLK           ( 4) : enabeld

04. DPM_MP0CLK           ( 5) : enabeld

05. DPM_LINK             ( 6) : enabeld

06. DPM_DCEFCLK          ( 7) : enabeld

07. DS_GFXCLK            (10) : enabeld

08. DS_SOCCLK            (11) : enabeld

09. DS_LCLK              (12) : disabled

10. PPT                  (23) : enabeld

11. TDC                  (24) : enabeld

12. THERMAL              (33) : enabeld

13. RM                   (35) : disabled

14. DS_DCEFCLK           (13) : enabeld

15. ACDC                 (28) : enabeld

16. VR0HOT               (29) : enabeld

17. VR1HOT               (30) : disabled

18. FW_CTF               (31) : enabeld

19. LED_DISPLAY          (36) : disabled

20. FAN_CONTROL          (32) : enabeld

21. GFX_EDC              (25) : enabeld

22. GFXOFF               (17) : disabled

23. DPM_GFX_PACE         ( 2) : disabled

24. MEM_VDDCI_SCALING    ( 8) : enabeld

25. MEM_MVDD_SCALING     ( 9) : enabeld

26. DS_UCLK              (14) : disabled

27. GFX_ULV              (15) : enabeld

28. FW_DSTATE            (16) : enabeld

29. BACO                 (18) : enabeld

30. VCN_PG               (19) : enabeld

31. JPEG_PG              (20) : disabled

32. USB_PG               (21) : disabled

33. RSMU_SMN_CG          (22) : enabeld

34. APCC_PLUS            (26) : disabled

35. GTHR                 (27) : disabled

36. GFX_DCS              (34) : disabled

37. GFX_SS               (37) : enabeld

38. OUT_OF_BAND_MONITOR  (38) : disabled

39. TEMP_DEPENDENT_VMIN  (39) : disabled

40. MMHUB_PG             (40) : disabled

41. ATHUB_PG             (41) : enabeld



________________________________

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 1:11 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu



1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.

Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c        |  24 +--
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    |  61 +++++++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |   8 +-
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
 5 files changed, 75 insertions(+), 336 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 866097d5cf26..9e8e8a65d9bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -788,10 +788,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 }

 /**
- * DOC: ppfeatures
+ * DOC: pp_features
  *
  * The amdgpu driver provides a sysfs API for adjusting what powerplay
- * features to be enabled. The file ppfeatures is used for this. And
+ * features to be enabled. The file pp_features is used for this. And
  * this is only available for Vega10 and later dGPUs.
  *
  * Reading back the file will show you the followings:
@@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
  * the corresponding bit from original ppfeature masks and input the
  * new ppfeature masks.
  */
-static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 const char *buf,
                 size_t count)
@@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         pr_debug("featuremask = 0x%llx\n", featuremask);

         if (is_support_sw_smu(adev)) {
-               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
+               ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
                 if (ret)
                         return -EINVAL;
         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
@@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
         return count;
 }

-static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
+static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
                 struct device_attribute *attr,
                 char *buf)
 {
@@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
         struct amdgpu_device *adev = ddev->dev_private;

         if (is_support_sw_smu(adev)) {
-               return smu_get_ppfeature_status(&adev->smu, buf);
+               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
         } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
                 return amdgpu_dpm_get_ppfeature_status(adev, buf);

@@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
 static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
                 amdgpu_get_memory_busy_percent, NULL);
 static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
-static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
-               amdgpu_get_ppfeature_status,
-               amdgpu_set_ppfeature_status);
+static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
+               amdgpu_get_pp_feature_status,
+               amdgpu_set_pp_feature_status);
 static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);

 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
@@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU)) {
                 ret = device_create_file(adev->dev,
-                               &dev_attr_ppfeatures);
+                               &dev_attr_pp_features);
                 if (ret) {
                         DRM_ERROR("failed to create device file "
-                                       "ppfeatures\n");
+                                       "pp_features\n");
                         return ret;
                 }
         }
@@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
                 device_remove_file(adev->dev, &dev_attr_unique_id);
         if ((adev->asic_type >= CHIP_VEGA10) &&
             !(adev->flags & AMD_IS_APU))
-               device_remove_file(adev->dev, &dev_attr_ppfeatures);
+               device_remove_file(adev->dev, &dev_attr_pp_features);
 }

 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e881de955388..90833ff2fe00 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask
         return __smu_feature_names[feature];
 }

+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
+{
+       size_t size = 0;
+       int ret = 0, i = 0;
+       uint32_t feature_mask[2] = { 0 };
+       int32_t feature_index = 0;
+       uint32_t count = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               goto failed;
+
+       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
+                       feature_mask[1], feature_mask[0]);
+
+       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+               feature_index = smu_feature_get_index(smu, i);
+               if (feature_index < 0)
+                       continue;
+               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
+                              count++,
+                              smu_get_feature_name(smu, i),
+                              feature_index,
+                              !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
+       }
+
+failed:
+       return size;
+}
+
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
+{
+       int ret = 0;
+       uint32_t feature_mask[2] = { 0 };
+       uint64_t feature_2_enabled = 0;
+       uint64_t feature_2_disabled = 0;
+       uint64_t feature_enables = 0;
+
+       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
+       if (ret)
+               return ret;
+
+       feature_enables = ((uint64_t)feature_mask[1] << 32 | (uint64_t)feature_mask[0]);
+
+       feature_2_enabled  = ~feature_enables & new_mask;
+       feature_2_disabled = feature_enables & ~new_mask;
+
+       if (feature_2_enabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
+               if (ret)
+                       ret;
+       }
+       if (feature_2_disabled) {
+               ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t *smu_version)
 {
         int ret = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index abc2644b4c07..ac9e9d5d8a5c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -432,8 +432,6 @@ struct pptable_funcs {
                                       uint32_t *mclk_mask,
                                       uint32_t *soc_mask);
         int (*set_cpu_power_state)(struct smu_context *smu);
-       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t ppfeatures);
-       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
         bool (*is_dpm_running)(struct smu_context *smu);
         int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
         int (*set_thermal_fan_table)(struct smu_context *smu);
@@ -713,10 +711,6 @@ struct smu_funcs
         ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
 #define smu_set_xgmi_pstate(smu, pstate) \
                 ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
-#define smu_set_ppfeature_status(smu, ppfeatures) \
-       ((smu)->ppt_funcs->set_ppfeature_status ? (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
-#define smu_get_ppfeature_status(smu, buf) \
-       ((smu)->ppt_funcs->get_ppfeature_status ? (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
 #define smu_set_watermarks_table(smu, tab, clock_ranges) \
         ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
 #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
@@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type)
 int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
+size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
+int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask);

 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c873228bf05f..cd0920093a5e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
         return 0;
 }

-static int navi10_get_ppfeature_status(struct smu_context *smu,
-                                      char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "DPM_GFXCLK",
-                               "DPM_GFX_PACE",
-                               "DPM_UCLK",
-                               "DPM_SOCCLK",
-                               "DPM_MP0CLK",
-                               "DPM_LINK",
-                               "DPM_DCEFCLK",
-                               "MEM_VDDCI_SCALING",
-                               "MEM_MVDD_SCALING",
-                               "DS_GFXCLK",
-                               "DS_SOCCLK",
-                               "DS_LCLK",
-                               "DS_DCEFCLK",
-                               "DS_UCLK",
-                               "GFX_ULV",
-                               "FW_DSTATE",
-                               "GFXOFF",
-                               "BACO",
-                               "VCN_PG",
-                               "JPEG_PG",
-                               "USB_PG",
-                               "RSMU_SMN_CG",
-                               "PPT",
-                               "TDC",
-                               "GFX_EDC",
-                               "APCC_PLUS",
-                               "GTHR",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "FAN_CONTROL",
-                               "THERMAL",
-                               "GFX_DCS",
-                               "RM",
-                               "LED_DISPLAY",
-                               "GFX_SS",
-                               "OUT_OF_BAND_MONITOR",
-                               "TEMP_DEPENDENT_VMIN",
-                               "MMHUB_PG",
-                               "ATHUB_PG"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[GetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < (sizeof(ppfeature_name) / sizeof(ppfeature_name[0])); i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int navi10_enable_smc_features(struct smu_context *smu,
-                                     bool enabled,
-                                     uint64_t feature_masks)
-{
-       struct smu_feature *feature = &smu->smu_feature;
-       uint32_t feature_low, feature_high;
-       uint32_t feature_mask[2];
-       int ret = 0;
-
-       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
-       feature_high = (uint32_t)((feature_masks & 0xFFFFFFFF00000000ULL) >> 32);
-
-       if (enabled) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 feature_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 feature_high);
-               if (ret)
-                       return ret;
-       }
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       mutex_lock(&feature->mutex);
-       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
-                   feature->feature_num);
-       mutex_unlock(&feature->mutex);
-
-       return 0;
-}
-
-static int navi10_set_ppfeature_status(struct smu_context *smu,
-                                      uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint32_t feature_mask[2];
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[SetPPfeatureStatus] Failed to get enabled smc features!",
-                       return ret);
-       features_enabled = (uint64_t)feature_mask[0] |
-                          (uint64_t)feature_mask[1] << 32;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = navi10_enable_smc_features(smu, false, features_to_disable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to disable smc features!",
-                               return ret);
-       }
-
-       if (features_to_enable) {
-               ret = navi10_enable_smc_features(smu, true, features_to_enable);
-               PP_ASSERT_WITH_CODE(!ret,
-                               "[SetPPfeatureStatus] Failed to enable smc features!",
-                               return ret);
-       }
-
-       return 0;
-}
-
 static int navi10_set_peak_clock_by_device(struct smu_context *smu)
 {
         struct amdgpu_device *adev = smu->adev;
@@ -1689,8 +1526,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
         .set_watermarks_table = navi10_set_watermarks_table,
         .read_sensor = navi10_read_sensor,
         .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
-       .get_ppfeature_status = navi10_get_ppfeature_status,
-       .set_ppfeature_status = navi10_set_ppfeature_status,
         .set_performance_level = navi10_set_performance_level,
         .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
 };
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index c06a9472c3b2..52c8fc9f1ff4 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct smu_context *smu, bool enable)
         return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, enable);
 }

-static int vega20_get_enabled_smc_features(struct smu_context *smu,
-               uint64_t *features_enabled)
-{
-       uint32_t feature_mask[2] = {0, 0};
-       int ret = 0;
-
-       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
-       if (ret)
-               return ret;
-
-       *features_enabled = ((((uint64_t)feature_mask[0] << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
-                       (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK));
-
-       return ret;
-}
-
-static int vega20_enable_smc_features(struct smu_context *smu,
-               bool enable, uint64_t feature_mask)
-{
-       uint32_t smu_features_low, smu_features_high;
-       int ret = 0;
-
-       smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
-       smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
-
-       if (enable) {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       } else {
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-                                                 smu_features_low);
-               if (ret)
-                       return ret;
-               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-                                                 smu_features_high);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-
-}
-
-static int vega20_get_ppfeature_status(struct smu_context *smu, char *buf)
-{
-       static const char *ppfeature_name[] = {
-                               "DPM_PREFETCHER",
-                               "GFXCLK_DPM",
-                               "UCLK_DPM",
-                               "SOCCLK_DPM",
-                               "UVD_DPM",
-                               "VCE_DPM",
-                               "ULV",
-                               "MP0CLK_DPM",
-                               "LINK_DPM",
-                               "DCEFCLK_DPM",
-                               "GFXCLK_DS",
-                               "SOCCLK_DS",
-                               "LCLK_DS",
-                               "PPT",
-                               "TDC",
-                               "THERMAL",
-                               "GFX_PER_CU_CG",
-                               "RM",
-                               "DCEFCLK_DS",
-                               "ACDC",
-                               "VR0HOT",
-                               "VR1HOT",
-                               "FW_CTF",
-                               "LED_DISPLAY",
-                               "FAN_CONTROL",
-                               "GFX_EDC",
-                               "GFXOFF",
-                               "CG",
-                               "FCLK_DPM",
-                               "FCLK_DS",
-                               "MP1CLK_DS",
-                               "MP0CLK_DS",
-                               "XGMI",
-                               "ECC"};
-       static const char *output_title[] = {
-                               "FEATURES",
-                               "BITMASK",
-                               "ENABLEMENT"};
-       uint64_t features_enabled;
-       int i;
-       int ret = 0;
-       int size = 0;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", features_enabled);
-       size += sprintf(buf + size, "%-19s %-22s %s\n",
-                               output_title[0],
-                               output_title[1],
-                               output_title[2]);
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
-                                       ppfeature_name[i],
-                                       1ULL << i,
-                                       (features_enabled & (1ULL << i)) ? "Y" : "N");
-       }
-
-       return size;
-}
-
-static int vega20_set_ppfeature_status(struct smu_context *smu, uint64_t new_ppfeature_masks)
-{
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
-
-       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
-               return -EINVAL;
-
-       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
-       if (ret)
-               return ret;
-
-       features_to_disable =
-               features_enabled & ~new_ppfeature_masks;
-       features_to_enable =
-               ~features_enabled & new_ppfeature_masks;
-
-       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
-       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
-
-       if (features_to_disable) {
-               ret = vega20_enable_smc_features(smu, false, features_to_disable);
-               if (ret)
-                       return ret;
-       }
-
-       if (features_to_enable) {
-               ret = vega20_enable_smc_features(smu, true, features_to_enable);
-               if (ret)
-                       return ret;
-       }
-
-       return 0;
-}
-
 static bool vega20_is_dpm_running(struct smu_context *smu)
 {
         int ret = 0;
@@ -3311,8 +3160,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
         .force_dpm_limit_value = vega20_force_dpm_limit_value,
         .unforce_dpm_levels = vega20_unforce_dpm_levels,
         .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
-       .set_ppfeature_status = vega20_set_ppfeature_status,
-       .get_ppfeature_status = vega20_get_ppfeature_status,
         .is_dpm_running = vega20_is_dpm_running,
         .set_thermal_fan_table = vega20_set_thermal_fan_table,
         .get_fan_speed_percent = vega20_get_fan_speed_percent,
--
2.22.0

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_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply related	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                         ` <BN6PR12MB1809E62D6BFE3224637F25D9F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-25 13:14                           ` StDenis, Tom
       [not found]                             ` <f76aeb2d-01be-d629-72e9-a96f702a73e0-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: StDenis, Tom @ 2019-07-25 13:14 UTC (permalink / raw)
  To: Deucher, Alexander, Huang, Ray, Wang, Kevin(Yang),
	Quan, Evan, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang,
	Hawking
  Cc: Feng, Kenneth

No it doesn't.  We get clocks for --top from the sensors interface.


On 2019-07-25 9:01 a.m., Deucher, Alexander wrote:
> Tom, does umr use it?
>
> Alex
> ------------------------------------------------------------------------
> *From:* Huang, Ray <Ray.Huang@amd.com>
> *Sent:* Thursday, July 25, 2019 4:49 AM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang@amd.com>; Quan, Evan 
> <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org 
> <amd-gfx@lists.freedesktop.org>; Zhang, Hawking 
> <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
> *Cc:* Feng, Kenneth <Kenneth.Feng@amd.com>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature 
> status function in smu
>
> Any other user mode tool use the “ppfeature” sysfs interface?
>
> Thanks,
>
> Ray
>
> *From:* Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
> *Sent:* Thursday, July 25, 2019 4:44 PM
> *To:* Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org; 
> Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander 
> <Alexander.Deucher@amd.com>
> *Cc:* Huang, Ray <Ray.Huang@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature 
> status function in smu
>
> in fact, i don't want to change this sysfs name from "ppfeatures" to 
> "pp_features",
>
> but it seems that don't have same name format with other pp sysfs node.
>
> the other powerplay sysfs name have "pp_" prefix, i think we'd better 
> to change it name to "pp_features"
>
> eg:
>
> pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk 
>  pp_force_state  pp_num_states  pp_sclk_od
> pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od   
>    pp_power_profile_mode  pp_table
>
> @Deucher, Alexander <mailto:Alexander.Deucher@amd.com> @Zhang, Hawking 
> <mailto:Hawking.Zhang@amd.com>
>
> Could you give us some idea about it,
>
> Thanks.
>
> Best Regards,
> Kevin
>
> ------------------------------------------------------------------------
>
> *From:*Quan, Evan <Evan.Quan@amd.com <mailto:Evan.Quan@amd.com>>
> *Sent:* Thursday, July 25, 2019 4:30 PM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang@amd.com 
> <mailto:Kevin1.Wang@amd.com>>; amd-gfx@lists.freedesktop.org 
> <mailto:amd-gfx@lists.freedesktop.org> <amd-gfx@lists.freedesktop.org 
> <mailto:amd-gfx@lists.freedesktop.org>>
> *Cc:* Deucher, Alexander <Alexander.Deucher@amd.com 
> <mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang@amd.com 
> <mailto:Ray.Huang@amd.com>>; Feng, Kenneth <Kenneth.Feng@amd.com 
> <mailto:Kenneth.Feng@amd.com>>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature 
> status function in smu
>
> To keep backward compatibility, we cannot change the sysfs file naming.
>
> But it’s a good idea to summarize these as common APIs.
>
> Regards,
>
> Evan
>
> *From:* amd-gfx <amd-gfx-bounces@lists.freedesktop.org 
> <mailto:amd-gfx-bounces@lists.freedesktop.org>> *On Behalf Of *Wang, 
> Kevin(Yang)
> *Sent:* Thursday, July 25, 2019 4:10 PM
> *To:* amd-gfx@lists.freedesktop.org <mailto:amd-gfx@lists.freedesktop.org>
> *Cc:* Deucher, Alexander <Alexander.Deucher@amd.com 
> <mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang@amd.com 
> <mailto:Ray.Huang@amd.com>>; Feng, Kenneth <Kenneth.Feng@amd.com 
> <mailto:Kenneth.Feng@amd.com>>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature 
> status function in smu
>
> add sample data from sysfs pp_features with this patch.
>
> print format:
>
> index. feature name (Hardware Message ID): state
>
> /sudo find /sys -name "pp_features" -exec cat {} \;/
>
> features high: 0x00000623 low: 0xb3cdaffb
>
> 00. DPM_PREFETCHER       ( 0) : enabeld
>
> 01. DPM_GFXCLK           ( 1) : enabeld
>
> 02. DPM_UCLK             ( 3) : enabeld
>
> 03. DPM_SOCCLK           ( 4) : enabeld
>
> 04. DPM_MP0CLK           ( 5) : enabeld
>
> 05. DPM_LINK             ( 6) : enabeld
>
> 06. DPM_DCEFCLK          ( 7) : enabeld
>
> 07. DS_GFXCLK            (10) : enabeld
>
> 08. DS_SOCCLK            (11) : enabeld
>
> 09. DS_LCLK              (12) : disabled
>
> 10. PPT                (23) : enabeld
>
> 11. TDC                (24) : enabeld
>
> 12. THERMAL              (33) : enabeld
>
> 13. RM                 (35) : disabled
>
> 14. DS_DCEFCLK           (13) : enabeld
>
> 15. ACDC                 (28) : enabeld
>
> 16. VR0HOT               (29) : enabeld
>
> 17. VR1HOT               (30) : disabled
>
> 18. FW_CTF               (31) : enabeld
>
> 19. LED_DISPLAY          (36) : disabled
>
> 20. FAN_CONTROL          (32) : enabeld
>
> 21. GFX_EDC              (25) : enabeld
>
> 22. GFXOFF               (17) : disabled
>
> 23. DPM_GFX_PACE         ( 2) : disabled
>
> 24. MEM_VDDCI_SCALING    ( 8) : enabeld
>
> 25. MEM_MVDD_SCALING     ( 9) : enabeld
>
> 26. DS_UCLK              (14) : disabled
>
> 27. GFX_ULV              (15) : enabeld
>
> 28. FW_DSTATE            (16) : enabeld
>
> 29. BACO                 (18) : enabeld
>
> 30. VCN_PG               (19) : enabeld
>
> 31. JPEG_PG              (20) : disabled
>
> 32. USB_PG               (21) : disabled
>
> 33. RSMU_SMN_CG          (22) : enabeld
>
> 34. APCC_PLUS            (26) : disabled
>
> 35. GTHR                 (27) : disabled
>
> 36. GFX_DCS              (34) : disabled
>
> 37. GFX_SS               (37) : enabeld
>
> 38. OUT_OF_BAND_MONITOR  (38) : disabled
>
> 39. TEMP_DEPENDENT_VMIN  (39) : disabled
>
> 40. MMHUB_PG             (40) : disabled
>
> 41. ATHUB_PG             (41) : enabeld
>
> ------------------------------------------------------------------------
>
> *From:*Wang, Kevin(Yang) <Kevin1.Wang@amd.com 
> <mailto:Kevin1.Wang@amd.com>>
> *Sent:* Thursday, July 25, 2019 1:11 PM
> *To:* amd-gfx@lists.freedesktop.org 
> <mailto:amd-gfx@lists.freedesktop.org> <amd-gfx@lists.freedesktop.org 
> <mailto:amd-gfx@lists.freedesktop.org>>
> *Cc:* Feng, Kenneth <Kenneth.Feng@amd.com 
> <mailto:Kenneth.Feng@amd.com>>; Huang, Ray <Ray.Huang@amd.com 
> <mailto:Ray.Huang@amd.com>>; Deucher, Alexander 
> <Alexander.Deucher@amd.com <mailto:Alexander.Deucher@amd.com>>; Wang, 
> Kevin(Yang) <Kevin1.Wang@amd.com <mailto:Kevin1.Wang@amd.com>>
> *Subject:* [PATCH 5/5] drm/amd/powerplay: implment sysfs feature 
> status function in smu
>
> 1. Unified feature enable status format in sysfs
> 2. Rename ppfeature to pp_features to adapt other pp sysfs node name
> 3. this function support all asic, not asic related function.
>
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com 
> <mailto:kevin1.wang@amd.com>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  24 +--
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  61 +++++++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   8 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
>  5 files changed, 75 insertions(+), 336 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 866097d5cf26..9e8e8a65d9bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -788,10 +788,10 @@ static ssize_t 
> amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  }
>
>  /**
> - * DOC: ppfeatures
> + * DOC: pp_features
>   *
>   * The amdgpu driver provides a sysfs API for adjusting what powerplay
> - * features to be enabled. The file ppfeatures is used for this. And
> + * features to be enabled. The file pp_features is used for this. And
>   * this is only available for Vega10 and later dGPUs.
>   *
>   * Reading back the file will show you the followings:
> @@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct 
> device *dev,
>   * the corresponding bit from original ppfeature masks and input the
>   * new ppfeature masks.
>   */
> -static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  const char *buf,
>                  size_t count)
> @@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct 
> device *dev,
>          pr_debug("featuremask = 0x%llx\n", featuremask);
>
>          if (is_support_sw_smu(adev)) {
> -               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
> +               ret = smu_sys_set_pp_feature_mask(&adev->smu, 
> featuremask);
>                  if (ret)
>                          return -EINVAL;
>          } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
> @@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct 
> device *dev,
>          return count;
>  }
>
> -static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  char *buf)
>  {
> @@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct 
> device *dev,
>          struct amdgpu_device *adev = ddev->dev_private;
>
>          if (is_support_sw_smu(adev)) {
> -               return smu_get_ppfeature_status(&adev->smu, buf);
> +               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
>          } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
>                  return amdgpu_dpm_get_ppfeature_status(adev, buf);
>
> @@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
>  static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
>                  amdgpu_get_memory_busy_percent, NULL);
>  static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
> -static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
> -               amdgpu_get_ppfeature_status,
> -               amdgpu_set_ppfeature_status);
> +static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
> +               amdgpu_get_pp_feature_status,
> +               amdgpu_set_pp_feature_status);
>  static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> @@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device 
> *adev)
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU)) {
>                  ret = device_create_file(adev->dev,
> - &dev_attr_ppfeatures);
> + &dev_attr_pp_features);
>                  if (ret) {
>                          DRM_ERROR("failed to create device file "
> - "ppfeatures\n");
> + "pp_features\n");
>                          return ret;
>                  }
>          }
> @@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device 
> *adev)
> device_remove_file(adev->dev, &dev_attr_unique_id);
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU))
> -               device_remove_file(adev->dev, &dev_attr_ppfeatures);
> +               device_remove_file(adev->dev, &dev_attr_pp_features);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index e881de955388..90833ff2fe00 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context 
> *smu, enum smu_feature_mask
>          return __smu_feature_names[feature];
>  }
>
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
> +{
> +       size_t size = 0;
> +       int ret = 0, i = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       int32_t feature_index = 0;
> +       uint32_t count = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               goto failed;
> +
> +       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
> +                       feature_mask[1], feature_mask[0]);
> +
> +       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
> +               feature_index = smu_feature_get_index(smu, i);
> +               if (feature_index < 0)
> +                       continue;
> +               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
> +                              count++,
> + smu_get_feature_name(smu, i),
> +                              feature_index,
> + !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
> +       }
> +
> +failed:
> +       return size;
> +}
> +
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t 
> new_mask)
> +{
> +       int ret = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       uint64_t feature_2_enabled = 0;
> +       uint64_t feature_2_disabled = 0;
> +       uint64_t feature_enables = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               return ret;
> +
> +       feature_enables = ((uint64_t)feature_mask[1] << 32 | 
> (uint64_t)feature_mask[0]);
> +
> +       feature_2_enabled  = ~feature_enables & new_mask;
> +       feature_2_disabled = feature_enables & ~new_mask;
> +
> +       if (feature_2_enabled) {
> +               ret = smu_feature_update_enable_state(smu, 
> feature_2_enabled, true);
> +               if (ret)
> +                       ret;
> +       }
> +       if (feature_2_disabled) {
> +               ret = smu_feature_update_enable_state(smu, 
> feature_2_disabled, false);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return ret;
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t 
> *if_version, uint32_t *smu_version)
>  {
>          int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index abc2644b4c07..ac9e9d5d8a5c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -432,8 +432,6 @@ struct pptable_funcs {
>                                        uint32_t *mclk_mask,
>                                        uint32_t *soc_mask);
>          int (*set_cpu_power_state)(struct smu_context *smu);
> -       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t 
> ppfeatures);
> -       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
>          bool (*is_dpm_running)(struct smu_context *smu);
>          int (*tables_init)(struct smu_context *smu, struct smu_table 
> *tables);
>          int (*set_thermal_fan_table)(struct smu_context *smu);
> @@ -713,10 +711,6 @@ struct smu_funcs
> ((smu)->ppt_funcs->dpm_set_vce_enable ? 
> (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
>  #define smu_set_xgmi_pstate(smu, pstate) \
> ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), 
> (pstate)) : 0)
> -#define smu_set_ppfeature_status(smu, ppfeatures) \
> - ((smu)->ppt_funcs->set_ppfeature_status ? 
> (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
> -#define smu_get_ppfeature_status(smu, buf) \
> - ((smu)->ppt_funcs->get_ppfeature_status ? 
> (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
>  #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> ((smu)->ppt_funcs->set_watermarks_table ? 
> (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
>  #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> @@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context 
> *smu, enum smu_clk_type clk_type)
>  int smu_feature_update_enable_state(struct smu_context *smu, uint64_t 
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum 
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum 
> smu_feature_mask feature);
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t 
> new_mask);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228bf05f..cd0920093a5e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct 
> smu_context *smu, uint32_t *clocks_
>          return 0;
>  }
>
> -static int navi10_get_ppfeature_status(struct smu_context *smu,
> -                                      char *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "DPM_GFXCLK",
> -                               "DPM_GFX_PACE",
> -                               "DPM_UCLK",
> -                               "DPM_SOCCLK",
> -                               "DPM_MP0CLK",
> -                               "DPM_LINK",
> -                               "DPM_DCEFCLK",
> - "MEM_VDDCI_SCALING",
> - "MEM_MVDD_SCALING",
> -                               "DS_GFXCLK",
> -                               "DS_SOCCLK",
> -                               "DS_LCLK",
> -                               "DS_DCEFCLK",
> -                               "DS_UCLK",
> -                               "GFX_ULV",
> -                               "FW_DSTATE",
> -                               "GFXOFF",
> -                               "BACO",
> -                               "VCN_PG",
> -                               "JPEG_PG",
> -                               "USB_PG",
> -                               "RSMU_SMN_CG",
> -                               "PPT",
> -                               "TDC",
> -                               "GFX_EDC",
> -                               "APCC_PLUS",
> -                               "GTHR",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "FAN_CONTROL",
> -                               "THERMAL",
> -                               "GFX_DCS",
> -                               "RM",
> -                               "LED_DISPLAY",
> -                               "GFX_SS",
> - "OUT_OF_BAND_MONITOR",
> - "TEMP_DEPENDENT_VMIN",
> -                               "MMHUB_PG",
> -                               "ATHUB_PG"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[GetPPfeatureStatus] Failed to get enabled 
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", 
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < (sizeof(ppfeature_name) / 
> sizeof(ppfeature_name[0])); i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int navi10_enable_smc_features(struct smu_context *smu,
> -                                     bool enabled,
> -                                     uint64_t feature_masks)
> -{
> -       struct smu_feature *feature = &smu->smu_feature;
> -       uint32_t feature_low, feature_high;
> -       uint32_t feature_mask[2];
> -       int ret = 0;
> -
> -       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
> -       feature_high = (uint32_t)((feature_masks & 
> 0xFFFFFFFF00000000ULL) >> 32);
> -
> -       if (enabled) {
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       mutex_lock(&feature->mutex);
> -       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
> -                   feature->feature_num);
> -       mutex_unlock(&feature->mutex);
> -
> -       return 0;
> -}
> -
> -static int navi10_set_ppfeature_status(struct smu_context *smu,
> -                                      uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[SetPPfeatureStatus] Failed to get enabled 
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = navi10_enable_smc_features(smu, false, 
> features_to_disable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to disable smc features!",
> -                               return ret);
> -       }
> -
> -       if (features_to_enable) {
> -               ret = navi10_enable_smc_features(smu, true, 
> features_to_enable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to enable smc features!",
> -                               return ret);
> -       }
> -
> -       return 0;
> -}
> -
>  static int navi10_set_peak_clock_by_device(struct smu_context *smu)
>  {
>          struct amdgpu_device *adev = smu->adev;
> @@ -1689,8 +1526,6 @@ static const struct pptable_funcs 
> navi10_ppt_funcs = {
>          .set_watermarks_table = navi10_set_watermarks_table,
>          .read_sensor = navi10_read_sensor,
>          .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
> -       .get_ppfeature_status = navi10_get_ppfeature_status,
> -       .set_ppfeature_status = navi10_set_ppfeature_status,
>          .set_performance_level = navi10_set_performance_level,
>          .get_thermal_temperature_range = 
> navi10_get_thermal_temperature_range,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c 
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c06a9472c3b2..52c8fc9f1ff4 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct 
> smu_context *smu, bool enable)
>          return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT, 
> enable);
>  }
>
> -static int vega20_get_enabled_smc_features(struct smu_context *smu,
> -               uint64_t *features_enabled)
> -{
> -       uint32_t feature_mask[2] = {0, 0};
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       *features_enabled = ((((uint64_t)feature_mask[0] << 
> SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
> - (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) & 
> SMU_FEATURES_HIGH_MASK));
> -
> -       return ret;
> -}
> -
> -static int vega20_enable_smc_features(struct smu_context *smu,
> -               bool enable, uint64_t feature_mask)
> -{
> -       uint32_t smu_features_low, smu_features_high;
> -       int ret = 0;
> -
> -       smu_features_low = (uint32_t)((feature_mask & 
> SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
> -       smu_features_high = (uint32_t)((feature_mask & 
> SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
> -
> -       if (enable) {
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu, 
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -
> -}
> -
> -static int vega20_get_ppfeature_status(struct smu_context *smu, char 
> *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "GFXCLK_DPM",
> -                               "UCLK_DPM",
> -                               "SOCCLK_DPM",
> -                               "UVD_DPM",
> -                               "VCE_DPM",
> -                               "ULV",
> -                               "MP0CLK_DPM",
> -                               "LINK_DPM",
> -                               "DCEFCLK_DPM",
> -                               "GFXCLK_DS",
> -                               "SOCCLK_DS",
> -                               "LCLK_DS",
> -                               "PPT",
> -                               "TDC",
> -                               "THERMAL",
> -                               "GFX_PER_CU_CG",
> -                               "RM",
> -                               "DCEFCLK_DS",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "LED_DISPLAY",
> -                               "FAN_CONTROL",
> -                               "GFX_EDC",
> -                               "GFXOFF",
> -                               "CG",
> -                               "FCLK_DPM",
> -                               "FCLK_DS",
> -                               "MP1CLK_DS",
> -                               "MP0CLK_DS",
> -                               "XGMI",
> -                               "ECC"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n", 
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int vega20_set_ppfeature_status(struct smu_context *smu, 
> uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
> -               return -EINVAL;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = vega20_enable_smc_features(smu, false, 
> features_to_disable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       if (features_to_enable) {
> -               ret = vega20_enable_smc_features(smu, true, 
> features_to_enable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -}
> -
>  static bool vega20_is_dpm_running(struct smu_context *smu)
>  {
>          int ret = 0;
> @@ -3311,8 +3160,6 @@ static const struct pptable_funcs 
> vega20_ppt_funcs = {
>          .force_dpm_limit_value = vega20_force_dpm_limit_value,
>          .unforce_dpm_levels = vega20_unforce_dpm_levels,
>          .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
> -       .set_ppfeature_status = vega20_set_ppfeature_status,
> -       .get_ppfeature_status = vega20_get_ppfeature_status,
>          .is_dpm_running = vega20_is_dpm_running,
>          .set_thermal_fan_table = vega20_set_thermal_fan_table,
>          .get_fan_speed_percent = vega20_get_fan_speed_percent,
> -- 
> 2.22.0
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                             ` <f76aeb2d-01be-d629-72e9-a96f702a73e0-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-26  9:05                               ` Wang, Kevin(Yang)
       [not found]                                 ` <BN8PR12MB3283A9239266F64A93F2E3DDA2C00-h6+T2+wrnx1KUVg95YpnwwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  0 siblings, 1 reply; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-26  9:05 UTC (permalink / raw)
  To: StDenis, Tom, Deucher, Alexander, Huang, Ray, Quan, Evan,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang, Hawking
  Cc: Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 33597 bytes --]

@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>

Hi Alex,

it seems not application will use this sysfs, can we rename it from "ppfeatures" to "pp_features"?
this patch sets is pending.

Best Regards,
Kevin
________________________________
From: StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 9:14 PM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan@amd.com>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

No it doesn't.  We get clocks for --top from the sensors interface.


On 2019-07-25 9:01 a.m., Deucher, Alexander wrote:
> Tom, does umr use it?
>
> Alex
> ------------------------------------------------------------------------
> *From:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Thursday, July 25, 2019 4:49 AM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan
> <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking
> <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> Any other user mode tool use the “ppfeature” sysfs interface?
>
> Thanks,
>
> Ray
>
> *From:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Thursday, July 25, 2019 4:44 PM
> *To:* Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org;
> Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
> *Cc:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> in fact, i don't want to change this sysfs name from "ppfeatures" to
> "pp_features",
>
> but it seems that don't have same name format with other pp sysfs node.
>
> the other powerplay sysfs name have "pp_" prefix, i think we'd better
> to change it name to "pp_features"
>
> eg:
>
> pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk
>  pp_force_state  pp_num_states  pp_sclk_od
> pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od
>    pp_power_profile_mode  pp_table
>
> @Deucher, Alexander <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking
> <mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
>
> Could you give us some idea about it,
>
> Thanks.
>
> Best Regards,
> Kevin
>
> ------------------------------------------------------------------------
>
> *From:*Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org <mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 4:30 PM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> To keep backward compatibility, we cannot change the sysfs file naming.
>
> But it’s a good idea to summarize these as common APIs.
>
> Regards,
>
> Evan
>
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>> *On Behalf Of *Wang,
> Kevin(Yang)
> *Sent:* Thursday, July 25, 2019 4:10 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> add sample data from sysfs pp_features with this patch.
>
> print format:
>
> index. feature name (Hardware Message ID): state
>
> /sudo find /sys -name "pp_features" -exec cat {} \;/
>
> features high: 0x00000623 low: 0xb3cdaffb
>
> 00. DPM_PREFETCHER       ( 0) : enabeld
>
> 01. DPM_GFXCLK           ( 1) : enabeld
>
> 02. DPM_UCLK             ( 3) : enabeld
>
> 03. DPM_SOCCLK           ( 4) : enabeld
>
> 04. DPM_MP0CLK           ( 5) : enabeld
>
> 05. DPM_LINK             ( 6) : enabeld
>
> 06. DPM_DCEFCLK          ( 7) : enabeld
>
> 07. DS_GFXCLK            (10) : enabeld
>
> 08. DS_SOCCLK            (11) : enabeld
>
> 09. DS_LCLK              (12) : disabled
>
> 10. PPT                (23) : enabeld
>
> 11. TDC                (24) : enabeld
>
> 12. THERMAL              (33) : enabeld
>
> 13. RM                 (35) : disabled
>
> 14. DS_DCEFCLK           (13) : enabeld
>
> 15. ACDC                 (28) : enabeld
>
> 16. VR0HOT               (29) : enabeld
>
> 17. VR1HOT               (30) : disabled
>
> 18. FW_CTF               (31) : enabeld
>
> 19. LED_DISPLAY          (36) : disabled
>
> 20. FAN_CONTROL          (32) : enabeld
>
> 21. GFX_EDC              (25) : enabeld
>
> 22. GFXOFF               (17) : disabled
>
> 23. DPM_GFX_PACE         ( 2) : disabled
>
> 24. MEM_VDDCI_SCALING    ( 8) : enabeld
>
> 25. MEM_MVDD_SCALING     ( 9) : enabeld
>
> 26. DS_UCLK              (14) : disabled
>
> 27. GFX_ULV              (15) : enabeld
>
> 28. FW_DSTATE            (16) : enabeld
>
> 29. BACO                 (18) : enabeld
>
> 30. VCN_PG               (19) : enabeld
>
> 31. JPEG_PG              (20) : disabled
>
> 32. USB_PG               (21) : disabled
>
> 33. RSMU_SMN_CG          (22) : enabeld
>
> 34. APCC_PLUS            (26) : disabled
>
> 35. GTHR                 (27) : disabled
>
> 36. GFX_DCS              (34) : disabled
>
> 37. GFX_SS               (37) : enabeld
>
> 38. OUT_OF_BAND_MONITOR  (38) : disabled
>
> 39. TEMP_DEPENDENT_VMIN  (39) : disabled
>
> 40. MMHUB_PG             (40) : disabled
>
> 41. ATHUB_PG             (41) : enabeld
>
> ------------------------------------------------------------------------
>
> *From:*Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 1:11 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang,
> Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> 1. Unified feature enable status format in sysfs
> 2. Rename ppfeature to pp_features to adapt other pp sysfs node name
> 3. this function support all asic, not asic related function.
>
> Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org
> <mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  24 +--
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  61 +++++++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   8 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
>  5 files changed, 75 insertions(+), 336 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 866097d5cf26..9e8e8a65d9bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -788,10 +788,10 @@ static ssize_t
> amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  }
>
>  /**
> - * DOC: ppfeatures
> + * DOC: pp_features
>   *
>   * The amdgpu driver provides a sysfs API for adjusting what powerplay
> - * features to be enabled. The file ppfeatures is used for this. And
> + * features to be enabled. The file pp_features is used for this. And
>   * this is only available for Vega10 and later dGPUs.
>   *
>   * Reading back the file will show you the followings:
> @@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct
> device *dev,
>   * the corresponding bit from original ppfeature masks and input the
>   * new ppfeature masks.
>   */
> -static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  const char *buf,
>                  size_t count)
> @@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          pr_debug("featuremask = 0x%llx\n", featuremask);
>
>          if (is_support_sw_smu(adev)) {
> -               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
> +               ret = smu_sys_set_pp_feature_mask(&adev->smu,
> featuremask);
>                  if (ret)
>                          return -EINVAL;
>          } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
> @@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          return count;
>  }
>
> -static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  char *buf)
>  {
> @@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct
> device *dev,
>          struct amdgpu_device *adev = ddev->dev_private;
>
>          if (is_support_sw_smu(adev)) {
> -               return smu_get_ppfeature_status(&adev->smu, buf);
> +               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
>          } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
>                  return amdgpu_dpm_get_ppfeature_status(adev, buf);
>
> @@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
>  static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
>                  amdgpu_get_memory_busy_percent, NULL);
>  static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
> -static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
> -               amdgpu_get_ppfeature_status,
> -               amdgpu_set_ppfeature_status);
> +static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
> +               amdgpu_get_pp_feature_status,
> +               amdgpu_set_pp_feature_status);
>  static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> @@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev)
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU)) {
>                  ret = device_create_file(adev->dev,
> - &dev_attr_ppfeatures);
> + &dev_attr_pp_features);
>                  if (ret) {
>                          DRM_ERROR("failed to create device file "
> - "ppfeatures\n");
> + "pp_features\n");
>                          return ret;
>                  }
>          }
> @@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device
> *adev)
> device_remove_file(adev->dev, &dev_attr_unique_id);
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU))
> -               device_remove_file(adev->dev, &dev_attr_ppfeatures);
> +               device_remove_file(adev->dev, &dev_attr_pp_features);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index e881de955388..90833ff2fe00 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context
> *smu, enum smu_feature_mask
>          return __smu_feature_names[feature];
>  }
>
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
> +{
> +       size_t size = 0;
> +       int ret = 0, i = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       int32_t feature_index = 0;
> +       uint32_t count = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               goto failed;
> +
> +       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
> +                       feature_mask[1], feature_mask[0]);
> +
> +       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
> +               feature_index = smu_feature_get_index(smu, i);
> +               if (feature_index < 0)
> +                       continue;
> +               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
> +                              count++,
> + smu_get_feature_name(smu, i),
> +                              feature_index,
> + !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
> +       }
> +
> +failed:
> +       return size;
> +}
> +
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask)
> +{
> +       int ret = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       uint64_t feature_2_enabled = 0;
> +       uint64_t feature_2_disabled = 0;
> +       uint64_t feature_enables = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               return ret;
> +
> +       feature_enables = ((uint64_t)feature_mask[1] << 32 |
> (uint64_t)feature_mask[0]);
> +
> +       feature_2_enabled  = ~feature_enables & new_mask;
> +       feature_2_disabled = feature_enables & ~new_mask;
> +
> +       if (feature_2_enabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> +               if (ret)
> +                       ret;
> +       }
> +       if (feature_2_disabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return ret;
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t
> *if_version, uint32_t *smu_version)
>  {
>          int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index abc2644b4c07..ac9e9d5d8a5c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -432,8 +432,6 @@ struct pptable_funcs {
>                                        uint32_t *mclk_mask,
>                                        uint32_t *soc_mask);
>          int (*set_cpu_power_state)(struct smu_context *smu);
> -       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t
> ppfeatures);
> -       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
>          bool (*is_dpm_running)(struct smu_context *smu);
>          int (*tables_init)(struct smu_context *smu, struct smu_table
> *tables);
>          int (*set_thermal_fan_table)(struct smu_context *smu);
> @@ -713,10 +711,6 @@ struct smu_funcs
> ((smu)->ppt_funcs->dpm_set_vce_enable ?
> (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
>  #define smu_set_xgmi_pstate(smu, pstate) \
> ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu),
> (pstate)) : 0)
> -#define smu_set_ppfeature_status(smu, ppfeatures) \
> - ((smu)->ppt_funcs->set_ppfeature_status ?
> (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
> -#define smu_get_ppfeature_status(smu, buf) \
> - ((smu)->ppt_funcs->get_ppfeature_status ?
> (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
>  #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> ((smu)->ppt_funcs->set_watermarks_table ?
> (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
>  #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> @@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context
> *smu, enum smu_clk_type clk_type)
>  int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum
> smu_feature_mask feature);
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228bf05f..cd0920093a5e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct
> smu_context *smu, uint32_t *clocks_
>          return 0;
>  }
>
> -static int navi10_get_ppfeature_status(struct smu_context *smu,
> -                                      char *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "DPM_GFXCLK",
> -                               "DPM_GFX_PACE",
> -                               "DPM_UCLK",
> -                               "DPM_SOCCLK",
> -                               "DPM_MP0CLK",
> -                               "DPM_LINK",
> -                               "DPM_DCEFCLK",
> - "MEM_VDDCI_SCALING",
> - "MEM_MVDD_SCALING",
> -                               "DS_GFXCLK",
> -                               "DS_SOCCLK",
> -                               "DS_LCLK",
> -                               "DS_DCEFCLK",
> -                               "DS_UCLK",
> -                               "GFX_ULV",
> -                               "FW_DSTATE",
> -                               "GFXOFF",
> -                               "BACO",
> -                               "VCN_PG",
> -                               "JPEG_PG",
> -                               "USB_PG",
> -                               "RSMU_SMN_CG",
> -                               "PPT",
> -                               "TDC",
> -                               "GFX_EDC",
> -                               "APCC_PLUS",
> -                               "GTHR",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "FAN_CONTROL",
> -                               "THERMAL",
> -                               "GFX_DCS",
> -                               "RM",
> -                               "LED_DISPLAY",
> -                               "GFX_SS",
> - "OUT_OF_BAND_MONITOR",
> - "TEMP_DEPENDENT_VMIN",
> -                               "MMHUB_PG",
> -                               "ATHUB_PG"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[GetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < (sizeof(ppfeature_name) /
> sizeof(ppfeature_name[0])); i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int navi10_enable_smc_features(struct smu_context *smu,
> -                                     bool enabled,
> -                                     uint64_t feature_masks)
> -{
> -       struct smu_feature *feature = &smu->smu_feature;
> -       uint32_t feature_low, feature_high;
> -       uint32_t feature_mask[2];
> -       int ret = 0;
> -
> -       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
> -       feature_high = (uint32_t)((feature_masks &
> 0xFFFFFFFF00000000ULL) >> 32);
> -
> -       if (enabled) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       mutex_lock(&feature->mutex);
> -       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
> -                   feature->feature_num);
> -       mutex_unlock(&feature->mutex);
> -
> -       return 0;
> -}
> -
> -static int navi10_set_ppfeature_status(struct smu_context *smu,
> -                                      uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[SetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = navi10_enable_smc_features(smu, false,
> features_to_disable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to disable smc features!",
> -                               return ret);
> -       }
> -
> -       if (features_to_enable) {
> -               ret = navi10_enable_smc_features(smu, true,
> features_to_enable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to enable smc features!",
> -                               return ret);
> -       }
> -
> -       return 0;
> -}
> -
>  static int navi10_set_peak_clock_by_device(struct smu_context *smu)
>  {
>          struct amdgpu_device *adev = smu->adev;
> @@ -1689,8 +1526,6 @@ static const struct pptable_funcs
> navi10_ppt_funcs = {
>          .set_watermarks_table = navi10_set_watermarks_table,
>          .read_sensor = navi10_read_sensor,
>          .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
> -       .get_ppfeature_status = navi10_get_ppfeature_status,
> -       .set_ppfeature_status = navi10_set_ppfeature_status,
>          .set_performance_level = navi10_set_performance_level,
>          .get_thermal_temperature_range =
> navi10_get_thermal_temperature_range,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c06a9472c3b2..52c8fc9f1ff4 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct
> smu_context *smu, bool enable)
>          return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT,
> enable);
>  }
>
> -static int vega20_get_enabled_smc_features(struct smu_context *smu,
> -               uint64_t *features_enabled)
> -{
> -       uint32_t feature_mask[2] = {0, 0};
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       *features_enabled = ((((uint64_t)feature_mask[0] <<
> SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
> - (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) &
> SMU_FEATURES_HIGH_MASK));
> -
> -       return ret;
> -}
> -
> -static int vega20_enable_smc_features(struct smu_context *smu,
> -               bool enable, uint64_t feature_mask)
> -{
> -       uint32_t smu_features_low, smu_features_high;
> -       int ret = 0;
> -
> -       smu_features_low = (uint32_t)((feature_mask &
> SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
> -       smu_features_high = (uint32_t)((feature_mask &
> SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
> -
> -       if (enable) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -
> -}
> -
> -static int vega20_get_ppfeature_status(struct smu_context *smu, char
> *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "GFXCLK_DPM",
> -                               "UCLK_DPM",
> -                               "SOCCLK_DPM",
> -                               "UVD_DPM",
> -                               "VCE_DPM",
> -                               "ULV",
> -                               "MP0CLK_DPM",
> -                               "LINK_DPM",
> -                               "DCEFCLK_DPM",
> -                               "GFXCLK_DS",
> -                               "SOCCLK_DS",
> -                               "LCLK_DS",
> -                               "PPT",
> -                               "TDC",
> -                               "THERMAL",
> -                               "GFX_PER_CU_CG",
> -                               "RM",
> -                               "DCEFCLK_DS",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "LED_DISPLAY",
> -                               "FAN_CONTROL",
> -                               "GFX_EDC",
> -                               "GFXOFF",
> -                               "CG",
> -                               "FCLK_DPM",
> -                               "FCLK_DS",
> -                               "MP1CLK_DS",
> -                               "MP0CLK_DS",
> -                               "XGMI",
> -                               "ECC"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int vega20_set_ppfeature_status(struct smu_context *smu,
> uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
> -               return -EINVAL;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = vega20_enable_smc_features(smu, false,
> features_to_disable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       if (features_to_enable) {
> -               ret = vega20_enable_smc_features(smu, true,
> features_to_enable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -}
> -
>  static bool vega20_is_dpm_running(struct smu_context *smu)
>  {
>          int ret = 0;
> @@ -3311,8 +3160,6 @@ static const struct pptable_funcs
> vega20_ppt_funcs = {
>          .force_dpm_limit_value = vega20_force_dpm_limit_value,
>          .unforce_dpm_levels = vega20_unforce_dpm_levels,
>          .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
> -       .set_ppfeature_status = vega20_set_ppfeature_status,
> -       .get_ppfeature_status = vega20_get_ppfeature_status,
>          .is_dpm_running = vega20_is_dpm_running,
>          .set_thermal_fan_table = vega20_set_thermal_fan_table,
>          .get_fan_speed_percent = vega20_get_fan_speed_percent,
> --
> 2.22.0
>

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_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                                 ` <BN8PR12MB3283A9239266F64A93F2E3DDA2C00-h6+T2+wrnx1KUVg95YpnwwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-26 12:47                                   ` Huang, Ray
  2019-07-26 14:27                                   ` Deucher, Alexander
  1 sibling, 0 replies; 23+ messages in thread
From: Huang, Ray @ 2019-07-26 12:47 UTC (permalink / raw)
  To: Wang, Kevin(Yang),
	StDenis, Tom, Deucher, Alexander, Quan, Evan,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang, Hawking
  Cc: Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 36616 bytes --]

I am fine to align the interface name if no user mode use.

Acked-by: Huang Rui <ray.huang-5C7GfCeVMHo@public.gmane.org>

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, July 26, 2019 5:05 PM
To: StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>

Hi Alex,

it seems not application will use this sysfs, can we rename it from "ppfeatures" to "pp_features"?
this patch sets is pending.

Best Regards,
Kevin
________________________________
From: StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org<mailto:Tom.StDenis-5C7GfCeVMHo@public.gmane.org>>
Sent: Thursday, July 25, 2019 9:14 PM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

No it doesn't.  We get clocks for --top from the sensors interface.


On 2019-07-25 9:01 a.m., Deucher, Alexander wrote:
> Tom, does umr use it?
>
> Alex
> ------------------------------------------------------------------------
> *From:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 4:49 AM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; Quan, Evan
> <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9/rsn8yoX9R0@public.gmane.orgorg<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>; Zhang, Hawking
> <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> Any other user mode tool use the "ppfeature" sysfs interface?
>
> Thanks,
>
> Ray
>
> *From:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 4:44 PM
> *To:* Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>;
> Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org<mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>
> *Cc:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> in fact, i don't want to change this sysfs name from "ppfeatures" to
> "pp_features",
>
> but it seems that don't have same name format with other pp sysfs node.
>
> the other powerplay sysfs name have "pp_" prefix, i think we'd better
> to change it name to "pp_features"
>
> eg:
>
> pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk
>  pp_force_state  pp_num_states  pp_sclk_od
> pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od
>    pp_power_profile_mode  pp_table
>
> @Deucher, Alexander <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking
> <mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
>
> Could you give us some idea about it,
>
> Thanks.
>
> Best Regards,
> Kevin
>
> ------------------------------------------------------------------------
>
> *From:*Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org <mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 4:30 PM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org%20%0b>> <mailto:amd-gfx-PD4FTy7X32mqWrfYKbYh0A@public.gmane.orgktop.org>>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> To keep backward compatibility, we cannot change the sysfs file naming.
>
> But it's a good idea to summarize these as common APIs.
>
> Regards,
>
> Evan
>
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
<mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org%20%0b>> <mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>> *On Behalf Of *Wang,
> Kevin(Yang)
> *Sent:* Thursday, July 25, 2019 4:10 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> add sample data from sysfs pp_features with this patch.
>
> print format:
>
> index. feature name (Hardware Message ID): state
>
> /sudo find /sys -name "pp_features" -exec cat {} \;/
>
> features high: 0x00000623 low: 0xb3cdaffb
>
> 00. DPM_PREFETCHER       ( 0) : enabeld
>
> 01. DPM_GFXCLK           ( 1) : enabeld
>
> 02. DPM_UCLK             ( 3) : enabeld
>
> 03. DPM_SOCCLK           ( 4) : enabeld
>
> 04. DPM_MP0CLK           ( 5) : enabeld
>
> 05. DPM_LINK             ( 6) : enabeld
>
> 06. DPM_DCEFCLK          ( 7) : enabeld
>
> 07. DS_GFXCLK            (10) : enabeld
>
> 08. DS_SOCCLK            (11) : enabeld
>
> 09. DS_LCLK              (12) : disabled
>
> 10. PPT                (23) : enabeld
>
> 11. TDC                (24) : enabeld
>
> 12. THERMAL              (33) : enabeld
>
> 13. RM                 (35) : disabled
>
> 14. DS_DCEFCLK           (13) : enabeld
>
> 15. ACDC                 (28) : enabeld
>
> 16. VR0HOT               (29) : enabeld
>
> 17. VR1HOT               (30) : disabled
>
> 18. FW_CTF               (31) : enabeld
>
> 19. LED_DISPLAY          (36) : disabled
>
> 20. FAN_CONTROL          (32) : enabeld
>
> 21. GFX_EDC              (25) : enabeld
>
> 22. GFXOFF               (17) : disabled
>
> 23. DPM_GFX_PACE         ( 2) : disabled
>
> 24. MEM_VDDCI_SCALING    ( 8) : enabeld
>
> 25. MEM_MVDD_SCALING     ( 9) : enabeld
>
> 26. DS_UCLK              (14) : disabled
>
> 27. GFX_ULV              (15) : enabeld
>
> 28. FW_DSTATE            (16) : enabeld
>
> 29. BACO                 (18) : enabeld
>
> 30. VCN_PG               (19) : enabeld
>
> 31. JPEG_PG              (20) : disabled
>
> 32. USB_PG               (21) : disabled
>
> 33. RSMU_SMN_CG          (22) : enabeld
>
> 34. APCC_PLUS            (26) : disabled
>
> 35. GTHR                 (27) : disabled
>
> 36. GFX_DCS              (34) : disabled
>
> 37. GFX_SS               (37) : enabeld
>
> 38. OUT_OF_BAND_MONITOR  (38) : disabled
>
> 39. TEMP_DEPENDENT_VMIN  (39) : disabled
>
> 40. MMHUB_PG             (40) : disabled
>
> 41. ATHUB_PG             (41) : enabeld
>
> ------------------------------------------------------------------------
>
> *From:*Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 1:11 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org%20%0b>> <mailto:amd-gfx-PD4FTy7X32mqWrfYKbYh0A@public.gmane.orgktop.org>>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
<mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang,
> Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> 1. Unified feature enable status format in sysfs
> 2. Rename ppfeature to pp_features to adapt other pp sysfs node name
> 3. this function support all asic, not asic related function.
>
> Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org
<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org%20%0b>> <mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  24 +--
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  61 +++++++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   8 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
>  5 files changed, 75 insertions(+), 336 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 866097d5cf26..9e8e8a65d9bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -788,10 +788,10 @@ static ssize_t
> amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  }
>
>  /**
> - * DOC: ppfeatures
> + * DOC: pp_features
>   *
>   * The amdgpu driver provides a sysfs API for adjusting what powerplay
> - * features to be enabled. The file ppfeatures is used for this. And
> + * features to be enabled. The file pp_features is used for this. And
>   * this is only available for Vega10 and later dGPUs.
>   *
>   * Reading back the file will show you the followings:
> @@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct
> device *dev,
>   * the corresponding bit from original ppfeature masks and input the
>   * new ppfeature masks.
>   */
> -static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  const char *buf,
>                  size_t count)
> @@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          pr_debug("featuremask = 0x%llx\n", featuremask);
>
>          if (is_support_sw_smu(adev)) {
> -               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
> +               ret = smu_sys_set_pp_feature_mask(&adev->smu,
> featuremask);
>                  if (ret)
>                          return -EINVAL;
>          } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
> @@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          return count;
>  }
>
> -static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  char *buf)
>  {
> @@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct
> device *dev,
>          struct amdgpu_device *adev = ddev->dev_private;
>
>          if (is_support_sw_smu(adev)) {
> -               return smu_get_ppfeature_status(&adev->smu, buf);
> +               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
>          } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
>                  return amdgpu_dpm_get_ppfeature_status(adev, buf);
>
> @@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
>  static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
>                  amdgpu_get_memory_busy_percent, NULL);
>  static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
> -static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
> -               amdgpu_get_ppfeature_status,
> -               amdgpu_set_ppfeature_status);
> +static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
> +               amdgpu_get_pp_feature_status,
> +               amdgpu_set_pp_feature_status);
>  static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> @@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev)
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU)) {
>                  ret = device_create_file(adev->dev,
> - &dev_attr_ppfeatures);
> + &dev_attr_pp_features);
>                  if (ret) {
>                          DRM_ERROR("failed to create device file "
> - "ppfeatures\n");
> + "pp_features\n");
>                          return ret;
>                  }
>          }
> @@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device
> *adev)
> device_remove_file(adev->dev, &dev_attr_unique_id);
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU))
> -               device_remove_file(adev->dev, &dev_attr_ppfeatures);
> +               device_remove_file(adev->dev, &dev_attr_pp_features);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index e881de955388..90833ff2fe00 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context
> *smu, enum smu_feature_mask
>          return __smu_feature_names[feature];
>  }
>
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
> +{
> +       size_t size = 0;
> +       int ret = 0, i = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       int32_t feature_index = 0;
> +       uint32_t count = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               goto failed;
> +
> +       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
> +                       feature_mask[1], feature_mask[0]);
> +
> +       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
> +               feature_index = smu_feature_get_index(smu, i);
> +               if (feature_index < 0)
> +                       continue;
> +               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
> +                              count++,
> + smu_get_feature_name(smu, i),
> +                              feature_index,
> + !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
> +       }
> +
> +failed:
> +       return size;
> +}
> +
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask)
> +{
> +       int ret = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       uint64_t feature_2_enabled = 0;
> +       uint64_t feature_2_disabled = 0;
> +       uint64_t feature_enables = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               return ret;
> +
> +       feature_enables = ((uint64_t)feature_mask[1] << 32 |
> (uint64_t)feature_mask[0]);
> +
> +       feature_2_enabled  = ~feature_enables & new_mask;
> +       feature_2_disabled = feature_enables & ~new_mask;
> +
> +       if (feature_2_enabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> +               if (ret)
> +                       ret;
> +       }
> +       if (feature_2_disabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return ret;
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t
> *if_version, uint32_t *smu_version)
>  {
>          int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index abc2644b4c07..ac9e9d5d8a5c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -432,8 +432,6 @@ struct pptable_funcs {
>                                        uint32_t *mclk_mask,
>                                        uint32_t *soc_mask);
>          int (*set_cpu_power_state)(struct smu_context *smu);
> -       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t
> ppfeatures);
> -       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
>          bool (*is_dpm_running)(struct smu_context *smu);
>          int (*tables_init)(struct smu_context *smu, struct smu_table
> *tables);
>          int (*set_thermal_fan_table)(struct smu_context *smu);
> @@ -713,10 +711,6 @@ struct smu_funcs
> ((smu)->ppt_funcs->dpm_set_vce_enable ?
> (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
>  #define smu_set_xgmi_pstate(smu, pstate) \
> ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu),
> (pstate)) : 0)
> -#define smu_set_ppfeature_status(smu, ppfeatures) \
> - ((smu)->ppt_funcs->set_ppfeature_status ?
> (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
> -#define smu_get_ppfeature_status(smu, buf) \
> - ((smu)->ppt_funcs->get_ppfeature_status ?
> (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
>  #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> ((smu)->ppt_funcs->set_watermarks_table ?
> (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
>  #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> @@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context
> *smu, enum smu_clk_type clk_type)
>  int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum
> smu_feature_mask feature);
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228bf05f..cd0920093a5e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct
> smu_context *smu, uint32_t *clocks_
>          return 0;
>  }
>
> -static int navi10_get_ppfeature_status(struct smu_context *smu,
> -                                      char *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "DPM_GFXCLK",
> -                               "DPM_GFX_PACE",
> -                               "DPM_UCLK",
> -                               "DPM_SOCCLK",
> -                               "DPM_MP0CLK",
> -                               "DPM_LINK",
> -                               "DPM_DCEFCLK",
> - "MEM_VDDCI_SCALING",
> - "MEM_MVDD_SCALING",
> -                               "DS_GFXCLK",
> -                               "DS_SOCCLK",
> -                               "DS_LCLK",
> -                               "DS_DCEFCLK",
> -                               "DS_UCLK",
> -                               "GFX_ULV",
> -                               "FW_DSTATE",
> -                               "GFXOFF",
> -                               "BACO",
> -                               "VCN_PG",
> -                               "JPEG_PG",
> -                               "USB_PG",
> -                               "RSMU_SMN_CG",
> -                               "PPT",
> -                               "TDC",
> -                               "GFX_EDC",
> -                               "APCC_PLUS",
> -                               "GTHR",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "FAN_CONTROL",
> -                               "THERMAL",
> -                               "GFX_DCS",
> -                               "RM",
> -                               "LED_DISPLAY",
> -                               "GFX_SS",
> - "OUT_OF_BAND_MONITOR",
> - "TEMP_DEPENDENT_VMIN",
> -                               "MMHUB_PG",
> -                               "ATHUB_PG"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[GetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < (sizeof(ppfeature_name) /
> sizeof(ppfeature_name[0])); i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int navi10_enable_smc_features(struct smu_context *smu,
> -                                     bool enabled,
> -                                     uint64_t feature_masks)
> -{
> -       struct smu_feature *feature = &smu->smu_feature;
> -       uint32_t feature_low, feature_high;
> -       uint32_t feature_mask[2];
> -       int ret = 0;
> -
> -       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
> -       feature_high = (uint32_t)((feature_masks &
> 0xFFFFFFFF00000000ULL) >> 32);
> -
> -       if (enabled) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       mutex_lock(&feature->mutex);
> -       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
> -                   feature->feature_num);
> -       mutex_unlock(&feature->mutex);
> -
> -       return 0;
> -}
> -
> -static int navi10_set_ppfeature_status(struct smu_context *smu,
> -                                      uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[SetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = navi10_enable_smc_features(smu, false,
> features_to_disable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to disable smc features!",
> -                               return ret);
> -       }
> -
> -       if (features_to_enable) {
> -               ret = navi10_enable_smc_features(smu, true,
> features_to_enable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to enable smc features!",
> -                               return ret);
> -       }
> -
> -       return 0;
> -}
> -
>  static int navi10_set_peak_clock_by_device(struct smu_context *smu)
>  {
>          struct amdgpu_device *adev = smu->adev;
> @@ -1689,8 +1526,6 @@ static const struct pptable_funcs
> navi10_ppt_funcs = {
>          .set_watermarks_table = navi10_set_watermarks_table,
>          .read_sensor = navi10_read_sensor,
>          .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
> -       .get_ppfeature_status = navi10_get_ppfeature_status,
> -       .set_ppfeature_status = navi10_set_ppfeature_status,
>          .set_performance_level = navi10_set_performance_level,
>          .get_thermal_temperature_range =
> navi10_get_thermal_temperature_range,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c06a9472c3b2..52c8fc9f1ff4 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct
> smu_context *smu, bool enable)
>          return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT,
> enable);
>  }
>
> -static int vega20_get_enabled_smc_features(struct smu_context *smu,
> -               uint64_t *features_enabled)
> -{
> -       uint32_t feature_mask[2] = {0, 0};
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       *features_enabled = ((((uint64_t)feature_mask[0] <<
> SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
> - (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) &
> SMU_FEATURES_HIGH_MASK));
> -
> -       return ret;
> -}
> -
> -static int vega20_enable_smc_features(struct smu_context *smu,
> -               bool enable, uint64_t feature_mask)
> -{
> -       uint32_t smu_features_low, smu_features_high;
> -       int ret = 0;
> -
> -       smu_features_low = (uint32_t)((feature_mask &
> SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
> -       smu_features_high = (uint32_t)((feature_mask &
> SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
> -
> -       if (enable) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -
> -}
> -
> -static int vega20_get_ppfeature_status(struct smu_context *smu, char
> *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "GFXCLK_DPM",
> -                               "UCLK_DPM",
> -                               "SOCCLK_DPM",
> -                               "UVD_DPM",
> -                               "VCE_DPM",
> -                               "ULV",
> -                               "MP0CLK_DPM",
> -                               "LINK_DPM",
> -                               "DCEFCLK_DPM",
> -                               "GFXCLK_DS",
> -                               "SOCCLK_DS",
> -                               "LCLK_DS",
> -                               "PPT",
> -                               "TDC",
> -                               "THERMAL",
> -                               "GFX_PER_CU_CG",
> -                               "RM",
> -                               "DCEFCLK_DS",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "LED_DISPLAY",
> -                               "FAN_CONTROL",
> -                               "GFX_EDC",
> -                               "GFXOFF",
> -                               "CG",
> -                               "FCLK_DPM",
> -                               "FCLK_DS",
> -                               "MP1CLK_DS",
> -                               "MP0CLK_DS",
> -                               "XGMI",
> -                               "ECC"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int vega20_set_ppfeature_status(struct smu_context *smu,
> uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
> -               return -EINVAL;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = vega20_enable_smc_features(smu, false,
> features_to_disable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       if (features_to_enable) {
> -               ret = vega20_enable_smc_features(smu, true,
> features_to_enable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -}
> -
>  static bool vega20_is_dpm_running(struct smu_context *smu)
>  {
>          int ret = 0;
> @@ -3311,8 +3160,6 @@ static const struct pptable_funcs
> vega20_ppt_funcs = {
>          .force_dpm_limit_value = vega20_force_dpm_limit_value,
>          .unforce_dpm_levels = vega20_unforce_dpm_levels,
>          .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
> -       .set_ppfeature_status = vega20_set_ppfeature_status,
> -       .get_ppfeature_status = vega20_get_ppfeature_status,
>          .is_dpm_running = vega20_is_dpm_running,
>          .set_thermal_fan_table = vega20_set_thermal_fan_table,
>          .get_fan_speed_percent = vega20_get_fan_speed_percent,
> --
> 2.22.0
>

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_______________________________________________
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu
       [not found]                                 ` <BN8PR12MB3283A9239266F64A93F2E3DDA2C00-h6+T2+wrnx1KUVg95YpnwwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
  2019-07-26 12:47                                   ` Huang, Ray
@ 2019-07-26 14:27                                   ` Deucher, Alexander
  1 sibling, 0 replies; 23+ messages in thread
From: Deucher, Alexander @ 2019-07-26 14:27 UTC (permalink / raw)
  To: Wang, Kevin(Yang),
	StDenis, Tom, Huang, Ray, Quan, Evan,
	amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Zhang, Hawking
  Cc: Feng, Kenneth


[-- Attachment #1.1: Type: text/plain, Size: 34323 bytes --]

Sure.

Alex
________________________________
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, July 26, 2019 5:05 AM
To: StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

@Deucher, Alexander<mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>

Hi Alex,

it seems not application will use this sysfs, can we rename it from "ppfeatures" to "pp_features"?
this patch sets is pending.

Best Regards,
Kevin
________________________________
From: StDenis, Tom <Tom.StDenis-5C7GfCeVMHo@public.gmane.org>
Sent: Thursday, July 25, 2019 9:14 PM
To: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Huang, Ray <Ray.Huang@amd.com>; Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan@amd.com>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Cc: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu

No it doesn't.  We get clocks for --top from the sensors interface.


On 2019-07-25 9:01 a.m., Deucher, Alexander wrote:
> Tom, does umr use it?
>
> Alex
> ------------------------------------------------------------------------
> *From:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Thursday, July 25, 2019 4:49 AM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Quan, Evan
> <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>; Zhang, Hawking
> <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> Any other user mode tool use the “ppfeature” sysfs interface?
>
> Thanks,
>
> Ray
>
> *From:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Thursday, July 25, 2019 4:44 PM
> *To:* Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org;
> Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
> *Cc:* Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> in fact, i don't want to change this sysfs name from "ppfeatures" to
> "pp_features",
>
> but it seems that don't have same name format with other pp sysfs node.
>
> the other powerplay sysfs name have "pp_" prefix, i think we'd better
> to change it name to "pp_features"
>
> eg:
>
> pp_cur_state    pp_dpm_fclk  pp_dpm_pcie  pp_dpm_socclk
>  pp_force_state  pp_num_states  pp_sclk_od
> pp_dpm_dcefclk  pp_dpm_mclk  pp_dpm_sclk  pp_features    pp_mclk_od
>    pp_power_profile_mode  pp_table
>
> @Deucher, Alexander <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org> @Zhang, Hawking
> <mailto:Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
>
> Could you give us some idea about it,
>
> Thanks.
>
> Best Regards,
> Kevin
>
> ------------------------------------------------------------------------
>
> *From:*Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org <mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 4:30 PM
> *To:* Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* RE: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> To keep backward compatibility, we cannot change the sysfs file naming.
>
> But it’s a good idea to summarize these as common APIs.
>
> Regards,
>
> Evan
>
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>> *On Behalf Of *Wang,
> Kevin(Yang)
> *Sent:* Thursday, July 25, 2019 4:10 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> *Cc:* Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
> <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* Re: [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> add sample data from sysfs pp_features with this patch.
>
> print format:
>
> index. feature name (Hardware Message ID): state
>
> /sudo find /sys -name "pp_features" -exec cat {} \;/
>
> features high: 0x00000623 low: 0xb3cdaffb
>
> 00. DPM_PREFETCHER       ( 0) : enabeld
>
> 01. DPM_GFXCLK           ( 1) : enabeld
>
> 02. DPM_UCLK             ( 3) : enabeld
>
> 03. DPM_SOCCLK           ( 4) : enabeld
>
> 04. DPM_MP0CLK           ( 5) : enabeld
>
> 05. DPM_LINK             ( 6) : enabeld
>
> 06. DPM_DCEFCLK          ( 7) : enabeld
>
> 07. DS_GFXCLK            (10) : enabeld
>
> 08. DS_SOCCLK            (11) : enabeld
>
> 09. DS_LCLK              (12) : disabled
>
> 10. PPT                (23) : enabeld
>
> 11. TDC                (24) : enabeld
>
> 12. THERMAL              (33) : enabeld
>
> 13. RM                 (35) : disabled
>
> 14. DS_DCEFCLK           (13) : enabeld
>
> 15. ACDC                 (28) : enabeld
>
> 16. VR0HOT               (29) : enabeld
>
> 17. VR1HOT               (30) : disabled
>
> 18. FW_CTF               (31) : enabeld
>
> 19. LED_DISPLAY          (36) : disabled
>
> 20. FAN_CONTROL          (32) : enabeld
>
> 21. GFX_EDC              (25) : enabeld
>
> 22. GFXOFF               (17) : disabled
>
> 23. DPM_GFX_PACE         ( 2) : disabled
>
> 24. MEM_VDDCI_SCALING    ( 8) : enabeld
>
> 25. MEM_MVDD_SCALING     ( 9) : enabeld
>
> 26. DS_UCLK              (14) : disabled
>
> 27. GFX_ULV              (15) : enabeld
>
> 28. FW_DSTATE            (16) : enabeld
>
> 29. BACO                 (18) : enabeld
>
> 30. VCN_PG               (19) : enabeld
>
> 31. JPEG_PG              (20) : disabled
>
> 32. USB_PG               (21) : disabled
>
> 33. RSMU_SMN_CG          (22) : enabeld
>
> 34. APCC_PLUS            (26) : disabled
>
> 35. GTHR                 (27) : disabled
>
> 36. GFX_DCS              (34) : disabled
>
> 37. GFX_SS               (37) : enabeld
>
> 38. OUT_OF_BAND_MONITOR  (38) : disabled
>
> 39. TEMP_DEPENDENT_VMIN  (39) : disabled
>
> 40. MMHUB_PG             (40) : disabled
>
> 41. ATHUB_PG             (41) : enabeld
>
> ------------------------------------------------------------------------
>
> *From:*Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org
> <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Sent:* Thursday, July 25, 2019 1:11 PM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> <mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
> *Cc:* Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org
> <mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>; Huang, Ray <Ray.Huang-5C7GfCeVMHo@public.gmane.org
> <mailto:Ray.Huang-5C7GfCeVMHo@public.gmane.org>>; Deucher, Alexander
> <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org <mailto:Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>>; Wang,
> Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org <mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
> *Subject:* [PATCH 5/5] drm/amd/powerplay: implment sysfs feature
> status function in smu
>
> 1. Unified feature enable status format in sysfs
> 2. Rename ppfeature to pp_features to adapt other pp sysfs node name
> 3. this function support all asic, not asic related function.
>
> Signed-off-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org
> <mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |  24 +--
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c |  61 +++++++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h |   8 +-
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c    | 165 ------------------
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c    | 153 ----------------
>  5 files changed, 75 insertions(+), 336 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 866097d5cf26..9e8e8a65d9bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -788,10 +788,10 @@ static ssize_t
> amdgpu_get_pp_od_clk_voltage(struct device *dev,
>  }
>
>  /**
> - * DOC: ppfeatures
> + * DOC: pp_features
>   *
>   * The amdgpu driver provides a sysfs API for adjusting what powerplay
> - * features to be enabled. The file ppfeatures is used for this. And
> + * features to be enabled. The file pp_features is used for this. And
>   * this is only available for Vega10 and later dGPUs.
>   *
>   * Reading back the file will show you the followings:
> @@ -803,7 +803,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct
> device *dev,
>   * the corresponding bit from original ppfeature masks and input the
>   * new ppfeature masks.
>   */
> -static ssize_t amdgpu_set_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_set_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  const char *buf,
>                  size_t count)
> @@ -820,7 +820,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          pr_debug("featuremask = 0x%llx\n", featuremask);
>
>          if (is_support_sw_smu(adev)) {
> -               ret = smu_set_ppfeature_status(&adev->smu, featuremask);
> +               ret = smu_sys_set_pp_feature_mask(&adev->smu,
> featuremask);
>                  if (ret)
>                          return -EINVAL;
>          } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
> @@ -832,7 +832,7 @@ static ssize_t amdgpu_set_ppfeature_status(struct
> device *dev,
>          return count;
>  }
>
> -static ssize_t amdgpu_get_ppfeature_status(struct device *dev,
> +static ssize_t amdgpu_get_pp_feature_status(struct device *dev,
>                  struct device_attribute *attr,
>                  char *buf)
>  {
> @@ -840,7 +840,7 @@ static ssize_t amdgpu_get_ppfeature_status(struct
> device *dev,
>          struct amdgpu_device *adev = ddev->dev_private;
>
>          if (is_support_sw_smu(adev)) {
> -               return smu_get_ppfeature_status(&adev->smu, buf);
> +               return smu_sys_get_pp_feature_mask(&adev->smu, buf);
>          } else if (adev->powerplay.pp_funcs->get_ppfeature_status)
>                  return amdgpu_dpm_get_ppfeature_status(adev, buf);
>
> @@ -1500,9 +1500,9 @@ static DEVICE_ATTR(gpu_busy_percent, S_IRUGO,
>  static DEVICE_ATTR(mem_busy_percent, S_IRUGO,
>                  amdgpu_get_memory_busy_percent, NULL);
>  static DEVICE_ATTR(pcie_bw, S_IRUGO, amdgpu_get_pcie_bw, NULL);
> -static DEVICE_ATTR(ppfeatures, S_IRUGO | S_IWUSR,
> -               amdgpu_get_ppfeature_status,
> -               amdgpu_set_ppfeature_status);
> +static DEVICE_ATTR(pp_features, S_IRUGO | S_IWUSR,
> +               amdgpu_get_pp_feature_status,
> +               amdgpu_set_pp_feature_status);
>  static DEVICE_ATTR(unique_id, S_IRUGO, amdgpu_get_unique_id, NULL);
>
>  static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> @@ -2960,10 +2960,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev)
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU)) {
>                  ret = device_create_file(adev->dev,
> - &dev_attr_ppfeatures);
> + &dev_attr_pp_features);
>                  if (ret) {
>                          DRM_ERROR("failed to create device file "
> - "ppfeatures\n");
> + "pp_features\n");
>                          return ret;
>                  }
>          }
> @@ -3017,7 +3017,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device
> *adev)
> device_remove_file(adev->dev, &dev_attr_unique_id);
>          if ((adev->asic_type >= CHIP_VEGA10) &&
>              !(adev->flags & AMD_IS_APU))
> -               device_remove_file(adev->dev, &dev_attr_ppfeatures);
> +               device_remove_file(adev->dev, &dev_attr_pp_features);
>  }
>
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index e881de955388..90833ff2fe00 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -55,6 +55,67 @@ const char *smu_get_feature_name(struct smu_context
> *smu, enum smu_feature_mask
>          return __smu_feature_names[feature];
>  }
>
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
> +{
> +       size_t size = 0;
> +       int ret = 0, i = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       int32_t feature_index = 0;
> +       uint32_t count = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               goto failed;
> +
> +       size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
> +                       feature_mask[1], feature_mask[0]);
> +
> +       for (i = 0; i < SMU_FEATURE_COUNT; i++) {
> +               feature_index = smu_feature_get_index(smu, i);
> +               if (feature_index < 0)
> +                       continue;
> +               size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
> +                              count++,
> + smu_get_feature_name(smu, i),
> +                              feature_index,
> + !!smu_feature_is_enabled(smu, i) ? "enabeld" : "disabled");
> +       }
> +
> +failed:
> +       return size;
> +}
> +
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask)
> +{
> +       int ret = 0;
> +       uint32_t feature_mask[2] = { 0 };
> +       uint64_t feature_2_enabled = 0;
> +       uint64_t feature_2_disabled = 0;
> +       uint64_t feature_enables = 0;
> +
> +       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> +       if (ret)
> +               return ret;
> +
> +       feature_enables = ((uint64_t)feature_mask[1] << 32 |
> (uint64_t)feature_mask[0]);
> +
> +       feature_2_enabled  = ~feature_enables & new_mask;
> +       feature_2_disabled = feature_enables & ~new_mask;
> +
> +       if (feature_2_enabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_enabled, true);
> +               if (ret)
> +                       ret;
> +       }
> +       if (feature_2_disabled) {
> +               ret = smu_feature_update_enable_state(smu,
> feature_2_disabled, false);
> +               if (ret)
> +                       return ret;
> +       }
> +
> +       return ret;
> +}
> +
>  int smu_get_smc_version(struct smu_context *smu, uint32_t
> *if_version, uint32_t *smu_version)
>  {
>          int ret = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index abc2644b4c07..ac9e9d5d8a5c 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -432,8 +432,6 @@ struct pptable_funcs {
>                                        uint32_t *mclk_mask,
>                                        uint32_t *soc_mask);
>          int (*set_cpu_power_state)(struct smu_context *smu);
> -       int (*set_ppfeature_status)(struct smu_context *smu, uint64_t
> ppfeatures);
> -       int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
>          bool (*is_dpm_running)(struct smu_context *smu);
>          int (*tables_init)(struct smu_context *smu, struct smu_table
> *tables);
>          int (*set_thermal_fan_table)(struct smu_context *smu);
> @@ -713,10 +711,6 @@ struct smu_funcs
> ((smu)->ppt_funcs->dpm_set_vce_enable ?
> (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0)
>  #define smu_set_xgmi_pstate(smu, pstate) \
> ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu),
> (pstate)) : 0)
> -#define smu_set_ppfeature_status(smu, ppfeatures) \
> - ((smu)->ppt_funcs->set_ppfeature_status ?
> (smu)->ppt_funcs->set_ppfeature_status((smu), (ppfeatures)) : -EINVAL)
> -#define smu_get_ppfeature_status(smu, buf) \
> - ((smu)->ppt_funcs->get_ppfeature_status ?
> (smu)->ppt_funcs->get_ppfeature_status((smu), (buf)) : -EINVAL)
>  #define smu_set_watermarks_table(smu, tab, clock_ranges) \
> ((smu)->ppt_funcs->set_watermarks_table ?
> (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
>  #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
> @@ -804,5 +798,7 @@ bool smu_clk_dpm_is_enabled(struct smu_context
> *smu, enum smu_clk_type clk_type)
>  int smu_feature_update_enable_state(struct smu_context *smu, uint64_t
> feature_mask, bool enabled);
>  const char *smu_get_message_name(struct smu_context *smu, enum
> smu_message_type type);
>  const char *smu_get_feature_name(struct smu_context *smu, enum
> smu_feature_mask feature);
> +size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf);
> +int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t
> new_mask);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index c873228bf05f..cd0920093a5e 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -1422,169 +1422,6 @@ static int navi10_get_uclk_dpm_states(struct
> smu_context *smu, uint32_t *clocks_
>          return 0;
>  }
>
> -static int navi10_get_ppfeature_status(struct smu_context *smu,
> -                                      char *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "DPM_GFXCLK",
> -                               "DPM_GFX_PACE",
> -                               "DPM_UCLK",
> -                               "DPM_SOCCLK",
> -                               "DPM_MP0CLK",
> -                               "DPM_LINK",
> -                               "DPM_DCEFCLK",
> - "MEM_VDDCI_SCALING",
> - "MEM_MVDD_SCALING",
> -                               "DS_GFXCLK",
> -                               "DS_SOCCLK",
> -                               "DS_LCLK",
> -                               "DS_DCEFCLK",
> -                               "DS_UCLK",
> -                               "GFX_ULV",
> -                               "FW_DSTATE",
> -                               "GFXOFF",
> -                               "BACO",
> -                               "VCN_PG",
> -                               "JPEG_PG",
> -                               "USB_PG",
> -                               "RSMU_SMN_CG",
> -                               "PPT",
> -                               "TDC",
> -                               "GFX_EDC",
> -                               "APCC_PLUS",
> -                               "GTHR",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "FAN_CONTROL",
> -                               "THERMAL",
> -                               "GFX_DCS",
> -                               "RM",
> -                               "LED_DISPLAY",
> -                               "GFX_SS",
> - "OUT_OF_BAND_MONITOR",
> - "TEMP_DEPENDENT_VMIN",
> -                               "MMHUB_PG",
> -                               "ATHUB_PG"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[GetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < (sizeof(ppfeature_name) /
> sizeof(ppfeature_name[0])); i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int navi10_enable_smc_features(struct smu_context *smu,
> -                                     bool enabled,
> -                                     uint64_t feature_masks)
> -{
> -       struct smu_feature *feature = &smu->smu_feature;
> -       uint32_t feature_low, feature_high;
> -       uint32_t feature_mask[2];
> -       int ret = 0;
> -
> -       feature_low = (uint32_t)(feature_masks & 0xFFFFFFFF);
> -       feature_high = (uint32_t)((feature_masks &
> 0xFFFFFFFF00000000ULL) >> 32);
> -
> -       if (enabled) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 feature_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 feature_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       mutex_lock(&feature->mutex);
> -       bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
> -                   feature->feature_num);
> -       mutex_unlock(&feature->mutex);
> -
> -       return 0;
> -}
> -
> -static int navi10_set_ppfeature_status(struct smu_context *smu,
> -                                      uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint32_t feature_mask[2];
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       PP_ASSERT_WITH_CODE(!ret,
> -                       "[SetPPfeatureStatus] Failed to get enabled
> smc features!",
> -                       return ret);
> -       features_enabled = (uint64_t)feature_mask[0] |
> - (uint64_t)feature_mask[1] << 32;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = navi10_enable_smc_features(smu, false,
> features_to_disable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to disable smc features!",
> -                               return ret);
> -       }
> -
> -       if (features_to_enable) {
> -               ret = navi10_enable_smc_features(smu, true,
> features_to_enable);
> -               PP_ASSERT_WITH_CODE(!ret,
> - "[SetPPfeatureStatus] Failed to enable smc features!",
> -                               return ret);
> -       }
> -
> -       return 0;
> -}
> -
>  static int navi10_set_peak_clock_by_device(struct smu_context *smu)
>  {
>          struct amdgpu_device *adev = smu->adev;
> @@ -1689,8 +1526,6 @@ static const struct pptable_funcs
> navi10_ppt_funcs = {
>          .set_watermarks_table = navi10_set_watermarks_table,
>          .read_sensor = navi10_read_sensor,
>          .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
> -       .get_ppfeature_status = navi10_get_ppfeature_status,
> -       .set_ppfeature_status = navi10_set_ppfeature_status,
>          .set_performance_level = navi10_set_performance_level,
>          .get_thermal_temperature_range =
> navi10_get_thermal_temperature_range,
>  };
> diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> index c06a9472c3b2..52c8fc9f1ff4 100644
> --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
> @@ -2858,157 +2858,6 @@ static int vega20_dpm_set_vce_enable(struct
> smu_context *smu, bool enable)
>          return smu_feature_set_enabled(smu, SMU_FEATURE_DPM_VCE_BIT,
> enable);
>  }
>
> -static int vega20_get_enabled_smc_features(struct smu_context *smu,
> -               uint64_t *features_enabled)
> -{
> -       uint32_t feature_mask[2] = {0, 0};
> -       int ret = 0;
> -
> -       ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
> -       if (ret)
> -               return ret;
> -
> -       *features_enabled = ((((uint64_t)feature_mask[0] <<
> SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) |
> - (((uint64_t)feature_mask[1] << SMU_FEATURES_HIGH_SHIFT) &
> SMU_FEATURES_HIGH_MASK));
> -
> -       return ret;
> -}
> -
> -static int vega20_enable_smc_features(struct smu_context *smu,
> -               bool enable, uint64_t feature_mask)
> -{
> -       uint32_t smu_features_low, smu_features_high;
> -       int ret = 0;
> -
> -       smu_features_low = (uint32_t)((feature_mask &
> SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT);
> -       smu_features_high = (uint32_t)((feature_mask &
> SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT);
> -
> -       if (enable) {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_EnableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       } else {
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesLow,
> -                                                 smu_features_low);
> -               if (ret)
> -                       return ret;
> -               ret = smu_send_smc_msg_with_param(smu,
> SMU_MSG_DisableSmuFeaturesHigh,
> -                                                 smu_features_high);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -
> -}
> -
> -static int vega20_get_ppfeature_status(struct smu_context *smu, char
> *buf)
> -{
> -       static const char *ppfeature_name[] = {
> - "DPM_PREFETCHER",
> -                               "GFXCLK_DPM",
> -                               "UCLK_DPM",
> -                               "SOCCLK_DPM",
> -                               "UVD_DPM",
> -                               "VCE_DPM",
> -                               "ULV",
> -                               "MP0CLK_DPM",
> -                               "LINK_DPM",
> -                               "DCEFCLK_DPM",
> -                               "GFXCLK_DS",
> -                               "SOCCLK_DS",
> -                               "LCLK_DS",
> -                               "PPT",
> -                               "TDC",
> -                               "THERMAL",
> -                               "GFX_PER_CU_CG",
> -                               "RM",
> -                               "DCEFCLK_DS",
> -                               "ACDC",
> -                               "VR0HOT",
> -                               "VR1HOT",
> -                               "FW_CTF",
> -                               "LED_DISPLAY",
> -                               "FAN_CONTROL",
> -                               "GFX_EDC",
> -                               "GFXOFF",
> -                               "CG",
> -                               "FCLK_DPM",
> -                               "FCLK_DS",
> -                               "MP1CLK_DS",
> -                               "MP0CLK_DS",
> -                               "XGMI",
> -                               "ECC"};
> -       static const char *output_title[] = {
> -                               "FEATURES",
> -                               "BITMASK",
> -                               "ENABLEMENT"};
> -       uint64_t features_enabled;
> -       int i;
> -       int ret = 0;
> -       int size = 0;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       size += sprintf(buf + size, "Current ppfeatures: 0x%016llx\n",
> features_enabled);
> -       size += sprintf(buf + size, "%-19s %-22s %s\n",
> -                               output_title[0],
> -                               output_title[1],
> - output_title[2]);
> -       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
> -               size += sprintf(buf + size, "%-19s 0x%016llx %6s\n",
> - ppfeature_name[i],
> -                                       1ULL << i,
> - (features_enabled & (1ULL << i)) ? "Y" : "N");
> -       }
> -
> -       return size;
> -}
> -
> -static int vega20_set_ppfeature_status(struct smu_context *smu,
> uint64_t new_ppfeature_masks)
> -{
> -       uint64_t features_enabled;
> -       uint64_t features_to_enable;
> -       uint64_t features_to_disable;
> -       int ret = 0;
> -
> -       if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
> -               return -EINVAL;
> -
> -       ret = vega20_get_enabled_smc_features(smu, &features_enabled);
> -       if (ret)
> -               return ret;
> -
> -       features_to_disable =
> -               features_enabled & ~new_ppfeature_masks;
> -       features_to_enable =
> -               ~features_enabled & new_ppfeature_masks;
> -
> -       pr_debug("features_to_disable 0x%llx\n", features_to_disable);
> -       pr_debug("features_to_enable 0x%llx\n", features_to_enable);
> -
> -       if (features_to_disable) {
> -               ret = vega20_enable_smc_features(smu, false,
> features_to_disable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       if (features_to_enable) {
> -               ret = vega20_enable_smc_features(smu, true,
> features_to_enable);
> -               if (ret)
> -                       return ret;
> -       }
> -
> -       return 0;
> -}
> -
>  static bool vega20_is_dpm_running(struct smu_context *smu)
>  {
>          int ret = 0;
> @@ -3311,8 +3160,6 @@ static const struct pptable_funcs
> vega20_ppt_funcs = {
>          .force_dpm_limit_value = vega20_force_dpm_limit_value,
>          .unforce_dpm_levels = vega20_unforce_dpm_levels,
>          .get_profiling_clk_mask = vega20_get_profiling_clk_mask,
> -       .set_ppfeature_status = vega20_set_ppfeature_status,
> -       .get_ppfeature_status = vega20_get_ppfeature_status,
>          .is_dpm_running = vega20_is_dpm_running,
>          .set_thermal_fan_table = vega20_set_thermal_fan_table,
>          .get_fan_speed_percent = vega20_get_fan_speed_percent,
> --
> 2.22.0
>

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_______________________________________________
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level
       [not found] ` <20190725045403.7458-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-25  4:54   ` Wang, Kevin(Yang)
  0 siblings, 0 replies; 23+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-25  4:54 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Deucher, Alexander, Huang, Ray, Feng, Kenneth, Wang, Kevin(Yang)

this function is not ip or asic related function,
so move it to top level as public api in smu.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 40 ++++++++++++++++++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  4 +-
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 39 ------------------
 3 files changed, 40 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 8563f9083f4e..e881de955388 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -507,6 +507,41 @@ int smu_feature_init_dpm(struct smu_context *smu)
 
 	return ret;
 }
+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled)
+{
+	uint32_t feature_low = 0, feature_high = 0;
+	int ret = 0;
+
+	if (!smu->pm_enabled)
+		return ret;
+
+	feature_low = (feature_mask >> 0 ) & 0xffffffff;
+	feature_high = (feature_mask >> 32) & 0xffffffff;
+
+	if (enabled) {
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
+						  feature_low);
+		if (ret)
+			return ret;
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
+						  feature_high);
+		if (ret)
+			return ret;
+
+	} else {
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
+						  feature_low);
+		if (ret)
+			return ret;
+		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
+						  feature_high);
+		if (ret)
+			return ret;
+
+	}
+
+	return ret;
+}
 
 int smu_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask)
 {
@@ -532,6 +567,7 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 {
 	struct smu_feature *feature = &smu->smu_feature;
 	int feature_id;
+	uint64_t feature_mask = 0;
 	int ret = 0;
 
 	feature_id = smu_feature_get_index(smu, mask);
@@ -540,8 +576,10 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask,
 
 	WARN_ON(feature_id > feature->feature_num);
 
+	feature_mask = 1UL << feature_id;
+
 	mutex_lock(&feature->mutex);
-	ret = smu_feature_update_enable_state(smu, feature_id, enable);
+	ret = smu_feature_update_enable_state(smu, feature_mask, enable);
 	if (ret)
 		goto failed;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ba2385026b89..abc2644b4c07 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -479,7 +479,6 @@ struct smu_funcs
 	int (*init_display_count)(struct smu_context *smu, uint32_t count);
 	int (*set_allowed_mask)(struct smu_context *smu);
 	int (*get_enabled_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
-	int (*update_feature_enable_state)(struct smu_context *smu, uint32_t feature_id, bool enabled);
 	int (*notify_display_change)(struct smu_context *smu);
 	int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool def);
 	int (*set_power_limit)(struct smu_context *smu, uint32_t n);
@@ -595,8 +594,6 @@ struct smu_funcs
 	((smu)->funcs->get_enabled_mask? (smu)->funcs->get_enabled_mask((smu), (mask), (num)) : 0)
 #define smu_is_dpm_running(smu) \
 	((smu)->ppt_funcs->is_dpm_running ? (smu)->ppt_funcs->is_dpm_running((smu)) : 0)
-#define smu_feature_update_enable_state(smu, feature_id, enabled) \
-	((smu)->funcs->update_feature_enable_state? (smu)->funcs->update_feature_enable_state((smu), (feature_id), (enabled)) : 0)
 #define smu_notify_display_change(smu) \
 	((smu)->funcs->notify_display_change? (smu)->funcs->notify_display_change((smu)) : 0)
 #define smu_store_powerplay_table(smu) \
@@ -804,6 +801,7 @@ enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
 bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type);
+int smu_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled);
 const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type);
 const char *smu_get_feature_name(struct smu_context *smu, enum smu_feature_mask feature);
 
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index ccf6af055d03..93f3ffb8b471 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -795,44 +795,6 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
 	return ret;
 }
 
-static int smu_v11_0_update_feature_enable_state(struct smu_context *smu, uint32_t feature_id, bool enabled)
-{
-	uint32_t feature_low = 0, feature_high = 0;
-	int ret = 0;
-
-	if (!smu->pm_enabled)
-		return ret;
-	if (feature_id >= 0 && feature_id < 31)
-		feature_low = (1 << feature_id);
-	else if (feature_id > 31 && feature_id < 63)
-		feature_high = (1 << feature_id);
-	else
-		return -EINVAL;
-
-	if (enabled) {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_EnableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-
-	} else {
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesLow,
-						  feature_low);
-		if (ret)
-			return ret;
-		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_DisableSmuFeaturesHigh,
-						  feature_high);
-		if (ret)
-			return ret;
-
-	}
-
-	return ret;
-}
 
 static int smu_v11_0_set_allowed_mask(struct smu_context *smu)
 {
@@ -1781,7 +1743,6 @@ static const struct smu_funcs smu_v11_0_funcs = {
 	.set_allowed_mask = smu_v11_0_set_allowed_mask,
 	.get_enabled_mask = smu_v11_0_get_enabled_mask,
 	.system_features_control = smu_v11_0_system_features_control,
-	.update_feature_enable_state = smu_v11_0_update_feature_enable_state,
 	.notify_display_change = smu_v11_0_notify_display_change,
 	.get_power_limit = smu_v11_0_get_power_limit,
 	.set_power_limit = smu_v11_0_set_power_limit,
-- 
2.22.0

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^ permalink raw reply related	[flat|nested] 23+ messages in thread
end of thread, other threads:[~2019-07-26 14:27 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-25  5:11 [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h Wang, Kevin(Yang)
     [not found] ` <20190725051057.28862-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  5:11   ` [PATCH 2/5] drm/amd/powerplay: add smu message name support Wang, Kevin(Yang)
     [not found]     ` <20190725051057.28862-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  7:44       ` Feng, Kenneth
2019-07-25  5:11   ` [PATCH 3/5] drm/amd/powerplay: add smu feature " Wang, Kevin(Yang)
     [not found]     ` <20190725051057.28862-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  9:35       ` Quan, Evan
     [not found]         ` <MN2PR12MB3344FF4A8126C0263C3D2E7CE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25  9:47           ` Wang, Kevin(Yang)
2019-07-25  5:11   ` [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level Wang, Kevin(Yang)
     [not found]     ` <20190725051057.28862-4-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  9:29       ` Quan, Evan
     [not found]         ` <MN2PR12MB334402CBE2CB315E0205EC3BE4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25  9:50           ` Wang, Kevin(Yang)
2019-07-25  5:11   ` [PATCH 5/5] drm/amd/powerplay: implment sysfs feature status function in smu Wang, Kevin(Yang)
     [not found]     ` <20190725051057.28862-5-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  8:10       ` Wang, Kevin(Yang)
     [not found]         ` <MN2PR12MB32966C19A3EF83A1E868B25CA2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25  8:21           ` Feng, Kenneth
2019-07-25  8:30           ` Quan, Evan
     [not found]             ` <MN2PR12MB334476A964852FD3B092B385E4C10-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25  8:44               ` Wang, Kevin(Yang)
     [not found]                 ` <MN2PR12MB32968D539CA68CCE3E4AFFB6A2C10-rweVpJHSKTqAm9ToKNQgFgdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25  8:49                   ` Huang, Ray
     [not found]                     ` <MN2PR12MB33098222156F946AA7EABB26ECC10-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25 13:01                       ` Deucher, Alexander
     [not found]                         ` <BN6PR12MB1809E62D6BFE3224637F25D9F7C10-/b2+HYfkarSEx6ez0IUAagdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-25 13:14                           ` StDenis, Tom
     [not found]                             ` <f76aeb2d-01be-d629-72e9-a96f702a73e0-5C7GfCeVMHo@public.gmane.org>
2019-07-26  9:05                               ` Wang, Kevin(Yang)
     [not found]                                 ` <BN8PR12MB3283A9239266F64A93F2E3DDA2C00-h6+T2+wrnx1KUVg95YpnwwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-26 12:47                                   ` Huang, Ray
2019-07-26 14:27                                   ` Deucher, Alexander
2019-07-25  6:36   ` [PATCH 1/5] drm/amd/powerplay: move smu types to smu_types.h Feng, Kenneth
2019-07-25  9:31   ` Quan, Evan
  -- strict thread matches above, loose matches on Subject: below --
2019-07-25  4:54 Wang, Kevin(Yang)
     [not found] ` <20190725045403.7458-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-25  4:54   ` [PATCH 4/5] drm/amd/powerplay: move smu_feature_update_enable_state to up level Wang, Kevin(Yang)

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