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* [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check for smu
@ 2019-07-12  9:15 Wang, Kevin(Yang)
       [not found] ` <20190712091454.13478-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 6+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-12  9:15 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Quan, Evan, Feng, Kenneth, Wang, Kevin(Yang)

add this helper function to check dpm clk feature is enabled.

Change-Id: I51a4e9246d83d74a8e687fbc45983848adc960ca
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 71 +++++++++++++------
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
 2 files changed, 49 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index da4332d2dbbc..be90ae59dfa8 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -68,6 +68,10 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 	if (min <= 0 && max <= 0)
 		return -EINVAL;
 
+	ret = smu_feature_dpmclk_check(smu, clk_type);
+	if (ret)
+		return ret;
+
 	clk_id = smu_clk_get_index(smu, clk_type);
 	if (clk_id < 0)
 		return clk_id;
@@ -101,6 +105,10 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 	if (min <= 0 && max <= 0)
 		return -EINVAL;
 
+	ret = smu_feature_dpmclk_check(smu, clk_type);
+	if (ret)
+		return ret;
+
 	clk_id = smu_clk_get_index(smu, clk_type);
 	if (clk_id < 0)
 		return clk_id;
@@ -134,29 +142,9 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 	if (!min && !max)
 		return -EINVAL;
 
-	switch (clk_type) {
-	case SMU_MCLK:
-	case SMU_UCLK:
-		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
-			pr_warn("uclk dpm is not enabled\n");
-			return 0;
-		}
-		break;
-	case SMU_GFXCLK:
-	case SMU_SCLK:
-		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
-			pr_warn("gfxclk dpm is not enabled\n");
-			return 0;
-		}
-	case SMU_SOCCLK:
-		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
-			pr_warn("sockclk dpm is not enabled\n");
-			return 0;
-		}
-		break;
-	default:
-		break;
-	}
+	ret = smu_feature_dpmclk_check(smu, clk_type);
+	if (ret)
+		return ret;
 
 	mutex_lock(&smu->mutex);
 	clk_id = smu_clk_get_index(smu, clk_type);
@@ -199,6 +187,10 @@ int smu_get_dpm_freq_by_index(struct smu_context *smu, enum smu_clk_type clk_typ
 	if (!value)
 		return -EINVAL;
 
+	ret = smu_feature_dpmclk_check(smu, clk_type);
+	if (ret)
+		return ret;
+
 	clk_id = smu_clk_get_index(smu, clk_type);
 	if (clk_id < 0)
 		return clk_id;
@@ -227,6 +219,39 @@ int smu_get_dpm_level_count(struct smu_context *smu, enum smu_clk_type clk_type,
 	return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
 }
 
+int smu_feature_dpmclk_check(struct smu_context *smu, enum smu_clk_type clk_type)
+{
+	int ret = 0;
+
+	switch (clk_type) {
+	case SMU_MCLK:
+	case SMU_UCLK:
+		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+			pr_warn("uclk dpm is not enabled\n");
+			ret = -EACCES;
+		}
+		break;
+	case SMU_GFXCLK:
+	case SMU_SCLK:
+		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+			pr_warn("gfxclk dpm is not enabled\n");
+			ret = -EACCES;
+		}
+	case SMU_SOCCLK:
+		if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+			pr_warn("sockclk dpm is not enabled\n");
+			ret = -EACCES;
+		}
+		break;
+	default:
+		ret = 0;
+		break;
+	}
+
+	return ret;
+}
+
+
 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 			   bool gate)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index c97324ef7db2..0fbc8f489a49 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);
+int smu_feature_dpmclk_check(struct smu_context *smu, enum smu_clk_type clk_type);
 
 #endif
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/3] drm/amd/powerplay: avoid double check feature enabled
       [not found] ` <20190712091454.13478-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-12  9:15   ` Wang, Kevin(Yang)
       [not found]     ` <20190712091454.13478-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-12  9:15   ` [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu Wang, Kevin(Yang)
  2019-07-12  9:31   ` [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check " Quan, Evan
  2 siblings, 1 reply; 6+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-12  9:15 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Quan, Evan, Feng, Kenneth, Wang, Kevin(Yang)

the unforce_dpm_levels doesn't need to check feature enable,
because the smu_get_dpm_freq_range function has check feature logic.

Change-Id: I6ae62b355aa76a00f0f6e164cd9848fb32fc7c12
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++--------------
 1 file changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 16a4c1ca98cf..895a4e592d5a 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
 	return ret;
 }
 
-static int navi10_unforce_dpm_levels(struct smu_context *smu) {
-
+static int navi10_unforce_dpm_levels(struct smu_context *smu)
+{
 	int ret = 0, i = 0;
 	uint32_t min_freq, max_freq;
 	enum smu_clk_type clk_type;
 
-	struct clk_feature_map {
-		enum smu_clk_type clk_type;
-		uint32_t	feature;
-	} clk_feature_map[] = {
-		{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
-		{SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
-		{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
+	enum smu_clk_type clks[] = {
+		SMU_GFXCLK,
+		SMU_MCLK,
+		SMU_SOCCLK,
 	};
 
-	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
-		if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
-		    continue;
-
-		clk_type = clk_feature_map[i].clk_type;
-
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		clk_type = clks[i];
 		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
 		if (ret)
 			return ret;
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu
       [not found] ` <20190712091454.13478-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-12  9:15   ` [PATCH 2/3] drm/amd/powerplay: avoid double check feature enabled Wang, Kevin(Yang)
@ 2019-07-12  9:15   ` Wang, Kevin(Yang)
       [not found]     ` <20190712091454.13478-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-12  9:31   ` [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check " Quan, Evan
  2 siblings, 1 reply; 6+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-12  9:15 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Quan, Evan, Feng, Kenneth, Wang, Kevin(Yang)

the save dpm level should be save previous dpm profile level,
should not modified by get dpm level function.
eg: default auto
1. auto -> standard ==> dpm_level = standard, save_dpm = auto.
2. standard -> auto ==> dpm_level = auto, save_dpm = standard.

Change-Id: Ib6766e57cc187df4f0c89cc68dcee7efd77529fd
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index be90ae59dfa8..4abedf72a15e 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1428,17 +1428,16 @@ int smu_handle_task(struct smu_context *smu,
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
 {
 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+	enum amd_dpm_forced_level level;
 
 	if (!smu_dpm_ctx->dpm_context)
 		return -EINVAL;
 
 	mutex_lock(&(smu->mutex));
-	if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
-		smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
-	}
+	level = smu_dpm_ctx->dpm_level;
 	mutex_unlock(&(smu->mutex));
 
-	return smu_dpm_ctx->dpm_level;
+	return level;
 }
 
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
-- 
2.22.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* RE: [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check for smu
       [not found] ` <20190712091454.13478-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
  2019-07-12  9:15   ` [PATCH 2/3] drm/amd/powerplay: avoid double check feature enabled Wang, Kevin(Yang)
  2019-07-12  9:15   ` [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu Wang, Kevin(Yang)
@ 2019-07-12  9:31   ` Quan, Evan
  2 siblings, 0 replies; 6+ messages in thread
From: Quan, Evan @ 2019-07-12  9:31 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Feng, Kenneth

Please rename smu_feature_dpmclk_check as smu_is_clk_dpm_enabled or other more meaningful.

> +	switch (clk_type) {
> +	case SMU_MCLK:
> +	case SMU_UCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> +			pr_warn("uclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	case SMU_GFXCLK:
> +	case SMU_SCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> +			pr_warn("gfxclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +	case SMU_SOCCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> +			pr_warn("sockclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	default:
> +		ret = 0;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +

The code logic can be simplied as
switch (clk_type) {
	case SMU_MCLK:
	case SMU_UCLK:
                                  Clk_id = SMU_FEATURE_DPM_UCLK_BIT;
                                   Break;
	case SMU_GFXCLK:
	case SMU_SCLK:
                                    clk_id = SMU_FEATURE_DPM_GFXCLK_BIT;
                                    break;
......
}
if (!smu_feature_is_enabled(smu, clk_id)) {
			pr_warn("gfxclk dpm is not enabled\n");
			return 0;
}

Regards,
Evan
> -----Original Message-----
> From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
> Sent: Friday, July 12, 2019 5:15 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 1/3] drm/amd/powerplay: add helper of
> smu_feature_dpmclk_check for smu
> 
> add this helper function to check dpm clk feature is enabled.
> 
> Change-Id: I51a4e9246d83d74a8e687fbc45983848adc960ca
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c    | 71 +++++++++++++---
> ---
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  1 +
>  2 files changed, 49 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index da4332d2dbbc..be90ae59dfa8 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -68,6 +68,10 @@ int smu_set_soft_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (min <= 0 && max <= 0)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -101,6 +105,10 @@ int smu_set_hard_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (min <= 0 && max <= 0)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -134,29 +142,9 @@ int smu_get_dpm_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	if (!min && !max)
>  		return -EINVAL;
> 
> -	switch (clk_type) {
> -	case SMU_MCLK:
> -	case SMU_UCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> -			pr_warn("uclk dpm is not enabled\n");
> -			return 0;
> -		}
> -		break;
> -	case SMU_GFXCLK:
> -	case SMU_SCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> -			pr_warn("gfxclk dpm is not enabled\n");
> -			return 0;
> -		}
> -	case SMU_SOCCLK:
> -		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> -			pr_warn("sockclk dpm is not enabled\n");
> -			return 0;
> -		}
> -		break;
> -	default:
> -		break;
> -	}
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> 
>  	mutex_lock(&smu->mutex);
>  	clk_id = smu_clk_get_index(smu, clk_type); @@ -199,6 +187,10 @@
> int smu_get_dpm_freq_by_index(struct smu_context *smu, enum
> smu_clk_type clk_typ
>  	if (!value)
>  		return -EINVAL;
> 
> +	ret = smu_feature_dpmclk_check(smu, clk_type);
> +	if (ret)
> +		return ret;
> +
>  	clk_id = smu_clk_get_index(smu, clk_type);
>  	if (clk_id < 0)
>  		return clk_id;
> @@ -227,6 +219,39 @@ int smu_get_dpm_level_count(struct smu_context
> *smu, enum smu_clk_type clk_type,
>  	return smu_get_dpm_freq_by_index(smu, clk_type, 0xff, value);  }
> 
> +int smu_feature_dpmclk_check(struct smu_context *smu, enum
> smu_clk_type
> +clk_type) {
> +	int ret = 0;
> +
> +	switch (clk_type) {
> +	case SMU_MCLK:
> +	case SMU_UCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_UCLK_BIT)) {
> +			pr_warn("uclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	case SMU_GFXCLK:
> +	case SMU_SCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_GFXCLK_BIT)) {
> +			pr_warn("gfxclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +	case SMU_SOCCLK:
> +		if (!smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> +			pr_warn("sockclk dpm is not enabled\n");
> +			ret = -EACCES;
> +		}
> +		break;
> +	default:
> +		ret = 0;
> +		break;
> +	}
> +
> +	return ret;
> +}
> +
> +
>  int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t
> block_type,
>  			   bool gate)
>  {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index c97324ef7db2..0fbc8f489a49 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -973,5 +973,6 @@ int smu_set_hard_freq_range(struct smu_context
> *smu, enum smu_clk_type clk_type,  enum amd_dpm_forced_level
> smu_get_performance_level(struct smu_context *smu);  int
> smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level);  int smu_set_display_count(struct
> smu_context *smu, uint32_t count);
> +int smu_feature_dpmclk_check(struct smu_context *smu, enum
> smu_clk_type
> +clk_type);
> 
>  #endif
> --
> 2.22.0

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH 2/3] drm/amd/powerplay: avoid double check feature enabled
       [not found]     ` <20190712091454.13478-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-12  9:32       ` Quan, Evan
  0 siblings, 0 replies; 6+ messages in thread
From: Quan, Evan @ 2019-07-12  9:32 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Feng, Kenneth

> the unforce_dpm_levels doesn't need to check feature enable, because the
> smu_get_dpm_freq_range function has check feature logic.
enable -> enablement

With that fixed, reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
> Sent: Friday, July 12, 2019 5:15 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 2/3] drm/amd/powerplay: avoid double check feature
> enabled
> 
> the unforce_dpm_levels doesn't need to check feature enable, because the
> smu_get_dpm_freq_range function has check feature logic.
> 
> Change-Id: I6ae62b355aa76a00f0f6e164cd9848fb32fc7c12
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++--------------
>  1 file changed, 8 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> index 16a4c1ca98cf..895a4e592d5a 100644
> --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
> @@ -833,27 +833,20 @@ static int navi10_force_dpm_limit_value(struct
> smu_context *smu, bool highest)
>  	return ret;
>  }
> 
> -static int navi10_unforce_dpm_levels(struct smu_context *smu) {
> -
> +static int navi10_unforce_dpm_levels(struct smu_context *smu) {
>  	int ret = 0, i = 0;
>  	uint32_t min_freq, max_freq;
>  	enum smu_clk_type clk_type;
> 
> -	struct clk_feature_map {
> -		enum smu_clk_type clk_type;
> -		uint32_t	feature;
> -	} clk_feature_map[] = {
> -		{SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
> -		{SMU_MCLK,   SMU_FEATURE_DPM_UCLK_BIT},
> -		{SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
> +	enum smu_clk_type clks[] = {
> +		SMU_GFXCLK,
> +		SMU_MCLK,
> +		SMU_SOCCLK,
>  	};
> 
> -	for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
> -		if (!smu_feature_is_enabled(smu,
> clk_feature_map[i].feature))
> -		    continue;
> -
> -		clk_type = clk_feature_map[i].clk_type;
> -
> +	for (i = 0; i < ARRAY_SIZE(clks); i++) {
> +		clk_type = clks[i];
>  		ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq,
> &max_freq);
>  		if (ret)
>  			return ret;
> --
> 2.22.0

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^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu
       [not found]     ` <20190712091454.13478-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-12  9:36       ` Quan, Evan
  0 siblings, 0 replies; 6+ messages in thread
From: Quan, Evan @ 2019-07-12  9:36 UTC (permalink / raw)
  To: Wang, Kevin(Yang), amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: Xu, Feifei, Feng, Kenneth

> the save dpm level should be save previous dpm profile level, should not
> modified by get dpm level function.
Please give a better description to explain why this change is needed.


enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
 {
 	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
+	enum amd_dpm_forced_level level;
 
 	if (!smu_dpm_ctx->dpm_context)
 		return -EINVAL;
 
 	mutex_lock(&(smu->mutex));
-	if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level) {
-		smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
-	}
+	level = smu_dpm_ctx->dpm_level;
 	mutex_unlock(&(smu->mutex));
 
-	return smu_dpm_ctx->dpm_level;
+	return level;
 }

Can you simplify the interface further? Maybe just return smu_dpm_ctx->dpm_level and no lock needed.

With above addressed, the patch is eviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com>
> Sent: Friday, July 12, 2019 5:15 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Feng, Kenneth <Kenneth.Feng@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>; Xu, Feifei <Feifei.Xu@amd.com>; Wang,
> Kevin(Yang) <Kevin1.Wang@amd.com>
> Subject: [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu
> 
> the save dpm level should be save previous dpm profile level, should not
> modified by get dpm level function.
> eg: default auto
> 1. auto -> standard ==> dpm_level = standard, save_dpm = auto.
> 2. standard -> auto ==> dpm_level = auto, save_dpm = standard.
> 
> Change-Id: Ib6766e57cc187df4f0c89cc68dcee7efd77529fd
> Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index be90ae59dfa8..4abedf72a15e 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1428,17 +1428,16 @@ int smu_handle_task(struct smu_context *smu,
> enum amd_dpm_forced_level smu_get_performance_level(struct
> smu_context *smu)  {
>  	struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
> +	enum amd_dpm_forced_level level;
> 
>  	if (!smu_dpm_ctx->dpm_context)
>  		return -EINVAL;
> 
>  	mutex_lock(&(smu->mutex));
> -	if (smu_dpm_ctx->dpm_level != smu_dpm_ctx->saved_dpm_level)
> {
> -		smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx-
> >dpm_level;
> -	}
> +	level = smu_dpm_ctx->dpm_level;
>  	mutex_unlock(&(smu->mutex));
> 
> -	return smu_dpm_ctx->dpm_level;
> +	return level;
>  }
> 
>  int smu_force_performance_level(struct smu_context *smu, enum
> amd_dpm_forced_level level)
> --
> 2.22.0

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-07-12  9:36 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-12  9:15 [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check for smu Wang, Kevin(Yang)
     [not found] ` <20190712091454.13478-1-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-12  9:15   ` [PATCH 2/3] drm/amd/powerplay: avoid double check feature enabled Wang, Kevin(Yang)
     [not found]     ` <20190712091454.13478-2-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-12  9:32       ` Quan, Evan
2019-07-12  9:15   ` [PATCH 3/3] drm/amd/powerplay: fix save dpm level error for smu Wang, Kevin(Yang)
     [not found]     ` <20190712091454.13478-3-kevin1.wang-5C7GfCeVMHo@public.gmane.org>
2019-07-12  9:36       ` Quan, Evan
2019-07-12  9:31   ` [PATCH 1/3] drm/amd/powerplay: add helper of smu_feature_dpmclk_check " Quan, Evan

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