* [PATCH 0/5] Correct UVD/VCE/VCN powergate status retrieval
@ 2019-07-22 3:15 Evan Quan
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
VCN should be used for Vega20 later ASICs.
Evan Quan (5):
drm/amd/powerplay: add new sensor type for VCN powergate status
drm/amd/powerplay: support VCN powergate status retrieval on Raven
drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
drm/amd/powerplay: correct Navi10 VCN powergate control
drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 ++++++++++++-------
.../gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++
.../gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 +++------
5 files changed, 59 insertions(+), 37 deletions(-)
--
2.22.0
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 3:15 ` Evan Quan
[not found] ` <20190722031531.23437-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven Evan Quan
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 9733bbf9bc72..157e8546855d 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -123,6 +123,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
AMDGPU_PP_SENSOR_MIN_FAN_RPM,
AMDGPU_PP_SENSOR_MAX_FAN_RPM,
+ AMDGPU_PP_SENSOR_VCN_POWER,
};
enum amd_pp_task {
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status Evan Quan
@ 2019-07-22 3:15 ` Evan Quan
[not found] ` <20190722031531.23437-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU Evan Quan
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
Enable VCN powergate status report on Raven.
Change-Id: I60c793f8185ce6799b40a0cabd97d9c9fe5483fd
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index e32ae9d3373c..491a3cc776fc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1111,6 +1111,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size)
{
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
uint32_t sclk, mclk;
int ret = 0;
@@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
break;
+ case AMDGPU_PP_SENSOR_VCN_POWER:
+ *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
@@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
{
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
+
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0);
+ smu10_data->vcn_power_gated = true;
} else {
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
+ smu10_data->vcn_power_gated = false;
}
}
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status Evan Quan
2019-07-22 3:15 ` [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven Evan Quan
@ 2019-07-22 3:15 ` Evan Quan
[not found] ` <20190722031531.23437-4-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control Evan Quan
2019-07-22 3:15 ` [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval Evan Quan
4 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
Commonly used for VCN powergate status retrieval for SW SMU.
Change-Id: Ibc2f498848f728eb7727cd3fa889e91a2b09d07b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a837fa8..4e18f33a1bab 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -336,6 +336,10 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_VCN_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
--
2.22.0
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-07-22 3:15 ` [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU Evan Quan
@ 2019-07-22 3:15 ` Evan Quan
[not found] ` <20190722031531.23437-5-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval Evan Quan
4 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.
Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 ++++++++--------------
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bbae276..2198d373d38c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
{
int ret = 0;
- struct smu_power_context *smu_power = &smu->smu_power;
- struct smu_power_gate *power_gate = &smu_power->power_gate;
- if (enable && power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = false;
+ if (enable) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+ if (ret)
+ return ret;
} else {
- if (!enable && !power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = true;
- }
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ if (ret)
+ return ret;
}
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
return 0;
}
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-07-22 3:15 ` [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control Evan Quan
@ 2019-07-22 3:15 ` Evan Quan
[not found] ` <20190722031531.23437-6-evan.quan-5C7GfCeVMHo@public.gmane.org>
4 siblings, 1 reply; 13+ messages in thread
From: Evan Quan @ 2019-07-22 3:15 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Evan Quan
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.
Change-Id: Icc53d6fa176c48f0fc5348e79b8a5010357867eb
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +++++++++++++++++---------
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8f702cf5e080..f2b70db347a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -3065,28 +3065,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
- /* UVD clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
- if (!value) {
- seq_printf(m, "UVD: Disabled\n");
- } else {
- seq_printf(m, "UVD: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ if (adev->asic_type > CHIP_VEGA20) {
+ /* VCN clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "VCN: Disabled\n");
+ } else {
+ seq_printf(m, "VCN: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ }
}
- }
- seq_printf(m, "\n");
+ seq_printf(m, "\n");
+ } else {
+ /* UVD clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "UVD: Disabled\n");
+ } else {
+ seq_printf(m, "UVD: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ }
+ }
+ seq_printf(m, "\n");
- /* VCE clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
- if (!value) {
- seq_printf(m, "VCE: Disabled\n");
- } else {
- seq_printf(m, "VCE: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
+ /* VCE clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "VCE: Disabled\n");
+ } else {
+ seq_printf(m, "VCE: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
+ }
}
}
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status
[not found] ` <20190722031531.23437-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 4:26 ` Feng, Kenneth
[not found] ` <MN2PR12MB359851C9E6C7D57EE8E867188EC40-rweVpJHSKTohWwLleUddgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 13+ messages in thread
From: Feng, Kenneth @ 2019-07-22 4:26 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander, Quan, Evan
I just suggest that we use AMDGPU_PP_SENSOR_VCN_POWER_STATE instead of AMDGPU_PP_SENSOR_VCN_POWER,
since we gets the state of power on/off, not the real VCN power value.
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status
[CAUTION: External Email]
VCN is widely used in new ASICs and different from tranditional UVD and VCE.
Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 9733bbf9bc72..157e8546855d 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -123,6 +123,7 @@ enum amd_pp_sensors {
AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
AMDGPU_PP_SENSOR_MIN_FAN_RPM,
AMDGPU_PP_SENSOR_MAX_FAN_RPM,
+ AMDGPU_PP_SENSOR_VCN_POWER,
};
enum amd_pp_task {
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven
[not found] ` <20190722031531.23437-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 4:27 ` Feng, Kenneth
0 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-07-22 4:27 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander, Quan, Evan
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven
[CAUTION: External Email]
Enable VCN powergate status report on Raven.
Change-Id: I60c793f8185ce6799b40a0cabd97d9c9fe5483fd
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index e32ae9d3373c..491a3cc776fc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1111,6 +1111,7 @@ static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
void *value, int *size) {
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
+ *)(hwmgr->backend);
uint32_t sclk, mclk;
int ret = 0;
@@ -1132,6 +1133,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
case AMDGPU_PP_SENSOR_GPU_TEMP:
*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
break;
+ case AMDGPU_PP_SENSOR_VCN_POWER:
+ *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
@@ -1175,18 +1180,22 @@ static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) {
+ struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr
+ *)(hwmgr->backend);
+
if (bgate) {
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerDownVcn, 0);
+ smu10_data->vcn_power_gated = true;
} else {
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_PowerUpVcn, 0);
amdgpu_device_ip_set_powergating_state(hwmgr->adev,
AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_UNGATE);
+ smu10_data->vcn_power_gated = false;
}
}
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
[not found] ` <20190722031531.23437-4-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 4:28 ` Feng, Kenneth
0 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-07-22 4:28 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander, Quan, Evan
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:15 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
[CAUTION: External Email]
Commonly used for VCN powergate status retrieval for SW SMU.
Change-Id: Ibc2f498848f728eb7727cd3fa889e91a2b09d07b
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 416f9a837fa8..4e18f33a1bab 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -336,6 +336,10 @@ int smu_common_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor,
*(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_VCN_POWER:
+ *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT) ? 1 : 0;
+ *size = 4;
+ break;
default:
ret = -EINVAL;
break;
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
[not found] ` <20190722031531.23437-5-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 4:28 ` Feng, Kenneth
[not found] ` <MN2PR12MB3296FAF9BF4C2FBAF12C2496A2C40@MN2PR12MB3296.namprd12.prod.outlook.com>
0 siblings, 1 reply; 13+ messages in thread
From: Feng, Kenneth @ 2019-07-22 4:28 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander, Quan, Evan
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
[CAUTION: External Email]
No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN.
Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 ++++++++--------------
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bbae276..2198d373d38c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) {
int ret = 0;
- struct smu_power_context *smu_power = &smu->smu_power;
- struct smu_power_gate *power_gate = &smu_power->power_gate;
- if (enable && power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = false;
+ if (enable) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+ if (ret)
+ return ret;
} else {
- if (!enable && !power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = true;
- }
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ if (ret)
+ return ret;
}
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
return 0;
}
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
[not found] ` <20190722031531.23437-6-evan.quan-5C7GfCeVMHo@public.gmane.org>
@ 2019-07-22 4:29 ` Feng, Kenneth
0 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-07-22 4:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander, Quan, Evan
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan <Evan.Quan@amd.com>
Subject: [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
[CAUTION: External Email]
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs.
Change-Id: Icc53d6fa176c48f0fc5348e79b8a5010357867eb
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 56 +++++++++++++++++---------
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 8f702cf5e080..f2b70db347a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -3065,28 +3065,44 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
- /* UVD clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
- if (!value) {
- seq_printf(m, "UVD: Disabled\n");
- } else {
- seq_printf(m, "UVD: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ if (adev->asic_type > CHIP_VEGA20) {
+ /* VCN clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "VCN: Disabled\n");
+ } else {
+ seq_printf(m, "VCN: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ }
}
- }
- seq_printf(m, "\n");
+ seq_printf(m, "\n");
+ } else {
+ /* UVD clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "UVD: Disabled\n");
+ } else {
+ seq_printf(m, "UVD: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
+ }
+ }
+ seq_printf(m, "\n");
- /* VCE clocks */
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
- if (!value) {
- seq_printf(m, "VCE: Disabled\n");
- } else {
- seq_printf(m, "VCE: Enabled\n");
- if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
- seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
+ /* VCE clocks */
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
+ if (!value) {
+ seq_printf(m, "VCE: Disabled\n");
+ } else {
+ seq_printf(m, "VCE: Enabled\n");
+ if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
+ seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
+ }
}
}
--
2.22.0
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
[not found] ` <MN2PR12MB3344303C47BE91884B6D6293E4C40-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-22 6:45 ` Wang, Kevin(Yang)
0 siblings, 0 replies; 13+ messages in thread
From: Wang, Kevin(Yang) @ 2019-07-22 6:45 UTC (permalink / raw)
To: Quan, Evan, Feng, Kenneth, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander
[-- Attachment #1.1: Type: text/plain, Size: 6171 bytes --]
It's not necessary in the current code,
but if you update the implementation of the API one day,
your code won't look so strong.
I don't recommend it.
Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, July 22, 2019 2:42:26 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; Feng, Kenneth <Kenneth.Feng@amd.com>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
That does not really matters. The API will still return success even on smu_feature_set_enabled failure. It does not care about smu_feature_set_enabled failure.
But it helps me find another issue(about the naming smu_feature_set_enabled). I just sent out a patch to address that.
Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, July 22, 2019 1:39 PM
To: Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
you should check return value in smu anytime.
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org<mailto:kevin1.wang-5C7GfCeVMHo@public.gmane.org>>
Best Regards,
kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Feng, Kenneth <Kenneth.Feng-5C7GfCeVMHo@public.gmane.org<mailto:Kenneth.Feng-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, July 22, 2019 12:28:40 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32mMSPqsTGOZug@public.gmane.orgesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
Reviewed-by: Kenneth Feng <kenneth.feng-5C7GfCeVMHo@public.gmane.org<mailto:kenneth.feng-5C7GfCeVMHo@public.gmane.org>>
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org<mailto:Alexander.Deucher@amd.com>>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control
[CAUTION: External Email]
No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN.
Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 ++++++++--------------
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bbae276..2198d373d38c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable) {
int ret = 0;
- struct smu_power_context *smu_power = &smu->smu_power;
- struct smu_power_gate *power_gate = &smu_power->power_gate;
- if (enable && power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = false;
+ if (enable) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+ if (ret)
+ return ret;
} else {
- if (!enable && !power_gate->uvd_gated) {
- if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
- ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
- if (ret)
- return ret;
- }
- power_gate->uvd_gated = true;
- }
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ if (ret)
+ return ret;
}
+ smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
return 0;
}
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[-- Attachment #1.2: Type: text/html, Size: 12538 bytes --]
[-- Attachment #2: Type: text/plain, Size: 153 bytes --]
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* RE: [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status
[not found] ` <MN2PR12MB359851C9E6C7D57EE8E867188EC40-rweVpJHSKTohWwLleUddgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2019-07-22 6:47 ` Quan, Evan
0 siblings, 0 replies; 13+ messages in thread
From: Quan, Evan @ 2019-07-22 6:47 UTC (permalink / raw)
To: Feng, Kenneth, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Deucher, Alexander
Good point. It was following old naming style.
But I think we can make some changes to make it more understandable.
Let me address this in the V2 version.
Regards,
Evan
> -----Original Message-----
> From: Feng, Kenneth <Kenneth.Feng@amd.com>
> Sent: Monday, July 22, 2019 12:27 PM
> To: Quan, Evan <Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>
> Subject: RE: [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN
> powergate status
>
> I just suggest that we use AMDGPU_PP_SENSOR_VCN_POWER_STATE
> instead of AMDGPU_PP_SENSOR_VCN_POWER, since we gets the state of
> power on/off, not the real VCN power value.
> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
>
>
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Evan Quan
> Sent: Monday, July 22, 2019 11:15 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>
> Subject: [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN
> powergate status
>
> [CAUTION: External Email]
>
> VCN is widely used in new ASICs and different from tranditional UVD and VCE.
>
> Change-Id: I35c9db420734029e8f847dcdce23dff1204d70bc
> Signed-off-by: Evan Quan <evan.quan@amd.com>
> ---
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 9733bbf9bc72..157e8546855d 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -123,6 +123,7 @@ enum amd_pp_sensors {
> AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
> AMDGPU_PP_SENSOR_MIN_FAN_RPM,
> AMDGPU_PP_SENSOR_MAX_FAN_RPM,
> + AMDGPU_PP_SENSOR_VCN_POWER,
> };
>
> enum amd_pp_task {
> --
> 2.22.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-07-22 6:47 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-22 3:15 [PATCH 0/5] Correct UVD/VCE/VCN powergate status retrieval Evan Quan
[not found] ` <20190722031531.23437-1-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 3:15 ` [PATCH 1/5] drm/amd/powerplay: add new sensor type for VCN powergate status Evan Quan
[not found] ` <20190722031531.23437-2-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 4:26 ` Feng, Kenneth
[not found] ` <MN2PR12MB359851C9E6C7D57EE8E867188EC40-rweVpJHSKTohWwLleUddgQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-22 6:47 ` Quan, Evan
2019-07-22 3:15 ` [PATCH 2/5] drm/amd/powerplay: support VCN powergate status retrieval on Raven Evan Quan
[not found] ` <20190722031531.23437-3-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 4:27 ` Feng, Kenneth
2019-07-22 3:15 ` [PATCH 3/5] drm/amd/powerplay: support VCN powergate status retrieval for SW SMU Evan Quan
[not found] ` <20190722031531.23437-4-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 4:28 ` Feng, Kenneth
2019-07-22 3:15 ` [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control Evan Quan
[not found] ` <20190722031531.23437-5-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 4:28 ` Feng, Kenneth
[not found] ` <MN2PR12MB3296FAF9BF4C2FBAF12C2496A2C40@MN2PR12MB3296.namprd12.prod.outlook.com>
[not found] ` <MN2PR12MB3344303C47BE91884B6D6293E4C40@MN2PR12MB3344.namprd12.prod.outlook.com>
[not found] ` <MN2PR12MB3344303C47BE91884B6D6293E4C40-rweVpJHSKToDMgCC8P//OwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-22 6:45 ` Wang, Kevin(Yang)
2019-07-22 3:15 ` [PATCH 5/5] drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval Evan Quan
[not found] ` <20190722031531.23437-6-evan.quan-5C7GfCeVMHo@public.gmane.org>
2019-07-22 4:29 ` Feng, Kenneth
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