* [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
@ 2020-03-04 2:55 Prike Liang
2020-03-04 2:55 ` [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case Prike Liang
2020-03-09 13:10 ` [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Bjorn Helgaas
0 siblings, 2 replies; 5+ messages in thread
From: Prike Liang @ 2020-03-04 2:55 UTC (permalink / raw)
To: amd-gfx; +Cc: Prike Liang, Evan.quan, ray.huang
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.
cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e3398f9..d454493 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
{
int ret = 0;
- if (min <= 0 && max <= 0)
+ if (min < 0 && max < 0)
return -EINVAL;
if (!smu_clk_dpm_is_enabled(smu, clk_type))
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 93b8558..d52e624 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -461,9 +461,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
{
int ret = 0;
- if (max < min)
- return -EINVAL;
-
switch (clk_type) {
case SMU_GFXCLK:
case SMU_SCLK:
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
2020-03-04 2:55 [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Prike Liang
@ 2020-03-04 2:55 ` Prike Liang
2020-03-04 3:20 ` Quan, Evan
2020-03-09 13:10 ` [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Bjorn Helgaas
1 sibling, 1 reply; 5+ messages in thread
From: Prike Liang @ 2020-03-04 2:55 UTC (permalink / raw)
To: amd-gfx; +Cc: Prike Liang, Evan.quan, ray.huang
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index cca4820..653faad 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -111,8 +111,8 @@ static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(GFXCLK, CLOCK_GFXCLK),
CLK_MAP(SCLK, CLOCK_GFXCLK),
CLK_MAP(SOCCLK, CLOCK_SOCCLK),
- CLK_MAP(UCLK, CLOCK_UMCCLK),
- CLK_MAP(MCLK, CLOCK_UMCCLK),
+ CLK_MAP(UCLK, CLOCK_FCLK),
+ CLK_MAP(MCLK, CLOCK_FCLK),
};
static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
@@ -280,7 +280,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
break;
case SMU_MCLK:
count = NUM_MEMCLK_DPM_LEVELS;
- cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
+ cur_value = metrics.ClockFrequency[CLOCK_FCLK];
break;
case SMU_DCEFCLK:
count = NUM_DCFCLK_DPM_LEVELS;
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
2020-03-04 2:55 ` [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case Prike Liang
@ 2020-03-04 3:20 ` Quan, Evan
0 siblings, 0 replies; 5+ messages in thread
From: Quan, Evan @ 2020-03-04 3:20 UTC (permalink / raw)
To: Liang, Prike, amd-gfx; +Cc: Huang, Ray
Series is reviewed-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: Liang, Prike <Prike.Liang@amd.com>
Sent: Wednesday, March 4, 2020 10:56 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan <Evan.Quan@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liang, Prike <Prike.Liang@amd.com>
Subject: [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export
fclk frequency to user usage.
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index cca4820..653faad 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -111,8 +111,8 @@ static struct smu_12_0_cmn2aisc_mapping renoir_clk_map[SMU_CLK_COUNT] = {
CLK_MAP(GFXCLK, CLOCK_GFXCLK),
CLK_MAP(SCLK, CLOCK_GFXCLK),
CLK_MAP(SOCCLK, CLOCK_SOCCLK),
- CLK_MAP(UCLK, CLOCK_UMCCLK),
- CLK_MAP(MCLK, CLOCK_UMCCLK),
+ CLK_MAP(UCLK, CLOCK_FCLK),
+ CLK_MAP(MCLK, CLOCK_FCLK),
};
static struct smu_12_0_cmn2aisc_mapping renoir_table_map[SMU_TABLE_COUNT] = {
@@ -280,7 +280,7 @@ static int renoir_print_clk_levels(struct smu_context *smu,
break;
case SMU_MCLK:
count = NUM_MEMCLK_DPM_LEVELS;
- cur_value = metrics.ClockFrequency[CLOCK_UMCCLK];
+ cur_value = metrics.ClockFrequency[CLOCK_FCLK];
break;
case SMU_DCEFCLK:
count = NUM_DCFCLK_DPM_LEVELS;
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
2020-03-04 2:55 [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Prike Liang
2020-03-04 2:55 ` [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case Prike Liang
@ 2020-03-09 13:10 ` Bjorn Helgaas
2020-03-10 0:05 ` Liang, Prike
1 sibling, 1 reply; 5+ messages in thread
From: Bjorn Helgaas @ 2020-03-09 13:10 UTC (permalink / raw)
To: Prike Liang; +Cc: Alex Deucher, Evan.quan, ray.huang, linux-kernel, amd-gfx
On Wed, Mar 04, 2020 at 10:55:37AM +0800, Prike Liang wrote:
> This fix will handle some MP1 FW issue like as mclk dpm table in
> renoir has a reverse dpm clock layout and a zero frequency dpm level
> as following case.
>
> cat pp_dpm_mclk
> 0: 1200Mhz
> 1: 1200Mhz
> 2: 800Mhz
> 3: 0Mhz
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
> drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index e3398f9..d454493 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
> {
> int ret = 0;
>
> - if (min <= 0 && max <= 0)
> + if (min < 0 && max < 0)
This change causes the following Coverity warning because min and max
are both unsigned:
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max)
>>> CID 1460516: Integer handling issues (NO_EFFECT)
>>> This less-than-zero comparison of an unsigned value is never true. "min < 0U".
225 if (min < 0 && max < 0)
226 return -EINVAL;
> return -EINVAL;
>
> if (!smu_clk_dpm_is_enabled(smu, clk_type))
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^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range
2020-03-09 13:10 ` [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Bjorn Helgaas
@ 2020-03-10 0:05 ` Liang, Prike
0 siblings, 0 replies; 5+ messages in thread
From: Liang, Prike @ 2020-03-10 0:05 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Deucher, Alexander, Quan, Evan, Huang, Ray, linux-kernel, amd-gfx
> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Monday, March 9, 2020 9:11 PM
> To: Liang, Prike <Prike.Liang@amd.com>
> Cc: amd-gfx@lists.freedesktop.org; Quan, Evan <Evan.Quan@amd.com>;
> Huang, Ray <Ray.Huang@amd.com>; linux-kernel@vger.org; Deucher,
> Alexander <Alexander.Deucher@amd.com>
> Subject: Re: [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for
> setting clock range
>
> On Wed, Mar 04, 2020 at 10:55:37AM +0800, Prike Liang wrote:
> > This fix will handle some MP1 FW issue like as mclk dpm table in
> > renoir has a reverse dpm clock layout and a zero frequency dpm level
> > as following case.
> >
> > cat pp_dpm_mclk
> > 0: 1200Mhz
> > 1: 1200Mhz
> > 2: 800Mhz
> > 3: 0Mhz
> >
> > Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> > ---
> > drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 2 +-
> > drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 ---
> > 2 files changed, 1 insertion(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > index e3398f9..d454493 100644
> > --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> > @@ -214,7 +214,7 @@ int smu_set_soft_freq_range(struct smu_context
> > *smu, enum smu_clk_type clk_type, {
> > int ret = 0;
> >
> > - if (min <= 0 && max <= 0)
> > + if (min < 0 && max < 0)
>
> This change causes the following Coverity warning because min and max are
> both unsigned:
>
> int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type
> clk_type,
> uint32_t min, uint32_t max)
>
> >>> CID 1460516: Integer handling issues (NO_EFFECT)
> >>> This less-than-zero comparison of an unsigned value is never true.
> "min < 0U".
[Prike] Thanks and will fix the Coverity warning.
> 225 if (min < 0 && max < 0)
> 226 return -EINVAL;
>
> > return -EINVAL;
> >
> > if (!smu_clk_dpm_is_enabled(smu, clk_type))
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-03-10 0:05 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-03-04 2:55 [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Prike Liang
2020-03-04 2:55 ` [PATCH 2/2] drm/amd/powerplay: map mclk to fclk for COMBINATIONAL_BYPASS case Prike Liang
2020-03-04 3:20 ` Quan, Evan
2020-03-09 13:10 ` [PATCH 1/2] drm/amd/powerplay: fix pre-check condition for setting clock range Bjorn Helgaas
2020-03-10 0:05 ` Liang, Prike
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