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* [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
@ 2019-11-13 16:23 ` Alex Deucher
  0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2019-11-13 16:23 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher

So that the setting reflects what the hw supports. This will
be used in a subsequent patch so needs to be correct.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 57459a65eb44..ad39db49a29d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		vega20_set_ppt_funcs(smu);
 		break;
 	case CHIP_NAVI10:
@@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 		navi10_set_ppt_funcs(smu);
 		break;
 	case CHIP_ARCTURUS:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		arcturus_set_ppt_funcs(smu);
 		/* OD is not supported on Arcturus */
 		smu->od_enabled =false;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index a24beaa4fb01..443625c83ec9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
 
 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 {
+	struct amdgpu_device *adev = hwmgr->adev;
+
 	if (!hwmgr)
 		return -EINVAL;
 
@@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CI:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->smumgr_funcs = &ci_smu_funcs;
 		ci_set_asic_special_caps(hwmgr);
 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
@@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 		smu7_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_CZ:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->od_enabled = false;
 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		smu8_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_VI:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		switch (hwmgr->chip_id) {
 		case CHIP_TOPAZ:
@@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	case AMDGPU_FAMILY_AI:
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
+			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 			vega10_hwmgr_init(hwmgr);
@@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 			vega12_hwmgr_init(hwmgr);
 			break;
 		case CHIP_VEGA20:
+			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 			hwmgr->smumgr_funcs = &vega20_smu_funcs;
 			vega20_hwmgr_init(hwmgr);
-- 
2.23.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
@ 2019-11-13 16:23 ` Alex Deucher
  0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2019-11-13 16:23 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

So that the setting reflects what the hw supports. This will
be used in a subsequent patch so needs to be correct.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  | 2 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 57459a65eb44..ad39db49a29d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		vega20_set_ppt_funcs(smu);
 		break;
 	case CHIP_NAVI10:
@@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
 		navi10_set_ppt_funcs(smu);
 		break;
 	case CHIP_ARCTURUS:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		arcturus_set_ppt_funcs(smu);
 		/* OD is not supported on Arcturus */
 		smu->od_enabled =false;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index a24beaa4fb01..443625c83ec9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
 
 int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 {
+	struct amdgpu_device *adev = hwmgr->adev;
+
 	if (!hwmgr)
 		return -EINVAL;
 
@@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CI:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->smumgr_funcs = &ci_smu_funcs;
 		ci_set_asic_special_caps(hwmgr);
 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
@@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 		smu7_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_CZ:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->od_enabled = false;
 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		smu8_init_function_pointers(hwmgr);
 		break;
 	case AMDGPU_FAMILY_VI:
+		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 		switch (hwmgr->chip_id) {
 		case CHIP_TOPAZ:
@@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	case AMDGPU_FAMILY_AI:
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
+			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 			vega10_hwmgr_init(hwmgr);
@@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 			vega12_hwmgr_init(hwmgr);
 			break;
 		case CHIP_VEGA20:
+			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
 			hwmgr->smumgr_funcs = &vega20_smu_funcs;
 			vega20_hwmgr_init(hwmgr);
-- 
2.23.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu: don't read registers if gfxoff is enabled (v2)
@ 2019-11-13 16:23     ` Alex Deucher
  0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2019-11-13 16:23 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Evan Quan

When gfxoff is enabled, accessing gfx registers via MMIO
can lead to a hang.

v2: return cached registers properly.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c    | 27 ++++++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++++++++------------
 2 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index af68f9815f28..7283d6198b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -201,17 +201,25 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 	return val;
 }
 
-static uint32_t nv_get_register_value(struct amdgpu_device *adev,
+static int nv_get_register_value(struct amdgpu_device *adev,
 				      bool indexed, u32 se_num,
-				      u32 sh_num, u32 reg_offset)
+				      u32 sh_num, u32 reg_offset,
+				      u32 *value)
 {
 	if (indexed) {
-		return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+			return -EINVAL;
+		*value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
-			return adev->gfx.config.gb_addr_config;
-		return RREG32(reg_offset);
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+			*value = adev->gfx.config.gb_addr_config;
+		} else {
+			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+				return -EINVAL;
+			*value = RREG32(reg_offset);
+		}
 	}
+	return 0;
 }
 
 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -227,10 +235,9 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 			continue;
 
-		*value = nv_get_register_value(adev,
-					       nv_allowed_read_registers[i].grbm_indexed,
-					       se_num, sh_num, reg_offset);
-		return 0;
+		return nv_get_register_value(adev,
+					     nv_allowed_read_registers[i].grbm_indexed,
+					     se_num, sh_num, reg_offset, value);
 	}
 	return -EINVAL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 305ad3eec987..2cc16e9f39fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -363,19 +363,27 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
 	return val;
 }
 
-static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+static int soc15_get_register_value(struct amdgpu_device *adev,
 					 bool indexed, u32 se_num,
-					 u32 sh_num, u32 reg_offset)
+					 u32 sh_num, u32 reg_offset,
+					 u32 *value)
 {
 	if (indexed) {
-		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+			return -EINVAL;
+	        *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
-			return adev->gfx.config.gb_addr_config;
-		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
-			return adev->gfx.config.db_debug2;
-		return RREG32(reg_offset);
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+			*value = adev->gfx.config.gb_addr_config;
+		} else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
+			*value = adev->gfx.config.db_debug2;
+		} else {
+			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+				return -EINVAL;
+			*value = RREG32(reg_offset);
+		}
 	}
+	return 0;
 }
 
 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -391,10 +399,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 					+ en->reg_offset))
 			continue;
 
-		*value = soc15_get_register_value(adev,
-						  soc15_allowed_read_registers[i].grbm_indexed,
-						  se_num, sh_num, reg_offset);
-		return 0;
+		return soc15_get_register_value(adev,
+						soc15_allowed_read_registers[i].grbm_indexed,
+						se_num, sh_num, reg_offset, value);
 	}
 	return -EINVAL;
 }
-- 
2.23.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu: don't read registers if gfxoff is enabled (v2)
@ 2019-11-13 16:23     ` Alex Deucher
  0 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2019-11-13 16:23 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher, Evan Quan

When gfxoff is enabled, accessing gfx registers via MMIO
can lead to a hang.

v2: return cached registers properly.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205497
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c    | 27 ++++++++++++++++----------
 drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ++++++++++++++++++------------
 2 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index af68f9815f28..7283d6198b89 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -201,17 +201,25 @@ static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 	return val;
 }
 
-static uint32_t nv_get_register_value(struct amdgpu_device *adev,
+static int nv_get_register_value(struct amdgpu_device *adev,
 				      bool indexed, u32 se_num,
-				      u32 sh_num, u32 reg_offset)
+				      u32 sh_num, u32 reg_offset,
+				      u32 *value)
 {
 	if (indexed) {
-		return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+			return -EINVAL;
+		*value = nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
-			return adev->gfx.config.gb_addr_config;
-		return RREG32(reg_offset);
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+			*value = adev->gfx.config.gb_addr_config;
+		} else {
+			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+				return -EINVAL;
+			*value = RREG32(reg_offset);
+		}
 	}
+	return 0;
 }
 
 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -227,10 +235,9 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 		    (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 			continue;
 
-		*value = nv_get_register_value(adev,
-					       nv_allowed_read_registers[i].grbm_indexed,
-					       se_num, sh_num, reg_offset);
-		return 0;
+		return nv_get_register_value(adev,
+					     nv_allowed_read_registers[i].grbm_indexed,
+					     se_num, sh_num, reg_offset, value);
 	}
 	return -EINVAL;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 305ad3eec987..2cc16e9f39fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -363,19 +363,27 @@ static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_n
 	return val;
 }
 
-static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+static int soc15_get_register_value(struct amdgpu_device *adev,
 					 bool indexed, u32 se_num,
-					 u32 sh_num, u32 reg_offset)
+					 u32 sh_num, u32 reg_offset,
+					 u32 *value)
 {
 	if (indexed) {
-		return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+		if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+			return -EINVAL;
+	        *value = soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
 	} else {
-		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
-			return adev->gfx.config.gb_addr_config;
-		else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2))
-			return adev->gfx.config.db_debug2;
-		return RREG32(reg_offset);
+		if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) {
+			*value = adev->gfx.config.gb_addr_config;
+		} else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) {
+			*value = adev->gfx.config.db_debug2;
+		} else {
+			if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+				return -EINVAL;
+			*value = RREG32(reg_offset);
+		}
 	}
+	return 0;
 }
 
 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
@@ -391,10 +399,9 @@ static int soc15_read_register(struct amdgpu_device *adev, u32 se_num,
 					+ en->reg_offset))
 			continue;
 
-		*value = soc15_get_register_value(adev,
-						  soc15_allowed_read_registers[i].grbm_indexed,
-						  se_num, sh_num, reg_offset);
-		return 0;
+		return soc15_get_register_value(adev,
+						soc15_allowed_read_registers[i].grbm_indexed,
+						se_num, sh_num, reg_offset, value);
 	}
 	return -EINVAL;
 }
-- 
2.23.0

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
@ 2019-11-14  2:32     ` Quan, Evan
  0 siblings, 0 replies; 6+ messages in thread
From: Quan, Evan @ 2019-11-14  2:32 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Deucher, Alexander

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, November 14, 2019 12:23 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
> 
> So that the setting reflects what the hw supports. This will be used in a
> subsequent patch so needs to be correct.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 57459a65eb44..ad39db49a29d 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> 
>  	switch (adev->asic_type) {
>  	case CHIP_VEGA20:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		vega20_set_ppt_funcs(smu);
>  		break;
>  	case CHIP_NAVI10:
> @@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>  		navi10_set_ppt_funcs(smu);
>  		break;
>  	case CHIP_ARCTURUS:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		arcturus_set_ppt_funcs(smu);
>  		/* OD is not supported on Arcturus */
>  		smu->od_enabled =false;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index a24beaa4fb01..443625c83ec9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct
> pp_hwmgr *hwmgr)
> 
>  int hwmgr_early_init(struct pp_hwmgr *hwmgr)  {
> +	struct amdgpu_device *adev = hwmgr->adev;
> +
>  	if (!hwmgr)
>  		return -EINVAL;
> 
> @@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> 
>  	switch (hwmgr->chip_family) {
>  	case AMDGPU_FAMILY_CI:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->smumgr_funcs = &ci_smu_funcs;
>  		ci_set_asic_special_caps(hwmgr);
>  		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
> @@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  		smu7_init_function_pointers(hwmgr);
>  		break;
>  	case AMDGPU_FAMILY_CZ:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->od_enabled = false;
>  		hwmgr->smumgr_funcs = &smu8_smu_funcs;
>  		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  		smu8_init_function_pointers(hwmgr);
>  		break;
>  	case AMDGPU_FAMILY_VI:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  		switch (hwmgr->chip_id) {
>  		case CHIP_TOPAZ:
> @@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  	case AMDGPU_FAMILY_AI:
>  		switch (hwmgr->chip_id) {
>  		case CHIP_VEGA10:
> +			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  			hwmgr->smumgr_funcs = &vega10_smu_funcs;
>  			vega10_hwmgr_init(hwmgr);
> @@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  			vega12_hwmgr_init(hwmgr);
>  			break;
>  		case CHIP_VEGA20:
> +			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  			hwmgr->smumgr_funcs = &vega20_smu_funcs;
>  			vega20_hwmgr_init(hwmgr);
> --
> 2.23.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
@ 2019-11-14  2:32     ` Quan, Evan
  0 siblings, 0 replies; 6+ messages in thread
From: Quan, Evan @ 2019-11-14  2:32 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex
> Deucher
> Sent: Thursday, November 14, 2019 12:23 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK
> 
> So that the setting reflects what the hw supports. This will be used in a
> subsequent patch so needs to be correct.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index 57459a65eb44..ad39db49a29d 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -719,6 +719,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
> 
>  	switch (adev->asic_type) {
>  	case CHIP_VEGA20:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		vega20_set_ppt_funcs(smu);
>  		break;
>  	case CHIP_NAVI10:
> @@ -727,6 +728,7 @@ static int smu_set_funcs(struct amdgpu_device *adev)
>  		navi10_set_ppt_funcs(smu);
>  		break;
>  	case CHIP_ARCTURUS:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		arcturus_set_ppt_funcs(smu);
>  		/* OD is not supported on Arcturus */
>  		smu->od_enabled =false;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index a24beaa4fb01..443625c83ec9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -81,6 +81,8 @@ static void hwmgr_init_workload_prority(struct
> pp_hwmgr *hwmgr)
> 
>  int hwmgr_early_init(struct pp_hwmgr *hwmgr)  {
> +	struct amdgpu_device *adev = hwmgr->adev;
> +
>  	if (!hwmgr)
>  		return -EINVAL;
> 
> @@ -96,6 +98,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
> 
>  	switch (hwmgr->chip_family) {
>  	case AMDGPU_FAMILY_CI:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->smumgr_funcs = &ci_smu_funcs;
>  		ci_set_asic_special_caps(hwmgr);
>  		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
> @@ -106,12 +109,14 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  		smu7_init_function_pointers(hwmgr);
>  		break;
>  	case AMDGPU_FAMILY_CZ:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->od_enabled = false;
>  		hwmgr->smumgr_funcs = &smu8_smu_funcs;
>  		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  		smu8_init_function_pointers(hwmgr);
>  		break;
>  	case AMDGPU_FAMILY_VI:
> +		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  		switch (hwmgr->chip_id) {
>  		case CHIP_TOPAZ:
> @@ -153,6 +158,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  	case AMDGPU_FAMILY_AI:
>  		switch (hwmgr->chip_id) {
>  		case CHIP_VEGA10:
> +			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  			hwmgr->smumgr_funcs = &vega10_smu_funcs;
>  			vega10_hwmgr_init(hwmgr);
> @@ -162,6 +168,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  			vega12_hwmgr_init(hwmgr);
>  			break;
>  		case CHIP_VEGA20:
> +			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
>  			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
>  			hwmgr->smumgr_funcs = &vega20_smu_funcs;
>  			vega20_hwmgr_init(hwmgr);
> --
> 2.23.0
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-11-14  2:32 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-13 16:23 [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK Alex Deucher
2019-11-13 16:23 ` Alex Deucher
     [not found] ` <20191113162314.520605-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2019-11-13 16:23   ` [PATCH 2/2] drm/amdgpu: don't read registers if gfxoff is enabled (v2) Alex Deucher
2019-11-13 16:23     ` Alex Deucher
2019-11-14  2:32   ` [PATCH 1/2] drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK Quan, Evan
2019-11-14  2:32     ` Quan, Evan

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