* [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost
@ 2019-04-30 15:14 Trigger Huang
[not found] ` <1556637284-715-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Trigger Huang @ 2019-04-30 15:14 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Trigger.Huang-5C7GfCeVMHo
In Multi-VFs stress test, sometimes we see IRQ lost when running
benchmark, just rearm it.
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 37 +++++++++++++++++++++++++++++++++-
1 file changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 1b2f69a..8d89ab7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -31,7 +31,7 @@
#include "soc15_common.h"
#include "vega10_ih.h"
-
+#define MAX_REARM_RETRY 10
static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
@@ -382,6 +382,38 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
}
/**
+ * vega10_ih_irq_rearm - rearm IRQ if lost
+ *
+ * @adev: amdgpu_device pointer
+ *
+ */
+static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
+ struct amdgpu_ih_ring *ih)
+{
+ uint32_t reg_rptr = 0;
+ uint32_t v = 0;
+ uint32_t i = 0;
+
+ if (ih == &adev->irq.ih)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
+ else if (ih == &adev->irq.ih1)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
+ else if (ih == &adev->irq.ih2)
+ reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
+ else
+ return;
+
+ /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
+ for (i = 0; i < MAX_REARM_RETRY; i++) {
+ v = RREG32_NO_KIQ(reg_rptr);
+ if ((v < ih->ring_size) && (v != ih->rptr))
+ WDOORBELL32(ih->doorbell_index, ih->rptr);
+ else
+ break;
+ }
+}
+
+/**
* vega10_ih_set_rptr - set the IH ring buffer rptr
*
* @adev: amdgpu_device pointer
@@ -395,6 +427,9 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
/* XXX check if swapping is necessary on BE */
*ih->rptr_cpu = ih->rptr;
WDOORBELL32(ih->doorbell_index, ih->rptr);
+
+ if (amdgpu_sriov_vf(adev))
+ vega10_ih_irq_rearm(adev, ih);
} else if (ih == &adev->irq.ih) {
WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
} else if (ih == &adev->irq.ih1) {
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost
[not found] ` <1556637284-715-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
@ 2019-04-30 17:10 ` Christian König
[not found] ` <c9c462e1-f73f-64f0-31f8-3bbceefbea60-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Christian König @ 2019-04-30 17:10 UTC (permalink / raw)
To: Trigger Huang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 30.04.19 um 17:14 schrieb Trigger Huang:
> In Multi-VFs stress test, sometimes we see IRQ lost when running
> benchmark, just rearm it.
Well I think I have seen that on bare metal as well, it would certainly
explain some very odd behavior I've got from the IH block.
Have you pinged the hw guys about that already?
> Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 37 +++++++++++++++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 1b2f69a..8d89ab7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -31,7 +31,7 @@
> #include "soc15_common.h"
> #include "vega10_ih.h"
>
> -
> +#define MAX_REARM_RETRY 10
>
> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
>
> @@ -382,6 +382,38 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
> }
>
> /**
> + * vega10_ih_irq_rearm - rearm IRQ if lost
> + *
> + * @adev: amdgpu_device pointer
> + *
> + */
> +static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih)
> +{
> + uint32_t reg_rptr = 0;
> + uint32_t v = 0;
> + uint32_t i = 0;
> +
> + if (ih == &adev->irq.ih)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
> + else if (ih == &adev->irq.ih1)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
> + else if (ih == &adev->irq.ih2)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
> + else
> + return;
> +
> + /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
> + for (i = 0; i < MAX_REARM_RETRY; i++) {
> + v = RREG32_NO_KIQ(reg_rptr);
> + if ((v < ih->ring_size) && (v != ih->rptr))
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> + else
> + break;
> + }
> +}
> +
> +/**
> * vega10_ih_set_rptr - set the IH ring buffer rptr
> *
> * @adev: amdgpu_device pointer
> @@ -395,6 +427,9 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
> /* XXX check if swapping is necessary on BE */
> *ih->rptr_cpu = ih->rptr;
> WDOORBELL32(ih->doorbell_index, ih->rptr);
> +
> + if (amdgpu_sriov_vf(adev))
> + vega10_ih_irq_rearm(adev, ih);
> } else if (ih == &adev->irq.ih) {
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> } else if (ih == &adev->irq.ih1) {
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost
[not found] ` <c9c462e1-f73f-64f0-31f8-3bbceefbea60-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2019-04-30 17:25 ` Alex Deucher
2019-05-01 14:32 ` Huang, Trigger
1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2019-04-30 17:25 UTC (permalink / raw)
To: Christian Koenig; +Cc: amd-gfx list, Trigger Huang
On Tue, Apr 30, 2019 at 1:10 PM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 30.04.19 um 17:14 schrieb Trigger Huang:
> > In Multi-VFs stress test, sometimes we see IRQ lost when running
> > benchmark, just rearm it.
>
> Well I think I have seen that on bare metal as well, it would certainly
> explain some very odd behavior I've got from the IH block.
Maybe we should enable this for bare metal too in a follow up patch.
Alex
>
> Have you pinged the hw guys about that already?
>
> > Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
>
> Acked-by: Christian König <christian.koenig@amd.com>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 37 +++++++++++++++++++++++++++++++++-
> > 1 file changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > index 1b2f69a..8d89ab7 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> > @@ -31,7 +31,7 @@
> > #include "soc15_common.h"
> > #include "vega10_ih.h"
> >
> > -
> > +#define MAX_REARM_RETRY 10
> >
> > static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
> >
> > @@ -382,6 +382,38 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
> > }
> >
> > /**
> > + * vega10_ih_irq_rearm - rearm IRQ if lost
> > + *
> > + * @adev: amdgpu_device pointer
> > + *
> > + */
> > +static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
> > + struct amdgpu_ih_ring *ih)
> > +{
> > + uint32_t reg_rptr = 0;
> > + uint32_t v = 0;
> > + uint32_t i = 0;
> > +
> > + if (ih == &adev->irq.ih)
> > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
> > + else if (ih == &adev->irq.ih1)
> > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
> > + else if (ih == &adev->irq.ih2)
> > + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
> > + else
> > + return;
> > +
> > + /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
> > + for (i = 0; i < MAX_REARM_RETRY; i++) {
> > + v = RREG32_NO_KIQ(reg_rptr);
> > + if ((v < ih->ring_size) && (v != ih->rptr))
> > + WDOORBELL32(ih->doorbell_index, ih->rptr);
> > + else
> > + break;
> > + }
> > +}
> > +
> > +/**
> > * vega10_ih_set_rptr - set the IH ring buffer rptr
> > *
> > * @adev: amdgpu_device pointer
> > @@ -395,6 +427,9 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
> > /* XXX check if swapping is necessary on BE */
> > *ih->rptr_cpu = ih->rptr;
> > WDOORBELL32(ih->doorbell_index, ih->rptr);
> > +
> > + if (amdgpu_sriov_vf(adev))
> > + vega10_ih_irq_rearm(adev, ih);
> > } else if (ih == &adev->irq.ih) {
> > WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> > } else if (ih == &adev->irq.ih1) {
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost
[not found] ` <c9c462e1-f73f-64f0-31f8-3bbceefbea60-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-04-30 17:25 ` Alex Deucher
@ 2019-05-01 14:32 ` Huang, Trigger
1 sibling, 0 replies; 4+ messages in thread
From: Huang, Trigger @ 2019-05-01 14:32 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Hi Christian,
Yes, it is the HW guys who suggested to rearm it.
Thanks & Best Wishes,
Trigger Huang
-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: Wednesday, May 01, 2019 1:10 AM
To: Huang, Trigger <Trigger.Huang@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost
[CAUTION: External Email]
Am 30.04.19 um 17:14 schrieb Trigger Huang:
> In Multi-VFs stress test, sometimes we see IRQ lost when running
> benchmark, just rearm it.
Well I think I have seen that on bare metal as well, it would certainly explain some very odd behavior I've got from the IH block.
Have you pinged the hw guys about that already?
> Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 37 +++++++++++++++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 1b2f69a..8d89ab7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -31,7 +31,7 @@
> #include "soc15_common.h"
> #include "vega10_ih.h"
>
> -
> +#define MAX_REARM_RETRY 10
>
> static void vega10_ih_set_interrupt_funcs(struct amdgpu_device
> *adev);
>
> @@ -382,6 +382,38 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
> }
>
> /**
> + * vega10_ih_irq_rearm - rearm IRQ if lost
> + *
> + * @adev: amdgpu_device pointer
> + *
> + */
> +static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
> + struct amdgpu_ih_ring *ih) {
> + uint32_t reg_rptr = 0;
> + uint32_t v = 0;
> + uint32_t i = 0;
> +
> + if (ih == &adev->irq.ih)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
> + else if (ih == &adev->irq.ih1)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
> + else if (ih == &adev->irq.ih2)
> + reg_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
> + else
> + return;
> +
> + /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
> + for (i = 0; i < MAX_REARM_RETRY; i++) {
> + v = RREG32_NO_KIQ(reg_rptr);
> + if ((v < ih->ring_size) && (v != ih->rptr))
> + WDOORBELL32(ih->doorbell_index, ih->rptr);
> + else
> + break;
> + }
> +}
> +
> +/**
> * vega10_ih_set_rptr - set the IH ring buffer rptr
> *
> * @adev: amdgpu_device pointer
> @@ -395,6 +427,9 @@ static void vega10_ih_set_rptr(struct amdgpu_device *adev,
> /* XXX check if swapping is necessary on BE */
> *ih->rptr_cpu = ih->rptr;
> WDOORBELL32(ih->doorbell_index, ih->rptr);
> +
> + if (amdgpu_sriov_vf(adev))
> + vega10_ih_irq_rearm(adev, ih);
> } else if (ih == &adev->irq.ih) {
> WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);
> } else if (ih == &adev->irq.ih1) {
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-05-01 14:32 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-30 15:14 [PATCH] drm/amdgpu: Rearm IRQ in Vega10 SR-IOV if IRQ lost Trigger Huang
[not found] ` <1556637284-715-1-git-send-email-Trigger.Huang-5C7GfCeVMHo@public.gmane.org>
2019-04-30 17:10 ` Christian König
[not found] ` <c9c462e1-f73f-64f0-31f8-3bbceefbea60-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-04-30 17:25 ` Alex Deucher
2019-05-01 14:32 ` Huang, Trigger
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.