[PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

[PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

[Prike Liang]

From: Chengming Gui <Jack.Gui@amd.com>

add gfxoff_state_changed_by_workload to control gfxoff
when set power_profile_mode

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c       |  1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 31 ++++++++++++++++++++---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
 3 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 6cd6497..f1d326c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -92,6 +92,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	hwmgr_set_user_specify_caps(hwmgr);
 	hwmgr->fan_ctrl_is_in_default_mode = true;
 	hwmgr_init_workload_prority(hwmgr);
+	hwmgr->gfxoff_state_changed_by_workload = false;
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CI:
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 9a595f7..e32ae9d 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1258,21 +1258,46 @@ static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
 	return size;
 }
 
+static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
+{
+	struct amdgpu_device *adev = hwmgr->adev;
+	if ((adev->asic_type == CHIP_RAVEN) &&
+	    (adev->rev_id != 0x15d8) &&
+	    (hwmgr->smu_version >= 0x41e2b))
+		return true;
+	else
+		return false;
+}
+
 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
 {
 	int workload_type = 0;
+	int result = 0;
 
 	if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
 		pr_err("Invalid power profile mode %ld\n", input[size]);
 		return -EINVAL;
 	}
-	hwmgr->power_profile_mode = input[size];
+	if (hwmgr->power_profile_mode == input[size])
+		return 0;
 
 	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 	workload_type =
-		conv_power_profile_to_pplib_workload(hwmgr->power_profile_mode);
-	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
+		conv_power_profile_to_pplib_workload(input[size]);
+	if (workload_type &&
+	    smu10_is_raven1_refresh(hwmgr) &&
+	    !hwmgr->gfxoff_state_changed_by_workload) {
+		smu10_gfx_off_control(hwmgr, false);
+		hwmgr->gfxoff_state_changed_by_workload = true;
+	}
+	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
 						1 << workload_type);
+	if (!result)
+		hwmgr->power_profile_mode = input[size];
+	if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
+		smu10_gfx_off_control(hwmgr, true);
+		hwmgr->gfxoff_state_changed_by_workload = false;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index bac3d85..c92999a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -782,6 +782,7 @@ struct pp_hwmgr {
 	uint32_t workload_mask;
 	uint32_t workload_prority[Workload_Policy_Max];
 	uint32_t workload_setting[Workload_Policy_Max];
+	bool gfxoff_state_changed_by_workload;
 };
 
 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
-- 
2.7.4

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[PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1 refresh

[Prike Liang]

Use SMU firmware version to indentify the raven1 refresh device and
then load homologous RLC FW.

Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Suggested-by: Ray Huang<Ray.Huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++---------
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 15 +++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h     |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 14 +++++++++++++-
 4 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6fea2d1..44dd9d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1620,6 +1620,7 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
 {
 	int r = 0;
 	int i;
+	uint32_t smu_version;
 
 	if (adev->asic_type >= CHIP_VEGA10) {
 		for (i = 0; i < adev->num_ip_blocks; i++) {
@@ -1645,16 +1646,9 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev)
 			}
 		}
 	}
+	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
 
-	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
-		r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
-		if (r) {
-			pr_err("firmware loading failed\n");
-			return r;
-		}
-	}
-
-	return 0;
+	return r;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index bd40d5d..dae9a58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2668,6 +2668,21 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
 
 }
 
+int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version)
+{
+	int r;
+
+	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->load_firmware) {
+		r = adev->powerplay.pp_funcs->load_firmware(adev->powerplay.pp_handle);
+		if (r) {
+			pr_err("smu firmware loading failed\n");
+			return r;
+		}
+		*smu_version = adev->pm.fw_version;
+                return r ;
+	}
+}
+
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 {
 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
index f21a771..7ff0e76 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
@@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
 void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
+int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
 void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c763733..e233872 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -28,6 +28,7 @@
 #include "soc15.h"
 #include "soc15d.h"
 #include "amdgpu_atomfirmware.h"
+#include "amdgpu_pm.h"
 
 #include "gc/gc_9_0_offset.h"
 #include "gc/gc_9_0_sh_mask.h"
@@ -97,6 +98,7 @@ MODULE_FIRMWARE("amdgpu/raven2_me.bin");
 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
+MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
 
 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
 {
@@ -591,7 +593,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
 	case CHIP_RAVEN:
 		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
 			break;
-		if ((adev->gfx.rlc_fw_version < 531) ||
+		if ((adev->gfx.rlc_fw_version != 106 &&
+		     adev->gfx.rlc_fw_version < 531) ||
 		    (adev->gfx.rlc_fw_version == 53815) ||
 		    (adev->gfx.rlc_feature_version < 1) ||
 		    !adev->gfx.rlc.is_rlc_v2_1)
@@ -615,6 +618,8 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 	unsigned int i = 0;
 	uint16_t version_major;
 	uint16_t version_minor;
+	uint32_t smu_version;
+
 
 	DRM_DEBUG("\n");
 
@@ -681,10 +686,17 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 	 *          or revision >= 0xD8 && revision <= 0xDF
 	 * otherwise is PCO FP5
 	 */
+
 	if (!strcmp(chip_name, "picasso") &&
 		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) ||
 		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF))))
 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name);
+	else if (!strcmp(chip_name, "raven") && !amdgpu_pm_load_smu_firmware(adev, &smu_version) &&
+		(smu_version >= 0x41e2b))
+	/**
+	 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly.
+	 */
+		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name);
 	else
 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
-- 
2.7.4

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RE: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1 refresh

[Liang, Prike]

Ping for patches review.

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Prike Liang
> Sent: Friday, May 31, 2019 9:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Liang, Prike
> <Prike.Liang@amd.com>; Huang, Ray <Ray.Huang@amd.com>
> Subject: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1
> refresh
> 
> Use SMU firmware version to indentify the raven1 refresh device and then
> load homologous RLC FW.
> 
> Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> Suggested-by: Ray Huang<Ray.Huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++---------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 15 +++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h     |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 14 +++++++++++++-
>  4 files changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 6fea2d1..44dd9d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1620,6 +1620,7 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)  {
>  	int r = 0;
>  	int i;
> +	uint32_t smu_version;
> 
>  	if (adev->asic_type >= CHIP_VEGA10) {
>  		for (i = 0; i < adev->num_ip_blocks; i++) { @@ -1645,16
> +1646,9 @@ static int amdgpu_device_fw_loading(struct amdgpu_device
> *adev)
>  			}
>  		}
>  	}
> +	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
> 
> -	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> -		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> -		if (r) {
> -			pr_err("firmware loading failed\n");
> -			return r;
> -		}
> -	}
> -
> -	return 0;
> +	return r;
>  }
> 
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index bd40d5d..dae9a58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -2668,6 +2668,21 @@ void amdgpu_pm_print_power_states(struct
> amdgpu_device *adev)
> 
>  }
> 
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t
> +*smu_version) {
> +	int r;
> +
> +	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> +		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> +		if (r) {
> +			pr_err("smu firmware loading failed\n");
> +			return r;
> +		}
> +		*smu_version = adev->pm.fw_version;
> +                return r ;
> +	}
> +}
> +
>  int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)  {
>  	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> index f21a771..7ff0e76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> @@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct
> amdgpu_device *adev);  int amdgpu_pm_sysfs_init(struct amdgpu_device
> *adev);  void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);  void
> amdgpu_pm_print_power_states(struct amdgpu_device *adev);
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t
> +*smu_version);
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);  void
> amdgpu_dpm_thermal_work_handler(struct work_struct *work);  void
> amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); diff -
> -git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index c763733..e233872 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -28,6 +28,7 @@
>  #include "soc15.h"
>  #include "soc15d.h"
>  #include "amdgpu_atomfirmware.h"
> +#include "amdgpu_pm.h"
> 
>  #include "gc/gc_9_0_offset.h"
>  #include "gc/gc_9_0_sh_mask.h"
> @@ -97,6 +98,7 @@ MODULE_FIRMWARE("amdgpu/raven2_me.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
> +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
> 
>  static const struct soc15_reg_golden golden_settings_gc_9_0[] =  { @@ -
> 591,7 +593,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct
> amdgpu_device *adev)
>  	case CHIP_RAVEN:
>  		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
>  			break;
> -		if ((adev->gfx.rlc_fw_version < 531) ||
> +		if ((adev->gfx.rlc_fw_version != 106 &&
> +		     adev->gfx.rlc_fw_version < 531) ||
>  		    (adev->gfx.rlc_fw_version == 53815) ||
>  		    (adev->gfx.rlc_feature_version < 1) ||
>  		    !adev->gfx.rlc.is_rlc_v2_1)
> @@ -615,6 +618,8 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	unsigned int i = 0;
>  	uint16_t version_major;
>  	uint16_t version_minor;
> +	uint32_t smu_version;
> +
> 
>  	DRM_DEBUG("\n");
> 
> @@ -681,10 +686,17 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	 *          or revision >= 0xD8 && revision <= 0xDF
>  	 * otherwise is PCO FP5
>  	 */
> +
>  	if (!strcmp(chip_name, "picasso") &&
>  		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision
> <= 0xCF)) ||
>  		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision
> <= 0xDF))))
>  		snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_rlc_am4.bin", chip_name);
> +	else if (!strcmp(chip_name, "raven")
> && !amdgpu_pm_load_smu_firmware(adev, &smu_version) &&
> +		(smu_version >= 0x41e2b))
> +	/**
> +	 *SMC is loaded by SBIOS on APU and it's able to get the SMU version
> directly.
> +	 */
> +		snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_kicker_rlc.bin",
> +chip_name);
>  	else
>  		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin",
> chip_name);
>  	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1 refresh

[Huang, Ray]

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Prike Liang
> Sent: Friday, May 31, 2019 9:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Liang, Prike
> <Prike.Liang@amd.com>; Huang, Ray <Ray.Huang@amd.com>
> Subject: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1
> refresh
> 
> Use SMU firmware version to indentify the raven1 refresh device and
> then load homologous RLC FW.
> 
> Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> Suggested-by: Ray Huang<Ray.Huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++---------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 15 +++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h     |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 14 +++++++++++++-
>  4 files changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 6fea2d1..44dd9d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1620,6 +1620,7 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
>  {
>  	int r = 0;
>  	int i;
> +	uint32_t smu_version;
> 
>  	if (adev->asic_type >= CHIP_VEGA10) {
>  		for (i = 0; i < adev->num_ip_blocks; i++) {
> @@ -1645,16 +1646,9 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
>  			}
>  		}
>  	}
> +	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
> 
> -	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> -		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> -		if (r) {
> -			pr_err("firmware loading failed\n");
> -			return r;
> -		}
> -	}
> -
> -	return 0;
> +	return r;
>  }
> 
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index bd40d5d..dae9a58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -2668,6 +2668,21 @@ void amdgpu_pm_print_power_states(struct
> amdgpu_device *adev)
> 
>  }
> 
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t *smu_version)
> +{
> +	int r;
> +
> +	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> +		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> +		if (r) {
> +			pr_err("smu firmware loading failed\n");
> +			return r;
> +		}
> +		*smu_version = adev->pm.fw_version;
> +                return r ;
> +	}
> +}
> +
>  int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
>  {
>  	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> index f21a771..7ff0e76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> @@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct
> amdgpu_device *adev);
>  int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
>  void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
>  void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t *smu_version);
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
>  void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
>  void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index c763733..e233872 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -28,6 +28,7 @@
>  #include "soc15.h"
>  #include "soc15d.h"
>  #include "amdgpu_atomfirmware.h"
> +#include "amdgpu_pm.h"
> 
>  #include "gc/gc_9_0_offset.h"
>  #include "gc/gc_9_0_sh_mask.h"
> @@ -97,6 +98,7 @@ MODULE_FIRMWARE("amdgpu/raven2_me.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
> +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
> 
>  static const struct soc15_reg_golden golden_settings_gc_9_0[] =
>  {
> @@ -591,7 +593,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct
> amdgpu_device *adev)
>  	case CHIP_RAVEN:
>  		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
>  			break;
> -		if ((adev->gfx.rlc_fw_version < 531) ||
> +		if ((adev->gfx.rlc_fw_version != 106 &&
> +		     adev->gfx.rlc_fw_version < 531) ||
>  		    (adev->gfx.rlc_fw_version == 53815) ||
>  		    (adev->gfx.rlc_feature_version < 1) ||
>  		    !adev->gfx.rlc.is_rlc_v2_1)
> @@ -615,6 +618,8 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	unsigned int i = 0;
>  	uint16_t version_major;
>  	uint16_t version_minor;
> +	uint32_t smu_version;
> +
> 
>  	DRM_DEBUG("\n");
> 
> @@ -681,10 +686,17 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	 *          or revision >= 0xD8 && revision <= 0xDF
>  	 * otherwise is PCO FP5
>  	 */
> +
>  	if (!strcmp(chip_name, "picasso") &&
>  		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision
> <= 0xCF)) ||
>  		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision
> <= 0xDF))))
>  		snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_rlc_am4.bin", chip_name);
> +	else if (!strcmp(chip_name, "raven")
> && !amdgpu_pm_load_smu_firmware(adev, &smu_version) &&
> +		(smu_version >= 0x41e2b))
> +	/**
> +	 *SMC is loaded by SBIOS on APU and it's able to get the SMU version
> directly.
> +	 */
> +		snprintf(fw_name, sizeof(fw_name),

Please align the space of the comments with "snprintf". 

With this fixed, the series are Reviewed-by: Huang Rui <ray.huang@amd.com>

> "amdgpu/%s_kicker_rlc.bin", chip_name);
>  	else
>  		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin",
> chip_name);
>  	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
> --
> 2.7.4
> 
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1 refresh

[Quan, Evan]

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Prike Liang
> Sent: 2019年5月31日 21:11
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Liang, Prike
> <Prike.Liang@amd.com>; Huang, Ray <Ray.Huang@amd.com>
> Subject: [PATCH 2/2] drm/amd/amdgpu: add RLC firmware to support raven1
> refresh
> 
> Use SMU firmware version to indentify the raven1 refresh device and
> then load homologous RLC FW.
> 
> Change-Id: I7aaa67d8b59cfec03355d9199f7fb2c30ce39856
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> Suggested-by: Ray Huang<Ray.Huang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +++---------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c     | 15 +++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h     |  1 +
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 14 +++++++++++++-
>  4 files changed, 32 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 6fea2d1..44dd9d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1620,6 +1620,7 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
>  {
>  	int r = 0;
>  	int i;
> +	uint32_t smu_version;
> 
>  	if (adev->asic_type >= CHIP_VEGA10) {
>  		for (i = 0; i < adev->num_ip_blocks; i++) {
> @@ -1645,16 +1646,9 @@ static int amdgpu_device_fw_loading(struct
> amdgpu_device *adev)
>  			}
>  		}
>  	}
> +	r = amdgpu_pm_load_smu_firmware(adev, &smu_version);
> 
> -	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> -		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> -		if (r) {
> -			pr_err("firmware loading failed\n");
> -			return r;
> -		}
> -	}
> -
> -	return 0;
> +	return r;
>  }
> 
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index bd40d5d..dae9a58 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -2668,6 +2668,21 @@ void amdgpu_pm_print_power_states(struct
> amdgpu_device *adev)
> 
>  }
> 
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t *smu_version)
> +{
> +	int r;
> +
> +	if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs-
> >load_firmware) {
> +		r = adev->powerplay.pp_funcs->load_firmware(adev-
> >powerplay.pp_handle);
> +		if (r) {
> +			pr_err("smu firmware loading failed\n");
> +			return r;
> +		}
> +		*smu_version = adev->pm.fw_version;
> +                return r ;
> +	}
[Quan, Evan] there is  no return value on the else branch. There should be some compile warnings.
> +}
> +
>  int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
>  {
>  	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> index f21a771..7ff0e76 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h
> @@ -34,6 +34,7 @@ void amdgpu_pm_acpi_event_handler(struct
> amdgpu_device *adev);
>  int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
>  void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev);
>  void amdgpu_pm_print_power_states(struct amdgpu_device *adev);
> +int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev,
> uint32_t *smu_version);
>  void amdgpu_pm_compute_clocks(struct amdgpu_device *adev);
>  void amdgpu_dpm_thermal_work_handler(struct work_struct *work);
>  void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index c763733..e233872 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -28,6 +28,7 @@
>  #include "soc15.h"
>  #include "soc15d.h"
>  #include "amdgpu_atomfirmware.h"
> +#include "amdgpu_pm.h"
> 
>  #include "gc/gc_9_0_offset.h"
>  #include "gc/gc_9_0_sh_mask.h"
> @@ -97,6 +98,7 @@ MODULE_FIRMWARE("amdgpu/raven2_me.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
>  MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
> +MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin");
> 
>  static const struct soc15_reg_golden golden_settings_gc_9_0[] =
>  {
> @@ -591,7 +593,8 @@ static void gfx_v9_0_check_if_need_gfxoff(struct
> amdgpu_device *adev)
>  	case CHIP_RAVEN:
>  		if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
>  			break;
> -		if ((adev->gfx.rlc_fw_version < 531) ||
> +		if ((adev->gfx.rlc_fw_version != 106 &&
> +		     adev->gfx.rlc_fw_version < 531) ||
>  		    (adev->gfx.rlc_fw_version == 53815) ||
>  		    (adev->gfx.rlc_feature_version < 1) ||
>  		    !adev->gfx.rlc.is_rlc_v2_1)
> @@ -615,6 +618,8 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	unsigned int i = 0;
>  	uint16_t version_major;
>  	uint16_t version_minor;
> +	uint32_t smu_version;
> +
> 
>  	DRM_DEBUG("\n");
> 
> @@ -681,10 +686,17 @@ static int gfx_v9_0_init_microcode(struct
> amdgpu_device *adev)
>  	 *          or revision >= 0xD8 && revision <= 0xDF
>  	 * otherwise is PCO FP5
>  	 */
> +
>  	if (!strcmp(chip_name, "picasso") &&
>  		(((adev->pdev->revision >= 0xC8) && (adev->pdev->revision
> <= 0xCF)) ||
>  		((adev->pdev->revision >= 0xD8) && (adev->pdev->revision
> <= 0xDF))))
>  		snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_rlc_am4.bin", chip_name);
> +	else if (!strcmp(chip_name, "raven")
> && !amdgpu_pm_load_smu_firmware(adev, &smu_version) &&
[Quan, Evan] I cannot get the purpose to call amdgpu_pm_load_smu_firmware here.
Can you use adev->pm.fw_version directly?
> +		(smu_version >= 0x41e2b))
> +	/**
> +	 *SMC is loaded by SBIOS on APU and it's able to get the SMU version
> directly.
> +	 */
> +		snprintf(fw_name, sizeof(fw_name),
> "amdgpu/%s_kicker_rlc.bin", chip_name);
>  	else
>  		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin",
> chip_name);
>  	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode for raven1_refresh

[Quan, Evan]

Reviewed-by: Evan Quan <evan.quan@amd.com>

> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Prike Liang
> Sent: 2019年5月31日 21:11
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray
> <Ray.Huang@amd.com>; Gui, Jack <Jack.Gui@amd.com>
> Subject: [PATCH 1/2] drm/amd/powerplay: add set_power_profile_mode
> for raven1_refresh
> 
> From: Chengming Gui <Jack.Gui@amd.com>
> 
> add gfxoff_state_changed_by_workload to control gfxoff when set
> power_profile_mode
> 
> Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c       |  1 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 31
> ++++++++++++++++++++---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h         |  1 +
>  3 files changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index 6cd6497..f1d326c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -92,6 +92,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
>  	hwmgr_set_user_specify_caps(hwmgr);
>  	hwmgr->fan_ctrl_is_in_default_mode = true;
>  	hwmgr_init_workload_prority(hwmgr);
> +	hwmgr->gfxoff_state_changed_by_workload = false;
> 
>  	switch (hwmgr->chip_family) {
>  	case AMDGPU_FAMILY_CI:
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 9a595f7..e32ae9d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -1258,21 +1258,46 @@ static int
> smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>  	return size;
>  }
> 
> +static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) {
> +	struct amdgpu_device *adev = hwmgr->adev;
> +	if ((adev->asic_type == CHIP_RAVEN) &&
> +	    (adev->rev_id != 0x15d8) &&
> +	    (hwmgr->smu_version >= 0x41e2b))
> +		return true;
> +	else
> +		return false;
> +}
> +
>  static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long
> *input, uint32_t size)  {
>  	int workload_type = 0;
> +	int result = 0;
> 
>  	if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
>  		pr_err("Invalid power profile mode %ld\n", input[size]);
>  		return -EINVAL;
>  	}
> -	hwmgr->power_profile_mode = input[size];
> +	if (hwmgr->power_profile_mode == input[size])
> +		return 0;
> 
>  	/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
>  	workload_type =
> -		conv_power_profile_to_pplib_workload(hwmgr-
> >power_profile_mode);
> -	smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_ActiveProcessNotify,
> +		conv_power_profile_to_pplib_workload(input[size]);
> +	if (workload_type &&
> +	    smu10_is_raven1_refresh(hwmgr) &&
> +	    !hwmgr->gfxoff_state_changed_by_workload) {
> +		smu10_gfx_off_control(hwmgr, false);
> +		hwmgr->gfxoff_state_changed_by_workload = true;
> +	}
> +	result = smum_send_msg_to_smc_with_parameter(hwmgr,
> +PPSMC_MSG_ActiveProcessNotify,
>  						1 << workload_type);
> +	if (!result)
> +		hwmgr->power_profile_mode = input[size];
> +	if (workload_type && hwmgr->gfxoff_state_changed_by_workload)
> {
> +		smu10_gfx_off_control(hwmgr, true);
> +		hwmgr->gfxoff_state_changed_by_workload = false;
> +	}
> 
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index bac3d85..c92999a 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -782,6 +782,7 @@ struct pp_hwmgr {
>  	uint32_t workload_mask;
>  	uint32_t workload_prority[Workload_Policy_Max];
>  	uint32_t workload_setting[Workload_Policy_Max];
> +	bool gfxoff_state_changed_by_workload;
>  };
> 
>  int hwmgr_early_init(struct pp_hwmgr *hwmgr);
> --
> 2.7.4
> 
> _______________________________________________
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