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* [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus
@ 2019-08-09 11:26 Le Ma
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 13+ messages in thread
From: Le Ma @ 2019-08-09 11:26 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Le Ma

Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
    drm/amdgpu: enable gfx clock gating for Arcturus

Change-Id: I9d70319dd07f7d642416cb260f9f5b3342b6f3f2
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 261493a..aecba1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1122,6 +1122,7 @@ static int soc15_common_early_init(void *handle)
 			AMD_CG_SUPPORT_GFX_MGLS |
 			AMD_CG_SUPPORT_GFX_CGCG |
 			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
 			AMD_CG_SUPPORT_HDP_MGCG |
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 11:26   ` Le Ma
       [not found]     ` <1565350016-7071-2-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:26   ` [PATCH 3/4] drm/amdgpu: add mmhub clock gating " Le Ma
                     ` (3 subsequent siblings)
  4 siblings, 1 reply; 13+ messages in thread
From: Le Ma @ 2019-08-09 11:26 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Le Ma

Follow the hw spec, and no need to consider gfxoff on Arcturus

Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 78150ff..9b85a73 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4677,8 +4677,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 		/* enable cgcg FSM(0x0000363F) */
 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
 
-		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+		if (adev->asic_type == CHIP_ARCTURUS)
+			data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+		else
+			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
-- 
2.7.4

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 3/4] drm/amdgpu: add mmhub clock gating for Arcturus
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:26   ` [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus Le Ma
@ 2019-08-09 11:26   ` Le Ma
       [not found]     ` <1565350016-7071-3-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:26   ` [PATCH 4/4] drm/amdgpu: enable " Le Ma
                     ` (2 subsequent siblings)
  4 siblings, 1 reply; 13+ messages in thread
From: Le Ma @ 2019-08-09 11:26 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Le Ma

Add 2 mmhub instances CG

Change-Id: I76ab7a50cd9a40de3022f733787b42e4e5c4dbf5
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  12 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 126 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h |   3 +
 3 files changed, 135 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index cccb6e9..44ac122 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1465,9 +1465,9 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->asic_type == CHIP_ARCTURUS)
-		return 0;
-
-	mmhub_v1_0_set_clockgating(adev, state);
+		mmhub_v9_4_set_clockgating(adev, state);
+	else
+		mmhub_v1_0_set_clockgating(adev, state);
 
 	athub_v1_0_set_clockgating(adev, state);
 
@@ -1479,9 +1479,9 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	if (adev->asic_type == CHIP_ARCTURUS)
-		return;
-
-	mmhub_v1_0_get_clockgating(adev, flags);
+		mmhub_v9_4_get_clockgating(adev, flags);
+	else
+		mmhub_v1_0_get_clockgating(adev, flags);
 
 	athub_v1_0_get_clockgating(adev, flags);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 33b0de5..e52e4d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -515,3 +515,129 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
 				    i * MMHUB_INSTANCE_REGISTER_OFFSET;
 	}
 }
+
+static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+							bool enable)
+{
+	uint32_t def, data, def1, data1;
+	int i, j;
+	int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
+
+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+					mmATCL2_0_ATC_L2_MISC_CG,
+					i * MMHUB_INSTANCE_REGISTER_OFFSET);
+
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+			data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+		else
+			data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+
+		if (def != data)
+			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
+
+		for (j = 0; j < 5; j++) {
+			def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
+					mmDAGB0_CNTL_MISC2,
+					i * MMHUB_INSTANCE_REGISTER_OFFSET +
+					j * dist);
+			if (enable &&
+			    (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+				data1 &=
+				    ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+			} else {
+				data1 |=
+				    (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+				    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+			}
+
+			if (def1 != data1)
+				WREG32_SOC15_OFFSET(MMHUB, 0,
+					mmDAGB0_CNTL_MISC2,
+					i * MMHUB_INSTANCE_REGISTER_OFFSET +
+					j * dist, data1);
+
+			if (i == 1 && j == 3)
+				break;
+		}
+	}
+}
+
+static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+						       bool enable)
+{
+	uint32_t def, data;
+	int i;
+
+	for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+		def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+					mmATCL2_0_ATC_L2_MISC_CG,
+					i * MMHUB_INSTANCE_REGISTER_OFFSET);
+
+		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+			data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+		else
+			data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+		if (def != data)
+			WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+				i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
+	}
+}
+
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state)
+{
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	switch (adev->asic_type) {
+	case CHIP_ARCTURUS:
+		mmhub_v9_4_update_medium_grain_clock_gating(adev,
+				state == AMD_CG_STATE_GATE ? true : false);
+		mmhub_v9_4_update_medium_grain_light_sleep(adev,
+				state == AMD_CG_STATE_GATE ? true : false);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+/* TODO: get 2 mmhub instances CG state */
+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+	int data, data1;
+
+	if (amdgpu_sriov_vf(adev))
+		*flags = 0;
+
+	/* AMD_CG_SUPPORT_MC_MGCG */
+	data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+	data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+	if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
+	    !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+		       DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+		*flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+	/* AMD_CG_SUPPORT_MC_LS */
+	if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+		*flags |= AMD_CG_SUPPORT_MC_LS;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
index 9ba3dd8..d435cfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -29,5 +29,8 @@ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
 					 bool value);
 void mmhub_v9_4_init(struct amdgpu_device *adev);
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+			       enum amd_clockgating_state state);
+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);
 
 #endif
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:26   ` [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus Le Ma
  2019-08-09 11:26   ` [PATCH 3/4] drm/amdgpu: add mmhub clock gating " Le Ma
@ 2019-08-09 11:26   ` Le Ma
       [not found]     ` <1565350016-7071-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:29   ` [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus Wang, Kevin(Yang)
  2019-08-12  5:22   ` Feng, Kenneth
  4 siblings, 1 reply; 13+ messages in thread
From: Le Ma @ 2019-08-09 11:26 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Le Ma

Init MC_MGCG/LS flag. Also apply to athub CG.

Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c      | 4 +++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index e52e4d1..0cf7ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -615,7 +615,6 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
 	return 0;
 }
 
-/* TODO: get 2 mmhub instances CG state */
 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
 	int data, data1;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index aecba1c..235cb5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1126,7 +1126,9 @@ static int soc15_common_early_init(void *handle)
 			AMD_CG_SUPPORT_HDP_MGCG |
 			AMD_CG_SUPPORT_HDP_LS |
 			AMD_CG_SUPPORT_SDMA_MGCG |
-			AMD_CG_SUPPORT_SDMA_LS;
+			AMD_CG_SUPPORT_SDMA_LS |
+			AMD_CG_SUPPORT_MC_MGCG |
+			AMD_CG_SUPPORT_MC_LS;
 		adev->pg_flags = 0;
 		adev->external_rev_id = adev->rev_id + 0x32;
 		break;
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
                     ` (2 preceding siblings ...)
  2019-08-09 11:26   ` [PATCH 4/4] drm/amdgpu: enable " Le Ma
@ 2019-08-09 11:29   ` Wang, Kevin(Yang)
  2019-08-12  5:22   ` Feng, Kenneth
  4 siblings, 0 replies; 13+ messages in thread
From: Wang, Kevin(Yang) @ 2019-08-09 11:29 UTC (permalink / raw)
  To: Ma, Le, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 1674 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 9, 2019 7:26 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus

Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
    drm/amdgpu: enable gfx clock gating for Arcturus

Change-Id: I9d70319dd07f7d642416cb260f9f5b3342b6f3f2
Signed-off-by: Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 261493a..aecba1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1122,6 +1122,7 @@ static int soc15_common_early_init(void *handle)
                         AMD_CG_SUPPORT_GFX_MGLS |
                         AMD_CG_SUPPORT_GFX_CGCG |
                         AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_CP_LS |
                         AMD_CG_SUPPORT_HDP_MGCG |
                         AMD_CG_SUPPORT_HDP_LS |
                         AMD_CG_SUPPORT_SDMA_MGCG |
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[-- Attachment #1.2: Type: text/html, Size: 3682 bytes --]

[-- Attachment #2: Type: text/plain, Size: 153 bytes --]

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu: add mmhub clock gating for Arcturus
       [not found]     ` <1565350016-7071-3-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 11:29       ` Wang, Kevin(Yang)
  2019-08-12  5:37       ` Feng, Kenneth
  1 sibling, 0 replies; 13+ messages in thread
From: Wang, Kevin(Yang) @ 2019-08-09 11:29 UTC (permalink / raw)
  To: Ma, Le, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 8912 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 9, 2019 7:26 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 3/4] drm/amdgpu: add mmhub clock gating for Arcturus

Add 2 mmhub instances CG

Change-Id: I76ab7a50cd9a40de3022f733787b42e4e5c4dbf5
Signed-off-by: Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  12 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 126 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h |   3 +
 3 files changed, 135 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index cccb6e9..44ac122 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1465,9 +1465,9 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;

         if (adev->asic_type == CHIP_ARCTURUS)
-               return 0;
-
-       mmhub_v1_0_set_clockgating(adev, state);
+               mmhub_v9_4_set_clockgating(adev, state);
+       else
+               mmhub_v1_0_set_clockgating(adev, state);

         athub_v1_0_set_clockgating(adev, state);

@@ -1479,9 +1479,9 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;

         if (adev->asic_type == CHIP_ARCTURUS)
-               return;
-
-       mmhub_v1_0_get_clockgating(adev, flags);
+               mmhub_v9_4_get_clockgating(adev, flags);
+       else
+               mmhub_v1_0_get_clockgating(adev, flags);

         athub_v1_0_get_clockgating(adev, flags);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 33b0de5..e52e4d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -515,3 +515,129 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
                                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
         }
 }
+
+static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                                       bool enable)
+{
+       uint32_t def, data, def1, data1;
+       int i, j;
+       int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
+
+       for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+               def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmATCL2_0_ATC_L2_MISC_CG,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET);
+
+               if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+                       data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+               else
+                       data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+
+               if (def != data)
+                       WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+                               i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
+
+               for (j = 0; j < 5; j++) {
+                       def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmDAGB0_CNTL_MISC2,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET +
+                                       j * dist);
+                       if (enable &&
+                           (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+                               data1 &=
+                                   ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+                       } else {
+                               data1 |=
+                                   (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+                       }
+
+                       if (def1 != data1)
+                               WREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmDAGB0_CNTL_MISC2,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET +
+                                       j * dist, data1);
+
+                       if (i == 1 && j == 3)
+                               break;
+               }
+       }
+}
+
+static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+                                                      bool enable)
+{
+       uint32_t def, data;
+       int i;
+
+       for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+               def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmATCL2_0_ATC_L2_MISC_CG,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET);
+
+               if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+                       data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+               else
+                       data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+               if (def != data)
+                       WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+                               i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
+       }
+}
+
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state)
+{
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
+       switch (adev->asic_type) {
+       case CHIP_ARCTURUS:
+               mmhub_v9_4_update_medium_grain_clock_gating(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               mmhub_v9_4_update_medium_grain_light_sleep(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+/* TODO: get 2 mmhub instances CG state */
+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+       int data, data1;
+
+       if (amdgpu_sriov_vf(adev))
+               *flags = 0;
+
+       /* AMD_CG_SUPPORT_MC_MGCG */
+       data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+       data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+       if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
+           !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+               *flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+       /* AMD_CG_SUPPORT_MC_LS */
+       if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+               *flags |= AMD_CG_SUPPORT_MC_LS;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
index 9ba3dd8..d435cfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -29,5 +29,8 @@ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);
 void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
                                          bool value);
 void mmhub_v9_4_init(struct amdgpu_device *adev);
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state);
+void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);

 #endif
--
2.7.4

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^ permalink raw reply related	[flat|nested] 13+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus
       [not found]     ` <1565350016-7071-2-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 11:29       ` Wang, Kevin(Yang)
  2019-08-12  5:24       ` Feng, Kenneth
  1 sibling, 0 replies; 13+ messages in thread
From: Wang, Kevin(Yang) @ 2019-08-09 11:29 UTC (permalink / raw)
  To: Ma, Le, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 2241 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 9, 2019 7:26 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus

Follow the hw spec, and no need to consider gfxoff on Arcturus

Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
Signed-off-by: Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 78150ff..9b85a73 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4677,8 +4677,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
                 /* enable cgcg FSM(0x0000363F) */
                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

-               data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               if (adev->asic_type == CHIP_ARCTURUS)
+                       data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               else
+                       data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
--
2.7.4

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^ permalink raw reply related	[flat|nested] 13+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus
       [not found]     ` <1565350016-7071-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-09 11:30       ` Wang, Kevin(Yang)
  2019-08-12  5:41       ` Feng, Kenneth
  2019-08-12  5:52       ` Feng, Kenneth
  2 siblings, 0 replies; 13+ messages in thread
From: Wang, Kevin(Yang) @ 2019-08-09 11:30 UTC (permalink / raw)
  To: Ma, Le, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW


[-- Attachment #1.1: Type: text/plain, Size: 2271 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 9, 2019 7:26 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus

Init MC_MGCG/LS flag. Also apply to athub CG.

Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
Signed-off-by: Le Ma <le.ma-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c      | 4 +++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index e52e4d1..0cf7ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -615,7 +615,6 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
         return 0;
 }

-/* TODO: get 2 mmhub instances CG state */
 void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 {
         int data, data1;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index aecba1c..235cb5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1126,7 +1126,9 @@ static int soc15_common_early_init(void *handle)
                         AMD_CG_SUPPORT_HDP_MGCG |
                         AMD_CG_SUPPORT_HDP_LS |
                         AMD_CG_SUPPORT_SDMA_MGCG |
-                       AMD_CG_SUPPORT_SDMA_LS;
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS;
                 adev->pg_flags = 0;
                 adev->external_rev_id = adev->rev_id + 0x32;
                 break;
--
2.7.4

_______________________________________________
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^ permalink raw reply related	[flat|nested] 13+ messages in thread
* RE: [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus
       [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
                     ` (3 preceding siblings ...)
  2019-08-09 11:29   ` [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus Wang, Kevin(Yang)
@ 2019-08-12  5:22   ` Feng, Kenneth
  4 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-08-12  5:22 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ma, Le

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma
Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus

[CAUTION: External Email]

Missed AMD_CG_SUPPORT_GFX_CP_LS accidently when commit patch before
    drm/amdgpu: enable gfx clock gating for Arcturus

Change-Id: I9d70319dd07f7d642416cb260f9f5b3342b6f3f2
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 261493a..aecba1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1122,6 +1122,7 @@ static int soc15_common_early_init(void *handle)
                        AMD_CG_SUPPORT_GFX_MGLS |
                        AMD_CG_SUPPORT_GFX_CGCG |
                        AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_CP_LS |
                        AMD_CG_SUPPORT_HDP_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_SDMA_MGCG |
--
2.7.4

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_______________________________________________
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^ permalink raw reply related	[flat|nested] 13+ messages in thread
* RE: [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus
       [not found]     ` <1565350016-7071-2-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:29       ` Wang, Kevin(Yang)
@ 2019-08-12  5:24       ` Feng, Kenneth
  1 sibling, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-08-12  5:24 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ma, Le

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma
Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus

[CAUTION: External Email]

Follow the hw spec, and no need to consider gfxoff on Arcturus

Change-Id: Ib9cad79b1b9c096014447fc0a7d29cdb594e15e3
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 78150ff..9b85a73 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4677,8 +4677,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
                /* enable cgcg FSM(0x0000363F) */
                def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);

-               data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
-                       RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               if (adev->asic_type == CHIP_ARCTURUS)
+                       data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
+               else
+                       data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+                               RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
                if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
                        data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
                                RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
--
2.7.4

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_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* RE: [PATCH 3/4] drm/amdgpu: add mmhub clock gating for Arcturus
       [not found]     ` <1565350016-7071-3-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:29       ` Wang, Kevin(Yang)
@ 2019-08-12  5:37       ` Feng, Kenneth
  1 sibling, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-08-12  5:37 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ma, Le

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma
Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 3/4] drm/amdgpu: add mmhub clock gating for Arcturus

[CAUTION: External Email]

Add 2 mmhub instances CG

Change-Id: I76ab7a50cd9a40de3022f733787b42e4e5c4dbf5
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c   |  12 +--
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 126 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h |   3 +
 3 files changed, 135 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index cccb6e9..44ac122 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1465,9 +1465,9 @@ static int gmc_v9_0_set_clockgating_state(void *handle,
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;

        if (adev->asic_type == CHIP_ARCTURUS)
-               return 0;
-
-       mmhub_v1_0_set_clockgating(adev, state);
+               mmhub_v9_4_set_clockgating(adev, state);
+       else
+               mmhub_v1_0_set_clockgating(adev, state);

        athub_v1_0_set_clockgating(adev, state);

@@ -1479,9 +1479,9 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;

        if (adev->asic_type == CHIP_ARCTURUS)
-               return;
-
-       mmhub_v1_0_get_clockgating(adev, flags);
+               mmhub_v9_4_get_clockgating(adev, flags);
+       else
+               mmhub_v1_0_get_clockgating(adev, flags);

        athub_v1_0_get_clockgating(adev, flags);  } diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 33b0de5..e52e4d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -515,3 +515,129 @@ void mmhub_v9_4_init(struct amdgpu_device *adev)
                                    i * MMHUB_INSTANCE_REGISTER_OFFSET;
        }
 }
+
+static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                                       bool enable) {
+       uint32_t def, data, def1, data1;
+       int i, j;
+       int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
+
+       for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+               def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmATCL2_0_ATC_L2_MISC_CG,
+                                       i * 
+ MMHUB_INSTANCE_REGISTER_OFFSET);
+
+               if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+                       data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+               else
+                       data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
+
+               if (def != data)
+                       WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+                               i * MMHUB_INSTANCE_REGISTER_OFFSET, 
+ data);
+
+               for (j = 0; j < 5; j++) {
+                       def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmDAGB0_CNTL_MISC2,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET +
+                                       j * dist);
+                       if (enable &&
+                           (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
+                               data1 &=
+                                   ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+                       } else {
+                               data1 |=
+                                   (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                                   DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+                       }
+
+                       if (def1 != data1)
+                               WREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmDAGB0_CNTL_MISC2,
+                                       i * MMHUB_INSTANCE_REGISTER_OFFSET +
+                                       j * dist, data1);
+
+                       if (i == 1 && j == 3)
+                               break;
+               }
+       }
+}
+
+static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+                                                      bool enable) {
+       uint32_t def, data;
+       int i;
+
+       for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
+               def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
+                                       mmATCL2_0_ATC_L2_MISC_CG,
+                                       i * 
+ MMHUB_INSTANCE_REGISTER_OFFSET);
+
+               if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
+                       data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+               else
+                       data &= 
+ ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+               if (def != data)
+                       WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
+                               i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
+       }
+}
+
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state) {
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
+       switch (adev->asic_type) {
+       case CHIP_ARCTURUS:
+               mmhub_v9_4_update_medium_grain_clock_gating(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               mmhub_v9_4_update_medium_grain_light_sleep(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+/* TODO: get 2 mmhub instances CG state */ void 
+mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags) {
+       int data, data1;
+
+       if (amdgpu_sriov_vf(adev))
+               *flags = 0;
+
+       /* AMD_CG_SUPPORT_MC_MGCG */
+       data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+       data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
+
+       if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
+           !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+                      DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
+               *flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+       /* AMD_CG_SUPPORT_MC_LS */
+       if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+               *flags |= AMD_CG_SUPPORT_MC_LS; }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
index 9ba3dd8..d435cfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.h
@@ -29,5 +29,8 @@ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev);  void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev,
                                         bool value);  void mmhub_v9_4_init(struct amdgpu_device *adev);
+int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state); void 
+mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags);

 #endif
--
2.7.4

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus
       [not found]     ` <1565350016-7071-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:30       ` Wang, Kevin(Yang)
@ 2019-08-12  5:41       ` Feng, Kenneth
  2019-08-12  5:52       ` Feng, Kenneth
  2 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-08-12  5:41 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ma, Le

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma
Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus

[CAUTION: External Email]

Init MC_MGCG/LS flag. Also apply to athub CG.

Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c      | 4 +++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index e52e4d1..0cf7ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -615,7 +615,6 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
        return 0;
 }

-/* TODO: get 2 mmhub instances CG state */  void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)  {
        int data, data1;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index aecba1c..235cb5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1126,7 +1126,9 @@ static int soc15_common_early_init(void *handle)
                        AMD_CG_SUPPORT_HDP_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_SDMA_MGCG |
-                       AMD_CG_SUPPORT_SDMA_LS;
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x32;
                break;
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
* RE: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus
       [not found]     ` <1565350016-7071-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
  2019-08-09 11:30       ` Wang, Kevin(Yang)
  2019-08-12  5:41       ` Feng, Kenneth
@ 2019-08-12  5:52       ` Feng, Kenneth
  2 siblings, 0 replies; 13+ messages in thread
From: Feng, Kenneth @ 2019-08-12  5:52 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ma, Le

Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>

-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Le Ma
Sent: Friday, August 09, 2019 7:27 PM
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le <Le.Ma@amd.com>
Subject: [PATCH 4/4] drm/amdgpu: enable mmhub clock gating for Arcturus

[CAUTION: External Email]

Init MC_MGCG/LS flag. Also apply to athub CG.

Change-Id: Ic00cb8e6d69eb75dd32f34f778352cee93063ee0
Signed-off-by: Le Ma <le.ma@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 1 -
 drivers/gpu/drm/amd/amdgpu/soc15.c      | 4 +++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index e52e4d1..0cf7ef4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -615,7 +615,6 @@ int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
        return 0;
 }

-/* TODO: get 2 mmhub instances CG state */  void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)  {
        int data, data1;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index aecba1c..235cb5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1126,7 +1126,9 @@ static int soc15_common_early_init(void *handle)
                        AMD_CG_SUPPORT_HDP_MGCG |
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_SDMA_MGCG |
-                       AMD_CG_SUPPORT_SDMA_LS;
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x32;
                break;
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-08-12  5:52 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-09 11:26 [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus Le Ma
     [not found] ` <1565350016-7071-1-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-08-09 11:26   ` [PATCH 2/4] drm/amdgpu: increase CGCG gfx idle threshold for Arcturus Le Ma
     [not found]     ` <1565350016-7071-2-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-08-09 11:29       ` Wang, Kevin(Yang)
2019-08-12  5:24       ` Feng, Kenneth
2019-08-09 11:26   ` [PATCH 3/4] drm/amdgpu: add mmhub clock gating " Le Ma
     [not found]     ` <1565350016-7071-3-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-08-09 11:29       ` Wang, Kevin(Yang)
2019-08-12  5:37       ` Feng, Kenneth
2019-08-09 11:26   ` [PATCH 4/4] drm/amdgpu: enable " Le Ma
     [not found]     ` <1565350016-7071-4-git-send-email-le.ma-5C7GfCeVMHo@public.gmane.org>
2019-08-09 11:30       ` Wang, Kevin(Yang)
2019-08-12  5:41       ` Feng, Kenneth
2019-08-12  5:52       ` Feng, Kenneth
2019-08-09 11:29   ` [PATCH 1/4] drm/amdgpu: add GFX_CP_LS flag to Arcturus Wang, Kevin(Yang)
2019-08-12  5:22   ` Feng, Kenneth

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