[PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid

[PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid

[Clements, John]

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[AMD Public Use]

Submitting patch to enable RAS EEPROM support for sienna chichlid

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From 3878e7a1c25acbd58fc8e55adab7edbe5a5dc8c6 Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Tue, 21 Jul 2020 18:00:17 +0800
Subject: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid

RAS EEPROM init/access support

Signed-off-by: John Clements <john.clements@amd.com>
Change-Id: I2e5ffc759e32be011147dab7535f5bb08de2791c
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index c0096097bbcf..bfcccd3f82cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -30,6 +30,7 @@
 #define EEPROM_I2C_TARGET_ADDR_VEGA20    	0xA0
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS  	0xA8
 #define EEPROM_I2C_TARGET_ADDR_ARCTURUS_D342  	0xA0
+#define EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID   0xA0
 
 /*
  * The 2 macros bellow represent the actual size in bytes that
@@ -88,6 +89,10 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
 	case CHIP_ARCTURUS:
 		return __get_eeprom_i2c_addr_arct(adev, i2c_addr);
 
+	case CHIP_SIENNA_CICHLID:
+		*i2c_addr = EEPROM_I2C_TARGET_ADDR_SIENNA_CICHLID;
+		break;
+
 	default:
 		return false;
 	}
@@ -386,7 +391,9 @@ int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
 	struct eeprom_table_record *record;
 	struct amdgpu_device *adev = to_amdgpu_device(control);
 
-	if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
+	if (adev->asic_type != CHIP_VEGA20           &&
+	    adev->asic_type != CHIP_ARCTURUS         &&
+	    adev->asic_type != CHIP_SIENNA_CICHLID)
 		return 0;
 
 	buffs = kcalloc(num, EEPROM_ADDRESS_SIZE + EEPROM_TABLE_RECORD_SIZE,
-- 
2.17.1


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RE: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid

[Zhang, Hawking]

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[AMD Public Use]

-              if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
+             if (adev->asic_type != CHIP_VEGA20           &&
+                 adev->asic_type != CHIP_ARCTURUS         &&
+                 adev->asic_type != CHIP_SIENNA_CICHLID)
                               return 0;

Does it make sense to check UMC RAS availability through amdgpu_ras_is_supported, instead of check specific ASIC type one by one?

Also, it would be good to merge the upcoming logic from Guchun where we have a gloal flag to mark the availability of bad page retirement.

Thoughts?

Regards,
Hawking
From: Clements, John <John.Clements@amd.com>
Sent: Tuesday, July 21, 2020 18:02
To: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid


[AMD Public Use]

Submitting patch to enable RAS EEPROM support for sienna chichlid

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RE: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid

[Clements, John]

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[AMD Public Use]

Good points, I'll reorganize and resubmit the patch after Guchuns changes are in

From: Zhang, Hawking <Hawking.Zhang@amd.com>
Sent: Tuesday, July 21, 2020 7:11 PM
To: Clements, John <John.Clements@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>; Chen, Guchun <Guchun.Chen@amd.com>
Subject: RE: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid


[AMD Public Use]

-              if (adev->asic_type != CHIP_VEGA20 && adev->asic_type != CHIP_ARCTURUS)
+             if (adev->asic_type != CHIP_VEGA20           &&
+                 adev->asic_type != CHIP_ARCTURUS         &&
+                 adev->asic_type != CHIP_SIENNA_CICHLID)
                               return 0;

Does it make sense to check UMC RAS availability through amdgpu_ras_is_supported, instead of check specific ASIC type one by one?

Also, it would be good to merge the upcoming logic from Guchun where we have a gloal flag to mark the availability of bad page retirement.

Thoughts?

Regards,
Hawking
From: Clements, John <John.Clements@amd.com<mailto:John.Clements@amd.com>>
Sent: Tuesday, July 21, 2020 18:02
To: amd-gfx list <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>; Zhang, Hawking <Hawking.Zhang@amd.com<mailto:Hawking.Zhang@amd.com>>
Subject: [PATCH] drm/amdgpu: add RAS EEPROM support for sienna chichlid


[AMD Public Use]

Submitting patch to enable RAS EEPROM support for sienna chichlid

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