* [PATCH 2/6] drm/amdgpu: clean up discovery testing
2020-05-28 21:35 [PATCH 1/6] drm/amdgpu: skip gpu_info firmware if discovery info is available Alex Deucher
@ 2020-05-28 21:35 ` Alex Deucher
2020-05-28 21:35 ` [PATCH 3/6] drm/amdgpu: use IP discovery table for renoir Alex Deucher
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-05-28 21:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than checking of the variable is enabled and the
chip is the right family check for the presence of the
discovery table.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 716f1f7ebe3d..febcecc5c6b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1533,7 +1533,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
adev->firmware.gpu_info_fw = NULL;
- if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10) {
+ if (adev->discovery_bin) {
amdgpu_discovery_get_gfx_info(adev);
return 0;
}
@@ -3363,7 +3363,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
if (IS_ENABLED(CONFIG_PERF_EVENTS))
amdgpu_pmu_fini(adev);
- if (amdgpu_discovery && adev->asic_type >= CHIP_NAVI10)
+ if (adev->discovery_bin)
amdgpu_discovery_fini(adev);
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/6] drm/amdgpu: use IP discovery table for renoir
2020-05-28 21:35 [PATCH 1/6] drm/amdgpu: skip gpu_info firmware if discovery info is available Alex Deucher
2020-05-28 21:35 ` [PATCH 2/6] drm/amdgpu: clean up discovery testing Alex Deucher
@ 2020-05-28 21:35 ` Alex Deucher
2020-05-28 21:35 ` [PATCH 4/6] drm/amdgpu/nv: allow access to SDMA status registers Alex Deucher
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-05-28 21:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Rather than relying on gpu info firmware.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
Can someone test this on renoir?
drivers/gpu/drm/amd/amdgpu/soc15.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c7c9e07962b9..623745b2d8b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -670,14 +670,25 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
int soc15_set_ip_blocks(struct amdgpu_device *adev)
{
+ int r;
+
/* Set IP register base before any HW register access */
switch (adev->asic_type) {
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN:
- case CHIP_RENOIR:
vega10_reg_base_init(adev);
break;
+ case CHIP_RENOIR:
+ if (amdgpu_discovery) {
+ r = amdgpu_discovery_reg_base_init(adev);
+ if (r) {
+ DRM_WARN("failed to init reg base from ip discovery table, "
+ "fallback to legacy init method\n");
+ vega10_reg_base_init(adev);
+ }
+ }
+ break;
case CHIP_VEGA20:
vega20_reg_base_init(adev);
break;
--
2.25.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/6] drm/amdgpu/nv: allow access to SDMA status registers
2020-05-28 21:35 [PATCH 1/6] drm/amdgpu: skip gpu_info firmware if discovery info is available Alex Deucher
2020-05-28 21:35 ` [PATCH 2/6] drm/amdgpu: clean up discovery testing Alex Deucher
2020-05-28 21:35 ` [PATCH 3/6] drm/amdgpu: use IP discovery table for renoir Alex Deucher
@ 2020-05-28 21:35 ` Alex Deucher
2020-05-28 21:35 ` [PATCH 5/6] drm/amdgpu/nv: remove some dead code Alex Deucher
2020-05-28 21:35 ` [PATCH 6/6] drm/amdgpu/nv: enable init reset check Alex Deucher
4 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-05-28 21:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
For access via ioctl for tools like umr and mesa.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 6655dd2009b6..61eea26922ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -188,10 +188,8 @@ static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
-#if 0 /* TODO: will set it when SDMA header is available */
{ SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
{ SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
-#endif
{ SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
{ SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
--
2.25.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 5/6] drm/amdgpu/nv: remove some dead code
2020-05-28 21:35 [PATCH 1/6] drm/amdgpu: skip gpu_info firmware if discovery info is available Alex Deucher
` (2 preceding siblings ...)
2020-05-28 21:35 ` [PATCH 4/6] drm/amdgpu/nv: allow access to SDMA status registers Alex Deucher
@ 2020-05-28 21:35 ` Alex Deucher
2020-05-28 21:35 ` [PATCH 6/6] drm/amdgpu/nv: enable init reset check Alex Deucher
4 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2020-05-28 21:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
navi never supported the pci config reset. Neither did
vega.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 34 ---------------------------------
1 file changed, 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 61eea26922ce..0f927fcff0d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -254,31 +254,6 @@ static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
return -EINVAL;
}
-#if 0
-static void nv_gpu_pci_config_reset(struct amdgpu_device *adev)
-{
- u32 i;
-
- dev_info(adev->dev, "GPU pci config reset\n");
-
- /* disable BM */
- pci_clear_master(adev->pdev);
- /* reset */
- amdgpu_pci_config_reset(adev);
-
- udelay(100);
-
- /* wait for asic to come out of reset */
- for (i = 0; i < adev->usec_timeout; i++) {
- u32 memsize = nbio_v2_3_get_memsize(adev);
- if (memsize != 0xffffffff)
- break;
- udelay(1);
- }
-
-}
-#endif
-
static int nv_asic_mode1_reset(struct amdgpu_device *adev)
{
u32 i;
@@ -336,15 +311,6 @@ nv_asic_reset_method(struct amdgpu_device *adev)
static int nv_asic_reset(struct amdgpu_device *adev)
{
-
- /* FIXME: it doesn't work since vega10 */
-#if 0
- amdgpu_atombios_scratch_regs_engine_hung(adev, true);
-
- nv_gpu_pci_config_reset(adev);
-
- amdgpu_atombios_scratch_regs_engine_hung(adev, false);
-#endif
int ret = 0;
struct smu_context *smu = &adev->smu;
--
2.25.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 6/6] drm/amdgpu/nv: enable init reset check
2020-05-28 21:35 [PATCH 1/6] drm/amdgpu: skip gpu_info firmware if discovery info is available Alex Deucher
` (3 preceding siblings ...)
2020-05-28 21:35 ` [PATCH 5/6] drm/amdgpu/nv: remove some dead code Alex Deucher
@ 2020-05-28 21:35 ` Alex Deucher
2020-05-29 3:02 ` Zhang, Hawking
2020-05-29 3:02 ` Quan, Evan
4 siblings, 2 replies; 8+ messages in thread
From: Alex Deucher @ 2020-05-28 21:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
gpu reset is implemented for navi so we can enable this.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 0f927fcff0d5..fd3b9e21a5bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -41,6 +41,7 @@
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "smuio/smuio_11_0_0_offset.h"
+#include "mp/mp_11_0_offset.h"
#include "soc15.h"
#include "soc15_common.h"
@@ -514,7 +515,6 @@ static bool nv_need_full_reset(struct amdgpu_device *adev)
static bool nv_need_reset_on_init(struct amdgpu_device *adev)
{
-#if 0
u32 sol_reg;
if (adev->flags & AMD_IS_APU)
@@ -526,8 +526,7 @@ static bool nv_need_reset_on_init(struct amdgpu_device *adev)
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol_reg)
return true;
-#endif
- /* TODO: re-enable it when mode1 reset is functional */
+
return false;
}
--
2.25.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* RE: [PATCH 6/6] drm/amdgpu/nv: enable init reset check
2020-05-28 21:35 ` [PATCH 6/6] drm/amdgpu/nv: enable init reset check Alex Deucher
@ 2020-05-29 3:02 ` Zhang, Hawking
2020-05-29 3:02 ` Quan, Evan
1 sibling, 0 replies; 8+ messages in thread
From: Zhang, Hawking @ 2020-05-29 3:02 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
The series is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Friday, May 29, 2020 05:35
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 6/6] drm/amdgpu/nv: enable init reset check
gpu reset is implemented for navi so we can enable this.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 0f927fcff0d5..fd3b9e21a5bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -41,6 +41,7 @@
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "smuio/smuio_11_0_0_offset.h"
+#include "mp/mp_11_0_offset.h"
#include "soc15.h"
#include "soc15_common.h"
@@ -514,7 +515,6 @@ static bool nv_need_full_reset(struct amdgpu_device *adev)
static bool nv_need_reset_on_init(struct amdgpu_device *adev) { -#if 0
u32 sol_reg;
if (adev->flags & AMD_IS_APU)
@@ -526,8 +526,7 @@ static bool nv_need_reset_on_init(struct amdgpu_device *adev)
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol_reg)
return true;
-#endif
- /* TODO: re-enable it when mode1 reset is functional */
+
return false;
}
--
2.25.4
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^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 6/6] drm/amdgpu/nv: enable init reset check
2020-05-28 21:35 ` [PATCH 6/6] drm/amdgpu/nv: enable init reset check Alex Deucher
2020-05-29 3:02 ` Zhang, Hawking
@ 2020-05-29 3:02 ` Quan, Evan
1 sibling, 0 replies; 8+ messages in thread
From: Quan, Evan @ 2020-05-29 3:02 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Deucher, Alexander
[AMD Official Use Only - Internal Distribution Only]
Patch 1-4 are acked-by: Evan Quan <evan.quan@amd.com>
Patch 5,6 are reviewed-by: Evan Quan <evan.quan@amd.com>
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Friday, May 29, 2020 5:35 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 6/6] drm/amdgpu/nv: enable init reset check
gpu reset is implemented for navi so we can enable this.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 0f927fcff0d5..fd3b9e21a5bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -41,6 +41,7 @@
#include "hdp/hdp_5_0_0_offset.h"
#include "hdp/hdp_5_0_0_sh_mask.h"
#include "smuio/smuio_11_0_0_offset.h"
+#include "mp/mp_11_0_offset.h"
#include "soc15.h"
#include "soc15_common.h"
@@ -514,7 +515,6 @@ static bool nv_need_full_reset(struct amdgpu_device *adev)
static bool nv_need_reset_on_init(struct amdgpu_device *adev)
{
-#if 0
u32 sol_reg;
if (adev->flags & AMD_IS_APU)
@@ -526,8 +526,7 @@ static bool nv_need_reset_on_init(struct amdgpu_device *adev)
sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
if (sol_reg)
return true;
-#endif
-/* TODO: re-enable it when mode1 reset is functional */
+
return false;
}
--
2.25.4
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