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* [PATCH] drm/amd/display: Fix build break
@ 2021-06-08 15:36 Anson Jacob
  2021-06-08 15:38 ` Deucher, Alexander
  0 siblings, 1 reply; 2+ messages in thread
From: Anson Jacob @ 2021-06-08 15:36 UTC (permalink / raw)
  To: amd-gfx
  Cc: Eryk.Brol, Sunpeng.Li, Harry.Wentland, qingqing.zhuo,
	Rodrigo.Siqueira, roman.li, Anson.Jacob, Aurabindo.Pillai,
	Bhawanpreet.Lakha, bindu.r

1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm")

Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 -
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 6bdab06667c9..62904d7ca100 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -202,7 +202,6 @@ struct dccg_registers {
 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
 	uint32_t PHYDSYMCLK_CLOCK_CNTL;
 	uint32_t PHYESYMCLK_CLOCK_CNTL;
-	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
 	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
 	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
 	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 69da1493b277..e3048f8827d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
 	.z10_restore = dcn31_z10_restore,
 	.is_abm_supported = dcn31_is_abm_supported,
 	.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };
 
 static const struct hwseq_private_funcs dcn31_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = {
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
 	.update_odm = dcn20_update_odm,
 	.dsc_pg_control = dcn31_dsc_pg_control,
-	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
-- 
2.25.1

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^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amd/display: Fix build break
  2021-06-08 15:36 [PATCH] drm/amd/display: Fix build break Anson Jacob
@ 2021-06-08 15:38 ` Deucher, Alexander
  0 siblings, 0 replies; 2+ messages in thread
From: Deucher, Alexander @ 2021-06-08 15:38 UTC (permalink / raw)
  To: Jacob, Anson, amd-gfx
  Cc: Brol, Eryk, Li, Sun peng (Leo),
	Lakha, Bhawanpreet, Zhuo,  Qingqing, Siqueira, Rodrigo, Li,
	Roman, Pillai,  Aurabindo, Wentland, Harry, R, Bindu


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[Public]

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Anson Jacob <Anson.Jacob@amd.com>
Sent: Tuesday, June 8, 2021 11:36 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Brol, Eryk <Eryk.Brol@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Li, Roman <Roman.Li@amd.com>; Jacob, Anson <Anson.Jacob@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd.com>; R, Bindu <Bindu.R@amd.com>
Subject: [PATCH] drm/amd/display: Fix build break

1. Remove duplicate OTG_PIXEL_RATE_CNTL from dccg_registers
2. Fixes: 18827ee0cc28 ("drm/amd/display: Refactor visual confirm")

Signed-off-by: Anson Jacob <Anson.Jacob@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 1 -
 drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c | 3 +--
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 6bdab06667c9..62904d7ca100 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -202,7 +202,6 @@ struct dccg_registers {
 #if defined(CONFIG_DRM_AMD_DC_DCN3_1)
         uint32_t PHYDSYMCLK_CLOCK_CNTL;
         uint32_t PHYESYMCLK_CLOCK_CNTL;
-       uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
         uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
         uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
         uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
index 69da1493b277..e3048f8827d2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c
@@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = {
         .z10_restore = dcn31_z10_restore,
         .is_abm_supported = dcn31_is_abm_supported,
         .set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
+       .update_visual_confirm_color = dcn20_update_visual_confirm_color,
 };

 static const struct hwseq_private_funcs dcn31_private_funcs = {
@@ -129,8 +130,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = {
         .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
         .update_odm = dcn20_update_odm,
         .dsc_pg_control = dcn31_dsc_pg_control,
-       .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
-       .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
         .set_hdr_multiplier = dcn10_set_hdr_multiplier,
         .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
         .wait_for_blank_complete = dcn20_wait_for_blank_complete,
--
2.25.1

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2021-06-08 15:38 ` Deucher, Alexander

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