* [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
This RFC is to start discussion over extending dpll interface
with possibility to:
- read a phase offset between signals on pin and dpll,
- adjust a phase of pin's signal.
The RFC is based on latest version of dpll interface submitted for
net-next [1].
[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
Arkadiusz Kubalewski (4):
dpll: docs: add support for pin signal phase offset/adjust
dpll: spec: add support for pin-dpll signal phase offset/adjust
dpll: netlink/core: add support for pin-dpll signal phase
offset/adjust
ice: dpll: implement phase related callbacks
Documentation/driver-api/dpll.rst | 53 ++++-
Documentation/netlink/specs/dpll.yaml | 33 +++-
drivers/dpll/dpll_netlink.c | 99 +++++++++-
drivers/dpll/dpll_nl.c | 8 +-
drivers/dpll/dpll_nl.h | 2 +-
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
include/linux/dpll.h | 18 ++
include/uapi/linux/dpll.h | 8 +-
9 files changed, 443 insertions(+), 12 deletions(-)
--
2.38.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
This RFC is to start discussion over extending dpll interface
with possibility to:
- read a phase offset between signals on pin and dpll,
- adjust a phase of pin's signal.
The RFC is based on latest version of dpll interface submitted for
net-next [1].
[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
Arkadiusz Kubalewski (4):
dpll: docs: add support for pin signal phase offset/adjust
dpll: spec: add support for pin-dpll signal phase offset/adjust
dpll: netlink/core: add support for pin-dpll signal phase
offset/adjust
ice: dpll: implement phase related callbacks
Documentation/driver-api/dpll.rst | 53 ++++-
Documentation/netlink/specs/dpll.yaml | 33 +++-
drivers/dpll/dpll_netlink.c | 99 +++++++++-
drivers/dpll/dpll_nl.c | 8 +-
drivers/dpll/dpll_nl.h | 2 +-
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
include/linux/dpll.h | 18 ++
include/uapi/linux/dpll.h | 8 +-
9 files changed, 443 insertions(+), 12 deletions(-)
--
2.38.1
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
This RFC is to start discussion over extending dpll interface
with possibility to:
- read a phase offset between signals on pin and dpll,
- adjust a phase of pin's signal.
The RFC is based on latest version of dpll interface submitted for
net-next [1].
[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
Arkadiusz Kubalewski (4):
dpll: docs: add support for pin signal phase offset/adjust
dpll: spec: add support for pin-dpll signal phase offset/adjust
dpll: netlink/core: add support for pin-dpll signal phase
offset/adjust
ice: dpll: implement phase related callbacks
Documentation/driver-api/dpll.rst | 53 ++++-
Documentation/netlink/specs/dpll.yaml | 33 +++-
drivers/dpll/dpll_netlink.c | 99 +++++++++-
drivers/dpll/dpll_nl.c | 8 +-
drivers/dpll/dpll_nl.h | 2 +-
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
include/linux/dpll.h | 18 ++
include/uapi/linux/dpll.h | 8 +-
9 files changed, 443 insertions(+), 12 deletions(-)
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH net-next 1/4] dpll: docs: add support for pin signal phase offset/adjust
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
-1 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add documentation on:
- measurment of phase of signal between pin and dpll
- adjustment of pin signal phase
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/driver-api/dpll.rst | 53 ++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
index bb52f1b8c0be..59634a3513bd 100644
--- a/Documentation/driver-api/dpll.rst
+++ b/Documentation/driver-api/dpll.rst
@@ -173,6 +173,47 @@ in order to configure active input of a MUX-type pin, the user needs to
request desired pin state of the child pin on the parent pin,
as described in the ``MUX-type pins`` chapter.
+Phase offset measurement and adjustment
+========================================
+
+Device may provide ability to measure a phase difference between signals
+on a pin and its parent dpll device. If pin-dpll phase offset measurement
+is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
+attribute for each parent dpll device.
+
+Device may also provide ability to adjust a signal phase on a pin.
+If pin phase adjustment is supported, minimal and maximal values that pin
+handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
+with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
+attributes. Configured phase adjust value is provided with
+``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
+requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
+
+ =============================== ======================================
+ ``DPLL_A_PIN_ID`` configured pin id
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent dpll device
+ ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
+ configuration on given parent dpll
+ device
+ ``DPLL_A_PIN_PARENT_ID`` parent dpll device id
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll device
+ =============================== ======================================
+
+All phase related values are provided in pico seconds, which represents
+time differnece between signals phase. The negative value means that
+phase of signal on pin is earlier in time than dpll's signal. Positive
+value means that phase of signal on pin is later in time than signal of
+a dpll.
+
+Phase adjust (also min and max) values are integers, but measured phase
+offset values are fractional with 3-digit decimal places and shell be
+divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
+modulo divided to get fractional part.
+
Configuration commands group
============================
@@ -263,6 +304,12 @@ according to attribute purpose.
frequencies
``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
@@ -270,8 +317,10 @@ according to attribute purpose.
dpll device
``DPLL_A_PIN_STATE`` attr state of pin on the parent
dpll device
- ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
+ ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
parent dpll device
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll
``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent pin id
@@ -284,6 +333,8 @@ according to attribute purpose.
``DPLL_CMD_PIN_SET`` command to set pins configuration
``DPLL_A_PIN_ID`` attr unique a pin ID
``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
device configuration request
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
--
2.38.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 1/4] dpll: docs: add support for pin signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add documentation on:
- measurment of phase of signal between pin and dpll
- adjustment of pin signal phase
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/driver-api/dpll.rst | 53 ++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
index bb52f1b8c0be..59634a3513bd 100644
--- a/Documentation/driver-api/dpll.rst
+++ b/Documentation/driver-api/dpll.rst
@@ -173,6 +173,47 @@ in order to configure active input of a MUX-type pin, the user needs to
request desired pin state of the child pin on the parent pin,
as described in the ``MUX-type pins`` chapter.
+Phase offset measurement and adjustment
+========================================
+
+Device may provide ability to measure a phase difference between signals
+on a pin and its parent dpll device. If pin-dpll phase offset measurement
+is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
+attribute for each parent dpll device.
+
+Device may also provide ability to adjust a signal phase on a pin.
+If pin phase adjustment is supported, minimal and maximal values that pin
+handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
+with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
+attributes. Configured phase adjust value is provided with
+``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
+requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
+
+ =============================== ======================================
+ ``DPLL_A_PIN_ID`` configured pin id
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent dpll device
+ ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
+ configuration on given parent dpll
+ device
+ ``DPLL_A_PIN_PARENT_ID`` parent dpll device id
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll device
+ =============================== ======================================
+
+All phase related values are provided in pico seconds, which represents
+time differnece between signals phase. The negative value means that
+phase of signal on pin is earlier in time than dpll's signal. Positive
+value means that phase of signal on pin is later in time than signal of
+a dpll.
+
+Phase adjust (also min and max) values are integers, but measured phase
+offset values are fractional with 3-digit decimal places and shell be
+divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
+modulo divided to get fractional part.
+
Configuration commands group
============================
@@ -263,6 +304,12 @@ according to attribute purpose.
frequencies
``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
@@ -270,8 +317,10 @@ according to attribute purpose.
dpll device
``DPLL_A_PIN_STATE`` attr state of pin on the parent
dpll device
- ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
+ ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
parent dpll device
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll
``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent pin id
@@ -284,6 +333,8 @@ according to attribute purpose.
``DPLL_CMD_PIN_SET`` command to set pins configuration
``DPLL_A_PIN_ID`` attr unique a pin ID
``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
device configuration request
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 1/4] dpll: docs: add support for pin signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
Add documentation on:
- measurment of phase of signal between pin and dpll
- adjustment of pin signal phase
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/driver-api/dpll.rst | 53 ++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
index bb52f1b8c0be..59634a3513bd 100644
--- a/Documentation/driver-api/dpll.rst
+++ b/Documentation/driver-api/dpll.rst
@@ -173,6 +173,47 @@ in order to configure active input of a MUX-type pin, the user needs to
request desired pin state of the child pin on the parent pin,
as described in the ``MUX-type pins`` chapter.
+Phase offset measurement and adjustment
+========================================
+
+Device may provide ability to measure a phase difference between signals
+on a pin and its parent dpll device. If pin-dpll phase offset measurement
+is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
+attribute for each parent dpll device.
+
+Device may also provide ability to adjust a signal phase on a pin.
+If pin phase adjustment is supported, minimal and maximal values that pin
+handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
+with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
+attributes. Configured phase adjust value is provided with
+``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
+requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
+
+ =============================== ======================================
+ ``DPLL_A_PIN_ID`` configured pin id
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent dpll device
+ ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
+ configuration on given parent dpll
+ device
+ ``DPLL_A_PIN_PARENT_ID`` parent dpll device id
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll device
+ =============================== ======================================
+
+All phase related values are provided in pico seconds, which represents
+time differnece between signals phase. The negative value means that
+phase of signal on pin is earlier in time than dpll's signal. Positive
+value means that phase of signal on pin is later in time than signal of
+a dpll.
+
+Phase adjust (also min and max) values are integers, but measured phase
+offset values are fractional with 3-digit decimal places and shell be
+divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and
+modulo divided to get fractional part.
+
Configuration commands group
============================
@@ -263,6 +304,12 @@ according to attribute purpose.
frequencies
``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
+ ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase
+ adjustment
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
@@ -270,8 +317,10 @@ according to attribute purpose.
dpll device
``DPLL_A_PIN_STATE`` attr state of pin on the parent
dpll device
- ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
+ ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the
parent dpll device
+ ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
+ between a pin and parent dpll
``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin
the pin is connected with
``DPLL_A_PIN_PARENT_ID`` attr parent pin id
@@ -284,6 +333,8 @@ according to attribute purpose.
``DPLL_CMD_PIN_SET`` command to set pins configuration
``DPLL_A_PIN_ID`` attr unique a pin ID
``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin
+ ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase
+ adjustment on parent device
``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll
device configuration request
``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id
--
2.38.1
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 2/4] dpll: spec: add support for pin-dpll signal phase offset/adjust
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
-1 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/netlink/specs/dpll.yaml | 33 ++++++++++++++++++++++++++-
drivers/dpll/dpll_nl.c | 8 ++++---
drivers/dpll/dpll_nl.h | 2 +-
include/uapi/linux/dpll.h | 8 ++++++-
4 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 8b86b28b47a6..dc057494101f 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
name: dpll
-
+version: 2
doc: DPLL subsystem.
definitions:
@@ -164,6 +164,18 @@ definitions:
-
name: state-can-change
doc: pin state can be changed
+ -
+ type: const
+ name: phase-offset-divider
+ value: 1000
+ doc: |
+ phase offset divider allows userspace to calculate a value of
+ measured signal phase difference between a pin and dpll device
+ as a fractional value with three digit decimal precision.
+ Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
+ integer part of a measured phase offest value.
+ Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
+ fractional part of a measured phase offest value.
attribute-sets:
-
@@ -272,6 +284,18 @@ attribute-sets:
type: nest
multi-attr: true
nested-attributes: pin-parent-pin
+ -
+ name: phase-adjust-min
+ type: s32
+ -
+ name: phase-adjust-max
+ type: s32
+ -
+ name: phase-adjust
+ type: s32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-device
subset-of: pin
@@ -288,6 +312,9 @@ attribute-sets:
-
name: state
type: u32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-pin
subset-of: pin
@@ -439,6 +466,9 @@ operations:
- capabilities
- parent-device
- parent-pin
+ - phase-adjust-min
+ - phase-adjust-max
+ - phase-adjust
dump:
pre: dpll-lock-dumpit
@@ -466,6 +496,7 @@ operations:
- state
- parent-device
- parent-pin
+ - phase-adjust
-
name: pin-create-ntf
doc: Notification about pin appearing
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index 14064c8c783b..eaee5be7aa64 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -11,11 +11,12 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {
+const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {
[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
+ [DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },
};
const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
@@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
};
/* DPLL_CMD_PIN_SET - do */
-static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {
+static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {
[DPLL_A_PIN_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1]
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),
[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
+ [DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
};
/* Ops table for dpll */
@@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
.doit = dpll_nl_pin_set_doit,
.post_doit = dpll_pin_post_doit,
.policy = dpll_pin_set_nl_policy,
- .maxattr = DPLL_A_PIN_PARENT_PIN,
+ .maxattr = DPLL_A_PIN_PHASE_ADJUST,
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
},
};
diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h
index 1f67aaed4742..92d4c9c4f788 100644
--- a/drivers/dpll/dpll_nl.h
+++ b/drivers/dpll/dpll_nl.h
@@ -12,7 +12,7 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];
+extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 20ef0718f8dc..050f51b48ef8 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -7,7 +7,7 @@
#define _UAPI_LINUX_DPLL_H
#define DPLL_FAMILY_NAME "dpll"
-#define DPLL_FAMILY_VERSION 1
+#define DPLL_FAMILY_VERSION 2
/**
* enum dpll_mode - working modes a dpll can support, differentiates if and how
@@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
};
+#define DPLL_PHASE_OFFSET_DIVIDER 1000
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -173,6 +175,10 @@ enum dpll_a_pin {
DPLL_A_PIN_CAPABILITIES,
DPLL_A_PIN_PARENT_DEVICE,
DPLL_A_PIN_PARENT_PIN,
+ DPLL_A_PIN_PHASE_ADJUST_MIN,
+ DPLL_A_PIN_PHASE_ADJUST_MAX,
+ DPLL_A_PIN_PHASE_ADJUST,
+ DPLL_A_PIN_PHASE_OFFSET,
__DPLL_A_PIN_MAX,
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
--
2.38.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 2/4] dpll: spec: add support for pin-dpll signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/netlink/specs/dpll.yaml | 33 ++++++++++++++++++++++++++-
drivers/dpll/dpll_nl.c | 8 ++++---
drivers/dpll/dpll_nl.h | 2 +-
include/uapi/linux/dpll.h | 8 ++++++-
4 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 8b86b28b47a6..dc057494101f 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
name: dpll
-
+version: 2
doc: DPLL subsystem.
definitions:
@@ -164,6 +164,18 @@ definitions:
-
name: state-can-change
doc: pin state can be changed
+ -
+ type: const
+ name: phase-offset-divider
+ value: 1000
+ doc: |
+ phase offset divider allows userspace to calculate a value of
+ measured signal phase difference between a pin and dpll device
+ as a fractional value with three digit decimal precision.
+ Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
+ integer part of a measured phase offest value.
+ Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
+ fractional part of a measured phase offest value.
attribute-sets:
-
@@ -272,6 +284,18 @@ attribute-sets:
type: nest
multi-attr: true
nested-attributes: pin-parent-pin
+ -
+ name: phase-adjust-min
+ type: s32
+ -
+ name: phase-adjust-max
+ type: s32
+ -
+ name: phase-adjust
+ type: s32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-device
subset-of: pin
@@ -288,6 +312,9 @@ attribute-sets:
-
name: state
type: u32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-pin
subset-of: pin
@@ -439,6 +466,9 @@ operations:
- capabilities
- parent-device
- parent-pin
+ - phase-adjust-min
+ - phase-adjust-max
+ - phase-adjust
dump:
pre: dpll-lock-dumpit
@@ -466,6 +496,7 @@ operations:
- state
- parent-device
- parent-pin
+ - phase-adjust
-
name: pin-create-ntf
doc: Notification about pin appearing
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index 14064c8c783b..eaee5be7aa64 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -11,11 +11,12 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {
+const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {
[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
+ [DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },
};
const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
@@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
};
/* DPLL_CMD_PIN_SET - do */
-static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {
+static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {
[DPLL_A_PIN_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1]
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),
[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
+ [DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
};
/* Ops table for dpll */
@@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
.doit = dpll_nl_pin_set_doit,
.post_doit = dpll_pin_post_doit,
.policy = dpll_pin_set_nl_policy,
- .maxattr = DPLL_A_PIN_PARENT_PIN,
+ .maxattr = DPLL_A_PIN_PHASE_ADJUST,
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
},
};
diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h
index 1f67aaed4742..92d4c9c4f788 100644
--- a/drivers/dpll/dpll_nl.h
+++ b/drivers/dpll/dpll_nl.h
@@ -12,7 +12,7 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];
+extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 20ef0718f8dc..050f51b48ef8 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -7,7 +7,7 @@
#define _UAPI_LINUX_DPLL_H
#define DPLL_FAMILY_NAME "dpll"
-#define DPLL_FAMILY_VERSION 1
+#define DPLL_FAMILY_VERSION 2
/**
* enum dpll_mode - working modes a dpll can support, differentiates if and how
@@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
};
+#define DPLL_PHASE_OFFSET_DIVIDER 1000
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -173,6 +175,10 @@ enum dpll_a_pin {
DPLL_A_PIN_CAPABILITIES,
DPLL_A_PIN_PARENT_DEVICE,
DPLL_A_PIN_PARENT_PIN,
+ DPLL_A_PIN_PHASE_ADJUST_MIN,
+ DPLL_A_PIN_PHASE_ADJUST_MAX,
+ DPLL_A_PIN_PHASE_ADJUST,
+ DPLL_A_PIN_PHASE_OFFSET,
__DPLL_A_PIN_MAX,
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
--
2.38.1
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 2/4] dpll: spec: add support for pin-dpll signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
Documentation/netlink/specs/dpll.yaml | 33 ++++++++++++++++++++++++++-
drivers/dpll/dpll_nl.c | 8 ++++---
drivers/dpll/dpll_nl.h | 2 +-
include/uapi/linux/dpll.h | 8 ++++++-
4 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml
index 8b86b28b47a6..dc057494101f 100644
--- a/Documentation/netlink/specs/dpll.yaml
+++ b/Documentation/netlink/specs/dpll.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
name: dpll
-
+version: 2
doc: DPLL subsystem.
definitions:
@@ -164,6 +164,18 @@ definitions:
-
name: state-can-change
doc: pin state can be changed
+ -
+ type: const
+ name: phase-offset-divider
+ value: 1000
+ doc: |
+ phase offset divider allows userspace to calculate a value of
+ measured signal phase difference between a pin and dpll device
+ as a fractional value with three digit decimal precision.
+ Value of (DPLL_A_PHASE_OFFSET / DPLL_PHASE_OFFSET_DIVIDER) is an
+ integer part of a measured phase offest value.
+ Value of (DPLL_A_PHASE_OFFSET % DPLL_PHASE_OFFSET_DIVIDER) is a
+ fractional part of a measured phase offest value.
attribute-sets:
-
@@ -272,6 +284,18 @@ attribute-sets:
type: nest
multi-attr: true
nested-attributes: pin-parent-pin
+ -
+ name: phase-adjust-min
+ type: s32
+ -
+ name: phase-adjust-max
+ type: s32
+ -
+ name: phase-adjust
+ type: s32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-device
subset-of: pin
@@ -288,6 +312,9 @@ attribute-sets:
-
name: state
type: u32
+ -
+ name: phase-offset
+ type: s64
-
name: pin-parent-pin
subset-of: pin
@@ -439,6 +466,9 @@ operations:
- capabilities
- parent-device
- parent-pin
+ - phase-adjust-min
+ - phase-adjust-max
+ - phase-adjust
dump:
pre: dpll-lock-dumpit
@@ -466,6 +496,7 @@ operations:
- state
- parent-device
- parent-pin
+ - phase-adjust
-
name: pin-create-ntf
doc: Notification about pin appearing
diff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c
index 14064c8c783b..eaee5be7aa64 100644
--- a/drivers/dpll/dpll_nl.c
+++ b/drivers/dpll/dpll_nl.c
@@ -11,11 +11,12 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1] = {
+const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1] = {
[DPLL_A_PIN_PARENT_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
[DPLL_A_PIN_PRIO] = { .type = NLA_U32, },
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
+ [DPLL_A_PIN_PHASE_OFFSET] = { .type = NLA_S64, },
};
const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
@@ -61,7 +62,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
};
/* DPLL_CMD_PIN_SET - do */
-static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1] = {
+static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PHASE_ADJUST + 1] = {
[DPLL_A_PIN_ID] = { .type = NLA_U32, },
[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -69,6 +70,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_PARENT_PIN + 1]
[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
[DPLL_A_PIN_PARENT_DEVICE] = NLA_POLICY_NESTED(dpll_pin_parent_device_nl_policy),
[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
+ [DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
};
/* Ops table for dpll */
@@ -140,7 +142,7 @@ static const struct genl_split_ops dpll_nl_ops[] = {
.doit = dpll_nl_pin_set_doit,
.post_doit = dpll_pin_post_doit,
.policy = dpll_pin_set_nl_policy,
- .maxattr = DPLL_A_PIN_PARENT_PIN,
+ .maxattr = DPLL_A_PIN_PHASE_ADJUST,
.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
},
};
diff --git a/drivers/dpll/dpll_nl.h b/drivers/dpll/dpll_nl.h
index 1f67aaed4742..92d4c9c4f788 100644
--- a/drivers/dpll/dpll_nl.h
+++ b/drivers/dpll/dpll_nl.h
@@ -12,7 +12,7 @@
#include <uapi/linux/dpll.h>
/* Common nested types */
-extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_STATE + 1];
+extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
diff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h
index 20ef0718f8dc..050f51b48ef8 100644
--- a/include/uapi/linux/dpll.h
+++ b/include/uapi/linux/dpll.h
@@ -7,7 +7,7 @@
#define _UAPI_LINUX_DPLL_H
#define DPLL_FAMILY_NAME "dpll"
-#define DPLL_FAMILY_VERSION 1
+#define DPLL_FAMILY_VERSION 2
/**
* enum dpll_mode - working modes a dpll can support, differentiates if and how
@@ -138,6 +138,8 @@ enum dpll_pin_capabilities {
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
};
+#define DPLL_PHASE_OFFSET_DIVIDER 1000
+
enum dpll_a {
DPLL_A_ID = 1,
DPLL_A_MODULE_NAME,
@@ -173,6 +175,10 @@ enum dpll_a_pin {
DPLL_A_PIN_CAPABILITIES,
DPLL_A_PIN_PARENT_DEVICE,
DPLL_A_PIN_PARENT_PIN,
+ DPLL_A_PIN_PHASE_ADJUST_MIN,
+ DPLL_A_PIN_PHASE_ADJUST_MAX,
+ DPLL_A_PIN_PHASE_ADJUST,
+ DPLL_A_PIN_PHASE_OFFSET,
__DPLL_A_PIN_MAX,
DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
-1 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add callback ops for pin-dpll phase measurment.
Add callback for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke callbacks in dpll_netlink.c when filling the pin details to
provide user with phase related attribute values.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/dpll/dpll_netlink.c | 99 ++++++++++++++++++++++++++++++++++++-
include/linux/dpll.h | 18 +++++++
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index 764437a0661b..548517d9ca4c 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
return 0;
}
+static int
+dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s32 phase_adjust;
+ int ret;
+
+ if (!ops->phase_adjust_get)
+ return 0;
+ ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll),
+ &phase_adjust, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
+static int
+dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s64 phase_offset;
+ int ret;
+
+ if (!ops->phase_offset_get)
+ return 0;
+ ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), &phase_offset,
+ extack);
+ if (ret)
+ return ret;
+ if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),
+ &phase_offset, DPLL_A_PIN_PAD))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
static int
dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
@@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
if (ret)
goto nest_cancel;
ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
+ if (ret)
+ goto nest_cancel;
+ ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
if (ret)
goto nest_cancel;
nla_nest_end(msg, attr);
@@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
return -EMSGSIZE;
ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
+ prop->phase_range.min))
+ return -EMSGSIZE;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
+ prop->phase_range.max))
+ return -EMSGSIZE;
+ ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
if (ret)
return ret;
if (xa_empty(&pin->parent_refs))
@@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
return -EMSGSIZE;
- return ret;
+ return 0;
}
static int
@@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
return 0;
}
+static int
+dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
+ struct netlink_ext_ack *extack)
+{
+ struct dpll_pin_ref *ref;
+ unsigned long i;
+ s32 phase_adj;
+ int ret;
+
+ phase_adj = nla_get_s32(phase_adj_attr);
+ if (phase_adj > pin->prop->phase_range.max ||
+ phase_adj < pin->prop->phase_range.min) {
+ NL_SET_ERR_MSG(extack, "phase adjust value not supported");
+ return -EINVAL;
+ }
+ xa_for_each(&pin->dpll_refs, i, ref) {
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+
+ if (!ops->phase_adjust_set)
+ return -EOPNOTSUPP;
+ ret = ops->phase_adjust_set(pin,
+ dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), phase_adj,
+ extack);
+ if (ret)
+ return ret;
+ }
+ __dpll_pin_change_ntf(pin);
+
+ return 0;
+}
+
static int
dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
struct netlink_ext_ack *extack)
@@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
if (ret)
return ret;
break;
+ case DPLL_A_PIN_PHASE_ADJUST:
+ ret = dpll_pin_phase_adj_set(pin, a, info->extack);
+ if (ret)
+ return ret;
+ break;
case DPLL_A_PIN_PARENT_DEVICE:
ret = dpll_pin_parent_device_set(pin, a, info->extack);
if (ret)
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index bbc480cd2932..578fc5fa3750 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -68,6 +68,18 @@ struct dpll_pin_ops {
int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
const struct dpll_device *dpll, void *dpll_priv,
const u32 prio, struct netlink_ext_ack *extack);
+ int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack);
};
struct dpll_pin_frequency {
@@ -91,6 +103,11 @@ struct dpll_pin_frequency {
#define DPLL_PIN_FREQUENCY_DCF77 \
DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
+struct dpll_pin_phase_adjust_range {
+ s32 min;
+ s32 max;
+};
+
struct dpll_pin_properties {
const char *board_label;
const char *panel_label;
@@ -99,6 +116,7 @@ struct dpll_pin_properties {
unsigned long capabilities;
u32 freq_supported_num;
struct dpll_pin_frequency *freq_supported;
+ struct dpll_pin_phase_adjust_range phase_range;
};
#if IS_ENABLED(CONFIG_DPLL)
--
2.38.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
Add callback ops for pin-dpll phase measurment.
Add callback for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke callbacks in dpll_netlink.c when filling the pin details to
provide user with phase related attribute values.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/dpll/dpll_netlink.c | 99 ++++++++++++++++++++++++++++++++++++-
include/linux/dpll.h | 18 +++++++
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index 764437a0661b..548517d9ca4c 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
return 0;
}
+static int
+dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s32 phase_adjust;
+ int ret;
+
+ if (!ops->phase_adjust_get)
+ return 0;
+ ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll),
+ &phase_adjust, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
+static int
+dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s64 phase_offset;
+ int ret;
+
+ if (!ops->phase_offset_get)
+ return 0;
+ ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), &phase_offset,
+ extack);
+ if (ret)
+ return ret;
+ if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),
+ &phase_offset, DPLL_A_PIN_PAD))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
static int
dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
@@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
if (ret)
goto nest_cancel;
ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
+ if (ret)
+ goto nest_cancel;
+ ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
if (ret)
goto nest_cancel;
nla_nest_end(msg, attr);
@@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
return -EMSGSIZE;
ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
+ prop->phase_range.min))
+ return -EMSGSIZE;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
+ prop->phase_range.max))
+ return -EMSGSIZE;
+ ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
if (ret)
return ret;
if (xa_empty(&pin->parent_refs))
@@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
return -EMSGSIZE;
- return ret;
+ return 0;
}
static int
@@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
return 0;
}
+static int
+dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
+ struct netlink_ext_ack *extack)
+{
+ struct dpll_pin_ref *ref;
+ unsigned long i;
+ s32 phase_adj;
+ int ret;
+
+ phase_adj = nla_get_s32(phase_adj_attr);
+ if (phase_adj > pin->prop->phase_range.max ||
+ phase_adj < pin->prop->phase_range.min) {
+ NL_SET_ERR_MSG(extack, "phase adjust value not supported");
+ return -EINVAL;
+ }
+ xa_for_each(&pin->dpll_refs, i, ref) {
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+
+ if (!ops->phase_adjust_set)
+ return -EOPNOTSUPP;
+ ret = ops->phase_adjust_set(pin,
+ dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), phase_adj,
+ extack);
+ if (ret)
+ return ret;
+ }
+ __dpll_pin_change_ntf(pin);
+
+ return 0;
+}
+
static int
dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
struct netlink_ext_ack *extack)
@@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
if (ret)
return ret;
break;
+ case DPLL_A_PIN_PHASE_ADJUST:
+ ret = dpll_pin_phase_adj_set(pin, a, info->extack);
+ if (ret)
+ return ret;
+ break;
case DPLL_A_PIN_PARENT_DEVICE:
ret = dpll_pin_parent_device_set(pin, a, info->extack);
if (ret)
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index bbc480cd2932..578fc5fa3750 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -68,6 +68,18 @@ struct dpll_pin_ops {
int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
const struct dpll_device *dpll, void *dpll_priv,
const u32 prio, struct netlink_ext_ack *extack);
+ int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack);
};
struct dpll_pin_frequency {
@@ -91,6 +103,11 @@ struct dpll_pin_frequency {
#define DPLL_PIN_FREQUENCY_DCF77 \
DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
+struct dpll_pin_phase_adjust_range {
+ s32 min;
+ s32 max;
+};
+
struct dpll_pin_properties {
const char *board_label;
const char *panel_label;
@@ -99,6 +116,7 @@ struct dpll_pin_properties {
unsigned long capabilities;
u32 freq_supported_num;
struct dpll_pin_frequency *freq_supported;
+ struct dpll_pin_phase_adjust_range phase_range;
};
#if IS_ENABLED(CONFIG_DPLL)
--
2.38.1
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Add callback ops for pin-dpll phase measurment.
Add callback for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke callbacks in dpll_netlink.c when filling the pin details to
provide user with phase related attribute values.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/dpll/dpll_netlink.c | 99 ++++++++++++++++++++++++++++++++++++-
include/linux/dpll.h | 18 +++++++
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index 764437a0661b..548517d9ca4c 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
return 0;
}
+static int
+dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s32 phase_adjust;
+ int ret;
+
+ if (!ops->phase_adjust_get)
+ return 0;
+ ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll),
+ &phase_adjust, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
+static int
+dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s64 phase_offset;
+ int ret;
+
+ if (!ops->phase_offset_get)
+ return 0;
+ ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), &phase_offset,
+ extack);
+ if (ret)
+ return ret;
+ if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),
+ &phase_offset, DPLL_A_PIN_PAD))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
static int
dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
@@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
if (ret)
goto nest_cancel;
ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
+ if (ret)
+ goto nest_cancel;
+ ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
if (ret)
goto nest_cancel;
nla_nest_end(msg, attr);
@@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
return -EMSGSIZE;
ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
+ prop->phase_range.min))
+ return -EMSGSIZE;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
+ prop->phase_range.max))
+ return -EMSGSIZE;
+ ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
if (ret)
return ret;
if (xa_empty(&pin->parent_refs))
@@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
return -EMSGSIZE;
- return ret;
+ return 0;
}
static int
@@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
return 0;
}
+static int
+dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
+ struct netlink_ext_ack *extack)
+{
+ struct dpll_pin_ref *ref;
+ unsigned long i;
+ s32 phase_adj;
+ int ret;
+
+ phase_adj = nla_get_s32(phase_adj_attr);
+ if (phase_adj > pin->prop->phase_range.max ||
+ phase_adj < pin->prop->phase_range.min) {
+ NL_SET_ERR_MSG(extack, "phase adjust value not supported");
+ return -EINVAL;
+ }
+ xa_for_each(&pin->dpll_refs, i, ref) {
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+
+ if (!ops->phase_adjust_set)
+ return -EOPNOTSUPP;
+ ret = ops->phase_adjust_set(pin,
+ dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), phase_adj,
+ extack);
+ if (ret)
+ return ret;
+ }
+ __dpll_pin_change_ntf(pin);
+
+ return 0;
+}
+
static int
dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
struct netlink_ext_ack *extack)
@@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
if (ret)
return ret;
break;
+ case DPLL_A_PIN_PHASE_ADJUST:
+ ret = dpll_pin_phase_adj_set(pin, a, info->extack);
+ if (ret)
+ return ret;
+ break;
case DPLL_A_PIN_PARENT_DEVICE:
ret = dpll_pin_parent_device_set(pin, a, info->extack);
if (ret)
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index bbc480cd2932..578fc5fa3750 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -68,6 +68,18 @@ struct dpll_pin_ops {
int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
const struct dpll_device *dpll, void *dpll_priv,
const u32 prio, struct netlink_ext_ack *extack);
+ int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack);
};
struct dpll_pin_frequency {
@@ -91,6 +103,11 @@ struct dpll_pin_frequency {
#define DPLL_PIN_FREQUENCY_DCF77 \
DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
+struct dpll_pin_phase_adjust_range {
+ s32 min;
+ s32 max;
+};
+
struct dpll_pin_properties {
const char *board_label;
const char *panel_label;
@@ -99,6 +116,7 @@ struct dpll_pin_properties {
unsigned long capabilities;
u32 freq_supported_num;
struct dpll_pin_frequency *freq_supported;
+ struct dpll_pin_phase_adjust_range phase_range;
};
#if IS_ENABLED(CONFIG_DPLL)
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 4/4] ice: dpll: implement pin phase related callbacks
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
-1 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Implement new callback ops related to measurment and adjustment of
signal phase for pin-dpll in ice driver.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
2 files changed, 230 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 1faee9cb944d..6f7a2916f6c2 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -878,6 +878,203 @@ ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
return 0;
}
+/**
+ * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_pf *pf = p->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ *phase_adjust = p->phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
+/**
+ * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ * @type: type of a pin
+ *
+ * Helper for dpll subsystem callback. Handler for setting phase adjust value
+ * of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack,
+ enum ice_dpll_pin_type type)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+ u8 flag, flags_en = 0;
+ int ret;
+
+ mutex_lock(&pf->dplls.lock);
+ if (phase_adjust == p->phase_adjust) {
+ mutex_unlock(&pf->dplls.lock);
+ return 0;
+ }
+ switch (type) {
+ case ICE_DPLL_PIN_TYPE_INPUT:
+ flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
+ ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
+ 0, phase_adjust);
+ break;
+ case ICE_DPLL_PIN_TYPE_OUTPUT:
+ flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
+ ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
+ phase_adjust);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (!ret)
+ p->phase_adjust = phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+ if (ret)
+ NL_SET_ERR_MSG_FMT(extack,
+ "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
+ ret,
+ ice_aq_str(pf->hw.adminq.sq_last_status),
+ phase_adjust, p->idx, d->dpll_idx);
+
+ return ret;
+}
+
+/**
+ * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_INPUT);
+}
+
+/**
+ * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_OUTPUT);
+}
+
+#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
+#define ICE_DPLL_PHASE_OFFSET_FACTOR \
+ (DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
+/**
+ * ice_dpll_phase_offset_get - callback for get dpll phase shift value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase shift value between
+ * dpll's input and output.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset, struct netlink_ext_ack *extack)
+{
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ if (d->active_input == pin)
+ *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
+ else
+ *phase_offset = 0;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
/**
* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
* @pin: pointer to a pin
@@ -993,6 +1190,9 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
.prio_get = ice_dpll_input_prio_get,
.prio_set = ice_dpll_input_prio_set,
.direction_get = ice_dpll_input_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_input_phase_adjust_set,
+ .phase_offset_get = ice_dpll_phase_offset_get,
};
static const struct dpll_pin_ops ice_dpll_output_ops = {
@@ -1001,6 +1201,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
.state_on_dpll_get = ice_dpll_output_state_get,
.state_on_dpll_set = ice_dpll_output_state_set,
.direction_get = ice_dpll_output_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_output_phase_adjust_set,
};
static const struct dpll_device_ops ice_dpll_ops = {
@@ -1031,6 +1233,8 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
*/
static void ice_dpll_notify_changes(struct ice_dpll *d)
{
+ bool pin_notified = false;
+
if (d->prev_dpll_state != d->dpll_state) {
d->prev_dpll_state = d->dpll_state;
dpll_device_change_ntf(d->dpll);
@@ -1039,7 +1243,14 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
if (d->prev_input)
dpll_pin_change_ntf(d->prev_input);
d->prev_input = d->active_input;
- if (d->active_input)
+ if (d->active_input) {
+ dpll_pin_change_ntf(d->active_input);
+ pin_notified = true;
+ }
+ }
+ if (d->prev_phase_offset != d->phase_offset) {
+ d->prev_phase_offset = d->phase_offset;
+ if (!pin_notified && d->active_input)
dpll_pin_change_ntf(d->active_input);
}
}
@@ -1065,7 +1276,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
&d->input_idx, &d->ref_state, &d->eec_mode,
- &d->phase_shift, &d->dpll_state);
+ &d->phase_offset, &d->dpll_state);
dev_dbg(ice_pf_to_dev(pf),
"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
@@ -1656,6 +1867,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
return ret;
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
+ pins[i].prop.phase_range.min =
+ pf->dplls.input_phase_adj_max;
+ pins[i].prop.phase_range.max =
+ -pf->dplls.input_phase_adj_max;
+ } else {
+ pins[i].prop.phase_range.min =
+ pf->dplls.output_phase_adj_max,
+ pins[i].prop.phase_range.max =
+ -pf->dplls.output_phase_adj_max;
}
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethernet/intel/ice/ice_dpll.h
index 9c524c4bdfd7..5f23f82d31a9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.h
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.h
@@ -19,6 +19,7 @@
* @state: state of a pin
* @prop: pin properties
* @freq: current frequency of a pin
+ * @phase_adjust: current phase adjust value
*/
struct ice_dpll_pin {
struct dpll_pin *pin;
@@ -30,6 +31,7 @@ struct ice_dpll_pin {
u8 state[ICE_DPLL_RCLK_NUM_MAX];
struct dpll_pin_properties prop;
u32 freq;
+ s32 phase_adjust;
};
/** ice_dpll - store info required for DPLL control
@@ -40,7 +42,8 @@ struct ice_dpll_pin {
* @prev_input_idx: previously selected input index
* @ref_state: state of dpll reference signals
* @eec_mode: eec_mode dpll is configured for
- * @phase_shift: phase shift delay of a dpll
+ * @phase_offset: phase offset of active pin vs dpll signal
+ * @prev_phase_offset: previous phase offset of active pin vs dpll signal
* @input_prio: priorities of each input
* @dpll_state: current dpll sync state
* @prev_dpll_state: last dpll sync state
@@ -55,7 +58,8 @@ struct ice_dpll {
u8 prev_input_idx;
u8 ref_state;
u8 eec_mode;
- s64 phase_shift;
+ s64 phase_offset;
+ s64 prev_phase_offset;
u8 *input_prio;
enum dpll_lock_status dpll_state;
enum dpll_lock_status prev_dpll_state;
@@ -78,6 +82,8 @@ struct ice_dpll {
* @cgu_state_acq_err_num: number of errors returned during periodic work
* @base_rclk_idx: idx of first pin used for clock revocery pins
* @clock_id: clock_id of dplls
+ * @input_phase_adj_max: max phase adjust value for an input pins
+ * @output_phase_adj_max: max phase adjust value for an output pins
*/
struct ice_dplls {
struct kthread_worker *kworker;
--
2.38.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 4/4] ice: dpll: implement pin phase related callbacks
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
Implement new callback ops related to measurment and adjustment of
signal phase for pin-dpll in ice driver.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
2 files changed, 230 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 1faee9cb944d..6f7a2916f6c2 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -878,6 +878,203 @@ ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
return 0;
}
+/**
+ * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_pf *pf = p->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ *phase_adjust = p->phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
+/**
+ * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ * @type: type of a pin
+ *
+ * Helper for dpll subsystem callback. Handler for setting phase adjust value
+ * of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack,
+ enum ice_dpll_pin_type type)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+ u8 flag, flags_en = 0;
+ int ret;
+
+ mutex_lock(&pf->dplls.lock);
+ if (phase_adjust == p->phase_adjust) {
+ mutex_unlock(&pf->dplls.lock);
+ return 0;
+ }
+ switch (type) {
+ case ICE_DPLL_PIN_TYPE_INPUT:
+ flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
+ ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
+ 0, phase_adjust);
+ break;
+ case ICE_DPLL_PIN_TYPE_OUTPUT:
+ flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
+ ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
+ phase_adjust);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (!ret)
+ p->phase_adjust = phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+ if (ret)
+ NL_SET_ERR_MSG_FMT(extack,
+ "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
+ ret,
+ ice_aq_str(pf->hw.adminq.sq_last_status),
+ phase_adjust, p->idx, d->dpll_idx);
+
+ return ret;
+}
+
+/**
+ * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_INPUT);
+}
+
+/**
+ * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_OUTPUT);
+}
+
+#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
+#define ICE_DPLL_PHASE_OFFSET_FACTOR \
+ (DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
+/**
+ * ice_dpll_phase_offset_get - callback for get dpll phase shift value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase shift value between
+ * dpll's input and output.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset, struct netlink_ext_ack *extack)
+{
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ if (d->active_input == pin)
+ *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
+ else
+ *phase_offset = 0;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
/**
* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
* @pin: pointer to a pin
@@ -993,6 +1190,9 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
.prio_get = ice_dpll_input_prio_get,
.prio_set = ice_dpll_input_prio_set,
.direction_get = ice_dpll_input_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_input_phase_adjust_set,
+ .phase_offset_get = ice_dpll_phase_offset_get,
};
static const struct dpll_pin_ops ice_dpll_output_ops = {
@@ -1001,6 +1201,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
.state_on_dpll_get = ice_dpll_output_state_get,
.state_on_dpll_set = ice_dpll_output_state_set,
.direction_get = ice_dpll_output_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_output_phase_adjust_set,
};
static const struct dpll_device_ops ice_dpll_ops = {
@@ -1031,6 +1233,8 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
*/
static void ice_dpll_notify_changes(struct ice_dpll *d)
{
+ bool pin_notified = false;
+
if (d->prev_dpll_state != d->dpll_state) {
d->prev_dpll_state = d->dpll_state;
dpll_device_change_ntf(d->dpll);
@@ -1039,7 +1243,14 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
if (d->prev_input)
dpll_pin_change_ntf(d->prev_input);
d->prev_input = d->active_input;
- if (d->active_input)
+ if (d->active_input) {
+ dpll_pin_change_ntf(d->active_input);
+ pin_notified = true;
+ }
+ }
+ if (d->prev_phase_offset != d->phase_offset) {
+ d->prev_phase_offset = d->phase_offset;
+ if (!pin_notified && d->active_input)
dpll_pin_change_ntf(d->active_input);
}
}
@@ -1065,7 +1276,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
&d->input_idx, &d->ref_state, &d->eec_mode,
- &d->phase_shift, &d->dpll_state);
+ &d->phase_offset, &d->dpll_state);
dev_dbg(ice_pf_to_dev(pf),
"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
@@ -1656,6 +1867,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
return ret;
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
+ pins[i].prop.phase_range.min =
+ pf->dplls.input_phase_adj_max;
+ pins[i].prop.phase_range.max =
+ -pf->dplls.input_phase_adj_max;
+ } else {
+ pins[i].prop.phase_range.min =
+ pf->dplls.output_phase_adj_max,
+ pins[i].prop.phase_range.max =
+ -pf->dplls.output_phase_adj_max;
}
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethernet/intel/ice/ice_dpll.h
index 9c524c4bdfd7..5f23f82d31a9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.h
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.h
@@ -19,6 +19,7 @@
* @state: state of a pin
* @prop: pin properties
* @freq: current frequency of a pin
+ * @phase_adjust: current phase adjust value
*/
struct ice_dpll_pin {
struct dpll_pin *pin;
@@ -30,6 +31,7 @@ struct ice_dpll_pin {
u8 state[ICE_DPLL_RCLK_NUM_MAX];
struct dpll_pin_properties prop;
u32 freq;
+ s32 phase_adjust;
};
/** ice_dpll - store info required for DPLL control
@@ -40,7 +42,8 @@ struct ice_dpll_pin {
* @prev_input_idx: previously selected input index
* @ref_state: state of dpll reference signals
* @eec_mode: eec_mode dpll is configured for
- * @phase_shift: phase shift delay of a dpll
+ * @phase_offset: phase offset of active pin vs dpll signal
+ * @prev_phase_offset: previous phase offset of active pin vs dpll signal
* @input_prio: priorities of each input
* @dpll_state: current dpll sync state
* @prev_dpll_state: last dpll sync state
@@ -55,7 +58,8 @@ struct ice_dpll {
u8 prev_input_idx;
u8 ref_state;
u8 eec_mode;
- s64 phase_shift;
+ s64 phase_offset;
+ s64 prev_phase_offset;
u8 *input_prio;
enum dpll_lock_status dpll_state;
enum dpll_lock_status prev_dpll_state;
@@ -78,6 +82,8 @@ struct ice_dpll {
* @cgu_state_acq_err_num: number of errors returned during periodic work
* @base_rclk_idx: idx of first pin used for clock revocery pins
* @clock_id: clock_id of dplls
+ * @input_phase_adj_max: max phase adjust value for an input pins
+ * @output_phase_adj_max: max phase adjust value for an output pins
*/
struct ice_dplls {
struct kthread_worker *kworker;
--
2.38.1
_______________________________________________
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Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH net-next 4/4] ice: dpll: implement pin phase related callbacks
@ 2023-09-05 23:26 ` Arkadiusz Kubalewski
0 siblings, 0 replies; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-05 23:26 UTC (permalink / raw)
To: kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: linux-arm-kernel, poros, mschmidt, netdev, linux-clk, bvanassche,
intel-wired-lan, Arkadiusz Kubalewski
Implement new callback ops related to measurment and adjustment of
signal phase for pin-dpll in ice driver.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
2 files changed, 230 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 1faee9cb944d..6f7a2916f6c2 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -878,6 +878,203 @@ ice_dpll_output_direction(const struct dpll_pin *pin, void *pin_priv,
return 0;
}
+/**
+ * ice_dpll_pin_phase_adjust_get - callback for get pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase adjust value of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_pf *pf = p->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ *phase_adjust = p->phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
+/**
+ * ice_dpll_pin_phase_adjust_set - helper for setting a pin phase adjust value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ * @type: type of a pin
+ *
+ * Helper for dpll subsystem callback. Handler for setting phase adjust value
+ * of a pin.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_pin_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack,
+ enum ice_dpll_pin_type type)
+{
+ struct ice_dpll_pin *p = pin_priv;
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+ u8 flag, flags_en = 0;
+ int ret;
+
+ mutex_lock(&pf->dplls.lock);
+ if (phase_adjust == p->phase_adjust) {
+ mutex_unlock(&pf->dplls.lock);
+ return 0;
+ }
+ switch (type) {
+ case ICE_DPLL_PIN_TYPE_INPUT:
+ flag = ICE_AQC_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_ESYNC_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_ESYNC_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_IN_CFG_FLG2_INPUT_EN)
+ flags_en |= ICE_AQC_SET_CGU_IN_CFG_FLG2_INPUT_EN;
+ ret = ice_aq_set_input_pin_cfg(&pf->hw, p->idx, flag, flags_en,
+ 0, phase_adjust);
+ break;
+ case ICE_DPLL_PIN_TYPE_OUTPUT:
+ flag = ICE_AQC_SET_CGU_OUT_CFG_UPDATE_PHASE;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_OUT_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_OUT_EN;
+ if (p->flags[0] & ICE_AQC_GET_CGU_OUT_CFG_ESYNC_EN)
+ flag |= ICE_AQC_SET_CGU_OUT_CFG_ESYNC_EN;
+ ret = ice_aq_set_output_pin_cfg(&pf->hw, p->idx, flag, 0, 0,
+ phase_adjust);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (!ret)
+ p->phase_adjust = phase_adjust;
+ mutex_unlock(&pf->dplls.lock);
+ if (ret)
+ NL_SET_ERR_MSG_FMT(extack,
+ "err:%d %s failed to set pin phase_adjust:%d for pin:%u on dpll:%u\n",
+ ret,
+ ice_aq_str(pf->hw.adminq.sq_last_status),
+ phase_adjust, p->idx, d->dpll_idx);
+
+ return ret;
+}
+
+/**
+ * ice_dpll_input_phase_adjust_set - callback for set input pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on input
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_input_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_INPUT);
+}
+
+/**
+ * ice_dpll_output_phase_adjust_set - callback for set output pin phase adjust
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: phase_adjust to be set
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Wraps a handler for setting phase adjust on output
+ * pin.
+ *
+ * Context: Calls a function which acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_output_phase_adjust_set(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 phase_adjust,
+ struct netlink_ext_ack *extack)
+{
+ return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,
+ phase_adjust, extack,
+ ICE_DPLL_PIN_TYPE_OUTPUT);
+}
+
+#define ICE_DPLL_PHASE_OFFSET_DIVIDER 100
+#define ICE_DPLL_PHASE_OFFSET_FACTOR \
+ (DPLL_PHASE_OFFSET_DIVIDER / ICE_DPLL_PHASE_OFFSET_DIVIDER)
+/**
+ * ice_dpll_phase_offset_get - callback for get dpll phase shift value
+ * @pin: pointer to a pin
+ * @pin_priv: private data pointer passed on pin registration
+ * @dpll: registered dpll pointer
+ * @dpll_priv: private data pointer passed on dpll registration
+ * @phase_adjust: on success holds pin phase_adjust value
+ * @extack: error reporting
+ *
+ * Dpll subsystem callback. Handler for getting phase shift value between
+ * dpll's input and output.
+ *
+ * Context: Acquires pf->dplls.lock
+ * Return:
+ * * 0 - success
+ * * negative - error
+ */
+static int
+ice_dpll_phase_offset_get(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset, struct netlink_ext_ack *extack)
+{
+ struct ice_dpll *d = dpll_priv;
+ struct ice_pf *pf = d->pf;
+
+ mutex_lock(&pf->dplls.lock);
+ if (d->active_input == pin)
+ *phase_offset = d->phase_offset * ICE_DPLL_PHASE_OFFSET_FACTOR;
+ else
+ *phase_offset = 0;
+ mutex_unlock(&pf->dplls.lock);
+
+ return 0;
+}
+
/**
* ice_dpll_rclk_state_on_pin_set - set a state on rclk pin
* @pin: pointer to a pin
@@ -993,6 +1190,9 @@ static const struct dpll_pin_ops ice_dpll_input_ops = {
.prio_get = ice_dpll_input_prio_get,
.prio_set = ice_dpll_input_prio_set,
.direction_get = ice_dpll_input_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_input_phase_adjust_set,
+ .phase_offset_get = ice_dpll_phase_offset_get,
};
static const struct dpll_pin_ops ice_dpll_output_ops = {
@@ -1001,6 +1201,8 @@ static const struct dpll_pin_ops ice_dpll_output_ops = {
.state_on_dpll_get = ice_dpll_output_state_get,
.state_on_dpll_set = ice_dpll_output_state_set,
.direction_get = ice_dpll_output_direction,
+ .phase_adjust_get = ice_dpll_pin_phase_adjust_get,
+ .phase_adjust_set = ice_dpll_output_phase_adjust_set,
};
static const struct dpll_device_ops ice_dpll_ops = {
@@ -1031,6 +1233,8 @@ static u64 ice_generate_clock_id(struct ice_pf *pf)
*/
static void ice_dpll_notify_changes(struct ice_dpll *d)
{
+ bool pin_notified = false;
+
if (d->prev_dpll_state != d->dpll_state) {
d->prev_dpll_state = d->dpll_state;
dpll_device_change_ntf(d->dpll);
@@ -1039,7 +1243,14 @@ static void ice_dpll_notify_changes(struct ice_dpll *d)
if (d->prev_input)
dpll_pin_change_ntf(d->prev_input);
d->prev_input = d->active_input;
- if (d->active_input)
+ if (d->active_input) {
+ dpll_pin_change_ntf(d->active_input);
+ pin_notified = true;
+ }
+ }
+ if (d->prev_phase_offset != d->phase_offset) {
+ d->prev_phase_offset = d->phase_offset;
+ if (!pin_notified && d->active_input)
dpll_pin_change_ntf(d->active_input);
}
}
@@ -1065,7 +1276,7 @@ ice_dpll_update_state(struct ice_pf *pf, struct ice_dpll *d, bool init)
ret = ice_get_cgu_state(&pf->hw, d->dpll_idx, d->prev_dpll_state,
&d->input_idx, &d->ref_state, &d->eec_mode,
- &d->phase_shift, &d->dpll_state);
+ &d->phase_offset, &d->dpll_state);
dev_dbg(ice_pf_to_dev(pf),
"update dpll=%d, prev_src_idx:%u, src_idx:%u, state:%d, prev:%d mode:%d\n",
@@ -1656,6 +1867,15 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
return ret;
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
+ pins[i].prop.phase_range.min =
+ pf->dplls.input_phase_adj_max;
+ pins[i].prop.phase_range.max =
+ -pf->dplls.input_phase_adj_max;
+ } else {
+ pins[i].prop.phase_range.min =
+ pf->dplls.output_phase_adj_max,
+ pins[i].prop.phase_range.max =
+ -pf->dplls.output_phase_adj_max;
}
pins[i].prop.capabilities |=
DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.h b/drivers/net/ethernet/intel/ice/ice_dpll.h
index 9c524c4bdfd7..5f23f82d31a9 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.h
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.h
@@ -19,6 +19,7 @@
* @state: state of a pin
* @prop: pin properties
* @freq: current frequency of a pin
+ * @phase_adjust: current phase adjust value
*/
struct ice_dpll_pin {
struct dpll_pin *pin;
@@ -30,6 +31,7 @@ struct ice_dpll_pin {
u8 state[ICE_DPLL_RCLK_NUM_MAX];
struct dpll_pin_properties prop;
u32 freq;
+ s32 phase_adjust;
};
/** ice_dpll - store info required for DPLL control
@@ -40,7 +42,8 @@ struct ice_dpll_pin {
* @prev_input_idx: previously selected input index
* @ref_state: state of dpll reference signals
* @eec_mode: eec_mode dpll is configured for
- * @phase_shift: phase shift delay of a dpll
+ * @phase_offset: phase offset of active pin vs dpll signal
+ * @prev_phase_offset: previous phase offset of active pin vs dpll signal
* @input_prio: priorities of each input
* @dpll_state: current dpll sync state
* @prev_dpll_state: last dpll sync state
@@ -55,7 +58,8 @@ struct ice_dpll {
u8 prev_input_idx;
u8 ref_state;
u8 eec_mode;
- s64 phase_shift;
+ s64 phase_offset;
+ s64 prev_phase_offset;
u8 *input_prio;
enum dpll_lock_status dpll_state;
enum dpll_lock_status prev_dpll_state;
@@ -78,6 +82,8 @@ struct ice_dpll {
* @cgu_state_acq_err_num: number of errors returned during periodic work
* @base_rclk_idx: idx of first pin used for clock revocery pins
* @clock_id: clock_id of dplls
+ * @input_phase_adj_max: max phase adjust value for an input pins
+ * @output_phase_adj_max: max phase adjust value for an output pins
*/
struct ice_dplls {
struct kthread_worker *kworker;
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-06 8:02 ` Drewek, Wojciech
-1 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 8:02 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Arkadiusz Kubalewski
> Sent: Wednesday, September 6, 2023 1:26 AM
> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> pabeni@redhat.com; vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support
> for pin-dpll signal phase offset/adjust
>
> Add callback ops for pin-dpll phase measurment.
> Add callback for pin signal phase adjustment.
> Add min and max phase adjustment values to pin proprties.
> Invoke callbacks in dpll_netlink.c when filling the pin details to
> provide user with phase related attribute values.
>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> ---
> drivers/dpll/dpll_netlink.c | 99
> ++++++++++++++++++++++++++++++++++++-
> include/linux/dpll.h | 18 +++++++
> 2 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> index 764437a0661b..548517d9ca4c 100644
> --- a/drivers/dpll/dpll_netlink.c
> +++ b/drivers/dpll/dpll_netlink.c
> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> struct dpll_pin *pin,
> return 0;
> }
>
> +static int
> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s32 phase_adjust;
> + int ret;
> +
> + if (!ops->phase_adjust_get)
> + return 0;
Why 0 is returned here? If it's intended, I would put a comment stating why.
Same thing in dpll_msg_add_phase_offset.
> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll),
> + &phase_adjust, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> +static int
> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s64 phase_offset;
> + int ret;
> +
> + if (!ops->phase_offset_get)
> + return 0;
> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), &phase_offset,
> + extack);
> + if (ret)
> + return ret;
> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> sizeof(phase_offset),
> + &phase_offset, DPLL_A_PIN_PAD))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> static int
> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (ret)
> goto nest_cancel;
> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> + if (ret)
> + goto nest_cancel;
> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> if (ret)
> goto nest_cancel;
> nla_nest_end(msg, attr);
> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> return -EMSGSIZE;
> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> + prop->phase_range.min))
> + return -EMSGSIZE;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> + prop->phase_range.max))
> + return -EMSGSIZE;
> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> if (ret)
> return ret;
> if (xa_empty(&pin->parent_refs))
> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
> sk_buff *msg,
> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> return -EMSGSIZE;
>
> - return ret;
> + return 0;
> }
>
> static int
> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> dpll_device *dpll,
> return 0;
> }
>
> +static int
> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
> + struct netlink_ext_ack *extack)
> +{
> + struct dpll_pin_ref *ref;
> + unsigned long i;
> + s32 phase_adj;
> + int ret;
> +
> + phase_adj = nla_get_s32(phase_adj_attr);
> + if (phase_adj > pin->prop->phase_range.max ||
> + phase_adj < pin->prop->phase_range.min) {
> + NL_SET_ERR_MSG(extack, "phase adjust value not
> supported");
> + return -EINVAL;
> + }
> + xa_for_each(&pin->dpll_refs, i, ref) {
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> +
> + if (!ops->phase_adjust_set)
> + return -EOPNOTSUPP;
> + ret = ops->phase_adjust_set(pin,
> + dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), phase_adj,
> + extack);
> + if (ret)
> + return ret;
> + }
> + __dpll_pin_change_ntf(pin);
> +
> + return 0;
> +}
> +
> static int
> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
> struct netlink_ext_ack *extack)
> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct
> genl_info *info)
> if (ret)
> return ret;
> break;
> + case DPLL_A_PIN_PHASE_ADJUST:
> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> + if (ret)
> + return ret;
> + break;
> case DPLL_A_PIN_PARENT_DEVICE:
> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> if (ret)
> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> index bbc480cd2932..578fc5fa3750 100644
> --- a/include/linux/dpll.h
> +++ b/include/linux/dpll.h
> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> const struct dpll_device *dpll, void *dpll_priv,
> const u32 prio, struct netlink_ext_ack *extack);
> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s64 *phase_offset,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s32 *phase_adjust,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + const s32 phase_adjust,
> + struct netlink_ext_ack *extack);
> };
>
> struct dpll_pin_frequency {
> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> #define DPLL_PIN_FREQUENCY_DCF77 \
> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>
> +struct dpll_pin_phase_adjust_range {
> + s32 min;
> + s32 max;
> +};
> +
> struct dpll_pin_properties {
> const char *board_label;
> const char *panel_label;
> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> unsigned long capabilities;
> u32 freq_supported_num;
> struct dpll_pin_frequency *freq_supported;
> + struct dpll_pin_phase_adjust_range phase_range;
> };
>
> #if IS_ENABLED(CONFIG_DPLL)
> --
> 2.38.1
>
> _______________________________________________
> Intel-wired-lan mailing list
> Intel-wired-lan@osuosl.org
> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 8:02 ` Drewek, Wojciech
0 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 8:02 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Arkadiusz Kubalewski
> Sent: Wednesday, September 6, 2023 1:26 AM
> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> pabeni@redhat.com; vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support
> for pin-dpll signal phase offset/adjust
>
> Add callback ops for pin-dpll phase measurment.
> Add callback for pin signal phase adjustment.
> Add min and max phase adjustment values to pin proprties.
> Invoke callbacks in dpll_netlink.c when filling the pin details to
> provide user with phase related attribute values.
>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> ---
> drivers/dpll/dpll_netlink.c | 99
> ++++++++++++++++++++++++++++++++++++-
> include/linux/dpll.h | 18 +++++++
> 2 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> index 764437a0661b..548517d9ca4c 100644
> --- a/drivers/dpll/dpll_netlink.c
> +++ b/drivers/dpll/dpll_netlink.c
> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> struct dpll_pin *pin,
> return 0;
> }
>
> +static int
> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s32 phase_adjust;
> + int ret;
> +
> + if (!ops->phase_adjust_get)
> + return 0;
Why 0 is returned here? If it's intended, I would put a comment stating why.
Same thing in dpll_msg_add_phase_offset.
> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll),
> + &phase_adjust, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> +static int
> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s64 phase_offset;
> + int ret;
> +
> + if (!ops->phase_offset_get)
> + return 0;
> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), &phase_offset,
> + extack);
> + if (ret)
> + return ret;
> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> sizeof(phase_offset),
> + &phase_offset, DPLL_A_PIN_PAD))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> static int
> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (ret)
> goto nest_cancel;
> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> + if (ret)
> + goto nest_cancel;
> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> if (ret)
> goto nest_cancel;
> nla_nest_end(msg, attr);
> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> return -EMSGSIZE;
> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> + prop->phase_range.min))
> + return -EMSGSIZE;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> + prop->phase_range.max))
> + return -EMSGSIZE;
> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> if (ret)
> return ret;
> if (xa_empty(&pin->parent_refs))
> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
> sk_buff *msg,
> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> return -EMSGSIZE;
>
> - return ret;
> + return 0;
> }
>
> static int
> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> dpll_device *dpll,
> return 0;
> }
>
> +static int
> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
> + struct netlink_ext_ack *extack)
> +{
> + struct dpll_pin_ref *ref;
> + unsigned long i;
> + s32 phase_adj;
> + int ret;
> +
> + phase_adj = nla_get_s32(phase_adj_attr);
> + if (phase_adj > pin->prop->phase_range.max ||
> + phase_adj < pin->prop->phase_range.min) {
> + NL_SET_ERR_MSG(extack, "phase adjust value not
> supported");
> + return -EINVAL;
> + }
> + xa_for_each(&pin->dpll_refs, i, ref) {
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> +
> + if (!ops->phase_adjust_set)
> + return -EOPNOTSUPP;
> + ret = ops->phase_adjust_set(pin,
> + dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), phase_adj,
> + extack);
> + if (ret)
> + return ret;
> + }
> + __dpll_pin_change_ntf(pin);
> +
> + return 0;
> +}
> +
> static int
> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
> struct netlink_ext_ack *extack)
> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct
> genl_info *info)
> if (ret)
> return ret;
> break;
> + case DPLL_A_PIN_PHASE_ADJUST:
> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> + if (ret)
> + return ret;
> + break;
> case DPLL_A_PIN_PARENT_DEVICE:
> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> if (ret)
> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> index bbc480cd2932..578fc5fa3750 100644
> --- a/include/linux/dpll.h
> +++ b/include/linux/dpll.h
> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> const struct dpll_device *dpll, void *dpll_priv,
> const u32 prio, struct netlink_ext_ack *extack);
> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s64 *phase_offset,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s32 *phase_adjust,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + const s32 phase_adjust,
> + struct netlink_ext_ack *extack);
> };
>
> struct dpll_pin_frequency {
> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> #define DPLL_PIN_FREQUENCY_DCF77 \
> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>
> +struct dpll_pin_phase_adjust_range {
> + s32 min;
> + s32 max;
> +};
> +
> struct dpll_pin_properties {
> const char *board_label;
> const char *panel_label;
> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> unsigned long capabilities;
> u32 freq_supported_num;
> struct dpll_pin_frequency *freq_supported;
> + struct dpll_pin_phase_adjust_range phase_range;
> };
>
> #if IS_ENABLED(CONFIG_DPLL)
> --
> 2.38.1
>
> _______________________________________________
> Intel-wired-lan mailing list
> Intel-wired-lan@osuosl.org
> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 8:02 ` Drewek, Wojciech
0 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 8:02 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: netdev, intel-wired-lan, bvanassche, linux-arm-kernel, linux-clk
> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> Arkadiusz Kubalewski
> Sent: Wednesday, September 6, 2023 1:26 AM
> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> pabeni@redhat.com; vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support
> for pin-dpll signal phase offset/adjust
>
> Add callback ops for pin-dpll phase measurment.
> Add callback for pin signal phase adjustment.
> Add min and max phase adjustment values to pin proprties.
> Invoke callbacks in dpll_netlink.c when filling the pin details to
> provide user with phase related attribute values.
>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> ---
> drivers/dpll/dpll_netlink.c | 99
> ++++++++++++++++++++++++++++++++++++-
> include/linux/dpll.h | 18 +++++++
> 2 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> index 764437a0661b..548517d9ca4c 100644
> --- a/drivers/dpll/dpll_netlink.c
> +++ b/drivers/dpll/dpll_netlink.c
> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> struct dpll_pin *pin,
> return 0;
> }
>
> +static int
> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s32 phase_adjust;
> + int ret;
> +
> + if (!ops->phase_adjust_get)
> + return 0;
Why 0 is returned here? If it's intended, I would put a comment stating why.
Same thing in dpll_msg_add_phase_offset.
> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll),
> + &phase_adjust, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> +static int
> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> + struct dpll_pin_ref *ref,
> + struct netlink_ext_ack *extack)
> +{
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> + s64 phase_offset;
> + int ret;
> +
> + if (!ops->phase_offset_get)
> + return 0;
> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), &phase_offset,
> + extack);
> + if (ret)
> + return ret;
> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> sizeof(phase_offset),
> + &phase_offset, DPLL_A_PIN_PAD))
> + return -EMSGSIZE;
> +
> + return 0;
> +}
> +
> static int
> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (ret)
> goto nest_cancel;
> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> + if (ret)
> + goto nest_cancel;
> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> if (ret)
> goto nest_cancel;
> nla_nest_end(msg, attr);
> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
> dpll_pin *pin,
> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> return -EMSGSIZE;
> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> + if (ret)
> + return ret;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> + prop->phase_range.min))
> + return -EMSGSIZE;
> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> + prop->phase_range.max))
> + return -EMSGSIZE;
> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> if (ret)
> return ret;
> if (xa_empty(&pin->parent_refs))
> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
> sk_buff *msg,
> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> return -EMSGSIZE;
>
> - return ret;
> + return 0;
> }
>
> static int
> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> dpll_device *dpll,
> return 0;
> }
>
> +static int
> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
> + struct netlink_ext_ack *extack)
> +{
> + struct dpll_pin_ref *ref;
> + unsigned long i;
> + s32 phase_adj;
> + int ret;
> +
> + phase_adj = nla_get_s32(phase_adj_attr);
> + if (phase_adj > pin->prop->phase_range.max ||
> + phase_adj < pin->prop->phase_range.min) {
> + NL_SET_ERR_MSG(extack, "phase adjust value not
> supported");
> + return -EINVAL;
> + }
> + xa_for_each(&pin->dpll_refs, i, ref) {
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> +
> + if (!ops->phase_adjust_set)
> + return -EOPNOTSUPP;
> + ret = ops->phase_adjust_set(pin,
> + dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), phase_adj,
> + extack);
> + if (ret)
> + return ret;
> + }
> + __dpll_pin_change_ntf(pin);
> +
> + return 0;
> +}
> +
> static int
> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
> struct netlink_ext_ack *extack)
> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct
> genl_info *info)
> if (ret)
> return ret;
> break;
> + case DPLL_A_PIN_PHASE_ADJUST:
> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> + if (ret)
> + return ret;
> + break;
> case DPLL_A_PIN_PARENT_DEVICE:
> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> if (ret)
> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> index bbc480cd2932..578fc5fa3750 100644
> --- a/include/linux/dpll.h
> +++ b/include/linux/dpll.h
> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> const struct dpll_device *dpll, void *dpll_priv,
> const u32 prio, struct netlink_ext_ack *extack);
> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s64 *phase_offset,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + s32 *phase_adjust,
> + struct netlink_ext_ack *extack);
> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> + const struct dpll_device *dpll, void *dpll_priv,
> + const s32 phase_adjust,
> + struct netlink_ext_ack *extack);
> };
>
> struct dpll_pin_frequency {
> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> #define DPLL_PIN_FREQUENCY_DCF77 \
> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>
> +struct dpll_pin_phase_adjust_range {
> + s32 min;
> + s32 max;
> +};
> +
> struct dpll_pin_properties {
> const char *board_label;
> const char *panel_label;
> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> unsigned long capabilities;
> u32 freq_supported_num;
> struct dpll_pin_frequency *freq_supported;
> + struct dpll_pin_phase_adjust_range phase_range;
> };
>
> #if IS_ENABLED(CONFIG_DPLL)
> --
> 2.38.1
>
> _______________________________________________
> Intel-wired-lan mailing list
> Intel-wired-lan@osuosl.org
> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH net-next 0/4] dpll: add phase offset and phase adjust
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
(?)
@ 2023-09-06 8:37 ` Jiri Pirko
-1 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-09-06 8:37 UTC (permalink / raw)
To: Arkadiusz Kubalewski
Cc: kuba, jonathan.lemon, pabeni, vadim.fedorenko, linux-arm-kernel,
poros, mschmidt, netdev, linux-clk, bvanassche, intel-wired-lan
Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>This RFC is to start discussion over extending dpll interface
>with possibility to:
>- read a phase offset between signals on pin and dpll,
>- adjust a phase of pin's signal.
1) RFC patches should be marked as such
2) I suggest to postpone this after the first dpll patchset is merged
>
>The RFC is based on latest version of dpll interface submitted for
>net-next [1].
>
>[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
>
>Arkadiusz Kubalewski (4):
> dpll: docs: add support for pin signal phase offset/adjust
> dpll: spec: add support for pin-dpll signal phase offset/adjust
> dpll: netlink/core: add support for pin-dpll signal phase
> offset/adjust
> ice: dpll: implement phase related callbacks
>
> Documentation/driver-api/dpll.rst | 53 ++++-
> Documentation/netlink/specs/dpll.yaml | 33 +++-
> drivers/dpll/dpll_netlink.c | 99 +++++++++-
> drivers/dpll/dpll_nl.c | 8 +-
> drivers/dpll/dpll_nl.h | 2 +-
> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
> include/linux/dpll.h | 18 ++
> include/uapi/linux/dpll.h | 8 +-
> 9 files changed, 443 insertions(+), 12 deletions(-)
>
>--
>2.38.1
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-06 8:37 ` Jiri Pirko
0 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-09-06 8:37 UTC (permalink / raw)
To: Arkadiusz Kubalewski
Cc: vadim.fedorenko, bvanassche, netdev, intel-wired-lan,
jonathan.lemon, kuba, pabeni, linux-clk, linux-arm-kernel
Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>This RFC is to start discussion over extending dpll interface
>with possibility to:
>- read a phase offset between signals on pin and dpll,
>- adjust a phase of pin's signal.
1) RFC patches should be marked as such
2) I suggest to postpone this after the first dpll patchset is merged
>
>The RFC is based on latest version of dpll interface submitted for
>net-next [1].
>
>[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
>
>Arkadiusz Kubalewski (4):
> dpll: docs: add support for pin signal phase offset/adjust
> dpll: spec: add support for pin-dpll signal phase offset/adjust
> dpll: netlink/core: add support for pin-dpll signal phase
> offset/adjust
> ice: dpll: implement phase related callbacks
>
> Documentation/driver-api/dpll.rst | 53 ++++-
> Documentation/netlink/specs/dpll.yaml | 33 +++-
> drivers/dpll/dpll_netlink.c | 99 +++++++++-
> drivers/dpll/dpll_nl.c | 8 +-
> drivers/dpll/dpll_nl.h | 2 +-
> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
> include/linux/dpll.h | 18 ++
> include/uapi/linux/dpll.h | 8 +-
> 9 files changed, 443 insertions(+), 12 deletions(-)
>
>--
>2.38.1
>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-06 8:37 ` Jiri Pirko
0 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-09-06 8:37 UTC (permalink / raw)
To: Arkadiusz Kubalewski
Cc: kuba, jonathan.lemon, pabeni, vadim.fedorenko, linux-arm-kernel,
poros, mschmidt, netdev, linux-clk, bvanassche, intel-wired-lan
Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>This RFC is to start discussion over extending dpll interface
>with possibility to:
>- read a phase offset between signals on pin and dpll,
>- adjust a phase of pin's signal.
1) RFC patches should be marked as such
2) I suggest to postpone this after the first dpll patchset is merged
>
>The RFC is based on latest version of dpll interface submitted for
>net-next [1].
>
>[1] https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@linux.dev/
>
>Arkadiusz Kubalewski (4):
> dpll: docs: add support for pin signal phase offset/adjust
> dpll: spec: add support for pin-dpll signal phase offset/adjust
> dpll: netlink/core: add support for pin-dpll signal phase
> offset/adjust
> ice: dpll: implement phase related callbacks
>
> Documentation/driver-api/dpll.rst | 53 ++++-
> Documentation/netlink/specs/dpll.yaml | 33 +++-
> drivers/dpll/dpll_netlink.c | 99 +++++++++-
> drivers/dpll/dpll_nl.c | 8 +-
> drivers/dpll/dpll_nl.h | 2 +-
> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
> include/linux/dpll.h | 18 ++
> include/uapi/linux/dpll.h | 8 +-
> 9 files changed, 443 insertions(+), 12 deletions(-)
>
>--
>2.38.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-06 8:02 ` Drewek, Wojciech
(?)
@ 2023-09-06 10:26 ` Kubalewski, Arkadiusz
-1 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:26 UTC (permalink / raw)
To: Drewek, Wojciech, kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
>From: Drewek, Wojciech <wojciech.drewek@intel.com>
>Sent: Wednesday, September 6, 2023 10:02 AM
>
>> -----Original Message-----
>> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>> Arkadiusz Kubalewski
>> Sent: Wednesday, September 6, 2023 1:26 AM
>> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
>> pabeni@redhat.com; vadim.fedorenko@linux.dev
>> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
>> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
>> support
>> for pin-dpll signal phase offset/adjust
>>
>> Add callback ops for pin-dpll phase measurment.
>> Add callback for pin signal phase adjustment.
>> Add min and max phase adjustment values to pin proprties.
>> Invoke callbacks in dpll_netlink.c when filling the pin details to
>> provide user with phase related attribute values.
>>
>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>> ---
>> drivers/dpll/dpll_netlink.c | 99
>> ++++++++++++++++++++++++++++++++++++-
>> include/linux/dpll.h | 18 +++++++
>> 2 files changed, 116 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
>> index 764437a0661b..548517d9ca4c 100644
>> --- a/drivers/dpll/dpll_netlink.c
>> +++ b/drivers/dpll/dpll_netlink.c
>> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
>> struct dpll_pin *pin,
>> return 0;
>> }
>>
>> +static int
>> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s32 phase_adjust;
>> + int ret;
>> +
>> + if (!ops->phase_adjust_get)
>> + return 0;
>
>Why 0 is returned here? If it's intended, I would put a comment stating
>why.
>Same thing in dpll_msg_add_phase_offset.
The callback is optional, any driver implementing dpll interface doesn't
have to implement this callback and it must not be seen as an error.
Callback that are required are pointed out in documentation:
Documentation/driver-api/dpll.rst
All the optional callbacks are returning this way, I don't see a point
in adding extra comment here.
Thank you!
Arkadiusz
>
>> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll),
>> + &phase_adjust, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> +static int
>> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s64 phase_offset;
>> + int ret;
>> +
>> + if (!ops->phase_offset_get)
>> + return 0;
>> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), &phase_offset,
>> + extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
>> sizeof(phase_offset),
>> + &phase_offset, DPLL_A_PIN_PAD))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
>> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
>> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (ret)
>> goto nest_cancel;
>> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
>> + if (ret)
>> + goto nest_cancel;
>> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
>> if (ret)
>> goto nest_cancel;
>> nla_nest_end(msg, attr);
>> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
>> return -EMSGSIZE;
>> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
>> + prop->phase_range.min))
>> + return -EMSGSIZE;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
>> + prop->phase_range.max))
>> + return -EMSGSIZE;
>> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
>> if (ret)
>> return ret;
>> if (xa_empty(&pin->parent_refs))
>> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
>> sk_buff *msg,
>> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
>> return -EMSGSIZE;
>>
>> - return ret;
>> + return 0;
>> }
>>
>> static int
>> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
>> dpll_device *dpll,
>> return 0;
>> }
>>
>> +static int
>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>> *phase_adj_attr,
>> + struct netlink_ext_ack *extack)
>> +{
>> + struct dpll_pin_ref *ref;
>> + unsigned long i;
>> + s32 phase_adj;
>> + int ret;
>> +
>> + phase_adj = nla_get_s32(phase_adj_attr);
>> + if (phase_adj > pin->prop->phase_range.max ||
>> + phase_adj < pin->prop->phase_range.min) {
>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>> supported");
>> + return -EINVAL;
>> + }
>> + xa_for_each(&pin->dpll_refs, i, ref) {
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> +
>> + if (!ops->phase_adjust_set)
>> + return -EOPNOTSUPP;
>> + ret = ops->phase_adjust_set(pin,
>> + dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), phase_adj,
>> + extack);
>> + if (ret)
>> + return ret;
>> + }
>> + __dpll_pin_change_ntf(pin);
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
>> *parent_nest,
>> struct netlink_ext_ack *extack)
>> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
>> struct
>> genl_info *info)
>> if (ret)
>> return ret;
>> break;
>> + case DPLL_A_PIN_PHASE_ADJUST:
>> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
>> + if (ret)
>> + return ret;
>> + break;
>> case DPLL_A_PIN_PARENT_DEVICE:
>> ret = dpll_pin_parent_device_set(pin, a, info->extack);
>> if (ret)
>> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
>> index bbc480cd2932..578fc5fa3750 100644
>> --- a/include/linux/dpll.h
>> +++ b/include/linux/dpll.h
>> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
>> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
>> const struct dpll_device *dpll, void *dpll_priv,
>> const u32 prio, struct netlink_ext_ack *extack);
>> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s64 *phase_offset,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s32 *phase_adjust,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + const s32 phase_adjust,
>> + struct netlink_ext_ack *extack);
>> };
>>
>> struct dpll_pin_frequency {
>> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
>> #define DPLL_PIN_FREQUENCY_DCF77 \
>> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>>
>> +struct dpll_pin_phase_adjust_range {
>> + s32 min;
>> + s32 max;
>> +};
>> +
>> struct dpll_pin_properties {
>> const char *board_label;
>> const char *panel_label;
>> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
>> unsigned long capabilities;
>> u32 freq_supported_num;
>> struct dpll_pin_frequency *freq_supported;
>> + struct dpll_pin_phase_adjust_range phase_range;
>> };
>>
>> #if IS_ENABLED(CONFIG_DPLL)
>> --
>> 2.38.1
>>
>> _______________________________________________
>> Intel-wired-lan mailing list
>> Intel-wired-lan@osuosl.org
>> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 10:26 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:26 UTC (permalink / raw)
To: Drewek, Wojciech, kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
>From: Drewek, Wojciech <wojciech.drewek@intel.com>
>Sent: Wednesday, September 6, 2023 10:02 AM
>
>> -----Original Message-----
>> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>> Arkadiusz Kubalewski
>> Sent: Wednesday, September 6, 2023 1:26 AM
>> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
>> pabeni@redhat.com; vadim.fedorenko@linux.dev
>> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
>> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
>> support
>> for pin-dpll signal phase offset/adjust
>>
>> Add callback ops for pin-dpll phase measurment.
>> Add callback for pin signal phase adjustment.
>> Add min and max phase adjustment values to pin proprties.
>> Invoke callbacks in dpll_netlink.c when filling the pin details to
>> provide user with phase related attribute values.
>>
>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>> ---
>> drivers/dpll/dpll_netlink.c | 99
>> ++++++++++++++++++++++++++++++++++++-
>> include/linux/dpll.h | 18 +++++++
>> 2 files changed, 116 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
>> index 764437a0661b..548517d9ca4c 100644
>> --- a/drivers/dpll/dpll_netlink.c
>> +++ b/drivers/dpll/dpll_netlink.c
>> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
>> struct dpll_pin *pin,
>> return 0;
>> }
>>
>> +static int
>> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s32 phase_adjust;
>> + int ret;
>> +
>> + if (!ops->phase_adjust_get)
>> + return 0;
>
>Why 0 is returned here? If it's intended, I would put a comment stating
>why.
>Same thing in dpll_msg_add_phase_offset.
The callback is optional, any driver implementing dpll interface doesn't
have to implement this callback and it must not be seen as an error.
Callback that are required are pointed out in documentation:
Documentation/driver-api/dpll.rst
All the optional callbacks are returning this way, I don't see a point
in adding extra comment here.
Thank you!
Arkadiusz
>
>> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll),
>> + &phase_adjust, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> +static int
>> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s64 phase_offset;
>> + int ret;
>> +
>> + if (!ops->phase_offset_get)
>> + return 0;
>> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), &phase_offset,
>> + extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
>> sizeof(phase_offset),
>> + &phase_offset, DPLL_A_PIN_PAD))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
>> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
>> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (ret)
>> goto nest_cancel;
>> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
>> + if (ret)
>> + goto nest_cancel;
>> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
>> if (ret)
>> goto nest_cancel;
>> nla_nest_end(msg, attr);
>> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
>> return -EMSGSIZE;
>> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
>> + prop->phase_range.min))
>> + return -EMSGSIZE;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
>> + prop->phase_range.max))
>> + return -EMSGSIZE;
>> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
>> if (ret)
>> return ret;
>> if (xa_empty(&pin->parent_refs))
>> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
>> sk_buff *msg,
>> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
>> return -EMSGSIZE;
>>
>> - return ret;
>> + return 0;
>> }
>>
>> static int
>> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
>> dpll_device *dpll,
>> return 0;
>> }
>>
>> +static int
>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>> *phase_adj_attr,
>> + struct netlink_ext_ack *extack)
>> +{
>> + struct dpll_pin_ref *ref;
>> + unsigned long i;
>> + s32 phase_adj;
>> + int ret;
>> +
>> + phase_adj = nla_get_s32(phase_adj_attr);
>> + if (phase_adj > pin->prop->phase_range.max ||
>> + phase_adj < pin->prop->phase_range.min) {
>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>> supported");
>> + return -EINVAL;
>> + }
>> + xa_for_each(&pin->dpll_refs, i, ref) {
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> +
>> + if (!ops->phase_adjust_set)
>> + return -EOPNOTSUPP;
>> + ret = ops->phase_adjust_set(pin,
>> + dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), phase_adj,
>> + extack);
>> + if (ret)
>> + return ret;
>> + }
>> + __dpll_pin_change_ntf(pin);
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
>> *parent_nest,
>> struct netlink_ext_ack *extack)
>> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
>> struct
>> genl_info *info)
>> if (ret)
>> return ret;
>> break;
>> + case DPLL_A_PIN_PHASE_ADJUST:
>> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
>> + if (ret)
>> + return ret;
>> + break;
>> case DPLL_A_PIN_PARENT_DEVICE:
>> ret = dpll_pin_parent_device_set(pin, a, info->extack);
>> if (ret)
>> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
>> index bbc480cd2932..578fc5fa3750 100644
>> --- a/include/linux/dpll.h
>> +++ b/include/linux/dpll.h
>> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
>> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
>> const struct dpll_device *dpll, void *dpll_priv,
>> const u32 prio, struct netlink_ext_ack *extack);
>> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s64 *phase_offset,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s32 *phase_adjust,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + const s32 phase_adjust,
>> + struct netlink_ext_ack *extack);
>> };
>>
>> struct dpll_pin_frequency {
>> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
>> #define DPLL_PIN_FREQUENCY_DCF77 \
>> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>>
>> +struct dpll_pin_phase_adjust_range {
>> + s32 min;
>> + s32 max;
>> +};
>> +
>> struct dpll_pin_properties {
>> const char *board_label;
>> const char *panel_label;
>> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
>> unsigned long capabilities;
>> u32 freq_supported_num;
>> struct dpll_pin_frequency *freq_supported;
>> + struct dpll_pin_phase_adjust_range phase_range;
>> };
>>
>> #if IS_ENABLED(CONFIG_DPLL)
>> --
>> 2.38.1
>>
>> _______________________________________________
>> Intel-wired-lan mailing list
>> Intel-wired-lan@osuosl.org
>> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 10:26 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:26 UTC (permalink / raw)
To: Drewek, Wojciech, kuba, jiri, jonathan.lemon, pabeni, vadim.fedorenko
Cc: netdev, intel-wired-lan, bvanassche, linux-arm-kernel, linux-clk
>From: Drewek, Wojciech <wojciech.drewek@intel.com>
>Sent: Wednesday, September 6, 2023 10:02 AM
>
>> -----Original Message-----
>> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>> Arkadiusz Kubalewski
>> Sent: Wednesday, September 6, 2023 1:26 AM
>> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
>> pabeni@redhat.com; vadim.fedorenko@linux.dev
>> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
>> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
>> kernel@lists.infradead.org
>> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
>> support
>> for pin-dpll signal phase offset/adjust
>>
>> Add callback ops for pin-dpll phase measurment.
>> Add callback for pin signal phase adjustment.
>> Add min and max phase adjustment values to pin proprties.
>> Invoke callbacks in dpll_netlink.c when filling the pin details to
>> provide user with phase related attribute values.
>>
>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>> ---
>> drivers/dpll/dpll_netlink.c | 99
>> ++++++++++++++++++++++++++++++++++++-
>> include/linux/dpll.h | 18 +++++++
>> 2 files changed, 116 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
>> index 764437a0661b..548517d9ca4c 100644
>> --- a/drivers/dpll/dpll_netlink.c
>> +++ b/drivers/dpll/dpll_netlink.c
>> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
>> struct dpll_pin *pin,
>> return 0;
>> }
>>
>> +static int
>> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s32 phase_adjust;
>> + int ret;
>> +
>> + if (!ops->phase_adjust_get)
>> + return 0;
>
>Why 0 is returned here? If it's intended, I would put a comment stating
>why.
>Same thing in dpll_msg_add_phase_offset.
The callback is optional, any driver implementing dpll interface doesn't
have to implement this callback and it must not be seen as an error.
Callback that are required are pointed out in documentation:
Documentation/driver-api/dpll.rst
All the optional callbacks are returning this way, I don't see a point
in adding extra comment here.
Thank you!
Arkadiusz
>
>> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll),
>> + &phase_adjust, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> +static int
>> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
>> + struct dpll_pin_ref *ref,
>> + struct netlink_ext_ack *extack)
>> +{
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> + s64 phase_offset;
>> + int ret;
>> +
>> + if (!ops->phase_offset_get)
>> + return 0;
>> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), &phase_offset,
>> + extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
>> sizeof(phase_offset),
>> + &phase_offset, DPLL_A_PIN_PAD))
>> + return -EMSGSIZE;
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
>> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
>> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (ret)
>> goto nest_cancel;
>> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
>> + if (ret)
>> + goto nest_cancel;
>> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
>> if (ret)
>> goto nest_cancel;
>> nla_nest_end(msg, attr);
>> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct
>> dpll_pin *pin,
>> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
>> return -EMSGSIZE;
>> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
>> + if (ret)
>> + return ret;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
>> + prop->phase_range.min))
>> + return -EMSGSIZE;
>> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
>> + prop->phase_range.max))
>> + return -EMSGSIZE;
>> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
>> if (ret)
>> return ret;
>> if (xa_empty(&pin->parent_refs))
>> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct
>> sk_buff *msg,
>> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
>> return -EMSGSIZE;
>>
>> - return ret;
>> + return 0;
>> }
>>
>> static int
>> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
>> dpll_device *dpll,
>> return 0;
>> }
>>
>> +static int
>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>> *phase_adj_attr,
>> + struct netlink_ext_ack *extack)
>> +{
>> + struct dpll_pin_ref *ref;
>> + unsigned long i;
>> + s32 phase_adj;
>> + int ret;
>> +
>> + phase_adj = nla_get_s32(phase_adj_attr);
>> + if (phase_adj > pin->prop->phase_range.max ||
>> + phase_adj < pin->prop->phase_range.min) {
>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>> supported");
>> + return -EINVAL;
>> + }
>> + xa_for_each(&pin->dpll_refs, i, ref) {
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> +
>> + if (!ops->phase_adjust_set)
>> + return -EOPNOTSUPP;
>> + ret = ops->phase_adjust_set(pin,
>> + dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), phase_adj,
>> + extack);
>> + if (ret)
>> + return ret;
>> + }
>> + __dpll_pin_change_ntf(pin);
>> +
>> + return 0;
>> +}
>> +
>> static int
>> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
>> *parent_nest,
>> struct netlink_ext_ack *extack)
>> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
>> struct
>> genl_info *info)
>> if (ret)
>> return ret;
>> break;
>> + case DPLL_A_PIN_PHASE_ADJUST:
>> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
>> + if (ret)
>> + return ret;
>> + break;
>> case DPLL_A_PIN_PARENT_DEVICE:
>> ret = dpll_pin_parent_device_set(pin, a, info->extack);
>> if (ret)
>> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
>> index bbc480cd2932..578fc5fa3750 100644
>> --- a/include/linux/dpll.h
>> +++ b/include/linux/dpll.h
>> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
>> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
>> const struct dpll_device *dpll, void *dpll_priv,
>> const u32 prio, struct netlink_ext_ack *extack);
>> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s64 *phase_offset,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + s32 *phase_adjust,
>> + struct netlink_ext_ack *extack);
>> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
>> + const struct dpll_device *dpll, void *dpll_priv,
>> + const s32 phase_adjust,
>> + struct netlink_ext_ack *extack);
>> };
>>
>> struct dpll_pin_frequency {
>> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
>> #define DPLL_PIN_FREQUENCY_DCF77 \
>> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
>>
>> +struct dpll_pin_phase_adjust_range {
>> + s32 min;
>> + s32 max;
>> +};
>> +
>> struct dpll_pin_properties {
>> const char *board_label;
>> const char *panel_label;
>> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
>> unsigned long capabilities;
>> u32 freq_supported_num;
>> struct dpll_pin_frequency *freq_supported;
>> + struct dpll_pin_phase_adjust_range phase_range;
>> };
>>
>> #if IS_ENABLED(CONFIG_DPLL)
>> --
>> 2.38.1
>>
>> _______________________________________________
>> Intel-wired-lan mailing list
>> Intel-wired-lan@osuosl.org
>> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH net-next 0/4] dpll: add phase offset and phase adjust
2023-09-06 8:37 ` [Intel-wired-lan] " Jiri Pirko
(?)
@ 2023-09-06 10:30 ` Kubalewski, Arkadiusz
-1 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:30 UTC (permalink / raw)
To: Jiri Pirko
Cc: kuba, jonathan.lemon, pabeni, vadim.fedorenko, linux-arm-kernel,
poros, mschmidt, netdev, linux-clk, bvanassche, intel-wired-lan
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Wednesday, September 6, 2023 10:38 AM
>
>Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>This RFC is to start discussion over extending dpll interface with
>>possibility to:
>>- read a phase offset between signals on pin and dpll,
>>- adjust a phase of pin's signal.
>
>1) RFC patches should be marked as such
That is true, sorry about that, will fix it if there would be v2.
>2) I suggest to postpone this after the first dpll patchset is merged
Well this is exactly only to start discussion, I will resubmit the patches
after the merge of dpll, although we can decide some details already.
Thank you!
Arkadiusz
>
>>
>>The RFC is based on latest version of dpll interface submitted for
>>net-next [1].
>>
>>[1]
>>https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@
>>linux.dev/
>>
>>Arkadiusz Kubalewski (4):
>> dpll: docs: add support for pin signal phase offset/adjust
>> dpll: spec: add support for pin-dpll signal phase offset/adjust
>> dpll: netlink/core: add support for pin-dpll signal phase
>> offset/adjust
>> ice: dpll: implement phase related callbacks
>>
>> Documentation/driver-api/dpll.rst | 53 ++++-
>> Documentation/netlink/specs/dpll.yaml | 33 +++-
>> drivers/dpll/dpll_netlink.c | 99 +++++++++-
>> drivers/dpll/dpll_nl.c | 8 +-
>> drivers/dpll/dpll_nl.h | 2 +-
>> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
>> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
>> include/linux/dpll.h | 18 ++
>> include/uapi/linux/dpll.h | 8 +-
>> 9 files changed, 443 insertions(+), 12 deletions(-)
>>
>>--
>>2.38.1
>>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-06 10:30 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:30 UTC (permalink / raw)
To: Jiri Pirko
Cc: vadim.fedorenko, bvanassche, netdev, intel-wired-lan,
jonathan.lemon, kuba, pabeni, linux-clk, linux-arm-kernel
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Wednesday, September 6, 2023 10:38 AM
>
>Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>This RFC is to start discussion over extending dpll interface with
>>possibility to:
>>- read a phase offset between signals on pin and dpll,
>>- adjust a phase of pin's signal.
>
>1) RFC patches should be marked as such
That is true, sorry about that, will fix it if there would be v2.
>2) I suggest to postpone this after the first dpll patchset is merged
Well this is exactly only to start discussion, I will resubmit the patches
after the merge of dpll, although we can decide some details already.
Thank you!
Arkadiusz
>
>>
>>The RFC is based on latest version of dpll interface submitted for
>>net-next [1].
>>
>>[1]
>>https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@
>>linux.dev/
>>
>>Arkadiusz Kubalewski (4):
>> dpll: docs: add support for pin signal phase offset/adjust
>> dpll: spec: add support for pin-dpll signal phase offset/adjust
>> dpll: netlink/core: add support for pin-dpll signal phase
>> offset/adjust
>> ice: dpll: implement phase related callbacks
>>
>> Documentation/driver-api/dpll.rst | 53 ++++-
>> Documentation/netlink/specs/dpll.yaml | 33 +++-
>> drivers/dpll/dpll_netlink.c | 99 +++++++++-
>> drivers/dpll/dpll_nl.c | 8 +-
>> drivers/dpll/dpll_nl.h | 2 +-
>> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
>> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
>> include/linux/dpll.h | 18 ++
>> include/uapi/linux/dpll.h | 8 +-
>> 9 files changed, 443 insertions(+), 12 deletions(-)
>>
>>--
>>2.38.1
>>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [PATCH net-next 0/4] dpll: add phase offset and phase adjust
@ 2023-09-06 10:30 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-09-06 10:30 UTC (permalink / raw)
To: Jiri Pirko
Cc: kuba, jonathan.lemon, pabeni, vadim.fedorenko, linux-arm-kernel,
poros, mschmidt, netdev, linux-clk, bvanassche, intel-wired-lan
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Wednesday, September 6, 2023 10:38 AM
>
>Wed, Sep 06, 2023 at 01:26:06AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>This RFC is to start discussion over extending dpll interface with
>>possibility to:
>>- read a phase offset between signals on pin and dpll,
>>- adjust a phase of pin's signal.
>
>1) RFC patches should be marked as such
That is true, sorry about that, will fix it if there would be v2.
>2) I suggest to postpone this after the first dpll patchset is merged
Well this is exactly only to start discussion, I will resubmit the patches
after the merge of dpll, although we can decide some details already.
Thank you!
Arkadiusz
>
>>
>>The RFC is based on latest version of dpll interface submitted for
>>net-next [1].
>>
>>[1]
>>https://lore.kernel.org/netdev/20230824213132.827338-1-vadim.fedorenko@
>>linux.dev/
>>
>>Arkadiusz Kubalewski (4):
>> dpll: docs: add support for pin signal phase offset/adjust
>> dpll: spec: add support for pin-dpll signal phase offset/adjust
>> dpll: netlink/core: add support for pin-dpll signal phase
>> offset/adjust
>> ice: dpll: implement phase related callbacks
>>
>> Documentation/driver-api/dpll.rst | 53 ++++-
>> Documentation/netlink/specs/dpll.yaml | 33 +++-
>> drivers/dpll/dpll_netlink.c | 99 +++++++++-
>> drivers/dpll/dpll_nl.c | 8 +-
>> drivers/dpll/dpll_nl.h | 2 +-
>> drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +++++++++++++++++++++-
>> drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
>> include/linux/dpll.h | 18 ++
>> include/uapi/linux/dpll.h | 8 +-
>> 9 files changed, 443 insertions(+), 12 deletions(-)
>>
>>--
>>2.38.1
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-06 10:26 ` Kubalewski, Arkadiusz
(?)
@ 2023-09-06 11:45 ` Drewek, Wojciech
-1 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 11:45 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: netdev, intel-wired-lan, bvanassche, linux-arm-kernel, linux-clk
> -----Original Message-----
> From: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
> Sent: Wednesday, September 6, 2023 12:26 PM
> To: Drewek, Wojciech <wojciech.drewek@intel.com>; kuba@kernel.org;
> jiri@resnulli.us; jonathan.lemon@gmail.com; pabeni@redhat.com;
> vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> support for pin-dpll signal phase offset/adjust
>
> >From: Drewek, Wojciech <wojciech.drewek@intel.com>
> >Sent: Wednesday, September 6, 2023 10:02 AM
> >
> >> -----Original Message-----
> >> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> >> Arkadiusz Kubalewski
> >> Sent: Wednesday, September 6, 2023 1:26 AM
> >> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> >> pabeni@redhat.com; vadim.fedorenko@linux.dev
> >> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> >> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> >> kernel@lists.infradead.org
> >> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> >> support
> >> for pin-dpll signal phase offset/adjust
> >>
> >> Add callback ops for pin-dpll phase measurment.
> >> Add callback for pin signal phase adjustment.
> >> Add min and max phase adjustment values to pin proprties.
> >> Invoke callbacks in dpll_netlink.c when filling the pin details to
> >> provide user with phase related attribute values.
> >>
> >> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> >> ---
> >> drivers/dpll/dpll_netlink.c | 99
> >> ++++++++++++++++++++++++++++++++++++-
> >> include/linux/dpll.h | 18 +++++++
> >> 2 files changed, 116 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> >> index 764437a0661b..548517d9ca4c 100644
> >> --- a/drivers/dpll/dpll_netlink.c
> >> +++ b/drivers/dpll/dpll_netlink.c
> >> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> >> struct dpll_pin *pin,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin
> *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s32 phase_adjust;
> >> + int ret;
> >> +
> >> + if (!ops->phase_adjust_get)
> >> + return 0;
> >
> >Why 0 is returned here? If it's intended, I would put a comment stating
> >why.
> >Same thing in dpll_msg_add_phase_offset.
>
> The callback is optional, any driver implementing dpll interface doesn't
> have to implement this callback and it must not be seen as an error.
> Callback that are required are pointed out in documentation:
> Documentation/driver-api/dpll.rst
>
> All the optional callbacks are returning this way, I don't see a point
> in adding extra comment here.
>
> Thank you!
> Arkadiusz
I see,
Thanks
>
> >
> >> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll),
> >> + &phase_adjust, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int
> >> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s64 phase_offset;
> >> + int ret;
> >> +
> >> + if (!ops->phase_offset_get)
> >> + return 0;
> >> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), &phase_offset,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> >> sizeof(phase_offset),
> >> + &phase_offset, DPLL_A_PIN_PAD))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> >> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> >> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (ret)
> >> goto nest_cancel;
> >> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> >> + if (ret)
> >> + goto nest_cancel;
> >> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> >> if (ret)
> >> goto nest_cancel;
> >> nla_nest_end(msg, attr);
> >> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> >> return -EMSGSIZE;
> >> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> >> + prop->phase_range.min))
> >> + return -EMSGSIZE;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> >> + prop->phase_range.max))
> >> + return -EMSGSIZE;
> >> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> >> if (ret)
> >> return ret;
> >> if (xa_empty(&pin->parent_refs))
> >> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll,
> struct
> >> sk_buff *msg,
> >> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> >> return -EMSGSIZE;
> >>
> >> - return ret;
> >> + return 0;
> >> }
> >>
> >> static int
> >> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> >> dpll_device *dpll,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
> >> *phase_adj_attr,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + struct dpll_pin_ref *ref;
> >> + unsigned long i;
> >> + s32 phase_adj;
> >> + int ret;
> >> +
> >> + phase_adj = nla_get_s32(phase_adj_attr);
> >> + if (phase_adj > pin->prop->phase_range.max ||
> >> + phase_adj < pin->prop->phase_range.min) {
> >> + NL_SET_ERR_MSG(extack, "phase adjust value not
> >> supported");
> >> + return -EINVAL;
> >> + }
> >> + xa_for_each(&pin->dpll_refs, i, ref) {
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> +
> >> + if (!ops->phase_adjust_set)
> >> + return -EOPNOTSUPP;
> >> + ret = ops->phase_adjust_set(pin,
> >> + dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), phase_adj,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + }
> >> + __dpll_pin_change_ntf(pin);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
> >> *parent_nest,
> >> struct netlink_ext_ack *extack)
> >> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
> >> struct
> >> genl_info *info)
> >> if (ret)
> >> return ret;
> >> break;
> >> + case DPLL_A_PIN_PHASE_ADJUST:
> >> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> >> + if (ret)
> >> + return ret;
> >> + break;
> >> case DPLL_A_PIN_PARENT_DEVICE:
> >> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> >> if (ret)
> >> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> >> index bbc480cd2932..578fc5fa3750 100644
> >> --- a/include/linux/dpll.h
> >> +++ b/include/linux/dpll.h
> >> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> >> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> >> const struct dpll_device *dpll, void *dpll_priv,
> >> const u32 prio, struct netlink_ext_ack *extack);
> >> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s64 *phase_offset,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s32 *phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + const s32 phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> };
> >>
> >> struct dpll_pin_frequency {
> >> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> >> #define DPLL_PIN_FREQUENCY_DCF77 \
> >> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
> >>
> >> +struct dpll_pin_phase_adjust_range {
> >> + s32 min;
> >> + s32 max;
> >> +};
> >> +
> >> struct dpll_pin_properties {
> >> const char *board_label;
> >> const char *panel_label;
> >> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> >> unsigned long capabilities;
> >> u32 freq_supported_num;
> >> struct dpll_pin_frequency *freq_supported;
> >> + struct dpll_pin_phase_adjust_range phase_range;
> >> };
> >>
> >> #if IS_ENABLED(CONFIG_DPLL)
> >> --
> >> 2.38.1
> >>
> >> _______________________________________________
> >> Intel-wired-lan mailing list
> >> Intel-wired-lan@osuosl.org
> >> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 11:45 ` Drewek, Wojciech
0 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 11:45 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
> -----Original Message-----
> From: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
> Sent: Wednesday, September 6, 2023 12:26 PM
> To: Drewek, Wojciech <wojciech.drewek@intel.com>; kuba@kernel.org;
> jiri@resnulli.us; jonathan.lemon@gmail.com; pabeni@redhat.com;
> vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> support for pin-dpll signal phase offset/adjust
>
> >From: Drewek, Wojciech <wojciech.drewek@intel.com>
> >Sent: Wednesday, September 6, 2023 10:02 AM
> >
> >> -----Original Message-----
> >> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> >> Arkadiusz Kubalewski
> >> Sent: Wednesday, September 6, 2023 1:26 AM
> >> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> >> pabeni@redhat.com; vadim.fedorenko@linux.dev
> >> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> >> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> >> kernel@lists.infradead.org
> >> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> >> support
> >> for pin-dpll signal phase offset/adjust
> >>
> >> Add callback ops for pin-dpll phase measurment.
> >> Add callback for pin signal phase adjustment.
> >> Add min and max phase adjustment values to pin proprties.
> >> Invoke callbacks in dpll_netlink.c when filling the pin details to
> >> provide user with phase related attribute values.
> >>
> >> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> >> ---
> >> drivers/dpll/dpll_netlink.c | 99
> >> ++++++++++++++++++++++++++++++++++++-
> >> include/linux/dpll.h | 18 +++++++
> >> 2 files changed, 116 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> >> index 764437a0661b..548517d9ca4c 100644
> >> --- a/drivers/dpll/dpll_netlink.c
> >> +++ b/drivers/dpll/dpll_netlink.c
> >> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> >> struct dpll_pin *pin,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin
> *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s32 phase_adjust;
> >> + int ret;
> >> +
> >> + if (!ops->phase_adjust_get)
> >> + return 0;
> >
> >Why 0 is returned here? If it's intended, I would put a comment stating
> >why.
> >Same thing in dpll_msg_add_phase_offset.
>
> The callback is optional, any driver implementing dpll interface doesn't
> have to implement this callback and it must not be seen as an error.
> Callback that are required are pointed out in documentation:
> Documentation/driver-api/dpll.rst
>
> All the optional callbacks are returning this way, I don't see a point
> in adding extra comment here.
>
> Thank you!
> Arkadiusz
I see,
Thanks
>
> >
> >> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll),
> >> + &phase_adjust, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int
> >> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s64 phase_offset;
> >> + int ret;
> >> +
> >> + if (!ops->phase_offset_get)
> >> + return 0;
> >> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), &phase_offset,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> >> sizeof(phase_offset),
> >> + &phase_offset, DPLL_A_PIN_PAD))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> >> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> >> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (ret)
> >> goto nest_cancel;
> >> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> >> + if (ret)
> >> + goto nest_cancel;
> >> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> >> if (ret)
> >> goto nest_cancel;
> >> nla_nest_end(msg, attr);
> >> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> >> return -EMSGSIZE;
> >> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> >> + prop->phase_range.min))
> >> + return -EMSGSIZE;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> >> + prop->phase_range.max))
> >> + return -EMSGSIZE;
> >> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> >> if (ret)
> >> return ret;
> >> if (xa_empty(&pin->parent_refs))
> >> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll,
> struct
> >> sk_buff *msg,
> >> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> >> return -EMSGSIZE;
> >>
> >> - return ret;
> >> + return 0;
> >> }
> >>
> >> static int
> >> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> >> dpll_device *dpll,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
> >> *phase_adj_attr,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + struct dpll_pin_ref *ref;
> >> + unsigned long i;
> >> + s32 phase_adj;
> >> + int ret;
> >> +
> >> + phase_adj = nla_get_s32(phase_adj_attr);
> >> + if (phase_adj > pin->prop->phase_range.max ||
> >> + phase_adj < pin->prop->phase_range.min) {
> >> + NL_SET_ERR_MSG(extack, "phase adjust value not
> >> supported");
> >> + return -EINVAL;
> >> + }
> >> + xa_for_each(&pin->dpll_refs, i, ref) {
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> +
> >> + if (!ops->phase_adjust_set)
> >> + return -EOPNOTSUPP;
> >> + ret = ops->phase_adjust_set(pin,
> >> + dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), phase_adj,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + }
> >> + __dpll_pin_change_ntf(pin);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
> >> *parent_nest,
> >> struct netlink_ext_ack *extack)
> >> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
> >> struct
> >> genl_info *info)
> >> if (ret)
> >> return ret;
> >> break;
> >> + case DPLL_A_PIN_PHASE_ADJUST:
> >> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> >> + if (ret)
> >> + return ret;
> >> + break;
> >> case DPLL_A_PIN_PARENT_DEVICE:
> >> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> >> if (ret)
> >> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> >> index bbc480cd2932..578fc5fa3750 100644
> >> --- a/include/linux/dpll.h
> >> +++ b/include/linux/dpll.h
> >> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> >> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> >> const struct dpll_device *dpll, void *dpll_priv,
> >> const u32 prio, struct netlink_ext_ack *extack);
> >> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s64 *phase_offset,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s32 *phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + const s32 phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> };
> >>
> >> struct dpll_pin_frequency {
> >> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> >> #define DPLL_PIN_FREQUENCY_DCF77 \
> >> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
> >>
> >> +struct dpll_pin_phase_adjust_range {
> >> + s32 min;
> >> + s32 max;
> >> +};
> >> +
> >> struct dpll_pin_properties {
> >> const char *board_label;
> >> const char *panel_label;
> >> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> >> unsigned long capabilities;
> >> u32 freq_supported_num;
> >> struct dpll_pin_frequency *freq_supported;
> >> + struct dpll_pin_phase_adjust_range phase_range;
> >> };
> >>
> >> #if IS_ENABLED(CONFIG_DPLL)
> >> --
> >> 2.38.1
> >>
> >> _______________________________________________
> >> Intel-wired-lan mailing list
> >> Intel-wired-lan@osuosl.org
> >> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-09-06 11:45 ` Drewek, Wojciech
0 siblings, 0 replies; 50+ messages in thread
From: Drewek, Wojciech @ 2023-09-06 11:45 UTC (permalink / raw)
To: Kubalewski, Arkadiusz, kuba, jiri, jonathan.lemon, pabeni,
vadim.fedorenko
Cc: bvanassche, netdev, intel-wired-lan, linux-clk, linux-arm-kernel
> -----Original Message-----
> From: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
> Sent: Wednesday, September 6, 2023 12:26 PM
> To: Drewek, Wojciech <wojciech.drewek@intel.com>; kuba@kernel.org;
> jiri@resnulli.us; jonathan.lemon@gmail.com; pabeni@redhat.com;
> vadim.fedorenko@linux.dev
> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> support for pin-dpll signal phase offset/adjust
>
> >From: Drewek, Wojciech <wojciech.drewek@intel.com>
> >Sent: Wednesday, September 6, 2023 10:02 AM
> >
> >> -----Original Message-----
> >> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
> >> Arkadiusz Kubalewski
> >> Sent: Wednesday, September 6, 2023 1:26 AM
> >> To: kuba@kernel.org; jiri@resnulli.us; jonathan.lemon@gmail.com;
> >> pabeni@redhat.com; vadim.fedorenko@linux.dev
> >> Cc: bvanassche@acm.org; netdev@vger.kernel.org; intel-wired-
> >> lan@lists.osuosl.org; linux-clk@vger.kernel.org; linux-arm-
> >> kernel@lists.infradead.org
> >> Subject: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add
> >> support
> >> for pin-dpll signal phase offset/adjust
> >>
> >> Add callback ops for pin-dpll phase measurment.
> >> Add callback for pin signal phase adjustment.
> >> Add min and max phase adjustment values to pin proprties.
> >> Invoke callbacks in dpll_netlink.c when filling the pin details to
> >> provide user with phase related attribute values.
> >>
> >> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> >> ---
> >> drivers/dpll/dpll_netlink.c | 99
> >> ++++++++++++++++++++++++++++++++++++-
> >> include/linux/dpll.h | 18 +++++++
> >> 2 files changed, 116 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
> >> index 764437a0661b..548517d9ca4c 100644
> >> --- a/drivers/dpll/dpll_netlink.c
> >> +++ b/drivers/dpll/dpll_netlink.c
> >> @@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg,
> >> struct dpll_pin *pin,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin
> *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s32 phase_adjust;
> >> + int ret;
> >> +
> >> + if (!ops->phase_adjust_get)
> >> + return 0;
> >
> >Why 0 is returned here? If it's intended, I would put a comment stating
> >why.
> >Same thing in dpll_msg_add_phase_offset.
>
> The callback is optional, any driver implementing dpll interface doesn't
> have to implement this callback and it must not be seen as an error.
> Callback that are required are pointed out in documentation:
> Documentation/driver-api/dpll.rst
>
> All the optional callbacks are returning this way, I don't see a point
> in adding extra comment here.
>
> Thank you!
> Arkadiusz
I see,
Thanks
>
> >
> >> + ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll),
> >> + &phase_adjust, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static int
> >> +dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
> >> + struct dpll_pin_ref *ref,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> + s64 phase_offset;
> >> + int ret;
> >> +
> >> + if (!ops->phase_offset_get)
> >> + return 0;
> >> + ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), &phase_offset,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET,
> >> sizeof(phase_offset),
> >> + &phase_offset, DPLL_A_PIN_PAD))
> >> + return -EMSGSIZE;
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
> >> struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
> >> @@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (ret)
> >> goto nest_cancel;
> >> ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
> >> + if (ret)
> >> + goto nest_cancel;
> >> + ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
> >> if (ret)
> >> goto nest_cancel;
> >> nla_nest_end(msg, attr);
> >> @@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg,
> struct
> >> dpll_pin *pin,
> >> if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
> >> return -EMSGSIZE;
> >> ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
> >> + if (ret)
> >> + return ret;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
> >> + prop->phase_range.min))
> >> + return -EMSGSIZE;
> >> + if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
> >> + prop->phase_range.max))
> >> + return -EMSGSIZE;
> >> + ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
> >> if (ret)
> >> return ret;
> >> if (xa_empty(&pin->parent_refs))
> >> @@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll,
> struct
> >> sk_buff *msg,
> >> if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
> >> return -EMSGSIZE;
> >>
> >> - return ret;
> >> + return 0;
> >> }
> >>
> >> static int
> >> @@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct
> >> dpll_device *dpll,
> >> return 0;
> >> }
> >>
> >> +static int
> >> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
> >> *phase_adj_attr,
> >> + struct netlink_ext_ack *extack)
> >> +{
> >> + struct dpll_pin_ref *ref;
> >> + unsigned long i;
> >> + s32 phase_adj;
> >> + int ret;
> >> +
> >> + phase_adj = nla_get_s32(phase_adj_attr);
> >> + if (phase_adj > pin->prop->phase_range.max ||
> >> + phase_adj < pin->prop->phase_range.min) {
> >> + NL_SET_ERR_MSG(extack, "phase adjust value not
> >> supported");
> >> + return -EINVAL;
> >> + }
> >> + xa_for_each(&pin->dpll_refs, i, ref) {
> >> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> >> + struct dpll_device *dpll = ref->dpll;
> >> +
> >> + if (!ops->phase_adjust_set)
> >> + return -EOPNOTSUPP;
> >> + ret = ops->phase_adjust_set(pin,
> >> + dpll_pin_on_dpll_priv(dpll, pin),
> >> + dpll, dpll_priv(dpll), phase_adj,
> >> + extack);
> >> + if (ret)
> >> + return ret;
> >> + }
> >> + __dpll_pin_change_ntf(pin);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int
> >> dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr
> >> *parent_nest,
> >> struct netlink_ext_ack *extack)
> >> @@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin,
> >> struct
> >> genl_info *info)
> >> if (ret)
> >> return ret;
> >> break;
> >> + case DPLL_A_PIN_PHASE_ADJUST:
> >> + ret = dpll_pin_phase_adj_set(pin, a, info->extack);
> >> + if (ret)
> >> + return ret;
> >> + break;
> >> case DPLL_A_PIN_PARENT_DEVICE:
> >> ret = dpll_pin_parent_device_set(pin, a, info->extack);
> >> if (ret)
> >> diff --git a/include/linux/dpll.h b/include/linux/dpll.h
> >> index bbc480cd2932..578fc5fa3750 100644
> >> --- a/include/linux/dpll.h
> >> +++ b/include/linux/dpll.h
> >> @@ -68,6 +68,18 @@ struct dpll_pin_ops {
> >> int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
> >> const struct dpll_device *dpll, void *dpll_priv,
> >> const u32 prio, struct netlink_ext_ack *extack);
> >> + int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s64 *phase_offset,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + s32 *phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> + int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
> >> + const struct dpll_device *dpll, void *dpll_priv,
> >> + const s32 phase_adjust,
> >> + struct netlink_ext_ack *extack);
> >> };
> >>
> >> struct dpll_pin_frequency {
> >> @@ -91,6 +103,11 @@ struct dpll_pin_frequency {
> >> #define DPLL_PIN_FREQUENCY_DCF77 \
> >> DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
> >>
> >> +struct dpll_pin_phase_adjust_range {
> >> + s32 min;
> >> + s32 max;
> >> +};
> >> +
> >> struct dpll_pin_properties {
> >> const char *board_label;
> >> const char *panel_label;
> >> @@ -99,6 +116,7 @@ struct dpll_pin_properties {
> >> unsigned long capabilities;
> >> u32 freq_supported_num;
> >> struct dpll_pin_frequency *freq_supported;
> >> + struct dpll_pin_phase_adjust_range phase_range;
> >> };
> >>
> >> #if IS_ENABLED(CONFIG_DPLL)
> >> --
> >> 2.38.1
> >>
> >> _______________________________________________
> >> Intel-wired-lan mailing list
> >> Intel-wired-lan@osuosl.org
> >> https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 17:18 ` Jiri Pirko
@ 2023-10-04 9:13 ` Kubalewski, Arkadiusz
-1 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-04 9:13 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 7:19 PM
>
>Tue, Oct 03, 2023 at 04:29:13PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Jiri Pirko <jiri@resnulli.us>
>>>Sent: Tuesday, October 3, 2023 8:27 AM
>>>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>>>
>>>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com
>>>wrote:
>>>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>>>Vadim Fedorenko
>>>>>Sent: Monday, October 2, 2023 5:09 PM
>>>>>
>>>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>>> wrote:
>>>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>>>
>>>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>>>> with phase related attribute values.
>>>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>>>> for
>>>>>>>>> pin-set request.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>>>
>>>>>>>> [...]
>>>>>>>>
>>>>>>>>> +static int
>>>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>>>> *phase_adj_attr,
>>>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>>>> +{
>>>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>>>> + unsigned long i;
>>>>>>>>> + s32 phase_adj;
>>>>>>>>> + int ret;
>>>>>>>>> +
>>>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>>>> supported");
>>>>>>>>> + return -EINVAL;
>>>>>>>>> + }
>>>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>>>> +
>>>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>>>> + return -EOPNOTSUPP;
>>>>>>>>
>>>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>>>> with
>>>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>>>> them
>>>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>>>> apply
>>>>>>>> the change?
>>>>>>>>
>>>>>>>
>>>>>>> Well makes sense to me.
>>>>>>>
>>>>>>> Does following makes sense as a fix?
>>>>>>> We would call op for all devices which has been provided with the op.
>>>>>>> If device has no op -> add extack error, continue
>>>>>>
>>>>>> Is it real to expect some of the device support this and others don't?
>>>>>> Is it true for ice?
>>>>>> If not, I would got for all-or-nothing here.
>>>>>>
>>>>>
>>>>>But nothing blocks vendors to provide such configuration. Should we
>>>>>rollback the configuration? Otherwise we can easily make it
>>>>>inconsistent.
>>>>
>>>>Good point, in such case rollback might be required.
>>>>
>>>>>
>>>>>I'm more thinking of checking if all the devices returned error (or
>>>>>absence of operation callback) and then return error instead of 0 with
>>>>>extack filled in.
>>>>>
>>>>
>>>>Well, what if different devices would return different errors?
>>>>In general we would have to keep track of the error values returned in
>>>>such case.. Assuming one is different than the other - still need to
>>>>error
>>>>extack them out? I guess it would be easier to return common error if
>>>there
>>>
>>>In this case, it is common to return the first error hit and bail out,
>>>not trying the rest.
>>>
>>
>>OK, so now I see it like this:
>>-> check if all device implement callback, if not return EOPNOTSUPP;
>>-> get old phase_adjust
>>-> if new == old, return EINVAL
>
>0 would be better, no? User has what he desired.
>
Yes, that makes sense.
>
>>-> for each device: call phase_adjust_set, if fails, rollback all previous
>> successful attempts and return the failure code
>
>That would work.
>
Great, just sent v2.
Thanks!
Arkadiusz
>
>>?
>>
>>Thank you!
>>Arkadiusz
>>
>>>
>>>>were only failures and let the driver fill the errors on extack, smt
>>>>like:
>>>>
>>>> int miss_cb_num = 0, dev_num = 0, err_num;
>>>>
>>>> xa_for_each(&pin->dpll_refs, i, ref) {
>>>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>> struct dpll_device *dpll = ref->dpll;
>>>>
>>>> dev_num++;
>>>> if (!ops->phase_adjust_set) {
>>>> miss_cb_num++;
>>>> continue;
>>>> }
>>>> ret = ops->phase_adjust_set(pin,
>>>> dpll_pin_on_dpll_priv(dpll, pin),
>>>> dpll, dpll_priv(dpll), phase_adj,
>>>> extack);
>>>> if (ret)
>>>> err_num++;
>>>> }
>>>> if (dev_num == miss_cb_num)
>>>> return -EOPNOTSUPP;
>>>> if (dev_num == err_num)
>>>> return -EINVAL;
>>>> __dpll_pin_change_ntf(pin);
>>>> return 0;
>>>>
>>>>??
>>>>
>>>>Thank you!
>>>>Arkadiusz
>>>>
>>>>>>
>>>>>>> If device fails to set -> add extack error, continue
>>>>>>> Function always returns 0.
>>>>>>>
>>>>>>> Thank you!
>>>>>>> Arkadiusz
>>>>>>>
>>>>>>>>
>>>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>>>> + extack);
>>>>>>>>> + if (ret)
>>>>>>>>> + return ret;
>>>>>>>>> + }
>>>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>>>> +
>>>>>>>>> + return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>
>>>>>_______________________________________________
>>>>>Intel-wired-lan mailing list
>>>>>Intel-wired-lan@osuosl.org
>>>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
>>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-10-04 9:13 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-04 9:13 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, linux-doc, netdev, corbet, Brandeburg, Jesse,
Nguyen, Anthony L, kuba, intel-wired-lan, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 7:19 PM
>
>Tue, Oct 03, 2023 at 04:29:13PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Jiri Pirko <jiri@resnulli.us>
>>>Sent: Tuesday, October 3, 2023 8:27 AM
>>>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>>>
>>>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com
>>>wrote:
>>>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>>>Vadim Fedorenko
>>>>>Sent: Monday, October 2, 2023 5:09 PM
>>>>>
>>>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>>> wrote:
>>>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>>>
>>>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>>>> with phase related attribute values.
>>>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>>>> for
>>>>>>>>> pin-set request.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>>>
>>>>>>>> [...]
>>>>>>>>
>>>>>>>>> +static int
>>>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>>>> *phase_adj_attr,
>>>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>>>> +{
>>>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>>>> + unsigned long i;
>>>>>>>>> + s32 phase_adj;
>>>>>>>>> + int ret;
>>>>>>>>> +
>>>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>>>> supported");
>>>>>>>>> + return -EINVAL;
>>>>>>>>> + }
>>>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>>>> +
>>>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>>>> + return -EOPNOTSUPP;
>>>>>>>>
>>>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>>>> with
>>>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>>>> them
>>>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>>>> apply
>>>>>>>> the change?
>>>>>>>>
>>>>>>>
>>>>>>> Well makes sense to me.
>>>>>>>
>>>>>>> Does following makes sense as a fix?
>>>>>>> We would call op for all devices which has been provided with the op.
>>>>>>> If device has no op -> add extack error, continue
>>>>>>
>>>>>> Is it real to expect some of the device support this and others don't?
>>>>>> Is it true for ice?
>>>>>> If not, I would got for all-or-nothing here.
>>>>>>
>>>>>
>>>>>But nothing blocks vendors to provide such configuration. Should we
>>>>>rollback the configuration? Otherwise we can easily make it
>>>>>inconsistent.
>>>>
>>>>Good point, in such case rollback might be required.
>>>>
>>>>>
>>>>>I'm more thinking of checking if all the devices returned error (or
>>>>>absence of operation callback) and then return error instead of 0 with
>>>>>extack filled in.
>>>>>
>>>>
>>>>Well, what if different devices would return different errors?
>>>>In general we would have to keep track of the error values returned in
>>>>such case.. Assuming one is different than the other - still need to
>>>>error
>>>>extack them out? I guess it would be easier to return common error if
>>>there
>>>
>>>In this case, it is common to return the first error hit and bail out,
>>>not trying the rest.
>>>
>>
>>OK, so now I see it like this:
>>-> check if all device implement callback, if not return EOPNOTSUPP;
>>-> get old phase_adjust
>>-> if new == old, return EINVAL
>
>0 would be better, no? User has what he desired.
>
Yes, that makes sense.
>
>>-> for each device: call phase_adjust_set, if fails, rollback all previous
>> successful attempts and return the failure code
>
>That would work.
>
Great, just sent v2.
Thanks!
Arkadiusz
>
>>?
>>
>>Thank you!
>>Arkadiusz
>>
>>>
>>>>were only failures and let the driver fill the errors on extack, smt
>>>>like:
>>>>
>>>> int miss_cb_num = 0, dev_num = 0, err_num;
>>>>
>>>> xa_for_each(&pin->dpll_refs, i, ref) {
>>>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>> struct dpll_device *dpll = ref->dpll;
>>>>
>>>> dev_num++;
>>>> if (!ops->phase_adjust_set) {
>>>> miss_cb_num++;
>>>> continue;
>>>> }
>>>> ret = ops->phase_adjust_set(pin,
>>>> dpll_pin_on_dpll_priv(dpll, pin),
>>>> dpll, dpll_priv(dpll), phase_adj,
>>>> extack);
>>>> if (ret)
>>>> err_num++;
>>>> }
>>>> if (dev_num == miss_cb_num)
>>>> return -EOPNOTSUPP;
>>>> if (dev_num == err_num)
>>>> return -EINVAL;
>>>> __dpll_pin_change_ntf(pin);
>>>> return 0;
>>>>
>>>>??
>>>>
>>>>Thank you!
>>>>Arkadiusz
>>>>
>>>>>>
>>>>>>> If device fails to set -> add extack error, continue
>>>>>>> Function always returns 0.
>>>>>>>
>>>>>>> Thank you!
>>>>>>> Arkadiusz
>>>>>>>
>>>>>>>>
>>>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>>>> + extack);
>>>>>>>>> + if (ret)
>>>>>>>>> + return ret;
>>>>>>>>> + }
>>>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>>>> +
>>>>>>>>> + return 0;
>>>>>>>>> +}
>>>>>>>>> +
>>>>>
>>>>>_______________________________________________
>>>>>Intel-wired-lan mailing list
>>>>>Intel-wired-lan@osuosl.org
>>>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
>>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 17:19 ` Jiri Pirko
@ 2023-10-04 9:11 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-04 9:11 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 7:20 PM
>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>
>Tue, Oct 03, 2023 at 04:29:43PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Jiri Pirko <jiri@resnulli.us>
>>>Sent: Tuesday, October 3, 2023 8:32 AM
>>>
>>>Tue, Oct 03, 2023 at 01:03:00AM CEST, arkadiusz.kubalewski@intel.com
>>>wrote:
>>>>>From: Jiri Pirko <jiri@resnulli.us>
>>>>>Sent: Monday, October 2, 2023 5:04 PM
>>>>>
>>>>>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>>wrote:
>>>>>>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>>
>>>>>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>>> Invoke get callbacks when filling up the pin details to provide
>>>>>>>> user
>>>>>>>> with phase related attribute values.
>>>>>>>> Invoke phase-adjust set callback when phase-adjust value is
>>>>>>>> provided
>>>>>>>> for
>>>>>>>> pin-set request.
>>>>>>>>
>>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>>
>>>>>>>[...]
>>>>>>>
>>>>>>>> +static int
>>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>>> *phase_adj_attr,
>>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>>> +{
>>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>>> + unsigned long i;
>>>>>>>> + s32 phase_adj;
>>>>>>>> + int ret;
>>>>>>>> +
>>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>>> supported");
>>>>>>>> + return -EINVAL;
>>>>>>>> + }
>>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>>> +
>>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>>> + return -EOPNOTSUPP;
>>>>>>>
>>>>>>>I'm thinking about this part. We can potentially have dpll devices
>>>>>>>with
>>>>>>>different expectations on phase adjustments, right? And if one of
>>>>>>>them
>>>>>>>won't be able to adjust phase (or will fail in the next line), then
>>>>>>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>>adjusted. Doesn't look great. Can we think about different way to
>>>>>>>apply
>>>>>>>the change?
>>>>>>>
>>>>>>
>>>>>>Well makes sense to me.
>>>>>>
>>>>>>Does following makes sense as a fix?
>>>>>>We would call op for all devices which has been provided with the op.
>>>>>>If device has no op -> add extack error, continue
>>>>>
>>>>>Is it real to expect some of the device support this and others don't?
>>>>>Is it true for ice?
>>>>>If not, I would got for all-or-nothing here.
>>>>>
>>>>
>>>>Let's step back a bit.
>>>>The op itself is introduced as per pin-dpll tuple.. did this
>>>>intentionally,
>>>>to inform each dpll that the offset has been changed - in case dplls are
>>>>controlled by separated driver/firmware instances but still sharing the
>>>>pin.
>>>>Same way a pin frequency is being set, from user perspective on a pin, but
>>>>callback is called for each dpll the pin was registered with.
>>>>Whatever we do here, it shall be probably done for frequency_set()
>>>>callback as
>>>>well.
>>>>
>>>>The answers:
>>>>So far I don't know the device that might do it this way, it rather
>>>>supports
>>>>phase_adjust or not. In theory we allow such behavior to be implemented,
>>>>i.e.
>>>>pin is registered with 2 dplls, one has the callback, second not.
>>>
>>>If there is only theoretical device like that now, implement
>>>all-or-nothing. If such theoretical device appears in real, this could
>>>be changed. The UAPI would not change, no problem.
>>>
>>
>>I can live with it :)
>>
>>>
>>>>Current hardware of ice sets phase offset for a pin no matter on which
>>>>dpll
>>>>device callback was invoked.
>>>>"all-or-nothing" - do you mean to check all callback returns and then
>>>>decide
>>>>if it was successful?
>>>
>>>Check if all dplls have ops and only perform the action in such case. In
>>>case one of the dplls does not have the op filled, return -EOPNOTSUPP.
>>>
>>>
>>>Regarding the successful/failed op, I think you can just return. In
>>>these cases, when user performs multiaction cmd, he should be prepared
>>>to deal with consequences if part of this cmd fails. We don't have
>>>rollback for any other multiaction cmd in dpll, I don't see why this
>>>should be treated differently.
>>>
>>
>>We don't have it because no one have spotted it on review,
>>as mentioned the frequency_set behaves the same way,
>>we need one approach for all of those cases.
>>I am opting for having the rollback as suggested on the other thread.
>
>Okay, but let's do that consistently.
>
Sure, fixed in v2.
Thanks!
Arkadiusz
>>
>>Thank you!
>>Arkadiusz
>>
>>>
>>>>
>>>>Thank you!
>>>>Arkadiusz
>>>>
>>>>>
>>>>>>If device fails to set -> add extack error, continue
>>>>>>Function always returns 0.
>>>>>>
>>>>>>Thank you!
>>>>>>Arkadiusz
>>>>>>
>>>>>>>
>>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>>> + extack);
>>>>>>>> + if (ret)
>>>>>>>> + return ret;
>>>>>>>> + }
>>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 14:29 ` Kubalewski, Arkadiusz
@ 2023-10-03 17:19 ` Jiri Pirko
2023-10-04 9:11 ` Kubalewski, Arkadiusz
0 siblings, 1 reply; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 17:19 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
Tue, Oct 03, 2023 at 04:29:43PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Jiri Pirko <jiri@resnulli.us>
>>Sent: Tuesday, October 3, 2023 8:32 AM
>>
>>Tue, Oct 03, 2023 at 01:03:00AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>>From: Jiri Pirko <jiri@resnulli.us>
>>>>Sent: Monday, October 2, 2023 5:04 PM
>>>>
>>>>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>wrote:
>>>>>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>
>>>>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>> with phase related attribute values.
>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>> for
>>>>>>> pin-set request.
>>>>>>>
>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>
>>>>>>[...]
>>>>>>
>>>>>>> +static int
>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>> *phase_adj_attr,
>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>> +{
>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>> + unsigned long i;
>>>>>>> + s32 phase_adj;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>> supported");
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>> +
>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>> + return -EOPNOTSUPP;
>>>>>>
>>>>>>I'm thinking about this part. We can potentially have dpll devices with
>>>>>>different expectations on phase adjustments, right? And if one of them
>>>>>>won't be able to adjust phase (or will fail in the next line), then
>>>>>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>adjusted. Doesn't look great. Can we think about different way to apply
>>>>>>the change?
>>>>>>
>>>>>
>>>>>Well makes sense to me.
>>>>>
>>>>>Does following makes sense as a fix?
>>>>>We would call op for all devices which has been provided with the op.
>>>>>If device has no op -> add extack error, continue
>>>>
>>>>Is it real to expect some of the device support this and others don't?
>>>>Is it true for ice?
>>>>If not, I would got for all-or-nothing here.
>>>>
>>>
>>>Let's step back a bit.
>>>The op itself is introduced as per pin-dpll tuple.. did this
>>>intentionally,
>>>to inform each dpll that the offset has been changed - in case dplls are
>>>controlled by separated driver/firmware instances but still sharing the
>>>pin.
>>>Same way a pin frequency is being set, from user perspective on a pin, but
>>>callback is called for each dpll the pin was registered with.
>>>Whatever we do here, it shall be probably done for frequency_set()
>>>callback as
>>>well.
>>>
>>>The answers:
>>>So far I don't know the device that might do it this way, it rather
>>>supports
>>>phase_adjust or not. In theory we allow such behavior to be implemented,
>>>i.e.
>>>pin is registered with 2 dplls, one has the callback, second not.
>>
>>If there is only theoretical device like that now, implement
>>all-or-nothing. If such theoretical device appears in real, this could
>>be changed. The UAPI would not change, no problem.
>>
>
>I can live with it :)
>
>>
>>>Current hardware of ice sets phase offset for a pin no matter on which
>>>dpll
>>>device callback was invoked.
>>>"all-or-nothing" - do you mean to check all callback returns and then
>>>decide
>>>if it was successful?
>>
>>Check if all dplls have ops and only perform the action in such case. In
>>case one of the dplls does not have the op filled, return -EOPNOTSUPP.
>>
>>
>>Regarding the successful/failed op, I think you can just return. In
>>these cases, when user performs multiaction cmd, he should be prepared
>>to deal with consequences if part of this cmd fails. We don't have
>>rollback for any other multiaction cmd in dpll, I don't see why this
>>should be treated differently.
>>
>
>We don't have it because no one have spotted it on review,
>as mentioned the frequency_set behaves the same way,
>we need one approach for all of those cases.
>I am opting for having the rollback as suggested on the other thread.
Okay, but let's do that consistently.
>
>Thank you!
>Arkadiusz
>
>>
>>>
>>>Thank you!
>>>Arkadiusz
>>>
>>>>
>>>>>If device fails to set -> add extack error, continue
>>>>>Function always returns 0.
>>>>>
>>>>>Thank you!
>>>>>Arkadiusz
>>>>>
>>>>>>
>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>> + extack);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 14:29 ` Kubalewski, Arkadiusz
@ 2023-10-03 17:18 ` Jiri Pirko
-1 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 17:18 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
Tue, Oct 03, 2023 at 04:29:13PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Jiri Pirko <jiri@resnulli.us>
>>Sent: Tuesday, October 3, 2023 8:27 AM
>>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>>
>>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>>Vadim Fedorenko
>>>>Sent: Monday, October 2, 2023 5:09 PM
>>>>
>>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>> wrote:
>>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>>
>>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>>> with phase related attribute values.
>>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>>> for
>>>>>>>> pin-set request.
>>>>>>>>
>>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>>
>>>>>>> [...]
>>>>>>>
>>>>>>>> +static int
>>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>>> *phase_adj_attr,
>>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>>> +{
>>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>>> + unsigned long i;
>>>>>>>> + s32 phase_adj;
>>>>>>>> + int ret;
>>>>>>>> +
>>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>>> supported");
>>>>>>>> + return -EINVAL;
>>>>>>>> + }
>>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>>> +
>>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>>> + return -EOPNOTSUPP;
>>>>>>>
>>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>>> with
>>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>>> them
>>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>>> apply
>>>>>>> the change?
>>>>>>>
>>>>>>
>>>>>> Well makes sense to me.
>>>>>>
>>>>>> Does following makes sense as a fix?
>>>>>> We would call op for all devices which has been provided with the op.
>>>>>> If device has no op -> add extack error, continue
>>>>>
>>>>> Is it real to expect some of the device support this and others don't?
>>>>> Is it true for ice?
>>>>> If not, I would got for all-or-nothing here.
>>>>>
>>>>
>>>>But nothing blocks vendors to provide such configuration. Should we
>>>>rollback the configuration? Otherwise we can easily make it
>>>>inconsistent.
>>>
>>>Good point, in such case rollback might be required.
>>>
>>>>
>>>>I'm more thinking of checking if all the devices returned error (or
>>>>absence of operation callback) and then return error instead of 0 with
>>>>extack filled in.
>>>>
>>>
>>>Well, what if different devices would return different errors?
>>>In general we would have to keep track of the error values returned in
>>>such case.. Assuming one is different than the other - still need to error
>>>extack them out? I guess it would be easier to return common error if
>>there
>>
>>In this case, it is common to return the first error hit and bail out,
>>not trying the rest.
>>
>
>OK, so now I see it like this:
>-> check if all device implement callback, if not return EOPNOTSUPP;
>-> get old phase_adjust
>-> if new == old, return EINVAL
0 would be better, no? User has what he desired.
>-> for each device: call phase_adjust_set, if fails, rollback all previous
> successful attempts and return the failure code
That would work.
>?
>
>Thank you!
>Arkadiusz
>
>>
>>>were only failures and let the driver fill the errors on extack, smt like:
>>>
>>> int miss_cb_num = 0, dev_num = 0, err_num;
>>>
>>> xa_for_each(&pin->dpll_refs, i, ref) {
>>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>> struct dpll_device *dpll = ref->dpll;
>>>
>>> dev_num++;
>>> if (!ops->phase_adjust_set) {
>>> miss_cb_num++;
>>> continue;
>>> }
>>> ret = ops->phase_adjust_set(pin,
>>> dpll_pin_on_dpll_priv(dpll, pin),
>>> dpll, dpll_priv(dpll), phase_adj,
>>> extack);
>>> if (ret)
>>> err_num++;
>>> }
>>> if (dev_num == miss_cb_num)
>>> return -EOPNOTSUPP;
>>> if (dev_num == err_num)
>>> return -EINVAL;
>>> __dpll_pin_change_ntf(pin);
>>> return 0;
>>>
>>>??
>>>
>>>Thank you!
>>>Arkadiusz
>>>
>>>>>
>>>>>> If device fails to set -> add extack error, continue
>>>>>> Function always returns 0.
>>>>>>
>>>>>> Thank you!
>>>>>> Arkadiusz
>>>>>>
>>>>>>>
>>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>>> + extack);
>>>>>>>> + if (ret)
>>>>>>>> + return ret;
>>>>>>>> + }
>>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>
>>>>_______________________________________________
>>>>Intel-wired-lan mailing list
>>>>Intel-wired-lan@osuosl.org
>>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-10-03 17:18 ` Jiri Pirko
0 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 17:18 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, linux-doc, netdev, corbet, Brandeburg, Jesse,
Nguyen, Anthony L, kuba, intel-wired-lan, pabeni, davem
Tue, Oct 03, 2023 at 04:29:13PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Jiri Pirko <jiri@resnulli.us>
>>Sent: Tuesday, October 3, 2023 8:27 AM
>>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>>
>>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>>Vadim Fedorenko
>>>>Sent: Monday, October 2, 2023 5:09 PM
>>>>
>>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>>> wrote:
>>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>>
>>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>>> with phase related attribute values.
>>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>>> for
>>>>>>>> pin-set request.
>>>>>>>>
>>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>>
>>>>>>> [...]
>>>>>>>
>>>>>>>> +static int
>>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>>> *phase_adj_attr,
>>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>>> +{
>>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>>> + unsigned long i;
>>>>>>>> + s32 phase_adj;
>>>>>>>> + int ret;
>>>>>>>> +
>>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>>> supported");
>>>>>>>> + return -EINVAL;
>>>>>>>> + }
>>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>>> +
>>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>>> + return -EOPNOTSUPP;
>>>>>>>
>>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>>> with
>>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>>> them
>>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>>> apply
>>>>>>> the change?
>>>>>>>
>>>>>>
>>>>>> Well makes sense to me.
>>>>>>
>>>>>> Does following makes sense as a fix?
>>>>>> We would call op for all devices which has been provided with the op.
>>>>>> If device has no op -> add extack error, continue
>>>>>
>>>>> Is it real to expect some of the device support this and others don't?
>>>>> Is it true for ice?
>>>>> If not, I would got for all-or-nothing here.
>>>>>
>>>>
>>>>But nothing blocks vendors to provide such configuration. Should we
>>>>rollback the configuration? Otherwise we can easily make it
>>>>inconsistent.
>>>
>>>Good point, in such case rollback might be required.
>>>
>>>>
>>>>I'm more thinking of checking if all the devices returned error (or
>>>>absence of operation callback) and then return error instead of 0 with
>>>>extack filled in.
>>>>
>>>
>>>Well, what if different devices would return different errors?
>>>In general we would have to keep track of the error values returned in
>>>such case.. Assuming one is different than the other - still need to error
>>>extack them out? I guess it would be easier to return common error if
>>there
>>
>>In this case, it is common to return the first error hit and bail out,
>>not trying the rest.
>>
>
>OK, so now I see it like this:
>-> check if all device implement callback, if not return EOPNOTSUPP;
>-> get old phase_adjust
>-> if new == old, return EINVAL
0 would be better, no? User has what he desired.
>-> for each device: call phase_adjust_set, if fails, rollback all previous
> successful attempts and return the failure code
That would work.
>?
>
>Thank you!
>Arkadiusz
>
>>
>>>were only failures and let the driver fill the errors on extack, smt like:
>>>
>>> int miss_cb_num = 0, dev_num = 0, err_num;
>>>
>>> xa_for_each(&pin->dpll_refs, i, ref) {
>>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>> struct dpll_device *dpll = ref->dpll;
>>>
>>> dev_num++;
>>> if (!ops->phase_adjust_set) {
>>> miss_cb_num++;
>>> continue;
>>> }
>>> ret = ops->phase_adjust_set(pin,
>>> dpll_pin_on_dpll_priv(dpll, pin),
>>> dpll, dpll_priv(dpll), phase_adj,
>>> extack);
>>> if (ret)
>>> err_num++;
>>> }
>>> if (dev_num == miss_cb_num)
>>> return -EOPNOTSUPP;
>>> if (dev_num == err_num)
>>> return -EINVAL;
>>> __dpll_pin_change_ntf(pin);
>>> return 0;
>>>
>>>??
>>>
>>>Thank you!
>>>Arkadiusz
>>>
>>>>>
>>>>>> If device fails to set -> add extack error, continue
>>>>>> Function always returns 0.
>>>>>>
>>>>>> Thank you!
>>>>>> Arkadiusz
>>>>>>
>>>>>>>
>>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>>> + extack);
>>>>>>>> + if (ret)
>>>>>>>> + return ret;
>>>>>>>> + }
>>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>>> +
>>>>>>>> + return 0;
>>>>>>>> +}
>>>>>>>> +
>>>>
>>>>_______________________________________________
>>>>Intel-wired-lan mailing list
>>>>Intel-wired-lan@osuosl.org
>>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 6:32 ` Jiri Pirko
@ 2023-10-03 14:29 ` Kubalewski, Arkadiusz
2023-10-03 17:19 ` Jiri Pirko
0 siblings, 1 reply; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-03 14:29 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 8:32 AM
>
>Tue, Oct 03, 2023 at 01:03:00AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Jiri Pirko <jiri@resnulli.us>
>>>Sent: Monday, October 2, 2023 5:04 PM
>>>
>>>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>wrote:
>>>>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>
>>>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>> with phase related attribute values.
>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>> for
>>>>>> pin-set request.
>>>>>>
>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>
>>>>>[...]
>>>>>
>>>>>> +static int
>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>> *phase_adj_attr,
>>>>>> + struct netlink_ext_ack *extack)
>>>>>> +{
>>>>>> + struct dpll_pin_ref *ref;
>>>>>> + unsigned long i;
>>>>>> + s32 phase_adj;
>>>>>> + int ret;
>>>>>> +
>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>> supported");
>>>>>> + return -EINVAL;
>>>>>> + }
>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>> +
>>>>>> + if (!ops->phase_adjust_set)
>>>>>> + return -EOPNOTSUPP;
>>>>>
>>>>>I'm thinking about this part. We can potentially have dpll devices with
>>>>>different expectations on phase adjustments, right? And if one of them
>>>>>won't be able to adjust phase (or will fail in the next line), then
>>>>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>adjusted. Doesn't look great. Can we think about different way to apply
>>>>>the change?
>>>>>
>>>>
>>>>Well makes sense to me.
>>>>
>>>>Does following makes sense as a fix?
>>>>We would call op for all devices which has been provided with the op.
>>>>If device has no op -> add extack error, continue
>>>
>>>Is it real to expect some of the device support this and others don't?
>>>Is it true for ice?
>>>If not, I would got for all-or-nothing here.
>>>
>>
>>Let's step back a bit.
>>The op itself is introduced as per pin-dpll tuple.. did this
>>intentionally,
>>to inform each dpll that the offset has been changed - in case dplls are
>>controlled by separated driver/firmware instances but still sharing the
>>pin.
>>Same way a pin frequency is being set, from user perspective on a pin, but
>>callback is called for each dpll the pin was registered with.
>>Whatever we do here, it shall be probably done for frequency_set()
>>callback as
>>well.
>>
>>The answers:
>>So far I don't know the device that might do it this way, it rather
>>supports
>>phase_adjust or not. In theory we allow such behavior to be implemented,
>>i.e.
>>pin is registered with 2 dplls, one has the callback, second not.
>
>If there is only theoretical device like that now, implement
>all-or-nothing. If such theoretical device appears in real, this could
>be changed. The UAPI would not change, no problem.
>
I can live with it :)
>
>>Current hardware of ice sets phase offset for a pin no matter on which
>>dpll
>>device callback was invoked.
>>"all-or-nothing" - do you mean to check all callback returns and then
>>decide
>>if it was successful?
>
>Check if all dplls have ops and only perform the action in such case. In
>case one of the dplls does not have the op filled, return -EOPNOTSUPP.
>
>
>Regarding the successful/failed op, I think you can just return. In
>these cases, when user performs multiaction cmd, he should be prepared
>to deal with consequences if part of this cmd fails. We don't have
>rollback for any other multiaction cmd in dpll, I don't see why this
>should be treated differently.
>
We don't have it because no one have spotted it on review,
as mentioned the frequency_set behaves the same way,
we need one approach for all of those cases.
I am opting for having the rollback as suggested on the other thread.
Thank you!
Arkadiusz
>
>>
>>Thank you!
>>Arkadiusz
>>
>>>
>>>>If device fails to set -> add extack error, continue
>>>>Function always returns 0.
>>>>
>>>>Thank you!
>>>>Arkadiusz
>>>>
>>>>>
>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>> + extack);
>>>>>> + if (ret)
>>>>>> + return ret;
>>>>>> + }
>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-03 6:27 ` Jiri Pirko
@ 2023-10-03 14:29 ` Kubalewski, Arkadiusz
-1 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-03 14:29 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 8:27 AM
>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>
>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>Vadim Fedorenko
>>>Sent: Monday, October 2, 2023 5:09 PM
>>>
>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>> wrote:
>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>
>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>> with phase related attribute values.
>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>> for
>>>>>>> pin-set request.
>>>>>>>
>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> +static int
>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>> *phase_adj_attr,
>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>> +{
>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>> + unsigned long i;
>>>>>>> + s32 phase_adj;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>> supported");
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>> +
>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>> + return -EOPNOTSUPP;
>>>>>>
>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>> with
>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>> them
>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>> apply
>>>>>> the change?
>>>>>>
>>>>>
>>>>> Well makes sense to me.
>>>>>
>>>>> Does following makes sense as a fix?
>>>>> We would call op for all devices which has been provided with the op.
>>>>> If device has no op -> add extack error, continue
>>>>
>>>> Is it real to expect some of the device support this and others don't?
>>>> Is it true for ice?
>>>> If not, I would got for all-or-nothing here.
>>>>
>>>
>>>But nothing blocks vendors to provide such configuration. Should we
>>>rollback the configuration? Otherwise we can easily make it
>>>inconsistent.
>>
>>Good point, in such case rollback might be required.
>>
>>>
>>>I'm more thinking of checking if all the devices returned error (or
>>>absence of operation callback) and then return error instead of 0 with
>>>extack filled in.
>>>
>>
>>Well, what if different devices would return different errors?
>>In general we would have to keep track of the error values returned in
>>such case.. Assuming one is different than the other - still need to error
>>extack them out? I guess it would be easier to return common error if
>there
>
>In this case, it is common to return the first error hit and bail out,
>not trying the rest.
>
OK, so now I see it like this:
-> check if all device implement callback, if not return EOPNOTSUPP;
-> get old phase_adjust
-> if new == old, return EINVAL
-> for each device: call phase_adjust_set, if fails, rollback all previous
successful attempts and return the failure code
?
Thank you!
Arkadiusz
>
>>were only failures and let the driver fill the errors on extack, smt like:
>>
>> int miss_cb_num = 0, dev_num = 0, err_num;
>>
>> xa_for_each(&pin->dpll_refs, i, ref) {
>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> struct dpll_device *dpll = ref->dpll;
>>
>> dev_num++;
>> if (!ops->phase_adjust_set) {
>> miss_cb_num++;
>> continue;
>> }
>> ret = ops->phase_adjust_set(pin,
>> dpll_pin_on_dpll_priv(dpll, pin),
>> dpll, dpll_priv(dpll), phase_adj,
>> extack);
>> if (ret)
>> err_num++;
>> }
>> if (dev_num == miss_cb_num)
>> return -EOPNOTSUPP;
>> if (dev_num == err_num)
>> return -EINVAL;
>> __dpll_pin_change_ntf(pin);
>> return 0;
>>
>>??
>>
>>Thank you!
>>Arkadiusz
>>
>>>>
>>>>> If device fails to set -> add extack error, continue
>>>>> Function always returns 0.
>>>>>
>>>>> Thank you!
>>>>> Arkadiusz
>>>>>
>>>>>>
>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>> + extack);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>
>>>_______________________________________________
>>>Intel-wired-lan mailing list
>>>Intel-wired-lan@osuosl.org
>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-10-03 14:29 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-03 14:29 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, linux-doc, netdev, corbet, Brandeburg, Jesse,
Nguyen, Anthony L, kuba, intel-wired-lan, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Tuesday, October 3, 2023 8:27 AM
>To: Kubalewski, Arkadiusz <arkadiusz.kubalewski@intel.com>
>
>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>>Vadim Fedorenko
>>>Sent: Monday, October 2, 2023 5:09 PM
>>>
>>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>>> wrote:
>>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>>
>>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>>> with phase related attribute values.
>>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>>> for
>>>>>>> pin-set request.
>>>>>>>
>>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> +static int
>>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>>> *phase_adj_attr,
>>>>>>> + struct netlink_ext_ack *extack)
>>>>>>> +{
>>>>>>> + struct dpll_pin_ref *ref;
>>>>>>> + unsigned long i;
>>>>>>> + s32 phase_adj;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not
>>>>>>> supported");
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>>> +
>>>>>>> + if (!ops->phase_adjust_set)
>>>>>>> + return -EOPNOTSUPP;
>>>>>>
>>>>>> I'm thinking about this part. We can potentially have dpll devices
>>>>>> with
>>>>>> different expectations on phase adjustments, right? And if one of
>>>>>> them
>>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>>> adjusted. Doesn't look great. Can we think about different way to
>>>>>> apply
>>>>>> the change?
>>>>>>
>>>>>
>>>>> Well makes sense to me.
>>>>>
>>>>> Does following makes sense as a fix?
>>>>> We would call op for all devices which has been provided with the op.
>>>>> If device has no op -> add extack error, continue
>>>>
>>>> Is it real to expect some of the device support this and others don't?
>>>> Is it true for ice?
>>>> If not, I would got for all-or-nothing here.
>>>>
>>>
>>>But nothing blocks vendors to provide such configuration. Should we
>>>rollback the configuration? Otherwise we can easily make it
>>>inconsistent.
>>
>>Good point, in such case rollback might be required.
>>
>>>
>>>I'm more thinking of checking if all the devices returned error (or
>>>absence of operation callback) and then return error instead of 0 with
>>>extack filled in.
>>>
>>
>>Well, what if different devices would return different errors?
>>In general we would have to keep track of the error values returned in
>>such case.. Assuming one is different than the other - still need to error
>>extack them out? I guess it would be easier to return common error if
>there
>
>In this case, it is common to return the first error hit and bail out,
>not trying the rest.
>
OK, so now I see it like this:
-> check if all device implement callback, if not return EOPNOTSUPP;
-> get old phase_adjust
-> if new == old, return EINVAL
-> for each device: call phase_adjust_set, if fails, rollback all previous
successful attempts and return the failure code
?
Thank you!
Arkadiusz
>
>>were only failures and let the driver fill the errors on extack, smt like:
>>
>> int miss_cb_num = 0, dev_num = 0, err_num;
>>
>> xa_for_each(&pin->dpll_refs, i, ref) {
>> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> struct dpll_device *dpll = ref->dpll;
>>
>> dev_num++;
>> if (!ops->phase_adjust_set) {
>> miss_cb_num++;
>> continue;
>> }
>> ret = ops->phase_adjust_set(pin,
>> dpll_pin_on_dpll_priv(dpll, pin),
>> dpll, dpll_priv(dpll), phase_adj,
>> extack);
>> if (ret)
>> err_num++;
>> }
>> if (dev_num == miss_cb_num)
>> return -EOPNOTSUPP;
>> if (dev_num == err_num)
>> return -EINVAL;
>> __dpll_pin_change_ntf(pin);
>> return 0;
>>
>>??
>>
>>Thank you!
>>Arkadiusz
>>
>>>>
>>>>> If device fails to set -> add extack error, continue
>>>>> Function always returns 0.
>>>>>
>>>>> Thank you!
>>>>> Arkadiusz
>>>>>
>>>>>>
>>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>>> + extack);
>>>>>>> + if (ret)
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>
>>>_______________________________________________
>>>Intel-wired-lan mailing list
>>>Intel-wired-lan@osuosl.org
>>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 23:03 ` Kubalewski, Arkadiusz
@ 2023-10-03 6:32 ` Jiri Pirko
2023-10-03 14:29 ` Kubalewski, Arkadiusz
0 siblings, 1 reply; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 6:32 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
Tue, Oct 03, 2023 at 01:03:00AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Jiri Pirko <jiri@resnulli.us>
>>Sent: Monday, October 2, 2023 5:04 PM
>>
>>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>>
>>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>> Add min and max phase adjustment values to pin proprties.
>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>> with phase related attribute values.
>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>> for
>>>>> pin-set request.
>>>>>
>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>
>>>>[...]
>>>>
>>>>> +static int
>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>> *phase_adj_attr,
>>>>> + struct netlink_ext_ack *extack)
>>>>> +{
>>>>> + struct dpll_pin_ref *ref;
>>>>> + unsigned long i;
>>>>> + s32 phase_adj;
>>>>> + int ret;
>>>>> +
>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>> +
>>>>> + if (!ops->phase_adjust_set)
>>>>> + return -EOPNOTSUPP;
>>>>
>>>>I'm thinking about this part. We can potentially have dpll devices with
>>>>different expectations on phase adjustments, right? And if one of them
>>>>won't be able to adjust phase (or will fail in the next line), then
>>>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>adjusted. Doesn't look great. Can we think about different way to apply
>>>>the change?
>>>>
>>>
>>>Well makes sense to me.
>>>
>>>Does following makes sense as a fix?
>>>We would call op for all devices which has been provided with the op.
>>>If device has no op -> add extack error, continue
>>
>>Is it real to expect some of the device support this and others don't?
>>Is it true for ice?
>>If not, I would got for all-or-nothing here.
>>
>
>Let's step back a bit.
>The op itself is introduced as per pin-dpll tuple.. did this intentionally,
>to inform each dpll that the offset has been changed - in case dplls are
>controlled by separated driver/firmware instances but still sharing the pin.
>Same way a pin frequency is being set, from user perspective on a pin, but
>callback is called for each dpll the pin was registered with.
>Whatever we do here, it shall be probably done for frequency_set() callback as
>well.
>
>The answers:
>So far I don't know the device that might do it this way, it rather supports
>phase_adjust or not. In theory we allow such behavior to be implemented, i.e.
>pin is registered with 2 dplls, one has the callback, second not.
If there is only theoretical device like that now, implement
all-or-nothing. If such theoretical device appears in real, this could
be changed. The UAPI would not change, no problem.
>Current hardware of ice sets phase offset for a pin no matter on which dpll
>device callback was invoked.
>"all-or-nothing" - do you mean to check all callback returns and then decide
>if it was successful?
Check if all dplls have ops and only perform the action in such case. In
case one of the dplls does not have the op filled, return -EOPNOTSUPP.
Regarding the successful/failed op, I think you can just return. In
these cases, when user performs multiaction cmd, he should be prepared
to deal with consequences if part of this cmd fails. We don't have
rollback for any other multiaction cmd in dpll, I don't see why this
should be treated differently.
>
>Thank you!
>Arkadiusz
>
>>
>>>If device fails to set -> add extack error, continue
>>>Function always returns 0.
>>>
>>>Thank you!
>>>Arkadiusz
>>>
>>>>
>>>>> + ret = ops->phase_adjust_set(pin,
>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>> + extack);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> + __dpll_pin_change_ntf(pin);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 23:10 ` Kubalewski, Arkadiusz
@ 2023-10-03 6:27 ` Jiri Pirko
-1 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 6:27 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>Vadim Fedorenko
>>Sent: Monday, October 2, 2023 5:09 PM
>>
>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>> wrote:
>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>
>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>> with phase related attribute values.
>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>> for
>>>>>> pin-set request.
>>>>>>
>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>
>>>>> [...]
>>>>>
>>>>>> +static int
>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>> *phase_adj_attr,
>>>>>> + struct netlink_ext_ack *extack)
>>>>>> +{
>>>>>> + struct dpll_pin_ref *ref;
>>>>>> + unsigned long i;
>>>>>> + s32 phase_adj;
>>>>>> + int ret;
>>>>>> +
>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>>>> + return -EINVAL;
>>>>>> + }
>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>> +
>>>>>> + if (!ops->phase_adjust_set)
>>>>>> + return -EOPNOTSUPP;
>>>>>
>>>>> I'm thinking about this part. We can potentially have dpll devices with
>>>>> different expectations on phase adjustments, right? And if one of them
>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>> adjusted. Doesn't look great. Can we think about different way to apply
>>>>> the change?
>>>>>
>>>>
>>>> Well makes sense to me.
>>>>
>>>> Does following makes sense as a fix?
>>>> We would call op for all devices which has been provided with the op.
>>>> If device has no op -> add extack error, continue
>>>
>>> Is it real to expect some of the device support this and others don't?
>>> Is it true for ice?
>>> If not, I would got for all-or-nothing here.
>>>
>>
>>But nothing blocks vendors to provide such configuration. Should we
>>rollback the configuration? Otherwise we can easily make it
>>inconsistent.
>
>Good point, in such case rollback might be required.
>
>>
>>I'm more thinking of checking if all the devices returned error (or
>>absence of operation callback) and then return error instead of 0 with
>>extack filled in.
>>
>
>Well, what if different devices would return different errors?
>In general we would have to keep track of the error values returned in
>such case.. Assuming one is different than the other - still need to error
>extack them out? I guess it would be easier to return common error if there
In this case, it is common to return the first error hit and bail out,
not trying the rest.
>were only failures and let the driver fill the errors on extack, smt like:
>
> int miss_cb_num = 0, dev_num = 0, err_num;
>
> xa_for_each(&pin->dpll_refs, i, ref) {
> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> struct dpll_device *dpll = ref->dpll;
>
> dev_num++;
> if (!ops->phase_adjust_set) {
> miss_cb_num++;
> continue;
> }
> ret = ops->phase_adjust_set(pin,
> dpll_pin_on_dpll_priv(dpll, pin),
> dpll, dpll_priv(dpll), phase_adj,
> extack);
> if (ret)
> err_num++;
> }
> if (dev_num == miss_cb_num)
> return -EOPNOTSUPP;
> if (dev_num == err_num)
> return -EINVAL;
> __dpll_pin_change_ntf(pin);
> return 0;
>
>??
>
>Thank you!
>Arkadiusz
>
>>>
>>>> If device fails to set -> add extack error, continue
>>>> Function always returns 0.
>>>>
>>>> Thank you!
>>>> Arkadiusz
>>>>
>>>>>
>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>> + extack);
>>>>>> + if (ret)
>>>>>> + return ret;
>>>>>> + }
>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>
>>_______________________________________________
>>Intel-wired-lan mailing list
>>Intel-wired-lan@osuosl.org
>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-10-03 6:27 ` Jiri Pirko
0 siblings, 0 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-10-03 6:27 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, linux-doc, netdev, corbet, Brandeburg, Jesse,
Nguyen, Anthony L, kuba, intel-wired-lan, pabeni, davem
Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>>Vadim Fedorenko
>>Sent: Monday, October 2, 2023 5:09 PM
>>
>>On 02/10/2023 16:04, Jiri Pirko wrote:
>>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>>> wrote:
>>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>>
>>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>>> Add min and max phase adjustment values to pin proprties.
>>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>>> with phase related attribute values.
>>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>>> for
>>>>>> pin-set request.
>>>>>>
>>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>>
>>>>> [...]
>>>>>
>>>>>> +static int
>>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>>> *phase_adj_attr,
>>>>>> + struct netlink_ext_ack *extack)
>>>>>> +{
>>>>>> + struct dpll_pin_ref *ref;
>>>>>> + unsigned long i;
>>>>>> + s32 phase_adj;
>>>>>> + int ret;
>>>>>> +
>>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>>>> + return -EINVAL;
>>>>>> + }
>>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>>> +
>>>>>> + if (!ops->phase_adjust_set)
>>>>>> + return -EOPNOTSUPP;
>>>>>
>>>>> I'm thinking about this part. We can potentially have dpll devices with
>>>>> different expectations on phase adjustments, right? And if one of them
>>>>> won't be able to adjust phase (or will fail in the next line), then
>>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>>> adjusted. Doesn't look great. Can we think about different way to apply
>>>>> the change?
>>>>>
>>>>
>>>> Well makes sense to me.
>>>>
>>>> Does following makes sense as a fix?
>>>> We would call op for all devices which has been provided with the op.
>>>> If device has no op -> add extack error, continue
>>>
>>> Is it real to expect some of the device support this and others don't?
>>> Is it true for ice?
>>> If not, I would got for all-or-nothing here.
>>>
>>
>>But nothing blocks vendors to provide such configuration. Should we
>>rollback the configuration? Otherwise we can easily make it
>>inconsistent.
>
>Good point, in such case rollback might be required.
>
>>
>>I'm more thinking of checking if all the devices returned error (or
>>absence of operation callback) and then return error instead of 0 with
>>extack filled in.
>>
>
>Well, what if different devices would return different errors?
>In general we would have to keep track of the error values returned in
>such case.. Assuming one is different than the other - still need to error
>extack them out? I guess it would be easier to return common error if there
In this case, it is common to return the first error hit and bail out,
not trying the rest.
>were only failures and let the driver fill the errors on extack, smt like:
>
> int miss_cb_num = 0, dev_num = 0, err_num;
>
> xa_for_each(&pin->dpll_refs, i, ref) {
> const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> struct dpll_device *dpll = ref->dpll;
>
> dev_num++;
> if (!ops->phase_adjust_set) {
> miss_cb_num++;
> continue;
> }
> ret = ops->phase_adjust_set(pin,
> dpll_pin_on_dpll_priv(dpll, pin),
> dpll, dpll_priv(dpll), phase_adj,
> extack);
> if (ret)
> err_num++;
> }
> if (dev_num == miss_cb_num)
> return -EOPNOTSUPP;
> if (dev_num == err_num)
> return -EINVAL;
> __dpll_pin_change_ntf(pin);
> return 0;
>
>??
>
>Thank you!
>Arkadiusz
>
>>>
>>>> If device fails to set -> add extack error, continue
>>>> Function always returns 0.
>>>>
>>>> Thank you!
>>>> Arkadiusz
>>>>
>>>>>
>>>>>> + ret = ops->phase_adjust_set(pin,
>>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>>> + extack);
>>>>>> + if (ret)
>>>>>> + return ret;
>>>>>> + }
>>>>>> + __dpll_pin_change_ntf(pin);
>>>>>> +
>>>>>> + return 0;
>>>>>> +}
>>>>>> +
>>
>>_______________________________________________
>>Intel-wired-lan mailing list
>>Intel-wired-lan@osuosl.org
>>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* RE: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 15:09 ` Vadim Fedorenko
@ 2023-10-02 23:10 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-02 23:10 UTC (permalink / raw)
To: Vadim Fedorenko, Jiri Pirko
Cc: corbet, netdev, linux-doc, Brandeburg, Jesse, Nguyen, Anthony L,
intel-wired-lan, kuba, pabeni, davem
>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>Vadim Fedorenko
>Sent: Monday, October 2, 2023 5:09 PM
>
>On 02/10/2023 16:04, Jiri Pirko wrote:
>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>> wrote:
>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>
>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>> Add min and max phase adjustment values to pin proprties.
>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>> with phase related attribute values.
>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>> for
>>>>> pin-set request.
>>>>>
>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>
>>>> [...]
>>>>
>>>>> +static int
>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>> *phase_adj_attr,
>>>>> + struct netlink_ext_ack *extack)
>>>>> +{
>>>>> + struct dpll_pin_ref *ref;
>>>>> + unsigned long i;
>>>>> + s32 phase_adj;
>>>>> + int ret;
>>>>> +
>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>> +
>>>>> + if (!ops->phase_adjust_set)
>>>>> + return -EOPNOTSUPP;
>>>>
>>>> I'm thinking about this part. We can potentially have dpll devices with
>>>> different expectations on phase adjustments, right? And if one of them
>>>> won't be able to adjust phase (or will fail in the next line), then
>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>> adjusted. Doesn't look great. Can we think about different way to apply
>>>> the change?
>>>>
>>>
>>> Well makes sense to me.
>>>
>>> Does following makes sense as a fix?
>>> We would call op for all devices which has been provided with the op.
>>> If device has no op -> add extack error, continue
>>
>> Is it real to expect some of the device support this and others don't?
>> Is it true for ice?
>> If not, I would got for all-or-nothing here.
>>
>
>But nothing blocks vendors to provide such configuration. Should we
>rollback the configuration? Otherwise we can easily make it
>inconsistent.
Good point, in such case rollback might be required.
>
>I'm more thinking of checking if all the devices returned error (or
>absence of operation callback) and then return error instead of 0 with
>extack filled in.
>
Well, what if different devices would return different errors?
In general we would have to keep track of the error values returned in
such case.. Assuming one is different than the other - still need to error
extack them out? I guess it would be easier to return common error if there
were only failures and let the driver fill the errors on extack, smt like:
int miss_cb_num = 0, dev_num = 0, err_num;
xa_for_each(&pin->dpll_refs, i, ref) {
const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
struct dpll_device *dpll = ref->dpll;
dev_num++;
if (!ops->phase_adjust_set) {
miss_cb_num++;
continue;
}
ret = ops->phase_adjust_set(pin,
dpll_pin_on_dpll_priv(dpll, pin),
dpll, dpll_priv(dpll), phase_adj,
extack);
if (ret)
err_num++;
}
if (dev_num == miss_cb_num)
return -EOPNOTSUPP;
if (dev_num == err_num)
return -EINVAL;
__dpll_pin_change_ntf(pin);
return 0;
??
Thank you!
Arkadiusz
>>
>>> If device fails to set -> add extack error, continue
>>> Function always returns 0.
>>>
>>> Thank you!
>>> Arkadiusz
>>>
>>>>
>>>>> + ret = ops->phase_adjust_set(pin,
>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>> + extack);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> + __dpll_pin_change_ntf(pin);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>
>_______________________________________________
>Intel-wired-lan mailing list
>Intel-wired-lan@osuosl.org
>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
@ 2023-10-02 23:10 ` Kubalewski, Arkadiusz
0 siblings, 0 replies; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-02 23:10 UTC (permalink / raw)
To: Vadim Fedorenko, Jiri Pirko
Cc: linux-doc, netdev, corbet, Brandeburg, Jesse, intel-wired-lan,
kuba, Nguyen, Anthony L, pabeni, davem
>From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of
>Vadim Fedorenko
>Sent: Monday, October 2, 2023 5:09 PM
>
>On 02/10/2023 16:04, Jiri Pirko wrote:
>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com
>> wrote:
>>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>>
>>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>>> Add min and max phase adjustment values to pin proprties.
>>>>> Invoke get callbacks when filling up the pin details to provide user
>>>>> with phase related attribute values.
>>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>>> for
>>>>> pin-set request.
>>>>>
>>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>>
>>>> [...]
>>>>
>>>>> +static int
>>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>>> *phase_adj_attr,
>>>>> + struct netlink_ext_ack *extack)
>>>>> +{
>>>>> + struct dpll_pin_ref *ref;
>>>>> + unsigned long i;
>>>>> + s32 phase_adj;
>>>>> + int ret;
>>>>> +
>>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>>> + phase_adj < pin->prop->phase_range.min) {
>>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>>> + return -EINVAL;
>>>>> + }
>>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>>> + struct dpll_device *dpll = ref->dpll;
>>>>> +
>>>>> + if (!ops->phase_adjust_set)
>>>>> + return -EOPNOTSUPP;
>>>>
>>>> I'm thinking about this part. We can potentially have dpll devices with
>>>> different expectations on phase adjustments, right? And if one of them
>>>> won't be able to adjust phase (or will fail in the next line), then
>>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>> adjusted. Doesn't look great. Can we think about different way to apply
>>>> the change?
>>>>
>>>
>>> Well makes sense to me.
>>>
>>> Does following makes sense as a fix?
>>> We would call op for all devices which has been provided with the op.
>>> If device has no op -> add extack error, continue
>>
>> Is it real to expect some of the device support this and others don't?
>> Is it true for ice?
>> If not, I would got for all-or-nothing here.
>>
>
>But nothing blocks vendors to provide such configuration. Should we
>rollback the configuration? Otherwise we can easily make it
>inconsistent.
Good point, in such case rollback might be required.
>
>I'm more thinking of checking if all the devices returned error (or
>absence of operation callback) and then return error instead of 0 with
>extack filled in.
>
Well, what if different devices would return different errors?
In general we would have to keep track of the error values returned in
such case.. Assuming one is different than the other - still need to error
extack them out? I guess it would be easier to return common error if there
were only failures and let the driver fill the errors on extack, smt like:
int miss_cb_num = 0, dev_num = 0, err_num;
xa_for_each(&pin->dpll_refs, i, ref) {
const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
struct dpll_device *dpll = ref->dpll;
dev_num++;
if (!ops->phase_adjust_set) {
miss_cb_num++;
continue;
}
ret = ops->phase_adjust_set(pin,
dpll_pin_on_dpll_priv(dpll, pin),
dpll, dpll_priv(dpll), phase_adj,
extack);
if (ret)
err_num++;
}
if (dev_num == miss_cb_num)
return -EOPNOTSUPP;
if (dev_num == err_num)
return -EINVAL;
__dpll_pin_change_ntf(pin);
return 0;
??
Thank you!
Arkadiusz
>>
>>> If device fails to set -> add extack error, continue
>>> Function always returns 0.
>>>
>>> Thank you!
>>> Arkadiusz
>>>
>>>>
>>>>> + ret = ops->phase_adjust_set(pin,
>>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>>> + extack);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + }
>>>>> + __dpll_pin_change_ntf(pin);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>
>_______________________________________________
>Intel-wired-lan mailing list
>Intel-wired-lan@osuosl.org
>https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 15:04 ` Jiri Pirko
2023-10-02 15:09 ` Vadim Fedorenko
@ 2023-10-02 23:03 ` Kubalewski, Arkadiusz
2023-10-03 6:32 ` Jiri Pirko
1 sibling, 1 reply; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-02 23:03 UTC (permalink / raw)
To: Jiri Pirko
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
>From: Jiri Pirko <jiri@resnulli.us>
>Sent: Monday, October 2, 2023 5:04 PM
>
>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>
>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>> Add min and max phase adjustment values to pin proprties.
>>>> Invoke get callbacks when filling up the pin details to provide user
>>>> with phase related attribute values.
>>>> Invoke phase-adjust set callback when phase-adjust value is provided
>>>> for
>>>> pin-set request.
>>>>
>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>
>>>[...]
>>>
>>>> +static int
>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>> *phase_adj_attr,
>>>> + struct netlink_ext_ack *extack)
>>>> +{
>>>> + struct dpll_pin_ref *ref;
>>>> + unsigned long i;
>>>> + s32 phase_adj;
>>>> + int ret;
>>>> +
>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>> + phase_adj < pin->prop->phase_range.min) {
>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>> + return -EINVAL;
>>>> + }
>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>> + struct dpll_device *dpll = ref->dpll;
>>>> +
>>>> + if (!ops->phase_adjust_set)
>>>> + return -EOPNOTSUPP;
>>>
>>>I'm thinking about this part. We can potentially have dpll devices with
>>>different expectations on phase adjustments, right? And if one of them
>>>won't be able to adjust phase (or will fail in the next line), then
>>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>>adjusted. Doesn't look great. Can we think about different way to apply
>>>the change?
>>>
>>
>>Well makes sense to me.
>>
>>Does following makes sense as a fix?
>>We would call op for all devices which has been provided with the op.
>>If device has no op -> add extack error, continue
>
>Is it real to expect some of the device support this and others don't?
>Is it true for ice?
>If not, I would got for all-or-nothing here.
>
Let's step back a bit.
The op itself is introduced as per pin-dpll tuple.. did this intentionally,
to inform each dpll that the offset has been changed - in case dplls are
controlled by separated driver/firmware instances but still sharing the pin.
Same way a pin frequency is being set, from user perspective on a pin, but
callback is called for each dpll the pin was registered with.
Whatever we do here, it shall be probably done for frequency_set() callback as
well.
The answers:
So far I don't know the device that might do it this way, it rather supports
phase_adjust or not. In theory we allow such behavior to be implemented, i.e.
pin is registered with 2 dplls, one has the callback, second not.
Current hardware of ice sets phase offset for a pin no matter on which dpll
device callback was invoked.
"all-or-nothing" - do you mean to check all callback returns and then decide
if it was successful?
Thank you!
Arkadiusz
>
>>If device fails to set -> add extack error, continue
>>Function always returns 0.
>>
>>Thank you!
>>Arkadiusz
>>
>>>
>>>> + ret = ops->phase_adjust_set(pin,
>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>> + extack);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> + __dpll_pin_change_ntf(pin);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 15:04 ` Jiri Pirko
@ 2023-10-02 15:09 ` Vadim Fedorenko
2023-10-02 23:10 ` Kubalewski, Arkadiusz
2023-10-02 23:03 ` Kubalewski, Arkadiusz
1 sibling, 1 reply; 50+ messages in thread
From: Vadim Fedorenko @ 2023-10-02 15:09 UTC (permalink / raw)
To: Jiri Pirko, Kubalewski, Arkadiusz
Cc: corbet, netdev, linux-doc, Brandeburg, Jesse, Nguyen, Anthony L,
intel-wired-lan, kuba, pabeni, davem
On 02/10/2023 16:04, Jiri Pirko wrote:
> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>> From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>> Sent: Wednesday, September 27, 2023 8:09 PM
>>>
>>> On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>>> Add callback ops (get/set) for pin signal phase adjustment.
>>>> Add min and max phase adjustment values to pin proprties.
>>>> Invoke get callbacks when filling up the pin details to provide user
>>>> with phase related attribute values.
>>>> Invoke phase-adjust set callback when phase-adjust value is provided for
>>>> pin-set request.
>>>>
>>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>>
>>> [...]
>>>
>>>> +static int
>>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>>> *phase_adj_attr,
>>>> + struct netlink_ext_ack *extack)
>>>> +{
>>>> + struct dpll_pin_ref *ref;
>>>> + unsigned long i;
>>>> + s32 phase_adj;
>>>> + int ret;
>>>> +
>>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>>> + if (phase_adj > pin->prop->phase_range.max ||
>>>> + phase_adj < pin->prop->phase_range.min) {
>>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>>> + return -EINVAL;
>>>> + }
>>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>>> + struct dpll_device *dpll = ref->dpll;
>>>> +
>>>> + if (!ops->phase_adjust_set)
>>>> + return -EOPNOTSUPP;
>>>
>>> I'm thinking about this part. We can potentially have dpll devices with
>>> different expectations on phase adjustments, right? And if one of them
>>> won't be able to adjust phase (or will fail in the next line), then
>>> netlink will return EOPNOTSUPP while _some_ of the devices will be
>>> adjusted. Doesn't look great. Can we think about different way to apply
>>> the change?
>>>
>>
>> Well makes sense to me.
>>
>> Does following makes sense as a fix?
>> We would call op for all devices which has been provided with the op.
>> If device has no op -> add extack error, continue
>
> Is it real to expect some of the device support this and others don't?
> Is it true for ice?
> If not, I would got for all-or-nothing here.
>
But nothing blocks vendors to provide such configuration. Should we
rollback the configuration? Otherwise we can easily make it
inconsistent.
I'm more thinking of checking if all the devices returned error (or
absence of operation callback) and then return error instead of 0 with
extack filled in.
>
>> If device fails to set -> add extack error, continue
>> Function always returns 0.
>>
>> Thank you!
>> Arkadiusz
>>
>>>
>>>> + ret = ops->phase_adjust_set(pin,
>>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>>> + dpll, dpll_priv(dpll), phase_adj,
>>>> + extack);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> + __dpll_pin_change_ntf(pin);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-10-02 14:32 ` Kubalewski, Arkadiusz
@ 2023-10-02 15:04 ` Jiri Pirko
2023-10-02 15:09 ` Vadim Fedorenko
2023-10-02 23:03 ` Kubalewski, Arkadiusz
0 siblings, 2 replies; 50+ messages in thread
From: Jiri Pirko @ 2023-10-02 15:04 UTC (permalink / raw)
To: Kubalewski, Arkadiusz
Cc: Vadim Fedorenko, corbet, netdev, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, intel-wired-lan, kuba, pabeni, davem
Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalewski@intel.com wrote:
>>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>>Sent: Wednesday, September 27, 2023 8:09 PM
>>
>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>>> Add callback op (get) for pin-dpll phase-offset measurment.
>>> Add callback ops (get/set) for pin signal phase adjustment.
>>> Add min and max phase adjustment values to pin proprties.
>>> Invoke get callbacks when filling up the pin details to provide user
>>> with phase related attribute values.
>>> Invoke phase-adjust set callback when phase-adjust value is provided for
>>> pin-set request.
>>>
>>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>>
>>[...]
>>
>>> +static int
>>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>>> *phase_adj_attr,
>>> + struct netlink_ext_ack *extack)
>>> +{
>>> + struct dpll_pin_ref *ref;
>>> + unsigned long i;
>>> + s32 phase_adj;
>>> + int ret;
>>> +
>>> + phase_adj = nla_get_s32(phase_adj_attr);
>>> + if (phase_adj > pin->prop->phase_range.max ||
>>> + phase_adj < pin->prop->phase_range.min) {
>>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>>> + return -EINVAL;
>>> + }
>>> + xa_for_each(&pin->dpll_refs, i, ref) {
>>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>>> + struct dpll_device *dpll = ref->dpll;
>>> +
>>> + if (!ops->phase_adjust_set)
>>> + return -EOPNOTSUPP;
>>
>>I'm thinking about this part. We can potentially have dpll devices with
>>different expectations on phase adjustments, right? And if one of them
>>won't be able to adjust phase (or will fail in the next line), then
>>netlink will return EOPNOTSUPP while _some_ of the devices will be
>>adjusted. Doesn't look great. Can we think about different way to apply
>>the change?
>>
>
>Well makes sense to me.
>
>Does following makes sense as a fix?
>We would call op for all devices which has been provided with the op.
>If device has no op -> add extack error, continue
Is it real to expect some of the device support this and others don't?
Is it true for ice?
If not, I would got for all-or-nothing here.
>If device fails to set -> add extack error, continue
>Function always returns 0.
>
>Thank you!
>Arkadiusz
>
>>
>>> + ret = ops->phase_adjust_set(pin,
>>> + dpll_pin_on_dpll_priv(dpll, pin),
>>> + dpll, dpll_priv(dpll), phase_adj,
>>> + extack);
>>> + if (ret)
>>> + return ret;
>>> + }
>>> + __dpll_pin_change_ntf(pin);
>>> +
>>> + return 0;
>>> +}
>>> +
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https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-27 18:09 ` Vadim Fedorenko
@ 2023-10-02 14:32 ` Kubalewski, Arkadiusz
2023-10-02 15:04 ` Jiri Pirko
0 siblings, 1 reply; 50+ messages in thread
From: Kubalewski, Arkadiusz @ 2023-10-02 14:32 UTC (permalink / raw)
To: Vadim Fedorenko, netdev
Cc: jiri, corbet, intel-wired-lan, linux-doc, Brandeburg, Jesse,
Nguyen, Anthony L, kuba, pabeni, davem
>From: Vadim Fedorenko <vadim.fedorenko@linux.dev>
>Sent: Wednesday, September 27, 2023 8:09 PM
>
>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>> Add callback op (get) for pin-dpll phase-offset measurment.
>> Add callback ops (get/set) for pin signal phase adjustment.
>> Add min and max phase adjustment values to pin proprties.
>> Invoke get callbacks when filling up the pin details to provide user
>> with phase related attribute values.
>> Invoke phase-adjust set callback when phase-adjust value is provided for
>> pin-set request.
>>
>> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
>
>[...]
>
>> +static int
>> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr
>> *phase_adj_attr,
>> + struct netlink_ext_ack *extack)
>> +{
>> + struct dpll_pin_ref *ref;
>> + unsigned long i;
>> + s32 phase_adj;
>> + int ret;
>> +
>> + phase_adj = nla_get_s32(phase_adj_attr);
>> + if (phase_adj > pin->prop->phase_range.max ||
>> + phase_adj < pin->prop->phase_range.min) {
>> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
>> + return -EINVAL;
>> + }
>> + xa_for_each(&pin->dpll_refs, i, ref) {
>> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
>> + struct dpll_device *dpll = ref->dpll;
>> +
>> + if (!ops->phase_adjust_set)
>> + return -EOPNOTSUPP;
>
>I'm thinking about this part. We can potentially have dpll devices with
>different expectations on phase adjustments, right? And if one of them
>won't be able to adjust phase (or will fail in the next line), then
>netlink will return EOPNOTSUPP while _some_ of the devices will be
>adjusted. Doesn't look great. Can we think about different way to apply
>the change?
>
Well makes sense to me.
Does following makes sense as a fix?
We would call op for all devices which has been provided with the op.
If device has no op -> add extack error, continue
If device fails to set -> add extack error, continue
Function always returns 0.
Thank you!
Arkadiusz
>
>> + ret = ops->phase_adjust_set(pin,
>> + dpll_pin_on_dpll_priv(dpll, pin),
>> + dpll, dpll_priv(dpll), phase_adj,
>> + extack);
>> + if (ret)
>> + return ret;
>> + }
>> + __dpll_pin_change_ntf(pin);
>> +
>> + return 0;
>> +}
>> +
_______________________________________________
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https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-27 9:24 ` [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust Arkadiusz Kubalewski
@ 2023-09-27 18:09 ` Vadim Fedorenko
2023-10-02 14:32 ` Kubalewski, Arkadiusz
0 siblings, 1 reply; 50+ messages in thread
From: Vadim Fedorenko @ 2023-09-27 18:09 UTC (permalink / raw)
To: Arkadiusz Kubalewski, netdev
Cc: jiri, corbet, intel-wired-lan, linux-doc, jesse.brandeburg,
anthony.l.nguyen, kuba, pabeni, davem
On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
> Add callback op (get) for pin-dpll phase-offset measurment.
> Add callback ops (get/set) for pin signal phase adjustment.
> Add min and max phase adjustment values to pin proprties.
> Invoke get callbacks when filling up the pin details to provide user
> with phase related attribute values.
> Invoke phase-adjust set callback when phase-adjust value is provided for
> pin-set request.
>
> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
[...]
> +static int
> +dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
> + struct netlink_ext_ack *extack)
> +{
> + struct dpll_pin_ref *ref;
> + unsigned long i;
> + s32 phase_adj;
> + int ret;
> +
> + phase_adj = nla_get_s32(phase_adj_attr);
> + if (phase_adj > pin->prop->phase_range.max ||
> + phase_adj < pin->prop->phase_range.min) {
> + NL_SET_ERR_MSG(extack, "phase adjust value not supported");
> + return -EINVAL;
> + }
> + xa_for_each(&pin->dpll_refs, i, ref) {
> + const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
> + struct dpll_device *dpll = ref->dpll;
> +
> + if (!ops->phase_adjust_set)
> + return -EOPNOTSUPP;
I'm thinking about this part. We can potentially have dpll devices with
different expectations on phase adjustments, right? And if one of them
won't be able to adjust phase (or will fail in the next line), then
netlink will return EOPNOTSUPP while _some_ of the devices will be
adjusted. Doesn't look great. Can we think about different way to apply
the change?
> + ret = ops->phase_adjust_set(pin,
> + dpll_pin_on_dpll_priv(dpll, pin),
> + dpll, dpll_priv(dpll), phase_adj,
> + extack);
> + if (ret)
> + return ret;
> + }
> + __dpll_pin_change_ntf(pin);
> +
> + return 0;
> +}
> +
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^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust
2023-09-27 9:24 [PATCH net-next 0/4] dpll: add phase-offset and phase-adjust Arkadiusz Kubalewski
@ 2023-09-27 9:24 ` Arkadiusz Kubalewski
2023-09-27 18:09 ` Vadim Fedorenko
0 siblings, 1 reply; 50+ messages in thread
From: Arkadiusz Kubalewski @ 2023-09-27 9:24 UTC (permalink / raw)
To: netdev
Cc: jiri, corbet, intel-wired-lan, linux-doc, jesse.brandeburg,
Arkadiusz Kubalewski, anthony.l.nguyen, kuba, vadim.fedorenko,
pabeni, davem
Add callback op (get) for pin-dpll phase-offset measurment.
Add callback ops (get/set) for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke get callbacks when filling up the pin details to provide user
with phase related attribute values.
Invoke phase-adjust set callback when phase-adjust value is provided for
pin-set request.
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
---
drivers/dpll/dpll_netlink.c | 99 ++++++++++++++++++++++++++++++++++++-
include/linux/dpll.h | 18 +++++++
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
index e20daba6896a..b48fd556e490 100644
--- a/drivers/dpll/dpll_netlink.c
+++ b/drivers/dpll/dpll_netlink.c
@@ -212,6 +212,53 @@ dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
return 0;
}
+static int
+dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s32 phase_adjust;
+ int ret;
+
+ if (!ops->phase_adjust_get)
+ return 0;
+ ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll),
+ &phase_adjust, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
+static int
+dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
+ struct dpll_pin_ref *ref,
+ struct netlink_ext_ack *extack)
+{
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+ s64 phase_offset;
+ int ret;
+
+ if (!ops->phase_offset_get)
+ return 0;
+ ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), &phase_offset,
+ extack);
+ if (ret)
+ return ret;
+ if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset),
+ &phase_offset, DPLL_A_PIN_PAD))
+ return -EMSGSIZE;
+
+ return 0;
+}
+
static int
dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
struct dpll_pin_ref *ref, struct netlink_ext_ack *extack)
@@ -330,6 +377,9 @@ dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
if (ret)
goto nest_cancel;
ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
+ if (ret)
+ goto nest_cancel;
+ ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
if (ret)
goto nest_cancel;
nla_nest_end(msg, attr);
@@ -377,6 +427,15 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities))
return -EMSGSIZE;
ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
+ if (ret)
+ return ret;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
+ prop->phase_range.min))
+ return -EMSGSIZE;
+ if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX,
+ prop->phase_range.max))
+ return -EMSGSIZE;
+ ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
if (ret)
return ret;
if (xa_empty(&pin->parent_refs))
@@ -416,7 +475,7 @@ dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,
if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))
return -EMSGSIZE;
- return ret;
+ return 0;
}
static int
@@ -705,6 +764,39 @@ dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
return 0;
}
+static int
+dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
+ struct netlink_ext_ack *extack)
+{
+ struct dpll_pin_ref *ref;
+ unsigned long i;
+ s32 phase_adj;
+ int ret;
+
+ phase_adj = nla_get_s32(phase_adj_attr);
+ if (phase_adj > pin->prop->phase_range.max ||
+ phase_adj < pin->prop->phase_range.min) {
+ NL_SET_ERR_MSG(extack, "phase adjust value not supported");
+ return -EINVAL;
+ }
+ xa_for_each(&pin->dpll_refs, i, ref) {
+ const struct dpll_pin_ops *ops = dpll_pin_ops(ref);
+ struct dpll_device *dpll = ref->dpll;
+
+ if (!ops->phase_adjust_set)
+ return -EOPNOTSUPP;
+ ret = ops->phase_adjust_set(pin,
+ dpll_pin_on_dpll_priv(dpll, pin),
+ dpll, dpll_priv(dpll), phase_adj,
+ extack);
+ if (ret)
+ return ret;
+ }
+ __dpll_pin_change_ntf(pin);
+
+ return 0;
+}
+
static int
dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
struct netlink_ext_ack *extack)
@@ -793,6 +885,11 @@ dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
if (ret)
return ret;
break;
+ case DPLL_A_PIN_PHASE_ADJUST:
+ ret = dpll_pin_phase_adj_set(pin, a, info->extack);
+ if (ret)
+ return ret;
+ break;
case DPLL_A_PIN_PARENT_DEVICE:
ret = dpll_pin_parent_device_set(pin, a, info->extack);
if (ret)
diff --git a/include/linux/dpll.h b/include/linux/dpll.h
index bbc480cd2932..578fc5fa3750 100644
--- a/include/linux/dpll.h
+++ b/include/linux/dpll.h
@@ -68,6 +68,18 @@ struct dpll_pin_ops {
int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
const struct dpll_device *dpll, void *dpll_priv,
const u32 prio, struct netlink_ext_ack *extack);
+ int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s64 *phase_offset,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ s32 *phase_adjust,
+ struct netlink_ext_ack *extack);
+ int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
+ const struct dpll_device *dpll, void *dpll_priv,
+ const s32 phase_adjust,
+ struct netlink_ext_ack *extack);
};
struct dpll_pin_frequency {
@@ -91,6 +103,11 @@ struct dpll_pin_frequency {
#define DPLL_PIN_FREQUENCY_DCF77 \
DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
+struct dpll_pin_phase_adjust_range {
+ s32 min;
+ s32 max;
+};
+
struct dpll_pin_properties {
const char *board_label;
const char *panel_label;
@@ -99,6 +116,7 @@ struct dpll_pin_properties {
unsigned long capabilities;
u32 freq_supported_num;
struct dpll_pin_frequency *freq_supported;
+ struct dpll_pin_phase_adjust_range phase_range;
};
#if IS_ENABLED(CONFIG_DPLL)
--
2.38.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
end of thread, other threads:[~2023-10-04 9:13 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-05 23:26 [PATCH net-next 0/4] dpll: add phase offset and phase adjust Arkadiusz Kubalewski
2023-09-05 23:26 ` Arkadiusz Kubalewski
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
2023-09-05 23:26 ` [PATCH net-next 1/4] dpll: docs: add support for pin signal phase offset/adjust Arkadiusz Kubalewski
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
2023-09-05 23:26 ` Arkadiusz Kubalewski
2023-09-05 23:26 ` [PATCH net-next 2/4] dpll: spec: add support for pin-dpll " Arkadiusz Kubalewski
2023-09-05 23:26 ` Arkadiusz Kubalewski
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
2023-09-05 23:26 ` [PATCH net-next 3/4] dpll: netlink/core: " Arkadiusz Kubalewski
2023-09-05 23:26 ` Arkadiusz Kubalewski
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
2023-09-06 8:02 ` Drewek, Wojciech
2023-09-06 8:02 ` Drewek, Wojciech
2023-09-06 8:02 ` Drewek, Wojciech
2023-09-06 10:26 ` Kubalewski, Arkadiusz
2023-09-06 10:26 ` Kubalewski, Arkadiusz
2023-09-06 10:26 ` Kubalewski, Arkadiusz
2023-09-06 11:45 ` Drewek, Wojciech
2023-09-06 11:45 ` Drewek, Wojciech
2023-09-06 11:45 ` Drewek, Wojciech
2023-09-05 23:26 ` [PATCH net-next 4/4] ice: dpll: implement pin phase related callbacks Arkadiusz Kubalewski
2023-09-05 23:26 ` Arkadiusz Kubalewski
2023-09-05 23:26 ` [Intel-wired-lan] " Arkadiusz Kubalewski
2023-09-06 8:37 ` [PATCH net-next 0/4] dpll: add phase offset and phase adjust Jiri Pirko
2023-09-06 8:37 ` Jiri Pirko
2023-09-06 8:37 ` [Intel-wired-lan] " Jiri Pirko
2023-09-06 10:30 ` Kubalewski, Arkadiusz
2023-09-06 10:30 ` Kubalewski, Arkadiusz
2023-09-06 10:30 ` [Intel-wired-lan] " Kubalewski, Arkadiusz
2023-09-27 9:24 [PATCH net-next 0/4] dpll: add phase-offset and phase-adjust Arkadiusz Kubalewski
2023-09-27 9:24 ` [Intel-wired-lan] [PATCH net-next 3/4] dpll: netlink/core: add support for pin-dpll signal phase offset/adjust Arkadiusz Kubalewski
2023-09-27 18:09 ` Vadim Fedorenko
2023-10-02 14:32 ` Kubalewski, Arkadiusz
2023-10-02 15:04 ` Jiri Pirko
2023-10-02 15:09 ` Vadim Fedorenko
2023-10-02 23:10 ` Kubalewski, Arkadiusz
2023-10-02 23:10 ` Kubalewski, Arkadiusz
2023-10-03 6:27 ` Jiri Pirko
2023-10-03 6:27 ` Jiri Pirko
2023-10-03 14:29 ` Kubalewski, Arkadiusz
2023-10-03 14:29 ` Kubalewski, Arkadiusz
2023-10-03 17:18 ` Jiri Pirko
2023-10-03 17:18 ` Jiri Pirko
2023-10-04 9:13 ` Kubalewski, Arkadiusz
2023-10-04 9:13 ` Kubalewski, Arkadiusz
2023-10-02 23:03 ` Kubalewski, Arkadiusz
2023-10-03 6:32 ` Jiri Pirko
2023-10-03 14:29 ` Kubalewski, Arkadiusz
2023-10-03 17:19 ` Jiri Pirko
2023-10-04 9:11 ` Kubalewski, Arkadiusz
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