* [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes
@ 2023-07-25 21:27 Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Gustavo Sousa
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-25 21:27 UTC (permalink / raw)
To: intel-gfx
While 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD")
fixes the problem for lane reset logic, there are also more parts of the
implementation that need to take owned PHY lanes into consideration.
This series provides fixes for such places. The changes to the logic
have been tested on a machine with a Type-C connection in DP-Alt mode
using pin assignment D. In that mode, only PHY lane 0 is owned by
display and, without these fixes, we get message bus timeout errors
because we try to perform reads/writes on registers for the not-owned
PHY.
Gustavo Sousa (4):
drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
drm/i915: Simplify intel_cx0_program_phy_lane() with loop
drm/i915/cx0: Enable/disable TX only for owned PHY lanes
drm/i915/cx0: Program vswing only for owned lanes
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 155 ++++++++-----------
1 file changed, 66 insertions(+), 89 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
@ 2023-07-25 21:27 ` Gustavo Sousa
2023-08-02 21:41 ` Taylor, Clinton A
2023-07-25 21:27 ` [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop Gustavo Sousa
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-25 21:27 UTC (permalink / raw)
To: intel-gfx
There are more parts of C10/C20 programming that need to take owned
lanes into account. Define the function intel_cx0_get_owned_lane_mask()
and use it. There will be new users of that function in upcoming
changes.
BSpec: 64539
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++--------
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..b903ceb0b56a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
return ilog2(lane_mask);
}
+static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
+ struct intel_encoder *encoder)
+{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+ if (!intel_tc_port_in_dp_alt_mode(dig_port))
+ return INTEL_CX0_BOTH_LANES;
+
+ /*
+ * In DP-alt with pin assignment D, only PHY lane 0 is owned
+ * by display and lane 1 is owned by USB.
+ */
+ return intel_tc_port_fia_max_lane_count(dig_port) > 2
+ ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
+}
+
static void
assert_dc_off(struct drm_i915_private *i915)
{
@@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
{
enum port port = encoder->port;
enum phy phy = intel_port_to_phy(i915, port);
- bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
- u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
- INTEL_CX0_LANE0;
- u32 lane_pipe_reset = both_lanes ?
- XELPDP_LANE_PIPE_RESET(0) |
- XELPDP_LANE_PIPE_RESET(1) :
- XELPDP_LANE_PIPE_RESET(0);
- u32 lane_phy_current_status = both_lanes ?
- XELPDP_LANE_PHY_CURRENT_STATUS(0) |
- XELPDP_LANE_PHY_CURRENT_STATUS(1) :
- XELPDP_LANE_PHY_CURRENT_STATUS(0);
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
+ u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
+ u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
+ ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
+ : XELPDP_LANE_PIPE_RESET(0);
+ u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
+ ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
+ XELPDP_LANE_PHY_CURRENT_STATUS(1))
+ : XELPDP_LANE_PHY_CURRENT_STATUS(0);
if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
XELPDP_PORT_BUF_SOC_PHY_READY,
@@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
- intel_cx0_get_pclk_refclk_request(both_lanes ?
- INTEL_CX0_BOTH_LANES :
- INTEL_CX0_LANE0),
+ intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
- intel_cx0_get_pclk_refclk_ack(both_lanes ?
- INTEL_CX0_BOTH_LANES :
- INTEL_CX0_LANE0),
+ intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
--
2.41.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Gustavo Sousa
@ 2023-07-25 21:27 ` Gustavo Sousa
2023-07-31 11:04 ` Jani Nikula
2023-07-25 21:27 ` [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes Gustavo Sousa
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-25 21:27 UTC (permalink / raw)
To: intel-gfx
It is possible to generalize the "disable" value for the transmitters to
be a bit mask based on the port width and the port reversal boolean,
with a small exception for DP-alt mode with "x1" port width.
Simplify the code by using such a mask and a for-loop instead of using
switch-case statements.
BSpec: 64539
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
1 file changed, 20 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b903ceb0b56a..f10ebdfd696a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
struct intel_encoder *encoder, int lane_count,
bool lane_reversal)
{
- u8 l0t1, l0t2, l1t1, l1t2;
+ int i;
+ u8 disables;
bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
enum port port = encoder->port;
@@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
- /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
- l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
- l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
- l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
- l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
-
- l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
- l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
- l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
- l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
-
- if (lane_reversal) {
- switch (lane_count) {
- case 4:
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 3:
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 2:
- l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 1:
- l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- default:
- MISSING_CASE(lane_count);
- }
- } else {
- switch (lane_count) {
- case 4:
- l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 3:
- l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- fallthrough;
- case 2:
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- case 1:
- if (dp_alt_mode)
- l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
- else
- l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
- break;
- default:
- MISSING_CASE(lane_count);
- }
+ if (lane_reversal)
+ disables = REG_GENMASK8(3, 0) >> lane_count;
+ else
+ disables = REG_GENMASK8(3, 0) << lane_count;
+
+ if (dp_alt_mode && lane_count == 1) {
+ disables &= ~REG_GENMASK8(1, 0);
+ disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
}
- /* disable MLs */
- intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
- l0t1, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
- l0t2, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
- l1t1, MB_WRITE_COMMITTED);
- intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
- l1t2, MB_WRITE_COMMITTED);
+ /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
+ for (i = 0; i < 4; i++) {
+ int tx = i % 2 + 1;
+ u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+
+ intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
+ CONTROL2_DISABLE_SINGLE_TX,
+ disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
+ MB_WRITE_COMMITTED);
+ }
if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
--
2.41.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop Gustavo Sousa
@ 2023-07-25 21:27 ` Gustavo Sousa
2023-08-14 9:25 ` Kahola, Mika
2023-07-25 21:27 ` [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes Gustavo Sousa
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-25 21:27 UTC (permalink / raw)
To: intel-gfx
Display must not enable or disable transmitters for not-owned PHY lanes.
BSpec: 64539
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f10ebdfd696a..236124786631 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
int i;
u8 disables;
bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
enum port port = encoder->port;
if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_MSGBUS_ACCESS,
MB_WRITE_COMMITTED);
@@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
}
- /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
for (i = 0; i < 4; i++) {
int tx = i % 2 + 1;
u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+ if (!(owned_lane_mask & lane_mask))
+ continue;
+
intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
CONTROL2_DISABLE_SINGLE_TX,
disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
@@ -2637,7 +2640,7 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
}
if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
+ intel_cx0_rmw(i915, port, owned_lane_mask,
PHY_C10_VDR_CONTROL(1), 0,
C10_VDR_CTRL_UPDATE_CFG,
MB_WRITE_COMMITTED);
--
2.41.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
` (2 preceding siblings ...)
2023-07-25 21:27 ` [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes Gustavo Sousa
@ 2023-07-25 21:27 ` Gustavo Sousa
2023-08-14 9:27 ` Kahola, Mika
2023-07-25 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Fix C10/C20 implementation w.r.t. owned PHY lanes Patchwork
2023-07-26 4:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-25 21:27 UTC (permalink / raw)
To: intel-gfx
According to the BSpec, voltage swing programming should be done for
owned PHY lanes. Do not program a not-owned PHY lane.
BSpec: 74103, 74104
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 236124786631..cfb2093feb3b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
intel_wakeref_t wakeref;
int n_entries, ln;
@@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
}
if (intel_is_c10phy(i915, phy)) {
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CMN(3),
C10_CMN3_TXVBOOST_MASK,
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
MB_WRITE_UNCOMMITTED);
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_TX(1),
C10_TX1_TERMCTL_MASK,
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
MB_WRITE_COMMITTED);
@@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
for (ln = 0; ln < crtc_state->lane_count; ln++) {
int level = intel_ddi_level(encoder, crtc_state, ln);
- int lane, tx;
+ int lane = ln / 2;
+ int tx = ln % 2;
+ u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
- lane = ln / 2;
- tx = ln % 2;
+ if (!(lane_mask & owned_lane_mask))
+ continue;
- intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
MB_WRITE_COMMITTED);
- intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
+ intel_cx0_rmw(i915, encoder->port, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
MB_WRITE_COMMITTED);
}
/* Write Override enables in 0xD71 */
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
MB_WRITE_COMMITTED);
if (intel_is_c10phy(i915, phy))
- intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
intel_cx0_phy_transaction_end(encoder, wakeref);
--
2.41.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Fix C10/C20 implementation w.r.t. owned PHY lanes
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
` (3 preceding siblings ...)
2023-07-25 21:27 ` [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes Gustavo Sousa
@ 2023-07-25 22:34 ` Patchwork
2023-07-26 4:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-07-25 22:34 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7397 bytes --]
== Series Details ==
Series: Fix C10/C20 implementation w.r.t. owned PHY lanes
URL : https://patchwork.freedesktop.org/series/121334/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13422 -> Patchwork_121334v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_121334v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [PASS][1] -> [DMESG-FAIL][2] ([i915#4258] / [i915#7913])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@migrate:
- bat-mtlp-8: [PASS][3] -> [DMESG-FAIL][4] ([i915#7699])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-mtlp-8/igt@i915_selftest@live@migrate.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-mtlp-8/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#7911] / [i915#7920])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-rpls-1/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [PASS][7] -> [DMESG-WARN][8] ([i915#6367])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-rpls-2/igt@i915_selftest@live@slpc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-jsl-3: NOTRUN -> [SKIP][9] ([i915#7828])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-jsl-3/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: NOTRUN -> [ABORT][10] ([i915#8434])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: NOTRUN -> [SKIP][11] ([i915#1072])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-jsl-3: [ABORT][12] ([i915#5122]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-8700k: [FAIL][14] ([i915#7940]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-rkl-11600: [FAIL][16] ([i915#7940]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
- fi-tgl-1115g4: [FAIL][18] ([i915#7940]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-jsl-3: [FAIL][20] ([fdo#103375]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
#### Warnings ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][22] ([fdo#109271]) -> [FAIL][23] ([i915#7691])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [DMESG-FAIL][24] ([i915#8497]) -> [DMESG-FAIL][25] ([i915#7269])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-mtlp-8/igt@i915_selftest@live@requests.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@kms_psr@cursor_plane_move:
- bat-rplp-1: [ABORT][26] ([i915#8434] / [i915#8668]) -> [SKIP][27] ([i915#1072])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7269]: https://gitlab.freedesktop.org/drm/intel/issues/7269
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#8434]: https://gitlab.freedesktop.org/drm/intel/issues/8434
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* Linux: CI_DRM_13422 -> Patchwork_121334v1
CI-20190529: 20190529
CI_DRM_13422: a19adfa38acfde9a7a6e9f99b598c065e4f190bb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7403: c93b4e6ff2f3cd1a41667e63c7414cc239d88240 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_121334v1: a19adfa38acfde9a7a6e9f99b598c065e4f190bb @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
1c393db641ce drm/i915/cx0: Program vswing only for owned lanes
49db50b9023b drm/i915/cx0: Enable/disable TX only for owned PHY lanes
7bfdff985c6b drm/i915: Simplify intel_cx0_program_phy_lane() with loop
8bace12624c3 drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/index.html
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Fix C10/C20 implementation w.r.t. owned PHY lanes
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
` (4 preceding siblings ...)
2023-07-25 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Fix C10/C20 implementation w.r.t. owned PHY lanes Patchwork
@ 2023-07-26 4:56 ` Patchwork
5 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-07-26 4:56 UTC (permalink / raw)
To: Gustavo Sousa; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 56105 bytes --]
== Series Details ==
Series: Fix C10/C20 implementation w.r.t. owned PHY lanes
URL : https://patchwork.freedesktop.org/series/121334/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13422_full -> Patchwork_121334v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_121334v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_121334v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_121334v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_spin_batch@legacy@bsd1:
- shard-snb: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-snb4/igt@gem_spin_batch@legacy@bsd1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb7/igt@gem_spin_batch@legacy@bsd1.html
* igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-13/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-3.html
Known issues
------------
Here are the changes found in Patchwork_121334v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-mtlp: NOTRUN -> [SKIP][4] ([i915#7701])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@virtual-busy:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@drm_fdinfo@virtual-busy.html
* igt@feature_discovery@display-4x:
- shard-mtlp: NOTRUN -> [SKIP][6] ([i915#1839])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@feature_discovery@display-4x.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-dg1: [PASS][7] -> [ABORT][8] ([i915#7461] / [i915#8234])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-18/igt@gem_barrier_race@remote-request@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-12/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ccs@block-copy-compressed:
- shard-mtlp: NOTRUN -> [SKIP][9] ([i915#5325])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_ccs@block-copy-compressed.html
* igt@gem_close_race@multigpu-basic-process:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#7697])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_ctx_persistence@heartbeat-stop:
- shard-mtlp: NOTRUN -> [SKIP][11] ([i915#8555])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_ctx_persistence@heartbeat-stop.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_eio@in-flight-suspend:
- shard-dg2: [PASS][13] -> [FAIL][14] ([fdo#103375])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-3/igt@gem_eio@in-flight-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-5/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#8898])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_endless@dispatch@rcs0:
- shard-rkl: [PASS][16] -> [TIMEOUT][17] ([i915#3778])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-1/igt@gem_exec_endless@dispatch@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-2/igt@gem_exec_endless@dispatch@rcs0.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#3539])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: NOTRUN -> [FAIL][19] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-rkl: [PASS][20] -> [FAIL][21] ([i915#2842]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- shard-mtlp: NOTRUN -> [SKIP][22] ([i915#3281]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
* igt@gem_exec_reloc@basic-write-cpu-active:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#3281])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@gem_exec_reloc@basic-write-cpu-active.html
* igt@gem_exec_schedule@preempt-queue-chain:
- shard-mtlp: NOTRUN -> [SKIP][24] ([i915#4812]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-8/igt@gem_exec_schedule@preempt-queue-chain.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: NOTRUN -> [ABORT][25] ([i915#7975] / [i915#8213])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-mtlp: NOTRUN -> [SKIP][26] ([i915#4613])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-glk: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#4613])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk4/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [PASS][28] -> [TIMEOUT][29] ([i915#5493])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_wc@read-write:
- shard-mtlp: NOTRUN -> [SKIP][30] ([i915#4083])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_mmap_wc@read-write.html
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [PASS][31] -> [FAIL][32] ([i915#8295])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-snb2/igt@gem_ppgtt@blt-vs-render-ctx0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb6/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@gem_pread@exhaustion:
- shard-glk: NOTRUN -> [WARN][33] ([i915#2658])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk4/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-random:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#3282]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@gem_pwrite@basic-random.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#4270]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_readwrite@new-obj:
- shard-mtlp: NOTRUN -> [SKIP][36] ([i915#3282]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_readwrite@new-obj.html
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#8428])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#3297])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@set-cache-level:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#3297])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_userptr_blits@set-cache-level.html
* igt@gen7_exec_parse@basic-allocation:
- shard-mtlp: NOTRUN -> [SKIP][40] ([fdo#109289]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@allowed-all:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#2856]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#2856]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu: [PASS][43] -> [FAIL][44] ([i915#3989] / [i915#454])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-tglu-10/igt@i915_pm_dc@dc6-dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-tglu-3/igt@i915_pm_dc@dc6-dpms.html
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#3361])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_freq_mult@media-freq@gt1:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#6590]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@i915_pm_freq_mult@media-freq@gt1.html
* igt@i915_pm_rpm@cursor:
- shard-dg1: [PASS][47] -> [FAIL][48] ([i915#7940]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-19/igt@i915_pm_rpm@cursor.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-14/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: [PASS][49] -> [SKIP][50] ([i915#1397])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-12/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-8/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@drm-resources-equal:
- shard-rkl: [PASS][51] -> [FAIL][52] ([i915#7940])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-1/igt@i915_pm_rpm@drm-resources-equal.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-3/igt@i915_pm_rpm@drm-resources-equal.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg1: [PASS][53] -> [SKIP][54] ([i915#1397]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-18/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_sseu@full-enable:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#8437])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@query-topology-coherent-slice-mask:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#6188])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@i915_query@query-topology-coherent-slice-mask.html
* igt@i915_selftest@live@migrate:
- shard-mtlp: [PASS][57] -> [DMESG-FAIL][58] ([i915#7699])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-2/igt@i915_selftest@live@migrate.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-5/igt@i915_selftest@live@migrate.html
* igt@i915_suspend@basic-s2idle-without-i915:
- shard-snb: NOTRUN -> [DMESG-WARN][59] ([i915#8841])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb5/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4077]) +6 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#8502]) +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-b-vga-1:
- shard-snb: NOTRUN -> [FAIL][62] ([i915#8247]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb2/igt@kms_async_flips@crc@pipe-b-vga-1.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][63] ([i915#8247]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#404])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][65] ([fdo#111614]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-1/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: NOTRUN -> [FAIL][66] ([i915#5138])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][67] ([fdo#111614]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-mtlp: [PASS][68] -> [FAIL][69] ([i915#3743]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][70] ([fdo#111615]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#5190]) +5 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][72] ([i915#4538] / [i915#5190]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-mtlp: NOTRUN -> [SKIP][73] ([i915#6187])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3689] / [i915#3886] / [i915#5354]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][75] ([i915#3886] / [i915#6095]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +4 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk8/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#3689] / [i915#5354]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][78] ([i915#6095]) +14 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-mtlp: NOTRUN -> [SKIP][79] ([fdo#111827]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_edid@vga-edid-read:
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#7828]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_chamelium_edid@vga-edid-read.html
* igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#7828]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#7118])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@atomic@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][83] ([i915#7173])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-12/igt@kms_content_protection@atomic@pipe-a-dp-2.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-mtlp: NOTRUN -> [SKIP][84] ([i915#3299])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#3299])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#3555]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-mtlp: NOTRUN -> [SKIP][87] ([i915#3359]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-8/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-mtlp: NOTRUN -> [SKIP][88] ([i915#8814])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#4103] / [i915#4213]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-mtlp: NOTRUN -> [SKIP][90] ([i915#3546])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-dg2: NOTRUN -> [SKIP][91] ([fdo#109274] / [i915#5354]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][92] -> [FAIL][93] ([i915#2346])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#3555] / [i915#3840])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-snb: NOTRUN -> [SKIP][95] ([fdo#109271] / [fdo#111767])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-mtlp: NOTRUN -> [SKIP][96] ([i915#3637]) +6 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][97] -> [FAIL][98] ([i915#2122]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk1/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][99] ([i915#8810])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][100] ([i915#2672]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][101] ([i915#5354]) +19 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#1825]) +12 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#8708]) +5 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#3458]) +7 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][105] ([i915#8708]) +4 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#3555] / [i915#8228]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-1/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#6953])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-8/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][108] ([i915#8292])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][109] ([i915#8292])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-18/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#5176]) +7 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#5176]) +19 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][112] ([i915#5176]) +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#5176]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][114] ([i915#5235]) +5 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#5235]) +19 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#5235]) +19 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_prime@basic-crc-hybrid:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#6524])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#658])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-mtlp: NOTRUN -> [SKIP][120] ([i915#4348])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_dpms:
- shard-dg2: NOTRUN -> [SKIP][121] ([i915#1072]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_psr@psr2_dpms.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#4235])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#4235])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
* igt@kms_tv_load_detect@load-detect:
- shard-dg2: NOTRUN -> [SKIP][124] ([fdo#109309])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-c-query-busy-hang:
- shard-snb: NOTRUN -> [SKIP][125] ([fdo#109271]) +277 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb5/igt@kms_vblank@pipe-c-query-busy-hang.html
* igt@perf@global-sseu-config:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#7387])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@perf@global-sseu-config.html
* igt@prime_vgem@basic-fence-read:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#3708])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#3708] / [i915#4077])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@prime_vgem@coherency-gtt.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [PASS][129] -> [FAIL][130] ([i915#6015]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
* igt@v3d/v3d_mmap@mmap-bad-flags:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#2575]) +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@v3d/v3d_mmap@mmap-bad-flags.html
* igt@v3d/v3d_perfmon@create-perfmon-exceed:
- shard-glk: NOTRUN -> [SKIP][132] ([fdo#109271]) +91 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk4/igt@v3d/v3d_perfmon@create-perfmon-exceed.html
* igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][133] ([i915#2575]) +6 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][134] ([i915#7711])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@vc4/vc4_perfmon@create-two-perfmon.html
* igt@vc4/vc4_wait_bo@used-bo-1ns:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#7711]) +3 similar issues
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-2/igt@vc4/vc4_wait_bo@used-bo-1ns.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][136] ([i915#7742]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-1/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-rkl: [ABORT][138] ([i915#8952]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-6/igt@gem_barrier_race@remote-request@rcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-4/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ctx_persistence@saturated-hostile@rcs0:
- shard-dg2: [TIMEOUT][140] -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile@rcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@gem_ctx_persistence@saturated-hostile@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][142] ([i915#2842]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [FAIL][144] ([i915#2842]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-7/igt@gem_exec_fair@basic-none@bcs0.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg1: [SKIP][146] ([i915#1937]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-tglu: [FAIL][148] ([i915#3591]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: [SKIP][150] ([i915#1397]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-10/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
- shard-rkl: [SKIP][152] ([i915#1397]) -> [PASS][153] +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0:
- shard-tglu: [FAIL][154] ([i915#7940]) -> [PASS][155] +2 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-tglu-9/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-tglu-4/igt@i915_pm_rpm@gem-execbuf-stress@extra-wait-smem0.html
* igt@i915_pm_rpm@gem-execbuf-stress@lmem0:
- shard-dg1: [FAIL][156] ([i915#7940]) -> [PASS][157] +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-18/igt@i915_pm_rpm@gem-execbuf-stress@lmem0.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-12/igt@i915_pm_rpm@gem-execbuf-stress@lmem0.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-dg1: [SKIP][158] ([i915#1397]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-13/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [SKIP][160] -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-11/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][162] ([i915#5334]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-dg2: [FAIL][164] ([fdo#103375]) -> [PASS][165] +1 similar issue
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-5/igt@i915_suspend@basic-s3-without-i915.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-7/igt@i915_suspend@basic-s3-without-i915.html
- shard-rkl: [FAIL][166] ([fdo#103375]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-mtlp: [FAIL][168] ([i915#8248]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][170] ([i915#2346]) -> [PASS][171] +1 similar issue
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
- shard-glk: [FAIL][172] ([i915#2346]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-bo@all-pipes:
- shard-mtlp: [DMESG-WARN][174] ([i915#2017]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-4/igt@kms_cursor_legacy@single-bo@all-pipes.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-7/igt@kms_cursor_legacy@single-bo@all-pipes.html
* igt@perf@stress-open-close@0-rcs0:
- shard-glk: [ABORT][176] ([i915#5213] / [i915#7941]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-glk5/igt@perf@stress-open-close@0-rcs0.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-glk4/igt@perf@stress-open-close@0-rcs0.html
#### Warnings ####
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [ABORT][178] ([i915#8131]) -> [TIMEOUT][179] ([i915#8628])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-6/igt@gem_exec_whisper@basic-contexts-forked-all.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-mtlp: [ABORT][180] ([i915#8131]) -> [TIMEOUT][181] ([i915#7392])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-5/igt@gem_exec_whisper@basic-contexts-priority-all.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][182] ([i915#8561]) -> [DMESG-FAIL][183] ([i915#1982] / [i915#8561])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-5/igt@kms_async_flips@crc@pipe-a-edp-1.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-8/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-dg2: [TIMEOUT][184] -> [SKIP][185] ([i915#3689] / [i915#3886] / [i915#5354])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-11/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_rc_ccs_cc:
- shard-dg2: [TIMEOUT][186] -> [SKIP][187] ([i915#5354])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-11/igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_rc_ccs_cc.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_ccs@pipe-d-bad-aux-stride-4_tiled_mtl_rc_ccs_cc.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-dg2: [TIMEOUT][188] -> [SKIP][189] ([fdo#111827])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-11/igt@kms_chamelium_color@ctm-0-50.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][190] ([i915#7118]) -> [SKIP][191] ([i915#7118] / [i915#7162])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-5/igt@kms_content_protection@content_type_change.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-11/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][192] ([i915#7118] / [i915#7162]) -> [SKIP][193] ([i915#7118])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-12/igt@kms_content_protection@type1.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-8/igt@kms_content_protection@type1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [DMESG-FAIL][194] ([i915#2017] / [i915#5954]) -> [FAIL][195] ([i915#2346])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-mtlp-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][196] ([fdo#110189] / [i915#3955]) -> [SKIP][197] ([i915#3955])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][198] ([fdo#109285] / [i915#4098]) -> [SKIP][199] ([fdo#109285])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@cursor_plane_move:
- shard-dg1: [SKIP][200] ([i915#1072]) -> [SKIP][201] ([i915#1072] / [i915#4078]) +1 similar issue
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg1-14/igt@kms_psr@cursor_plane_move.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg1-18/igt@kms_psr@cursor_plane_move.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][202] ([i915#5493]) -> [CRASH][203] ([i915#7331])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-dg2-7/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-dg2-12/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@runner@aborted:
- shard-snb: ([FAIL][204], [FAIL][205], [FAIL][206]) ([i915#7812] / [i915#8848]) -> [FAIL][207] ([i915#7812])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-snb7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-snb7/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13422/shard-snb7/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/shard-snb5/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6187]: https://gitlab.freedesktop.org/drm/intel/issues/6187
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7812]: https://gitlab.freedesktop.org/drm/intel/issues/7812
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8295]: https://gitlab.freedesktop.org/drm/intel/issues/8295
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8437]: https://gitlab.freedesktop.org/drm/intel/issues/8437
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8628]: https://gitlab.freedesktop.org/drm/intel/issues/8628
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8848]: https://gitlab.freedesktop.org/drm/intel/issues/8848
[i915#8898]: https://gitlab.freedesktop.org/drm/intel/issues/8898
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#8952]: https://gitlab.freedesktop.org/drm/intel/issues/8952
Build changes
-------------
* Linux: CI_DRM_13422 -> Patchwork_121334v1
CI-20190529: 20190529
CI_DRM_13422: a19adfa38acfde9a7a6e9f99b598c065e4f190bb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7403: c93b4e6ff2f3cd1a41667e63c7414cc239d88240 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_121334v1: a19adfa38acfde9a7a6e9f99b598c065e4f190bb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_121334v1/index.html
[-- Attachment #2: Type: text/html, Size: 64969 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
2023-07-25 21:27 ` [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop Gustavo Sousa
@ 2023-07-31 11:04 ` Jani Nikula
2023-07-31 12:58 ` Gustavo Sousa
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2023-07-31 11:04 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx
On Tue, 25 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> It is possible to generalize the "disable" value for the transmitters to
> be a bit mask based on the port width and the port reversal boolean,
> with a small exception for DP-alt mode with "x1" port width.
>
> Simplify the code by using such a mask and a for-loop instead of using
> switch-case statements.
>
> BSpec: 64539
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
> 1 file changed, 20 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b903ceb0b56a..f10ebdfd696a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> struct intel_encoder *encoder, int lane_count,
> bool lane_reversal)
> {
> - u8 l0t1, l0t2, l1t1, l1t2;
> + int i;
> + u8 disables;
> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> enum port port = encoder->port;
>
> @@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
>
> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
> - l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> - l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
> - l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
> - l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
> -
> - l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
> - l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
> - l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
> - l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
> -
> - if (lane_reversal) {
> - switch (lane_count) {
> - case 4:
> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - fallthrough;
> - case 3:
> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - fallthrough;
> - case 2:
> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - fallthrough;
> - case 1:
> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - break;
> - default:
> - MISSING_CASE(lane_count);
> - }
> - } else {
> - switch (lane_count) {
> - case 4:
> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - fallthrough;
> - case 3:
> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - fallthrough;
> - case 2:
> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - break;
> - case 1:
> - if (dp_alt_mode)
> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - else
> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> - break;
> - default:
> - MISSING_CASE(lane_count);
> - }
> + if (lane_reversal)
> + disables = REG_GENMASK8(3, 0) >> lane_count;
> + else
> + disables = REG_GENMASK8(3, 0) << lane_count;
> +
> + if (dp_alt_mode && lane_count == 1) {
> + disables &= ~REG_GENMASK8(1, 0);
> + disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
> }
>
> - /* disable MLs */
> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> - l0t1, MB_WRITE_COMMITTED);
> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> - l0t2, MB_WRITE_COMMITTED);
> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> - l1t1, MB_WRITE_COMMITTED);
> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
> - l1t2, MB_WRITE_COMMITTED);
> + /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
> + for (i = 0; i < 4; i++) {
> + int tx = i % 2 + 1;
> + u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
I'm just catching up on mails and quickly eyeballing stuff, but
i / 2 == 0
looks suspect.
BR,
Jani.
> +
> + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
> + CONTROL2_DISABLE_SINGLE_TX,
> + disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
> + MB_WRITE_COMMITTED);
> + }
>
> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
2023-07-31 11:04 ` Jani Nikula
@ 2023-07-31 12:58 ` Gustavo Sousa
2023-07-31 15:14 ` Jani Nikula
0 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-31 12:58 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
Quoting Jani Nikula (2023-07-31 08:04:12-03:00)
>On Tue, 25 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> It is possible to generalize the "disable" value for the transmitters to
>> be a bit mask based on the port width and the port reversal boolean,
>> with a small exception for DP-alt mode with "x1" port width.
>>
>> Simplify the code by using such a mask and a for-loop instead of using
>> switch-case statements.
>>
>> BSpec: 64539
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
>> 1 file changed, 20 insertions(+), 59 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> index b903ceb0b56a..f10ebdfd696a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> @@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>> struct intel_encoder *encoder, int lane_count,
>> bool lane_reversal)
>> {
>> - u8 l0t1, l0t2, l1t1, l1t2;
>> + int i;
>> + u8 disables;
>> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
>> enum port port = encoder->port;
>>
>> @@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>> C10_VDR_CTRL_MSGBUS_ACCESS,
>> MB_WRITE_COMMITTED);
>>
>> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>> - l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
>> - l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
>> - l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
>> - l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
>> -
>> - l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
>> - l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
>> - l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
>> - l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
>> -
>> - if (lane_reversal) {
>> - switch (lane_count) {
>> - case 4:
>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - fallthrough;
>> - case 3:
>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - fallthrough;
>> - case 2:
>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - fallthrough;
>> - case 1:
>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - break;
>> - default:
>> - MISSING_CASE(lane_count);
>> - }
>> - } else {
>> - switch (lane_count) {
>> - case 4:
>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - fallthrough;
>> - case 3:
>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - fallthrough;
>> - case 2:
>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - break;
>> - case 1:
>> - if (dp_alt_mode)
>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - else
>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>> - break;
>> - default:
>> - MISSING_CASE(lane_count);
>> - }
>> + if (lane_reversal)
>> + disables = REG_GENMASK8(3, 0) >> lane_count;
>> + else
>> + disables = REG_GENMASK8(3, 0) << lane_count;
>> +
>> + if (dp_alt_mode && lane_count == 1) {
>> + disables &= ~REG_GENMASK8(1, 0);
>> + disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
>> }
>>
>> - /* disable MLs */
>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
>> - l0t1, MB_WRITE_COMMITTED);
>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
>> - l0t2, MB_WRITE_COMMITTED);
>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
>> - l1t1, MB_WRITE_COMMITTED);
>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
>> - l1t2, MB_WRITE_COMMITTED);
>> + /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>> + for (i = 0; i < 4; i++) {
>> + int tx = i % 2 + 1;
>> + u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>
>I'm just catching up on mails and quickly eyeballing stuff, but
>
> i / 2 == 0
>
>looks suspect.
i / 2 == 0 should give us the correct selection of lane_mask: the first two
iterations are for the first PHY lane and the last two are for the last PHY
lane.
--
Gustavo Sousa
>
>BR,
>Jani.
>
>> +
>> + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
>> + CONTROL2_DISABLE_SINGLE_TX,
>> + disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
>> + MB_WRITE_COMMITTED);
>> + }
>>
>> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
>> intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
2023-07-31 12:58 ` Gustavo Sousa
@ 2023-07-31 15:14 ` Jani Nikula
2023-07-31 16:03 ` Gustavo Sousa
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2023-07-31 15:14 UTC (permalink / raw)
To: Gustavo Sousa, intel-gfx
On Mon, 31 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2023-07-31 08:04:12-03:00)
>>On Tue, 25 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> It is possible to generalize the "disable" value for the transmitters to
>>> be a bit mask based on the port width and the port reversal boolean,
>>> with a small exception for DP-alt mode with "x1" port width.
>>>
>>> Simplify the code by using such a mask and a for-loop instead of using
>>> switch-case statements.
>>>
>>> BSpec: 64539
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
>>> 1 file changed, 20 insertions(+), 59 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> index b903ceb0b56a..f10ebdfd696a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>> @@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>>> struct intel_encoder *encoder, int lane_count,
>>> bool lane_reversal)
>>> {
>>> - u8 l0t1, l0t2, l1t1, l1t2;
>>> + int i;
>>> + u8 disables;
>>> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
>>> enum port port = encoder->port;
>>>
>>> @@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>>> C10_VDR_CTRL_MSGBUS_ACCESS,
>>> MB_WRITE_COMMITTED);
>>>
>>> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>>> - l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
>>> - l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
>>> - l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
>>> - l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
>>> -
>>> - l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
>>> - l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
>>> - l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
>>> - l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
>>> -
>>> - if (lane_reversal) {
>>> - switch (lane_count) {
>>> - case 4:
>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - fallthrough;
>>> - case 3:
>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - fallthrough;
>>> - case 2:
>>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - fallthrough;
>>> - case 1:
>>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - break;
>>> - default:
>>> - MISSING_CASE(lane_count);
>>> - }
>>> - } else {
>>> - switch (lane_count) {
>>> - case 4:
>>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - fallthrough;
>>> - case 3:
>>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - fallthrough;
>>> - case 2:
>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - break;
>>> - case 1:
>>> - if (dp_alt_mode)
>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - else
>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>> - break;
>>> - default:
>>> - MISSING_CASE(lane_count);
>>> - }
>>> + if (lane_reversal)
>>> + disables = REG_GENMASK8(3, 0) >> lane_count;
>>> + else
>>> + disables = REG_GENMASK8(3, 0) << lane_count;
>>> +
>>> + if (dp_alt_mode && lane_count == 1) {
>>> + disables &= ~REG_GENMASK8(1, 0);
>>> + disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
>>> }
>>>
>>> - /* disable MLs */
>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
>>> - l0t1, MB_WRITE_COMMITTED);
>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
>>> - l0t2, MB_WRITE_COMMITTED);
>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
>>> - l1t1, MB_WRITE_COMMITTED);
>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
>>> - l1t2, MB_WRITE_COMMITTED);
>>> + /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>>> + for (i = 0; i < 4; i++) {
>>> + int tx = i % 2 + 1;
>>> + u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>>
>>I'm just catching up on mails and quickly eyeballing stuff, but
>>
>> i / 2 == 0
>>
>>looks suspect.
>
> i / 2 == 0 should give us the correct selection of lane_mask: the first two
> iterations are for the first PHY lane and the last two are for the last PHY
> lane.
I think the most obvious way to express that is i < 2.
BR,
Jani.
>
> --
> Gustavo Sousa
>
>>
>>BR,
>>Jani.
>>
>>> +
>>> + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
>>> + CONTROL2_DISABLE_SINGLE_TX,
>>> + disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
>>> + MB_WRITE_COMMITTED);
>>> + }
>>>
>>> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
>>> intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
>>
>>--
>>Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop
2023-07-31 15:14 ` Jani Nikula
@ 2023-07-31 16:03 ` Gustavo Sousa
0 siblings, 0 replies; 16+ messages in thread
From: Gustavo Sousa @ 2023-07-31 16:03 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
Quoting Jani Nikula (2023-07-31 12:14:42-03:00)
>On Mon, 31 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Quoting Jani Nikula (2023-07-31 08:04:12-03:00)
>>>On Tue, 25 Jul 2023, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>>> It is possible to generalize the "disable" value for the transmitters to
>>>> be a bit mask based on the port width and the port reversal boolean,
>>>> with a small exception for DP-alt mode with "x1" port width.
>>>>
>>>> Simplify the code by using such a mask and a for-loop instead of using
>>>> switch-case statements.
>>>>
>>>> BSpec: 64539
>>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 79 +++++---------------
>>>> 1 file changed, 20 insertions(+), 59 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>>> index b903ceb0b56a..f10ebdfd696a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>>> @@ -2604,7 +2604,8 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>>>> struct intel_encoder *encoder, int lane_count,
>>>> bool lane_reversal)
>>>> {
>>>> - u8 l0t1, l0t2, l1t1, l1t2;
>>>> + int i;
>>>> + u8 disables;
>>>> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
>>>> enum port port = encoder->port;
>>>>
>>>> @@ -2614,66 +2615,26 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
>>>> C10_VDR_CTRL_MSGBUS_ACCESS,
>>>> MB_WRITE_COMMITTED);
>>>>
>>>> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>>>> - l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
>>>> - l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
>>>> - l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
>>>> - l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
>>>> -
>>>> - l0t1 |= CONTROL2_DISABLE_SINGLE_TX;
>>>> - l0t2 |= CONTROL2_DISABLE_SINGLE_TX;
>>>> - l1t1 |= CONTROL2_DISABLE_SINGLE_TX;
>>>> - l1t2 |= CONTROL2_DISABLE_SINGLE_TX;
>>>> -
>>>> - if (lane_reversal) {
>>>> - switch (lane_count) {
>>>> - case 4:
>>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - fallthrough;
>>>> - case 3:
>>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - fallthrough;
>>>> - case 2:
>>>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - fallthrough;
>>>> - case 1:
>>>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - break;
>>>> - default:
>>>> - MISSING_CASE(lane_count);
>>>> - }
>>>> - } else {
>>>> - switch (lane_count) {
>>>> - case 4:
>>>> - l1t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - fallthrough;
>>>> - case 3:
>>>> - l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - fallthrough;
>>>> - case 2:
>>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - break;
>>>> - case 1:
>>>> - if (dp_alt_mode)
>>>> - l0t2 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - else
>>>> - l0t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
>>>> - break;
>>>> - default:
>>>> - MISSING_CASE(lane_count);
>>>> - }
>>>> + if (lane_reversal)
>>>> + disables = REG_GENMASK8(3, 0) >> lane_count;
>>>> + else
>>>> + disables = REG_GENMASK8(3, 0) << lane_count;
>>>> +
>>>> + if (dp_alt_mode && lane_count == 1) {
>>>> + disables &= ~REG_GENMASK8(1, 0);
>>>> + disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
>>>> }
>>>>
>>>> - /* disable MLs */
>>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
>>>> - l0t1, MB_WRITE_COMMITTED);
>>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
>>>> - l0t2, MB_WRITE_COMMITTED);
>>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
>>>> - l1t1, MB_WRITE_COMMITTED);
>>>> - intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
>>>> - l1t2, MB_WRITE_COMMITTED);
>>>> + /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
>>>> + for (i = 0; i < 4; i++) {
>>>> + int tx = i % 2 + 1;
>>>> + u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>>>
>>>I'm just catching up on mails and quickly eyeballing stuff, but
>>>
>>> i / 2 == 0
>>>
>>>looks suspect.
>>
>> i / 2 == 0 should give us the correct selection of lane_mask: the first two
>> iterations are for the first PHY lane and the last two are for the last PHY
>> lane.
>
>I think the most obvious way to express that is i < 2.
Indeed. Thanks!
--
Gustavo Sousa
>
>BR,
>Jani.
>
>>
>> --
>> Gustavo Sousa
>>
>>>
>>>BR,
>>>Jani.
>>>
>>>> +
>>>> + intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
>>>> + CONTROL2_DISABLE_SINGLE_TX,
>>>> + disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0,
>>>> + MB_WRITE_COMMITTED);
>>>> + }
>>>>
>>>> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
>>>> intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
>>>
>>>--
>>>Jani Nikula, Intel Open Source Graphics Center
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
2023-07-25 21:27 ` [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Gustavo Sousa
@ 2023-08-02 21:41 ` Taylor, Clinton A
2023-08-03 14:02 ` Gustavo Sousa
0 siblings, 1 reply; 16+ messages in thread
From: Taylor, Clinton A @ 2023-08-02 21:41 UTC (permalink / raw)
To: Sousa, Gustavo, intel-gfx
On Tue, 2023-07-25 at 18:27 -0300, Gustavo Sousa wrote:
> There are more parts of C10/C20 programming that need to take owned
> lanes into account. Define the function intel_cx0_get_owned_lane_mask()
> and use it. There will be new users of that function in upcoming
> changes.
>
> BSpec: 64539
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++--------
> 1 file changed, 27 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1b00ef2c6185..b903ceb0b56a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
> return ilog2(lane_mask);
> }
>
> +static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
> + struct intel_encoder *encoder)
> +{
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> + if (!intel_tc_port_in_dp_alt_mode(dig_port))
> + return INTEL_CX0_BOTH_LANES;
> +
> + /*
> + * In DP-alt with pin assignment D, only PHY lane 0 is owned
> + * by display and lane 1 is owned by USB.
> + */
lane_revesal is not being handled here. Do we need to take lane_reversal into account
with Pin assignment D is being used?
-Clint
> + return intel_tc_port_fia_max_lane_count(dig_port) > 2
> + ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
> +}
> +
> static void
> assert_dc_off(struct drm_i915_private *i915)
> {
> @@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
> *i915,
> {
> enum port port = encoder->port;
> enum phy phy = intel_port_to_phy(i915, port);
> - bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
> - u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
> - INTEL_CX0_LANE0;
> - u32 lane_pipe_reset = both_lanes ?
> - XELPDP_LANE_PIPE_RESET(0) |
> - XELPDP_LANE_PIPE_RESET(1) :
> - XELPDP_LANE_PIPE_RESET(0);
> - u32 lane_phy_current_status = both_lanes ?
> - XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> - XELPDP_LANE_PHY_CURRENT_STATUS(1) :
> - XELPDP_LANE_PHY_CURRENT_STATUS(0);
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> + u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
> + u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
> + ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
> + : XELPDP_LANE_PIPE_RESET(0);
> + u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
> + ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> + XELPDP_LANE_PHY_CURRENT_STATUS(1))
> + : XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
> if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> XELPDP_PORT_BUF_SOC_PHY_READY,
> @@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
> *i915,
> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> - intel_cx0_get_pclk_refclk_request(both_lanes ?
> - INTEL_CX0_BOTH_LANES :
> - INTEL_CX0_LANE0),
> + intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> intel_cx0_get_pclk_refclk_request(lane_mask));
>
> if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> - intel_cx0_get_pclk_refclk_ack(both_lanes ?
> - INTEL_CX0_BOTH_LANE
> S :
> - INTEL_CX0_LANE0),
> + intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> intel_cx0_get_pclk_refclk_ack(lane_mask),
> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
2023-08-02 21:41 ` Taylor, Clinton A
@ 2023-08-03 14:02 ` Gustavo Sousa
2023-08-08 10:43 ` Kahola, Mika
0 siblings, 1 reply; 16+ messages in thread
From: Gustavo Sousa @ 2023-08-03 14:02 UTC (permalink / raw)
To: Taylor, Clinton A, intel-gfx
Quoting Taylor, Clinton A (2023-08-02 18:41:27-03:00)
>On Tue, 2023-07-25 at 18:27 -0300, Gustavo Sousa wrote:
>> There are more parts of C10/C20 programming that need to take owned
>> lanes into account. Define the function intel_cx0_get_owned_lane_mask()
>> and use it. There will be new users of that function in upcoming
>> changes.
>>
>> BSpec: 64539
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44 ++++++++++++--------
>> 1 file changed, 27 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> index 1b00ef2c6185..b903ceb0b56a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> @@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
>> return ilog2(lane_mask);
>> }
>>
>> +static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
>> + struct intel_encoder *encoder)
>> +{
>> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> +
>> + if (!intel_tc_port_in_dp_alt_mode(dig_port))
>> + return INTEL_CX0_BOTH_LANES;
>> +
>> + /*
>> + * In DP-alt with pin assignment D, only PHY lane 0 is owned
>> + * by display and lane 1 is owned by USB.
>> + */
> lane_revesal is not being handled here. Do we need to take lane_reversal into account
>with Pin assignment D is being used?
According to the BSpec, we should only care about lane reversal on native
connections, and both lanes are always owned for those cases.
In Type-C DP-alt mode, FIA handles stuff so that display hardware and software
does not need to handle lane reversal.
--
Gustavo Sousa
>
>-Clint
>
>> + return intel_tc_port_fia_max_lane_count(dig_port) > 2
>> + ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;
>> +}
>> +
>> static void
>> assert_dc_off(struct drm_i915_private *i915)
>> {
>> @@ -2534,17 +2550,15 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
>> *i915,
>> {
>> enum port port = encoder->port;
>> enum phy phy = intel_port_to_phy(i915, port);
>> - bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
>> - u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
>> - INTEL_CX0_LANE0;
>> - u32 lane_pipe_reset = both_lanes ?
>> - XELPDP_LANE_PIPE_RESET(0) |
>> - XELPDP_LANE_PIPE_RESET(1) :
>> - XELPDP_LANE_PIPE_RESET(0);
>> - u32 lane_phy_current_status = both_lanes ?
>> - XELPDP_LANE_PHY_CURRENT_STATUS(0) |
>> - XELPDP_LANE_PHY_CURRENT_STATUS(1) :
>> - XELPDP_LANE_PHY_CURRENT_STATUS(0);
>> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
>> + u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
>> + u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
>> + ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
>> + : XELPDP_LANE_PIPE_RESET(0);
>> + u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
>> + ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
>> + XELPDP_LANE_PHY_CURRENT_STATUS(1))
>> + : XELPDP_LANE_PHY_CURRENT_STATUS(0);
>>
>> if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
>> XELPDP_PORT_BUF_SOC_PHY_READY,
>> @@ -2564,15 +2578,11 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
>> *i915,
>> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>>
>> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
>> - intel_cx0_get_pclk_refclk_request(both_lanes ?
>> - INTEL_CX0_BOTH_LANES :
>> - INTEL_CX0_LANE0),
>> + intel_cx0_get_pclk_refclk_request(owned_lane_mask),
>> intel_cx0_get_pclk_refclk_request(lane_mask));
>>
>> if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
>> - intel_cx0_get_pclk_refclk_ack(both_lanes ?
>> - INTEL_CX0_BOTH_LANE
>> S :
>> - INTEL_CX0_LANE0),
>> + intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
>> intel_cx0_get_pclk_refclk_ack(lane_mask),
>> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
>> drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
2023-08-03 14:02 ` Gustavo Sousa
@ 2023-08-08 10:43 ` Kahola, Mika
0 siblings, 0 replies; 16+ messages in thread
From: Kahola, Mika @ 2023-08-08 10:43 UTC (permalink / raw)
To: Sousa, Gustavo, Taylor, Clinton A, intel-gfx
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Thursday, August 3, 2023 5:03 PM
> To: Taylor, Clinton A <clinton.a.taylor@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()
>
> Quoting Taylor, Clinton A (2023-08-02 18:41:27-03:00)
> >On Tue, 2023-07-25 at 18:27 -0300, Gustavo Sousa wrote:
> >> There are more parts of C10/C20 programming that need to take owned
> >> lanes into account. Define the function
> >> intel_cx0_get_owned_lane_mask() and use it. There will be new users
> >> of that function in upcoming changes.
> >>
> >> BSpec: 64539
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 44
> >> ++++++++++++--------
> >> 1 file changed, 27 insertions(+), 17 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> index 1b00ef2c6185..b903ceb0b56a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> @@ -46,6 +46,22 @@ static int lane_mask_to_lane(u8 lane_mask)
> >> return ilog2(lane_mask);
> >> }
> >>
> >> +static u8 intel_cx0_get_owned_lane_mask(struct drm_i915_private *i915,
> >> + struct intel_encoder
> >> +*encoder) {
> >> + struct intel_digital_port *dig_port =
> >> +enc_to_dig_port(encoder);
> >> +
> >> + if (!intel_tc_port_in_dp_alt_mode(dig_port))
> >> + return INTEL_CX0_BOTH_LANES;
> >> +
> >> + /*
> >> + * In DP-alt with pin assignment D, only PHY lane 0 is owned
> >> + * by display and lane 1 is owned by USB.
> >> + */
> > lane_revesal is not being handled here. Do we need to take
> >lane_reversal into account with Pin assignment D is being used?
>
> According to the BSpec, we should only care about lane reversal on native connections, and both lanes are always owned for
> those cases.
That's correct. The patch looks ok to me.
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
>
> In Type-C DP-alt mode, FIA handles stuff so that display hardware and software does not need to handle lane reversal.
>
> --
> Gustavo Sousa
>
> >
> >-Clint
> >
> >> + return intel_tc_port_fia_max_lane_count(dig_port) > 2
> >> + ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; }
> >> +
> >> static void
> >> assert_dc_off(struct drm_i915_private *i915) { @@ -2534,17 +2550,15
> >> @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private
> >> *i915, {
> >> enum port port = encoder->port;
> >> enum phy phy = intel_port_to_phy(i915, port);
> >> - bool both_lanes = intel_tc_port_fia_max_lane_count(enc_to_dig_port(encoder)) > 2;
> >> - u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 :
> >> - INTEL_CX0_LANE0;
> >> - u32 lane_pipe_reset = both_lanes ?
> >> - XELPDP_LANE_PIPE_RESET(0) |
> >> - XELPDP_LANE_PIPE_RESET(1) :
> >> - XELPDP_LANE_PIPE_RESET(0);
> >> - u32 lane_phy_current_status = both_lanes ?
> >> - XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> >> - XELPDP_LANE_PHY_CURRENT_STATUS(1) :
> >> - XELPDP_LANE_PHY_CURRENT_STATUS(0);
> >> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> >> + u8 lane_mask = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0;
> >> + u32 lane_pipe_reset = owned_lane_mask == INTEL_CX0_BOTH_LANES
> >> + ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1)
> >> + : XELPDP_LANE_PIPE_RESET(0);
> >> + u32 lane_phy_current_status = owned_lane_mask == INTEL_CX0_BOTH_LANES
> >> + ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) |
> >> + XELPDP_LANE_PHY_CURRENT_STATUS(1))
> >> + :
> >> + XELPDP_LANE_PHY_CURRENT_STATUS(0);
> >>
> >> if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> >>
> >> XELPDP_PORT_BUF_SOC_PHY_READY, @@ -2564,15 +2578,11 @@ static void
> >> intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
> >> phy_name(phy),
> >> XELPDP_PORT_RESET_START_TIMEOUT_US);
> >>
> >> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> >> - intel_cx0_get_pclk_refclk_request(both_lanes ?
> >> - INTEL_CX0_BOTH_LANES :
> >> - INTEL_CX0_LANE0),
> >> +
> >> + intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> >> intel_cx0_get_pclk_refclk_request(lane_mask));
> >>
> >> if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> >> - intel_cx0_get_pclk_refclk_ack(both_lanes ?
> >> - INTEL_CX0_BOTH_LANE
> >> S :
> >> - INTEL_CX0_LANE0),
> >> +
> >> + intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> >> intel_cx0_get_pclk_refclk_ack(lane_mask),
> >> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> >> drm_warn(&i915->drm, "PHY %c failed to request
> >> refclk after %dus.\n",
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
2023-07-25 21:27 ` [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes Gustavo Sousa
@ 2023-08-14 9:25 ` Kahola, Mika
0 siblings, 0 replies; 16+ messages in thread
From: Kahola, Mika @ 2023-08-14 9:25 UTC (permalink / raw)
To: Sousa, Gustavo, intel-gfx
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Wednesday, July 26, 2023 12:27 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>
> Subject: [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes
>
> Display must not enable or disable transmitters for not-owned PHY lanes.
>
> BSpec: 64539
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f10ebdfd696a..236124786631 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2607,10 +2607,11 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> int i;
> u8 disables;
> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> enum port port = encoder->port;
>
> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + intel_cx0_rmw(i915, port, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1), 0,
> C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> @@ -2625,11 +2626,13 @@ static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> disables |= REG_FIELD_PREP8(REG_GENMASK8(1, 0), 0x1);
> }
>
> - /* TODO: DP-alt MFD case where only one PHY lane should be programmed. */
> for (i = 0; i < 4; i++) {
> int tx = i % 2 + 1;
> u8 lane_mask = i / 2 == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>
> + if (!(owned_lane_mask & lane_mask))
> + continue;
> +
> intel_cx0_rmw(i915, port, lane_mask, PHY_CX0_TX_CONTROL(tx, 2),
> CONTROL2_DISABLE_SINGLE_TX,
> disables & BIT(i) ? CONTROL2_DISABLE_SINGLE_TX : 0, @@ -2637,7 +2640,7 @@ static void
> intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> }
>
> if (intel_is_c10phy(i915, intel_port_to_phy(i915, port)))
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> + intel_cx0_rmw(i915, port, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1), 0,
> C10_VDR_CTRL_UPDATE_CFG,
> MB_WRITE_COMMITTED);
> --
> 2.41.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes
2023-07-25 21:27 ` [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes Gustavo Sousa
@ 2023-08-14 9:27 ` Kahola, Mika
0 siblings, 0 replies; 16+ messages in thread
From: Kahola, Mika @ 2023-08-14 9:27 UTC (permalink / raw)
To: Sousa, Gustavo, intel-gfx
> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Wednesday, July 26, 2023 12:27 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>
> Subject: [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes
>
> According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY
> lane.
>
> BSpec: 74103, 74104
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 +++++++++++---------
> 1 file changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 236124786631..cfb2093feb3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -375,6 +375,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> const struct intel_ddi_buf_trans *trans;
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(i915, encoder);
> intel_wakeref_t wakeref;
> int n_entries, ln;
>
> @@ -387,13 +388,13 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> }
>
> if (intel_is_c10phy(i915, phy)) {
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CONTROL(1),
> 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CMN(3),
> C10_CMN3_TXVBOOST_MASK,
> C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
> MB_WRITE_UNCOMMITTED);
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_TX(1),
> C10_TX1_TERMCTL_MASK,
> C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
> MB_WRITE_COMMITTED);
> @@ -401,32 +402,34 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>
> for (ln = 0; ln < crtc_state->lane_count; ln++) {
> int level = intel_ddi_level(encoder, crtc_state, ln);
> - int lane, tx;
> + int lane = ln / 2;
> + int tx = ln % 2;
> + u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
>
> - lane = ln / 2;
> - tx = ln % 2;
> + if (!(lane_mask & owned_lane_mask))
> + continue;
>
> - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 0),
> C10_PHY_OVRD_LEVEL_MASK,
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
> MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 1),
> C10_PHY_OVRD_LEVEL_MASK,
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
> MB_WRITE_COMMITTED);
> - intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
> + intel_cx0_rmw(i915, encoder->port, lane_mask,
> +PHY_CX0_VDROVRD_CTL(lane, tx, 2),
> C10_PHY_OVRD_LEVEL_MASK,
> C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
> MB_WRITE_COMMITTED);
> }
>
> /* Write Override enables in 0xD71 */
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask, PHY_C10_VDR_OVRD,
> 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
> MB_WRITE_COMMITTED);
>
> if (intel_is_c10phy(i915, phy))
> - intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + intel_cx0_rmw(i915, encoder->port, owned_lane_mask,
> +PHY_C10_VDR_CONTROL(1),
> 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
> --
> 2.41.0
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-08-14 9:27 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-25 21:27 [Intel-gfx] [PATCH 0/4] Fix C10/C20 implementation w.r.t. owned PHY lanes Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 1/4] drm/i915/cx0: Add intel_cx0_get_owned_lane_mask() Gustavo Sousa
2023-08-02 21:41 ` Taylor, Clinton A
2023-08-03 14:02 ` Gustavo Sousa
2023-08-08 10:43 ` Kahola, Mika
2023-07-25 21:27 ` [Intel-gfx] [PATCH 2/4] drm/i915: Simplify intel_cx0_program_phy_lane() with loop Gustavo Sousa
2023-07-31 11:04 ` Jani Nikula
2023-07-31 12:58 ` Gustavo Sousa
2023-07-31 15:14 ` Jani Nikula
2023-07-31 16:03 ` Gustavo Sousa
2023-07-25 21:27 ` [Intel-gfx] [PATCH 3/4] drm/i915/cx0: Enable/disable TX only for owned PHY lanes Gustavo Sousa
2023-08-14 9:25 ` Kahola, Mika
2023-07-25 21:27 ` [Intel-gfx] [PATCH 4/4] drm/i915/cx0: Program vswing only for owned lanes Gustavo Sousa
2023-08-14 9:27 ` Kahola, Mika
2023-07-25 22:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Fix C10/C20 implementation w.r.t. owned PHY lanes Patchwork
2023-07-26 4:56 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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