From: Alan Douglas <adouglas@cadence.com> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "bhelgaas@google.com" <bhelgaas@google.com>, "kishon@ti.com" <kishon@ti.com>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "robh+dt@kernel.org" <robh+dt@kernel.org> Subject: RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP Date: Wed, 11 Jul 2018 14:00:56 +0000 [thread overview] Message-ID: <MWHPR07MB3502C9168407DA7C4B6CD3ECD85A0@MWHPR07MB3502.namprd07.prod.outlook.com> (raw) In-Reply-To: <20180711105805.GA17376@red-moon> On 11 July 2018 11:58, Lorenzo Pieralisi wrote: > On Mon, Jul 09, 2018 at 03:56:11PM +0000, Alan Douglas wrote: > > On 09 July 2018 16:34, Lorenzo Pieralisi wrote: > > > On Mon, Jun 25, 2018 at 09:30:52AM +0100, Alan Douglas wrote: > > > > These PM ops will enable/disable the optional PHYs if present. The > > > > AXI link-down register in the host driver is now cleared in > > > > cdns_pci_map_bus since the link-down bit will be set if the PHY has > > > > been disabled. It is not cleared when enabling the PHY, since the > > > > link will not yet be up. > > > > > > It is not entirely clear what you mean here, can you elaborate please ? > > Thanks for taking a look at this. > > There is a "Link down indication bit" register in the cadence PCIe IP > > AXI Configuration Registers, which will be set by the PCIe IP after > > each link- down occurrence. This bit must be cleared before > > continuing, or accesses will hang. When the PHY is disabled, the link > > will go down and this bit will be set by HW. It will also be set > > after a secondary bus reset. > > > > We cannot simply clear this bit when enabling the PHY, since at this > > stage the link may not come up (e.g. because the EP PHY is disabled), > > I understand the approach and the reasoning, I still would like to > understand the use case that explains "because the EP PHY is disabled" > above and, related to the same question, why isn't this needed in > current driver version given that the host controller is probed out > of reset, I will apply the series then and update the commit log. > > Lorenzo > Why isn't it needed with current? The current driver version can only be used where there is no Linux PHY required (e.g. in simulation or if the PHY was controlled in hardware or firmware.) Right now, I'm only aware of this driver being used in simulation and the only use-case that will lead to link-down is a secondary bus reset. In this case, there is a recovery time, and the PCIe HW can be configured to clear the link-down indication bit during that time using a hardware timer. If there is an implementation with the PHY controlled by hardware or firmware, the link-down indication bit should also be cleared external to the Linux driver. Use-case? The addition of PHY & PM ops to the driver allows it to be used for hw where the PHY is not being managed externally. There is a possible use case where two cadence RP & EP are running in a back-to-back configuration, and the link will not be established until both PHY have been enabled. At first power-up this is fine, because the link will not have gone down, and the link-down bit will not be set. During suspend/resume, the RP and EP will both power-down/up their respective PHYs, and so the link-down bit will be set. However, the EP will not power up its PHY until its resume is called, and this may be after the RP. This is what I mean by: "e.g. because the EP PHY is disabled", i.e. it's still disabled while resuming the RP. Thanks for asking about this, hope the explanation makes sense. One thing that I am now wondering about is the validity of powering down/up the EP PHY when handling suspend/resume. > > and so we need to clear it on the first access after link-up. In order > > to ensure this, I simply clear it on every config access, in > > cdns_pci_map_bus, I couldn't think of a good way to just do it once. > > > > Regards, > > Alan > > > Thank you, > > > Lorenzo > > > > > > > Signed-off-by: Alan Douglas <adouglas@cadence.com> > > > > --- > > > > drivers/pci/controller/pcie-cadence-ep.c | 1 + > > > > drivers/pci/controller/pcie-cadence-host.c | 3 ++ > > > > drivers/pci/controller/pcie-cadence.c | 30 ++++++++++++++++++++++++++++ > > > > drivers/pci/controller/pcie-cadence.h | 4 +++ > > > > 4 files changed, 38 insertions(+), 0 deletions(-) > > > > > > > > diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c > > > > index c02f33d..3eabd99 100644 > > > > --- a/drivers/pci/controller/pcie-cadence-ep.c > > > > +++ b/drivers/pci/controller/pcie-cadence-ep.c > > > > @@ -555,6 +555,7 @@ static void cdns_pcie_ep_shutdown(struct platform_device *pdev) > > > > .driver = { > > > > .name = "cdns-pcie-ep", > > > > .of_match_table = cdns_pcie_ep_of_match, > > > > + .pm = &cdns_pcie_pm_ops, > > > > }, > > > > .probe = cdns_pcie_ep_probe, > > > > .shutdown = cdns_pcie_ep_shutdown, > > > > diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c > > > > index 36f3109..e3e9b7d 100644 > > > > --- a/drivers/pci/controller/pcie-cadence-host.c > > > > +++ b/drivers/pci/controller/pcie-cadence-host.c > > > > @@ -61,6 +61,8 @@ struct cdns_pcie_rc { > > > > /* Check that the link is up */ > > > > if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) > > > > return NULL; > > > > + /* Clear AXI link-down status */ > > > > + cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); > > > > > > > > /* Update Output registers for AXI region 0. */ > > > > addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) | > > > > @@ -345,6 +347,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) > > > > .driver = { > > > > .name = "cdns-pcie-host", > > > > .of_match_table = cdns_pcie_host_of_match, > > > > + .pm = &cdns_pcie_pm_ops, > > > > }, > > > > .probe = cdns_pcie_host_probe, > > > > }; > > > > diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c > > > > index 2edc126..86f1b00 100644 > > > > --- a/drivers/pci/controller/pcie-cadence.c > > > > +++ b/drivers/pci/controller/pcie-cadence.c > > > > @@ -217,3 +217,33 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) > > > > > > > > return ret; > > > > } > > > > + > > > > +#ifdef CONFIG_PM_SLEEP > > > > +static int cdns_pcie_suspend_noirq(struct device *dev) > > > > +{ > > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > > + > > > > + cdns_pcie_disable_phy(pcie); > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +static int cdns_pcie_resume_noirq(struct device *dev) > > > > +{ > > > > + struct cdns_pcie *pcie = dev_get_drvdata(dev); > > > > + int ret; > > > > + > > > > + ret = cdns_pcie_enable_phy(pcie); > > > > + if (ret) { > > > > + dev_err(dev, "failed to enable phy\n"); > > > > + return ret; > > > > + } > > > > + > > > > + return 0; > > > > +} > > > > +#endif > > > > + > > > > +const struct dev_pm_ops cdns_pcie_pm_ops = { > > > > + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, > > > > + cdns_pcie_resume_noirq) > > > > +}; > > > > diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h > > > > index b342c80..ae6bf2a 100644 > > > > --- a/drivers/pci/controller/pcie-cadence.h > > > > +++ b/drivers/pci/controller/pcie-cadence.h > > > > @@ -166,6 +166,9 @@ > > > > #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ > > > > (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) > > > > > > > > +/* AXI link down register */ > > > > +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) > > > > + > > > > enum cdns_pcie_rp_bar { > > > > RP_BAR0, > > > > RP_BAR1, > > > > @@ -314,5 +317,6 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, > > > > void cdns_pcie_disable_phy(struct cdns_pcie *pcie); > > > > int cdns_pcie_enable_phy(struct cdns_pcie *pcie); > > > > int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); > > > > +extern const struct dev_pm_ops cdns_pcie_pm_ops; > > > > > > > > #endif /* _PCIE_CADENCE_H */ > > > > -- > > > > 1.7.1 > > > >
WARNING: multiple messages have this Message-ID (diff)
From: Alan Douglas <adouglas@cadence.com> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: "bhelgaas@google.com" <bhelgaas@google.com>, "kishon@ti.com" <kishon@ti.com>, "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "robh+dt@kernel.org" <robh+dt@kernel.org> Subject: RE: [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP Date: Wed, 11 Jul 2018 14:00:56 +0000 [thread overview] Message-ID: <MWHPR07MB3502C9168407DA7C4B6CD3ECD85A0@MWHPR07MB3502.namprd07.prod.outlook.com> (raw) In-Reply-To: <20180711105805.GA17376@red-moon> T24gMTEgSnVseSAyMDE4IDExOjU4LCBMb3JlbnpvIFBpZXJhbGlzaSB3cm90ZToNCj4gT24gTW9u LCBKdWwgMDksIDIwMTggYXQgMDM6NTY6MTFQTSArMDAwMCwgQWxhbiBEb3VnbGFzIHdyb3RlOg0K PiA+IE9uIDA5IEp1bHkgMjAxOCAxNjozNCwgTG9yZW56byBQaWVyYWxpc2kgd3JvdGU6DQo+ID4g PiBPbiBNb24sIEp1biAyNSwgMjAxOCBhdCAwOTozMDo1MkFNICswMTAwLCBBbGFuIERvdWdsYXMg d3JvdGU6DQo+ID4gPiA+IFRoZXNlIFBNIG9wcyB3aWxsIGVuYWJsZS9kaXNhYmxlIHRoZSBvcHRp b25hbCBQSFlzIGlmIHByZXNlbnQuICBUaGUNCj4gPiA+ID4gQVhJIGxpbmstZG93biByZWdpc3Rl ciBpbiB0aGUgaG9zdCBkcml2ZXIgaXMgbm93IGNsZWFyZWQgaW4NCj4gPiA+ID4gY2Ruc19wY2lf bWFwX2J1cyBzaW5jZSB0aGUgbGluay1kb3duIGJpdCB3aWxsIGJlIHNldCBpZiB0aGUgUEhZIGhh cw0KPiA+ID4gPiBiZWVuIGRpc2FibGVkLiAgSXQgaXMgbm90IGNsZWFyZWQgd2hlbiBlbmFibGlu ZyB0aGUgUEhZLCBzaW5jZSB0aGUNCj4gPiA+ID4gbGluayB3aWxsIG5vdCB5ZXQgYmUgdXAuDQo+ ID4gPg0KPiA+ID4gSXQgaXMgbm90IGVudGlyZWx5IGNsZWFyIHdoYXQgeW91IG1lYW4gaGVyZSwg Y2FuIHlvdSBlbGFib3JhdGUgcGxlYXNlID8NCj4gPiBUaGFua3MgZm9yIHRha2luZyBhIGxvb2sg YXQgdGhpcy4NCj4gPiBUaGVyZSBpcyBhICJMaW5rIGRvd24gaW5kaWNhdGlvbiBiaXQiIHJlZ2lz dGVyIGluIHRoZSBjYWRlbmNlIFBDSWUgSVANCj4gPiBBWEkgQ29uZmlndXJhdGlvbiAgUmVnaXN0 ZXJzLCB3aGljaCB3aWxsIGJlIHNldCBieSB0aGUgUENJZSBJUCBhZnRlcg0KPiA+IGVhY2ggbGlu ay0gZG93biBvY2N1cnJlbmNlLiAgVGhpcyBiaXQgbXVzdCBiZSBjbGVhcmVkIGJlZm9yZQ0KPiA+ IGNvbnRpbnVpbmcsIG9yIGFjY2Vzc2VzIHdpbGwgaGFuZy4gIFdoZW4gdGhlIFBIWSBpcyBkaXNh YmxlZCwgdGhlIGxpbmsNCj4gPiB3aWxsIGdvIGRvd24gYW5kIHRoaXMgYml0IHdpbGwgYmUgc2V0 IGJ5IEhXLiAgSXQgd2lsbCBhbHNvIGJlIHNldA0KPiA+IGFmdGVyIGEgc2Vjb25kYXJ5IGJ1cyBy ZXNldC4NCj4gPg0KPiA+IFdlIGNhbm5vdCBzaW1wbHkgY2xlYXIgdGhpcyBiaXQgd2hlbiBlbmFi bGluZyB0aGUgUEhZLCBzaW5jZSBhdCB0aGlzDQo+ID4gc3RhZ2UgdGhlIGxpbmsgbWF5IG5vdCBj b21lIHVwIChlLmcuIGJlY2F1c2UgdGhlIEVQIFBIWSBpcyBkaXNhYmxlZCksDQo+IA0KPiBJIHVu ZGVyc3RhbmQgdGhlIGFwcHJvYWNoIGFuZCB0aGUgcmVhc29uaW5nLCBJIHN0aWxsIHdvdWxkIGxp a2UgdG8NCj4gdW5kZXJzdGFuZCB0aGUgdXNlIGNhc2UgdGhhdCBleHBsYWlucyAiYmVjYXVzZSB0 aGUgRVAgUEhZIGlzIGRpc2FibGVkIg0KPiBhYm92ZSBhbmQsIHJlbGF0ZWQgdG8gdGhlIHNhbWUg cXVlc3Rpb24sIHdoeSBpc24ndCB0aGlzIG5lZWRlZCBpbg0KPiBjdXJyZW50IGRyaXZlciB2ZXJz aW9uIGdpdmVuIHRoYXQgdGhlIGhvc3QgY29udHJvbGxlciBpcyBwcm9iZWQgb3V0DQo+IG9mIHJl c2V0LCBJIHdpbGwgYXBwbHkgdGhlIHNlcmllcyB0aGVuIGFuZCB1cGRhdGUgdGhlIGNvbW1pdCBs b2cuDQo+IA0KPiBMb3JlbnpvDQo+IA0KV2h5IGlzbid0IGl0IG5lZWRlZCB3aXRoIGN1cnJlbnQ/ DQpUaGUgY3VycmVudCBkcml2ZXIgdmVyc2lvbiBjYW4gb25seSBiZSB1c2VkIHdoZXJlIHRoZXJl IGlzIG5vIExpbnV4IFBIWQ0KcmVxdWlyZWQgKGUuZy4gaW4gc2ltdWxhdGlvbiBvciBpZiB0aGUg UEhZIHdhcyBjb250cm9sbGVkIGluIGhhcmR3YXJlDQpvciBmaXJtd2FyZS4pICBSaWdodCBub3cs IEknbSBvbmx5IGF3YXJlIG9mIHRoaXMgZHJpdmVyIGJlaW5nIHVzZWQgaW4NCnNpbXVsYXRpb24g YW5kIHRoZSBvbmx5IHVzZS1jYXNlIHRoYXQgd2lsbCBsZWFkIHRvIGxpbmstZG93biBpcyBhDQpz ZWNvbmRhcnkgYnVzIHJlc2V0LiAgSW4gdGhpcyBjYXNlLCB0aGVyZSBpcyBhIHJlY292ZXJ5IHRp bWUsIGFuZCB0aGUNClBDSWUgSFcgY2FuIGJlIGNvbmZpZ3VyZWQgdG8gY2xlYXIgdGhlIGxpbmst ZG93biBpbmRpY2F0aW9uIGJpdCBkdXJpbmcNCnRoYXQgdGltZSB1c2luZyBhIGhhcmR3YXJlIHRp bWVyLiAgSWYgdGhlcmUgaXMgYW4gaW1wbGVtZW50YXRpb24gd2l0aCB0aGUNClBIWSBjb250cm9s bGVkIGJ5IGhhcmR3YXJlIG9yIGZpcm13YXJlLCB0aGUgbGluay1kb3duIGluZGljYXRpb24gYml0 DQpzaG91bGQgYWxzbyBiZSBjbGVhcmVkIGV4dGVybmFsIHRvIHRoZSBMaW51eCBkcml2ZXIuDQoN ClVzZS1jYXNlPw0KVGhlIGFkZGl0aW9uIG9mIFBIWSAmIFBNIG9wcyB0byB0aGUgZHJpdmVyIGFs bG93cyBpdCB0byBiZSB1c2VkIGZvciBodw0Kd2hlcmUgdGhlIFBIWSBpcyBub3QgYmVpbmcgbWFu YWdlZCBleHRlcm5hbGx5LiAgVGhlcmUgaXMgYSBwb3NzaWJsZSB1c2UgDQpjYXNlICB3aGVyZSB0 d28gY2FkZW5jZSBSUCAmIEVQIGFyZSBydW5uaW5nIGluIGEgYmFjay10by1iYWNrIGNvbmZpZ3Vy YXRpb24sDQphbmQgdGhlICBsaW5rIHdpbGwgbm90IGJlIGVzdGFibGlzaGVkIHVudGlsIGJvdGgg UEhZIGhhdmUgYmVlbiBlbmFibGVkLiAgQXQNCmZpcnN0IHBvd2VyLXVwIHRoaXMgaXMgZmluZSwg YmVjYXVzZSB0aGUgbGluayB3aWxsIG5vdCBoYXZlIGdvbmUgZG93biwgYW5kDQp0aGUgbGluay1k b3duIGJpdCB3aWxsIG5vdCBiZSBzZXQuICBEdXJpbmcgc3VzcGVuZC9yZXN1bWUsIHRoZSBSUCBh bmQgRVANCndpbGwgYm90aCBwb3dlci1kb3duL3VwIHRoZWlyIHJlc3BlY3RpdmUgUEhZcywgYW5k IHNvIHRoZSBsaW5rLWRvd24gYml0DQp3aWxsIGJlIHNldC4gIEhvd2V2ZXIsIHRoZSBFUCB3aWxs IG5vdCBwb3dlciB1cCBpdHMgUEhZIHVudGlsIGl0cyByZXN1bWUgaXMNCmNhbGxlZCwgYW5kIHRo aXMgbWF5IGJlIGFmdGVyIHRoZSBSUC4gIFRoaXMgaXMgd2hhdCBJIG1lYW4gYnk6IA0KImUuZy4g YmVjYXVzZSB0aGUgRVAgUEhZIGlzIGRpc2FibGVkIiwgaS5lLiBpdCdzIHN0aWxsIGRpc2FibGVk IHdoaWxlIHJlc3VtaW5nDQp0aGUgUlAuDQoNClRoYW5rcyBmb3IgYXNraW5nIGFib3V0IHRoaXMs IGhvcGUgdGhlIGV4cGxhbmF0aW9uIG1ha2VzIHNlbnNlLiAgT25lIHRoaW5nDQp0aGF0IEkgYW0g bm93IHdvbmRlcmluZyBhYm91dCBpcyB0aGUgdmFsaWRpdHkgb2YgcG93ZXJpbmcgZG93bi91cCB0 aGUgRVANClBIWSB3aGVuIGhhbmRsaW5nIHN1c3BlbmQvcmVzdW1lLg0KDQo+ID4gYW5kIHNvIHdl IG5lZWQgdG8gY2xlYXIgaXQgb24gdGhlIGZpcnN0IGFjY2VzcyBhZnRlciBsaW5rLXVwLiBJbiBv cmRlcg0KPiA+IHRvIGVuc3VyZSB0aGlzLCBJIHNpbXBseSBjbGVhciBpdCBvbiBldmVyeSBjb25m aWcgYWNjZXNzLCBpbg0KPiA+IGNkbnNfcGNpX21hcF9idXMsIEkgY291bGRuJ3QgdGhpbmsgb2Yg YSBnb29kIHdheSB0byBqdXN0IGRvIGl0IG9uY2UuDQo+ID4NCj4gPiBSZWdhcmRzLA0KPiA+IEFs YW4NCj4gPiA+IFRoYW5rIHlvdSwNCj4gPiA+IExvcmVuem8NCj4gPiA+DQo+ID4gPiA+IFNpZ25l ZC1vZmYtYnk6IEFsYW4gRG91Z2xhcyA8YWRvdWdsYXNAY2FkZW5jZS5jb20+DQo+ID4gPiA+IC0t LQ0KPiA+ID4gPiAgZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLWNhZGVuY2UtZXAuYyAgIHwg ICAgMSArDQo+ID4gPiA+ICBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtY2FkZW5jZS1ob3N0 LmMgfCAgICAzICsrDQo+ID4gPiA+ICBkcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtY2FkZW5j ZS5jICAgICAgfCAgIDMwICsrKysrKysrKysrKysrKysrKysrKysrKysrKysNCj4gPiA+ID4gIGRy aXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS1jYWRlbmNlLmggICAgICB8ICAgIDQgKysrDQo+ID4g PiA+ICA0IGZpbGVzIGNoYW5nZWQsIDM4IGluc2VydGlvbnMoKyksIDAgZGVsZXRpb25zKC0pDQo+ ID4gPiA+DQo+ID4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUt Y2FkZW5jZS1lcC5jIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLWNhZGVuY2UtZXAuYw0K PiA+ID4gPiBpbmRleCBjMDJmMzNkLi4zZWFiZDk5IDEwMDY0NA0KPiA+ID4gPiAtLS0gYS9kcml2 ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtY2FkZW5jZS1lcC5jDQo+ID4gPiA+ICsrKyBiL2RyaXZl cnMvcGNpL2NvbnRyb2xsZXIvcGNpZS1jYWRlbmNlLWVwLmMNCj4gPiA+ID4gQEAgLTU1NSw2ICs1 NTUsNyBAQCBzdGF0aWMgdm9pZCBjZG5zX3BjaWVfZXBfc2h1dGRvd24oc3RydWN0IHBsYXRmb3Jt X2RldmljZSAqcGRldikNCj4gPiA+ID4gIAkuZHJpdmVyID0gew0KPiA+ID4gPiAgCQkubmFtZSA9 ICJjZG5zLXBjaWUtZXAiLA0KPiA+ID4gPiAgCQkub2ZfbWF0Y2hfdGFibGUgPSBjZG5zX3BjaWVf ZXBfb2ZfbWF0Y2gsDQo+ID4gPiA+ICsJCS5wbQk9ICZjZG5zX3BjaWVfcG1fb3BzLA0KPiA+ID4g PiAgCX0sDQo+ID4gPiA+ICAJLnByb2JlID0gY2Ruc19wY2llX2VwX3Byb2JlLA0KPiA+ID4gPiAg CS5zaHV0ZG93biA9IGNkbnNfcGNpZV9lcF9zaHV0ZG93biwNCj4gPiA+ID4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvcGNpZS1jYWRlbmNlLWhvc3QuYyBiL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpZS1jYWRlbmNlLWhvc3QuYw0KPiA+ID4gPiBpbmRleCAzNmYzMTA5Li5l M2U5YjdkIDEwMDY0NA0KPiA+ID4gPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUt Y2FkZW5jZS1ob3N0LmMNCj4gPiA+ID4gKysrIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2ll LWNhZGVuY2UtaG9zdC5jDQo+ID4gPiA+IEBAIC02MSw2ICs2MSw4IEBAIHN0cnVjdCBjZG5zX3Bj aWVfcmMgew0KPiA+ID4gPiAgCS8qIENoZWNrIHRoYXQgdGhlIGxpbmsgaXMgdXAgKi8NCj4gPiA+ ID4gIAlpZiAoIShjZG5zX3BjaWVfcmVhZGwocGNpZSwgQ0ROU19QQ0lFX0xNX0JBU0UpICYgMHgx KSkNCj4gPiA+ID4gIAkJcmV0dXJuIE5VTEw7DQo+ID4gPiA+ICsJLyogQ2xlYXIgQVhJIGxpbmst ZG93biBzdGF0dXMgKi8NCj4gPiA+ID4gKwljZG5zX3BjaWVfd3JpdGVsKHBjaWUsIENETlNfUENJ RV9BVF9MSU5LRE9XTiwgMHgwKTsNCj4gPiA+ID4NCj4gPiA+ID4gIAkvKiBVcGRhdGUgT3V0cHV0 IHJlZ2lzdGVycyBmb3IgQVhJIHJlZ2lvbiAwLiAqLw0KPiA+ID4gPiAgCWFkZHIwID0gQ0ROU19Q Q0lFX0FUX09CX1JFR0lPTl9QQ0lfQUREUjBfTkJJVFMoMTIpIHwNCj4gPiA+ID4gQEAgLTM0NSw2 ICszNDcsNyBAQCBzdGF0aWMgaW50IGNkbnNfcGNpZV9ob3N0X3Byb2JlKHN0cnVjdCBwbGF0Zm9y bV9kZXZpY2UgKnBkZXYpDQo+ID4gPiA+ICAJLmRyaXZlciA9IHsNCj4gPiA+ID4gIAkJLm5hbWUg PSAiY2Rucy1wY2llLWhvc3QiLA0KPiA+ID4gPiAgCQkub2ZfbWF0Y2hfdGFibGUgPSBjZG5zX3Bj aWVfaG9zdF9vZl9tYXRjaCwNCj4gPiA+ID4gKwkJLnBtCT0gJmNkbnNfcGNpZV9wbV9vcHMsDQo+ ID4gPiA+ICAJfSwNCj4gPiA+ID4gIAkucHJvYmUgPSBjZG5zX3BjaWVfaG9zdF9wcm9iZSwNCj4g PiA+ID4gIH07DQo+ID4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3Bj aWUtY2FkZW5jZS5jIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLWNhZGVuY2UuYw0KPiA+ ID4gPiBpbmRleCAyZWRjMTI2Li44NmYxYjAwIDEwMDY0NA0KPiA+ID4gPiAtLS0gYS9kcml2ZXJz L3BjaS9jb250cm9sbGVyL3BjaWUtY2FkZW5jZS5jDQo+ID4gPiA+ICsrKyBiL2RyaXZlcnMvcGNp L2NvbnRyb2xsZXIvcGNpZS1jYWRlbmNlLmMNCj4gPiA+ID4gQEAgLTIxNywzICsyMTcsMzMgQEAg aW50IGNkbnNfcGNpZV9pbml0X3BoeShzdHJ1Y3QgZGV2aWNlICpkZXYsIHN0cnVjdCBjZG5zX3Bj aWUgKnBjaWUpDQo+ID4gPiA+DQo+ID4gPiA+ICAJcmV0dXJuIHJldDsNCj4gPiA+ID4gIH0NCj4g PiA+ID4gKw0KPiA+ID4gPiArI2lmZGVmIENPTkZJR19QTV9TTEVFUA0KPiA+ID4gPiArc3RhdGlj IGludCBjZG5zX3BjaWVfc3VzcGVuZF9ub2lycShzdHJ1Y3QgZGV2aWNlICpkZXYpDQo+ID4gPiA+ ICt7DQo+ID4gPiA+ICsJc3RydWN0IGNkbnNfcGNpZSAqcGNpZSA9IGRldl9nZXRfZHJ2ZGF0YShk ZXYpOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJY2Ruc19wY2llX2Rpc2FibGVfcGh5KHBjaWUpOw0K PiA+ID4gPiArDQo+ID4gPiA+ICsJcmV0dXJuIDA7DQo+ID4gPiA+ICt9DQo+ID4gPiA+ICsNCj4g PiA+ID4gK3N0YXRpYyBpbnQgY2Ruc19wY2llX3Jlc3VtZV9ub2lycShzdHJ1Y3QgZGV2aWNlICpk ZXYpDQo+ID4gPiA+ICt7DQo+ID4gPiA+ICsJc3RydWN0IGNkbnNfcGNpZSAqcGNpZSA9IGRldl9n ZXRfZHJ2ZGF0YShkZXYpOw0KPiA+ID4gPiArCWludCByZXQ7DQo+ID4gPiA+ICsNCj4gPiA+ID4g KwlyZXQgPSBjZG5zX3BjaWVfZW5hYmxlX3BoeShwY2llKTsNCj4gPiA+ID4gKwlpZiAocmV0KSB7 DQo+ID4gPiA+ICsJCWRldl9lcnIoZGV2LCAiZmFpbGVkIHRvIGVuYWJsZSBwaHlcbiIpOw0KPiA+ ID4gPiArCQlyZXR1cm4gcmV0Ow0KPiA+ID4gPiArCX0NCj4gPiA+ID4gKw0KPiA+ID4gPiArCXJl dHVybiAwOw0KPiA+ID4gPiArfQ0KPiA+ID4gPiArI2VuZGlmDQo+ID4gPiA+ICsNCj4gPiA+ID4g K2NvbnN0IHN0cnVjdCBkZXZfcG1fb3BzIGNkbnNfcGNpZV9wbV9vcHMgPSB7DQo+ID4gPiA+ICsJ U0VUX05PSVJRX1NZU1RFTV9TTEVFUF9QTV9PUFMoY2Ruc19wY2llX3N1c3BlbmRfbm9pcnEsDQo+ ID4gPiA+ICsJCQkJICAgICAgY2Ruc19wY2llX3Jlc3VtZV9ub2lycSkNCj4gPiA+ID4gK307DQo+ ID4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9jb250cm9sbGVyL3BjaWUtY2FkZW5jZS5o IGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9wY2llLWNhZGVuY2UuaA0KPiA+ID4gPiBpbmRleCBi MzQyYzgwLi5hZTZiZjJhIDEwMDY0NA0KPiA+ID4gPiAtLS0gYS9kcml2ZXJzL3BjaS9jb250cm9s bGVyL3BjaWUtY2FkZW5jZS5oDQo+ID4gPiA+ICsrKyBiL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIv cGNpZS1jYWRlbmNlLmgNCj4gPiA+ID4gQEAgLTE2Niw2ICsxNjYsOSBAQA0KPiA+ID4gPiAgI2Rl ZmluZSBDRE5TX1BDSUVfQVRfSUJfUlBfQkFSX0FERFIxKGJhcikgXA0KPiA+ID4gPiAgCShDRE5T X1BDSUVfQVRfQkFTRSArIDB4MDgwNCArIChiYXIpICogMHgwMDA4KQ0KPiA+ID4gPg0KPiA+ID4g PiArLyogQVhJIGxpbmsgZG93biByZWdpc3RlciAqLw0KPiA+ID4gPiArI2RlZmluZSBDRE5TX1BD SUVfQVRfTElOS0RPV04gKENETlNfUENJRV9BVF9CQVNFICsgMHgwODI0KQ0KPiA+ID4gPiArDQo+ ID4gPiA+ICBlbnVtIGNkbnNfcGNpZV9ycF9iYXIgew0KPiA+ID4gPiAgCVJQX0JBUjAsDQo+ID4g PiA+ICAJUlBfQkFSMSwNCj4gPiA+ID4gQEAgLTMxNCw1ICszMTcsNiBAQCB2b2lkIGNkbnNfcGNp ZV9zZXRfb3V0Ym91bmRfcmVnaW9uX2Zvcl9ub3JtYWxfbXNnKHN0cnVjdCBjZG5zX3BjaWUgKnBj aWUsIHU4IGZuLA0KPiA+ID4gPiAgdm9pZCBjZG5zX3BjaWVfZGlzYWJsZV9waHkoc3RydWN0IGNk bnNfcGNpZSAqcGNpZSk7DQo+ID4gPiA+ICBpbnQgY2Ruc19wY2llX2VuYWJsZV9waHkoc3RydWN0 IGNkbnNfcGNpZSAqcGNpZSk7DQo+ID4gPiA+ICBpbnQgY2Ruc19wY2llX2luaXRfcGh5KHN0cnVj dCBkZXZpY2UgKmRldiwgc3RydWN0IGNkbnNfcGNpZSAqcGNpZSk7DQo+ID4gPiA+ICtleHRlcm4g Y29uc3Qgc3RydWN0IGRldl9wbV9vcHMgY2Ruc19wY2llX3BtX29wczsNCj4gPiA+ID4NCj4gPiA+ ID4gICNlbmRpZiAvKiBfUENJRV9DQURFTkNFX0ggKi8NCj4gPiA+ID4gLS0NCj4gPiA+ID4gMS43 LjENCj4gPiA+ID4NCg==
next prev parent reply other threads:[~2018-07-11 14:05 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-06-25 8:30 [PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-06-25 8:30 ` [PATCH 1/5] PCI: cadence: Update cdns_pcie_writel function signature Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-06-25 8:30 ` [PATCH 2/5] PCI: cadence: Add generic PHY support to host and EP drivers Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-06-25 8:30 ` [PATCH 3/5] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-07-03 21:01 ` Rob Herring 2018-06-25 8:30 ` [PATCH 4/5] PCI: cadence: Add Power Management ops for host and EP Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-07-09 15:33 ` Lorenzo Pieralisi 2018-07-09 15:56 ` Alan Douglas 2018-07-09 15:56 ` Alan Douglas 2018-07-11 10:58 ` Lorenzo Pieralisi 2018-07-11 14:00 ` Alan Douglas [this message] 2018-07-11 14:00 ` Alan Douglas 2018-06-25 8:30 ` [PATCH 5/5] PCI: cadence: Add shutdown callback to host driver Alan Douglas 2018-06-25 8:30 ` Alan Douglas 2018-07-13 13:02 ` [PATCH 0/5] PCI: cadence: Host and EP driver updates for PHY and power management Lorenzo Pieralisi
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