[PATCH 0/5] riscv: Add new SBI v0.2 extensions support

[PATCH 0/5] riscv: Add new SBI v0.2 extensions support

[Bin Meng]

The SBI v0.2 introduces a base extension which is backward compatible
with v0.1. Implement all helper functions and minimum required SBI
calls from v0.2 for now. All other base extension function will be
added later as per need.

As v0.2 calling convention is backward compatible with v0.1, remove
the v0.1 helper functions and just use v0.2 calling convention.

2 new Kconfig options CONFIG_SBI and CONFIG_SBI_V01 are introduced
and turned on by default for S-mode U-Boot. If you want to use SBI
v0.2 calling convention, turn off CONFIG_SBI_V01.

This series depends on
http://patchwork.ozlabs.org/project/uboot/list/?series=162772


Bin Meng (5):
  riscv: Mark existing SBI as v0.1 SBI
  riscv: Add basic support for SBI v0.2
  riscv: Add SBI v0.2 extension definitions
  riscv: Introduce a new config for SBI v0.1
  riscv: Implement new SBI v0.2 extensions

 arch/riscv/Kconfig           |  13 +++
 arch/riscv/include/asm/sbi.h | 168 +++++++++++++++++++++-----------------
 arch/riscv/lib/Makefile      |   1 +
 arch/riscv/lib/sbi.c         | 187 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 297 insertions(+), 72 deletions(-)
 create mode 100644 arch/riscv/lib/sbi.c

-- 
2.7.4

[PATCH 1/5] riscv: Mark existing SBI as v0.1 SBI

[Bin Meng]

As per the new SBI specification, current SBI implementation version
is defined as 0.1 and will be removed/replaced in future. Each of the
function call in 0.1 is defined as a separate extension which makes
easier to replace them one at a time.

Rename existing implementation to reflect that. This patch is just
a preparatory patch for SBI v0.2 and doesn't introduce any functional
changes.

This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407355/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/include/asm/sbi.h | 40 +++++++++++++++++++++-------------------
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index d5081f9..187ca58 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2015 Regents of the University of California
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
  *
  * Taken from Linux arch/riscv/include/asm/sbi.h
  */
@@ -10,15 +11,15 @@
 
 #include <linux/types.h>
 
-#define SBI_SET_TIMER 0
-#define SBI_CONSOLE_PUTCHAR 1
-#define SBI_CONSOLE_GETCHAR 2
-#define SBI_CLEAR_IPI 3
-#define SBI_SEND_IPI 4
-#define SBI_REMOTE_FENCE_I 5
-#define SBI_REMOTE_SFENCE_VMA 6
-#define SBI_REMOTE_SFENCE_VMA_ASID 7
-#define SBI_SHUTDOWN 8
+#define SBI_EXT_0_1_SET_TIMER 0x0
+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
+#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
+#define SBI_EXT_0_1_CLEAR_IPI 0x3
+#define SBI_EXT_0_1_SEND_IPI 0x4
+#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
+#define SBI_EXT_0_1_SHUTDOWN 0x8
 
 #define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
 	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
@@ -44,48 +45,48 @@
 
 static inline void sbi_console_putchar(int ch)
 {
-	SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
+	SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
 }
 
 static inline int sbi_console_getchar(void)
 {
-	return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
+	return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
 }
 
 static inline void sbi_set_timer(uint64_t stime_value)
 {
 #if __riscv_xlen == 32
-	SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
+	SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> 32);
 #else
-	SBI_CALL_1(SBI_SET_TIMER, stime_value);
+	SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
 #endif
 }
 
 static inline void sbi_shutdown(void)
 {
-	SBI_CALL_0(SBI_SHUTDOWN);
+	SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
 }
 
 static inline void sbi_clear_ipi(void)
 {
-	SBI_CALL_0(SBI_CLEAR_IPI);
+	SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
 }
 
 static inline void sbi_send_ipi(const unsigned long *hart_mask)
 {
-	SBI_CALL_1(SBI_SEND_IPI, hart_mask);
+	SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
 }
 
 static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
 {
-	SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
+	SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
 }
 
 static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
 					 unsigned long start,
 					 unsigned long size)
 {
-	SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
+	SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, size);
 }
 
 static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
@@ -93,7 +94,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
 					      unsigned long size,
 					      unsigned long asid)
 {
-	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
+	SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
+		   start, size, asid);
 }
 
 #endif
-- 
2.7.4

[PATCH 2/5] riscv: Add basic support for SBI v0.2

[Bin Meng]

The SBI v0.2 introduces a base extension which is backward compatible
with v0.1. Implement all helper functions and minimum required SBI
calls from v0.2 for now. All other base extension function will be
added later as per need.

As v0.2 calling convention is backward compatible with v0.1, remove
the v0.1 helper functions and just use v0.2 calling convention.

Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and
let CONFIG_SBI_IPI depend on it.

This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407363/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/Kconfig           |   5 ++
 arch/riscv/include/asm/sbi.h | 135 +++++++++++++-------------------
 arch/riscv/lib/Makefile      |   1 +
 arch/riscv/lib/sbi.c         | 181 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 243 insertions(+), 79 deletions(-)
 create mode 100644 arch/riscv/lib/sbi.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3338b78..09fff05 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -210,8 +210,13 @@ config NR_CPUS
 	  Stack memory is pre-allocated. U-Boot must therefore know the
 	  maximum number of CPUs that may be present.
 
+config SBI
+	bool
+	default y if RISCV_SMODE || SPL_RISCV_SMODE
+
 config SBI_IPI
 	bool
+	depends on SBI
 	default y if RISCV_SMODE || SPL_RISCV_SMODE
 	depends on SMP
 
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 187ca58..fc8637c 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -11,91 +11,68 @@
 
 #include <linux/types.h>
 
-#define SBI_EXT_0_1_SET_TIMER 0x0
-#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
-#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
-#define SBI_EXT_0_1_CLEAR_IPI 0x3
-#define SBI_EXT_0_1_SEND_IPI 0x4
-#define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
-#define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
-#define SBI_EXT_0_1_SHUTDOWN 0x8
+enum sbi_ext_id {
+	SBI_EXT_0_1_SET_TIMER = 0x0,
+	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
+	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
+	SBI_EXT_0_1_CLEAR_IPI = 0x3,
+	SBI_EXT_0_1_SEND_IPI = 0x4,
+	SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
+	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
+	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
+	SBI_EXT_0_1_SHUTDOWN = 0x8,
+	SBI_EXT_BASE = 0x10,
+};
 
-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
-	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
-	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);	\
-	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);	\
-	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);	\
-	register uintptr_t a7 asm ("a7") = (uintptr_t)(which);	\
-	asm volatile ("ecall"					\
-		      : "+r" (a0)				\
-		      : "r" (a1), "r" (a2), "r" (a3), "r" (a7)	\
-		      : "memory");				\
-	a0;							\
-})
+enum sbi_ext_base_fid {
+	SBI_EXT_BASE_GET_SPEC_VERSION = 0,
+	SBI_EXT_BASE_GET_IMP_ID,
+	SBI_EXT_BASE_GET_IMP_VERSION,
+	SBI_EXT_BASE_PROBE_EXT,
+	SBI_EXT_BASE_GET_MVENDORID,
+	SBI_EXT_BASE_GET_MARCHID,
+	SBI_EXT_BASE_GET_MIMPID,
+};
 
-/* Lazy implementations until SBI is finalized */
-#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0, 0)
-#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0, 0)
-#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0, 0)
-#define SBI_CALL_3(which, arg0, arg1, arg2) \
-		SBI_CALL(which, arg0, arg1, arg2, 0)
-#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
-		SBI_CALL(which, arg0, arg1, arg2, arg3)
+#define SBI_SPEC_VERSION_DEFAULT	0x1
+#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
+#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
+#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
 
-static inline void sbi_console_putchar(int ch)
-{
-	SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
-}
+/* SBI return error codes */
+#define SBI_SUCCESS			0
+#define SBI_ERR_FAILURE			-1
+#define SBI_ERR_NOT_SUPPORTED		-2
+#define SBI_ERR_INVALID_PARAM		-3
+#define SBI_ERR_DENIED			-4
+#define SBI_ERR_INVALID_ADDRESS		-5
 
-static inline int sbi_console_getchar(void)
-{
-	return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
-}
+extern unsigned long sbi_spec_version;
+struct sbiret {
+	long error;
+	long value;
+};
 
-static inline void sbi_set_timer(uint64_t stime_value)
-{
-#if __riscv_xlen == 32
-	SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >> 32);
-#else
-	SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
-#endif
-}
-
-static inline void sbi_shutdown(void)
-{
-	SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
-}
-
-static inline void sbi_clear_ipi(void)
-{
-	SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
-}
-
-static inline void sbi_send_ipi(const unsigned long *hart_mask)
-{
-	SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
-}
-
-static inline void sbi_remote_fence_i(const unsigned long *hart_mask)
-{
-	SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
-}
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5);
 
-static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
-					 unsigned long start,
-					 unsigned long size)
-{
-	SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start, size);
-}
+void sbi_console_putchar(int ch);
+int sbi_console_getchar(void);
+void sbi_clear_ipi(void);
+void sbi_shutdown(void);
+void sbi_set_timer(uint64_t stime_value);
+void sbi_send_ipi(const unsigned long *hart_mask);
+void sbi_remote_fence_i(const unsigned long *hart_mask);
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+			   unsigned long start,
+			   unsigned long size);
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+				unsigned long start,
+				unsigned long size,
+				unsigned long asid);
 
-static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
-					      unsigned long start,
-					      unsigned long size,
-					      unsigned long asid)
-{
-	SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
-		   start, size, asid);
-}
+int sbi_probe_extension(int ext);
 
 #endif
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c9179a5..adadbf4 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 else
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+obj-$(CONFIG_SBI) += sbi.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 endif
 obj-y	+= interrupts.o
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
new file mode 100644
index 0000000..4b6a9e0
--- /dev/null
+++ b/arch/riscv/lib/sbi.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SBI initialilization and all extension implementation.
+ *
+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
+ *
+ * Taken from Linux arch/riscv/kernel/sbi.c
+ */
+
+#include <common.h>
+#include <asm/encoding.h>
+#include <asm/sbi.h>
+
+/* default SBI version is 0.1 */
+unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
+
+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
+			unsigned long arg1, unsigned long arg2,
+			unsigned long arg3, unsigned long arg4,
+			unsigned long arg5)
+{
+	struct sbiret ret;
+
+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
+	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
+	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
+	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
+	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
+	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+	asm volatile ("ecall"
+		      : "+r" (a0), "+r" (a1)
+		      : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
+		      : "memory");
+	ret.error = a0;
+	ret.value = a1;
+
+	return ret;
+}
+
+/**
+ * sbi_console_putchar() - Writes given character to the console device.
+ * @ch: The data to be written to the console.
+ *
+ * Return: None
+ */
+void sbi_console_putchar(int ch)
+{
+	sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_console_getchar() - Reads a byte from console device.
+ *
+ * Returns the value read from console.
+ */
+int sbi_console_getchar(void)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
+
+	return ret.error;
+}
+
+/**
+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
+ *
+ * Return: None
+ */
+void sbi_clear_ipi(void)
+{
+	sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
+ *
+ * Return: None
+ */
+void sbi_shutdown(void)
+{
+	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_set_timer() - Program the timer for next timer event.
+ * @stime_value: The value after which next timer event should fire.
+ *
+ * Return: None
+ */
+void sbi_set_timer(uint64_t stime_value)
+{
+#if __riscv_xlen == 32
+	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+		  stime_value >> 32, 0, 0, 0, 0);
+#else
+	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+#endif
+}
+
+/**
+ * sbi_send_ipi() - Send an IPI to any hart.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_send_ipi(const unsigned long *hart_mask)
+{
+	sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+		  0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
+ * @hart_mask: A cpu mask containing all the target harts.
+ *
+ * Return: None
+ */
+void sbi_remote_fence_i(const unsigned long *hart_mask)
+{
+	sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
+		  0, 0, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given remote
+ *			     harts for the specified virtual address range.
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
+			   unsigned long start,
+			   unsigned long size)
+{
+	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+		  (unsigned long)hart_mask, start, size, 0, 0, 0);
+}
+
+/**
+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on given
+ * remote harts for a virtual address range belonging to a specific ASID.
+ *
+ * @hart_mask: A cpu mask containing all the target harts.
+ * @start: Start of the virtual address
+ * @size: Total size of the virtual address range.
+ * @asid: The value of address space identifier (ASID).
+ *
+ * Return: None
+ */
+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
+				unsigned long start,
+				unsigned long size,
+				unsigned long asid)
+{
+	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+		  (unsigned long)hart_mask, start, size, asid, 0, 0);
+}
+
+/**
+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
+ * @extid: The extension ID to be probed.
+ *
+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
+ */
+int sbi_probe_extension(int extid)
+{
+	struct sbiret ret;
+
+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
+			0, 0, 0, 0, 0);
+	if (!ret.error)
+		if (ret.value)
+			return ret.value;
+
+	return -ENOTSUPP;
+}
-- 
2.7.4

[PATCH 3/5] riscv: Add SBI v0.2 extension definitions

[Bin Meng]

Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention.

This patch just defines these new extensions.

This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407359/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/include/asm/sbi.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index fc8637c..6d3114c 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -22,6 +22,9 @@ enum sbi_ext_id {
 	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
 	SBI_EXT_0_1_SHUTDOWN = 0x8,
 	SBI_EXT_BASE = 0x10,
+	SBI_EXT_TIME = 0x54494D45,
+	SBI_EXT_IPI = 0x735049,
+	SBI_EXT_RFENCE = 0x52464E43,
 };
 
 enum sbi_ext_base_fid {
@@ -34,6 +37,20 @@ enum sbi_ext_base_fid {
 	SBI_EXT_BASE_GET_MIMPID,
 };
 
+enum sbi_ext_time_fid {
+	SBI_EXT_TIME_SET_TIMER = 0,
+};
+
+enum sbi_ext_ipi_fid {
+	SBI_EXT_IPI_SEND_IPI = 0,
+};
+
+enum sbi_ext_rfence_fid {
+	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
+};
+
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
 #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
-- 
2.7.4

[PATCH 4/5] riscv: Introduce a new config for SBI v0.1

[Bin Meng]

We now have SBI v0.2 which is more scalable and extendable to handle
future needs for RISC-V supervisor interfaces.

Introduce a new config and move all SBI v0.1 code under that config.
This allows to implement the new replacement SBI extensions cleanly
and remove v0.1 extensions easily in future. Currently, the config
is enabled by default. Once all M-mode software, with v0.1, is no
longer in use, this config option and all relevant code can be easily
removed.

This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407361/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 arch/riscv/Kconfig           | 8 ++++++++
 arch/riscv/include/asm/sbi.h | 4 ++++
 arch/riscv/lib/sbi.c         | 4 ++++
 3 files changed, 16 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 09fff05..cc87da7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -214,6 +214,14 @@ config SBI
 	bool
 	default y if RISCV_SMODE || SPL_RISCV_SMODE
 
+config SBI_V01
+	bool "SBI v0.1 support"
+	default y
+	depends on SBI
+	help
+	  This config allows kernel to use SBI v0.1 APIs. This will be
+	  deprecated in future once legacy M-mode software are no longer in use.
+
 config SBI_IPI
 	bool
 	depends on SBI
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 6d3114c..c65104f 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -12,6 +12,7 @@
 #include <linux/types.h>
 
 enum sbi_ext_id {
+#ifdef CONFIG_SBI_V01
 	SBI_EXT_0_1_SET_TIMER = 0x0,
 	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
 	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
@@ -21,6 +22,7 @@ enum sbi_ext_id {
 	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
 	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
 	SBI_EXT_0_1_SHUTDOWN = 0x8,
+#endif
 	SBI_EXT_BASE = 0x10,
 	SBI_EXT_TIME = 0x54494D45,
 	SBI_EXT_IPI = 0x735049,
@@ -75,10 +77,12 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 			unsigned long arg3, unsigned long arg4,
 			unsigned long arg5);
 
+#ifdef CONFIG_SBI_V01
 void sbi_console_putchar(int ch);
 int sbi_console_getchar(void);
 void sbi_clear_ipi(void);
 void sbi_shutdown(void);
+#endif
 void sbi_set_timer(uint64_t stime_value);
 void sbi_send_ipi(const unsigned long *hart_mask);
 void sbi_remote_fence_i(const unsigned long *hart_mask);
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 4b6a9e0..604a3a8 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -39,6 +39,8 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
 	return ret;
 }
 
+#ifdef CONFIG_SBI_V01
+
 /**
  * sbi_console_putchar() - Writes given character to the console device.
  * @ch: The data to be written to the console.
@@ -84,6 +86,8 @@ void sbi_shutdown(void)
 	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);
 }
 
+#endif /* CONFIG_SBI_V01 */
+
 /**
  * sbi_set_timer() - Program the timer for next timer event.
  * @stime_value: The value after which next timer event should fire.
-- 
2.7.4

[PATCH 5/5] riscv: Implement new SBI v0.2 extensions

[Bin Meng]

Few v0.1 SBI calls are being replaced by new SBI calls that follows
v0.2 calling convention.

Implement the replacement extensions and few additional new SBI
function calls that makes way for a better SBI interface in future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++
 arch/riscv/lib/sbi.c         | 16 +++++++++-------
 2 files changed, 33 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index c65104f..3595ee8 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -53,6 +53,30 @@ enum sbi_ext_rfence_fid {
 	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
 };
 
+#ifdef CONFIG_SBI_V01
+#define SBI_EXT_SET_TIMER		SBI_EXT_0_1_SET_TIMER
+#define SBI_FID_SET_TIMER		0
+#define SBI_EXT_SEND_IPI		SBI_EXT_0_1_SEND_IPI
+#define SBI_FID_SEND_IPI		0
+#define SBI_EXT_REMOTE_FENCE_I		SBI_EXT_0_1_REMOTE_FENCE_I
+#define SBI_FID_REMOTE_FENCE_I		0
+#define SBI_EXT_REMOTE_SFENCE_VMA	SBI_EXT_0_1_REMOTE_SFENCE_VMA
+#define SBI_FID_REMOTE_SFENCE_VMA	0
+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID
+#define SBI_FID_REMOTE_SFENCE_VMA_ASID	0
+#else
+#define SBI_EXT_SET_TIMER		SBI_EXT_TIME
+#define SBI_FID_SET_TIMER		SBI_EXT_TIME_SET_TIMER
+#define SBI_EXT_SEND_IPI		SBI_EXT_IPI
+#define SBI_FID_SEND_IPI		SBI_EXT_IPI_SEND_IPI
+#define SBI_EXT_REMOTE_FENCE_I		SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_FENCE_I		SBI_EXT_RFENCE_REMOTE_FENCE_I
+#define SBI_EXT_REMOTE_SFENCE_VMA	SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_SFENCE_VMA	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA
+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID	SBI_EXT_RFENCE
+#define SBI_FID_REMOTE_SFENCE_VMA_ASID	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
+#endif
+
 #define SBI_SPEC_VERSION_DEFAULT	0x1
 #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
 #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
index 604a3a8..7bdf071 100644
--- a/arch/riscv/lib/sbi.c
+++ b/arch/riscv/lib/sbi.c
@@ -97,10 +97,11 @@ void sbi_shutdown(void)
 void sbi_set_timer(uint64_t stime_value)
 {
 #if __riscv_xlen == 32
-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
 		  stime_value >> 32, 0, 0, 0, 0);
 #else
-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
+		  0, 0, 0, 0, 0);
 #endif
 }
 
@@ -112,7 +113,7 @@ void sbi_set_timer(uint64_t stime_value)
  */
 void sbi_send_ipi(const unsigned long *hart_mask)
 {
-	sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
+	sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned long)hart_mask,
 		  0, 0, 0, 0, 0);
 }
 
@@ -124,8 +125,8 @@ void sbi_send_ipi(const unsigned long *hart_mask)
  */
 void sbi_remote_fence_i(const unsigned long *hart_mask)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
-		  0, 0, 0, 0, 0);
+	sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I,
+		  (unsigned long)hart_mask, 0, 0, 0, 0, 0);
 }
 
 /**
@@ -141,7 +142,7 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
 			   unsigned long start,
 			   unsigned long size)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA, SBI_FID_REMOTE_SFENCE_VMA,
 		  (unsigned long)hart_mask, start, size, 0, 0, 0);
 }
 
@@ -161,7 +162,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
 				unsigned long size,
 				unsigned long asid)
 {
-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID,
+		  SBI_FID_REMOTE_SFENCE_VMA_ASID,
 		  (unsigned long)hart_mask, start, size, asid, 0, 0);
 }
 
-- 
2.7.4

[PATCH 1/5] riscv: Mark existing SBI as v0.1 SBI

[Pragnesh Patel]

Hi,

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng
>Sent: 10 March 2020 08:05
>To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>;
>Atish Patra <atish.patra@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u-
>boot at lists.denx.de>
>Subject: [PATCH 1/5] riscv: Mark existing SBI as v0.1 SBI
>
>As per the new SBI specification, current SBI implementation version is
>defined as 0.1 and will be removed/replaced in future. Each of the function
>call in 0.1 is defined as a separate extension which makes easier to replace
>them one at a time.
>
>Rename existing implementation to reflect that. This patch is just a
>preparatory patch for SBI v0.2 and doesn't introduce any functional changes.
>
>This commit is inspired from Linux kernel patch:
>https://patchwork.kernel.org/patch/11407355/
>
>Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>---
>
> arch/riscv/include/asm/sbi.h | 40 +++++++++++++++++++++-------------------
> 1 file changed, 21 insertions(+), 19 deletions(-)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>d5081f9..187ca58 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -1,6 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
>  * Copyright (C) 2015 Regents of the University of California
>+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
>  *
>  * Taken from Linux arch/riscv/include/asm/sbi.h
>  */
>@@ -10,15 +11,15 @@
>
> #include <linux/types.h>
>
>-#define SBI_SET_TIMER 0
>-#define SBI_CONSOLE_PUTCHAR 1
>-#define SBI_CONSOLE_GETCHAR 2
>-#define SBI_CLEAR_IPI 3
>-#define SBI_SEND_IPI 4
>-#define SBI_REMOTE_FENCE_I 5
>-#define SBI_REMOTE_SFENCE_VMA 6
>-#define SBI_REMOTE_SFENCE_VMA_ASID 7
>-#define SBI_SHUTDOWN 8
>+#define SBI_EXT_0_1_SET_TIMER 0x0
>+#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 #define
>+SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 #define SBI_EXT_0_1_CLEAR_IPI 0x3
>+#define SBI_EXT_0_1_SEND_IPI 0x4 #define SBI_EXT_0_1_REMOTE_FENCE_I
>0x5
>+#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 #define
>+SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 #define
>SBI_EXT_0_1_SHUTDOWN 0x8
>
> #define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
> 	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
>@@ -44,48 +45,48 @@
>
> static inline void sbi_console_putchar(int ch)  {
>-	SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch);
>+	SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
> }
>
> static inline int sbi_console_getchar(void)  {
>-	return SBI_CALL_0(SBI_CONSOLE_GETCHAR);
>+	return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
> }
>
> static inline void sbi_set_timer(uint64_t stime_value)  {  #if __riscv_xlen == 32
>-	SBI_CALL_2(SBI_SET_TIMER, stime_value, stime_value >> 32);
>+	SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >>
>32);
> #else
>-	SBI_CALL_1(SBI_SET_TIMER, stime_value);
>+	SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
> #endif
> }
>
> static inline void sbi_shutdown(void)
> {
>-	SBI_CALL_0(SBI_SHUTDOWN);
>+	SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
> }
>
> static inline void sbi_clear_ipi(void)
> {
>-	SBI_CALL_0(SBI_CLEAR_IPI);
>+	SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
> }
>
> static inline void sbi_send_ipi(const unsigned long *hart_mask)  {
>-	SBI_CALL_1(SBI_SEND_IPI, hart_mask);
>+	SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
> }
>
> static inline void sbi_remote_fence_i(const unsigned long *hart_mask)  {
>-	SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask);
>+	SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
> }
>
> static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
> 					 unsigned long start,
> 					 unsigned long size)
> {
>-	SBI_CALL_3(SBI_REMOTE_SFENCE_VMA, hart_mask, start, size);
>+	SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start,
>size);
> }
>
> static inline void sbi_remote_sfence_vma_asid(const unsigned long
>*hart_mask, @@ -93,7 +94,8 @@ static inline void
>sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> 					      unsigned long size,
> 					      unsigned long asid)
> {
>-	SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size,
>asid);
>+	SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
>+		   start, size, asid);
> }
>
> #endif

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

>--
>2.7.4

[PATCH 2/5] riscv: Add basic support for SBI v0.2

[Pragnesh Patel]

Hi Bin,

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng
>Sent: 10 March 2020 08:05
>To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>;
>Atish Patra <atish.patra@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u-
>boot at lists.denx.de>
>Subject: [PATCH 2/5] riscv: Add basic support for SBI v0.2
>
>The SBI v0.2 introduces a base extension which is backward compatible with
>v0.1. Implement all helper functions and minimum required SBI calls from
>v0.2 for now. All other base extension function will be added later as per
>need.
>
>As v0.2 calling convention is backward compatible with v0.1, remove the v0.1
>helper functions and just use v0.2 calling convention.
>
>Add a new Kconfig options CONFIG_SBI for the new SBI v0.2 codes, and let
>CONFIG_SBI_IPI depend on it.
>
>This commit is inspired from Linux kernel patch:
>https://patchwork.kernel.org/patch/11407363/
>
>Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>---
>
> arch/riscv/Kconfig           |   5 ++
> arch/riscv/include/asm/sbi.h | 135 +++++++++++++-------------------
> arch/riscv/lib/Makefile      |   1 +
> arch/riscv/lib/sbi.c         | 181
>+++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 243 insertions(+), 79 deletions(-)  create mode 100644
>arch/riscv/lib/sbi.c
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3338b78..09fff05
>100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -210,8 +210,13 @@ config NR_CPUS
> 	  Stack memory is pre-allocated. U-Boot must therefore know the
> 	  maximum number of CPUs that may be present.
>
>+config SBI
>+	bool
>+	default y if RISCV_SMODE || SPL_RISCV_SMODE
>+
> config SBI_IPI
> 	bool
>+	depends on SBI
> 	default y if RISCV_SMODE || SPL_RISCV_SMODE
> 	depends on SMP
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>187ca58..fc8637c 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -11,91 +11,68 @@
>
> #include <linux/types.h>
>
>-#define SBI_EXT_0_1_SET_TIMER 0x0
>-#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1 -#define
>SBI_EXT_0_1_CONSOLE_GETCHAR 0x2 -#define SBI_EXT_0_1_CLEAR_IPI 0x3 -
>#define SBI_EXT_0_1_SEND_IPI 0x4 -#define SBI_EXT_0_1_REMOTE_FENCE_I
>0x5 -#define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6 -#define
>SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7 -#define
>SBI_EXT_0_1_SHUTDOWN 0x8
>+enum sbi_ext_id {
>+	SBI_EXT_0_1_SET_TIMER = 0x0,
>+	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
>+	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
>+	SBI_EXT_0_1_CLEAR_IPI = 0x3,
>+	SBI_EXT_0_1_SEND_IPI = 0x4,
>+	SBI_EXT_0_1_REMOTE_FENCE_I = 0x5,
>+	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
>+	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
>+	SBI_EXT_0_1_SHUTDOWN = 0x8,
>+	SBI_EXT_BASE = 0x10,
>+};
>
>-#define SBI_CALL(which, arg0, arg1, arg2, arg3) ({		\
>-	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);	\
>-	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);	\
>-	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);	\
>-	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);	\
>-	register uintptr_t a7 asm ("a7") = (uintptr_t)(which);	\
>-	asm volatile ("ecall"					\
>-		      : "+r" (a0)				\
>-		      : "r" (a1), "r" (a2), "r" (a3), "r" (a7)	\
>-		      : "memory");				\
>-	a0;							\
>-})
>+enum sbi_ext_base_fid {
>+	SBI_EXT_BASE_GET_SPEC_VERSION = 0,
>+	SBI_EXT_BASE_GET_IMP_ID,
>+	SBI_EXT_BASE_GET_IMP_VERSION,
>+	SBI_EXT_BASE_PROBE_EXT,
>+	SBI_EXT_BASE_GET_MVENDORID,
>+	SBI_EXT_BASE_GET_MARCHID,
>+	SBI_EXT_BASE_GET_MIMPID,
>+};
>
>-/* Lazy implementations until SBI is finalized */ -#define SBI_CALL_0(which)
>SBI_CALL(which, 0, 0, 0, 0) -#define SBI_CALL_1(which, arg0) SBI_CALL(which,
>arg0, 0, 0, 0) -#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0,
>arg1, 0, 0) -#define SBI_CALL_3(which, arg0, arg1, arg2) \
>-		SBI_CALL(which, arg0, arg1, arg2, 0)
>-#define SBI_CALL_4(which, arg0, arg1, arg2, arg3) \
>-		SBI_CALL(which, arg0, arg1, arg2, arg3)
>+#define SBI_SPEC_VERSION_DEFAULT	0x1
>+#define SBI_SPEC_VERSION_MAJOR_SHIFT	24
>+#define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
>+#define SBI_SPEC_VERSION_MINOR_MASK	0xffffff
>
>-static inline void sbi_console_putchar(int ch) -{
>-	SBI_CALL_1(SBI_EXT_0_1_CONSOLE_PUTCHAR, ch);
>-}
>+/* SBI return error codes */
>+#define SBI_SUCCESS			0
>+#define SBI_ERR_FAILURE			-1
>+#define SBI_ERR_NOT_SUPPORTED		-2
>+#define SBI_ERR_INVALID_PARAM		-3
>+#define SBI_ERR_DENIED			-4
>+#define SBI_ERR_INVALID_ADDRESS		-5
>
>-static inline int sbi_console_getchar(void) -{
>-	return SBI_CALL_0(SBI_EXT_0_1_CONSOLE_GETCHAR);
>-}
>+extern unsigned long sbi_spec_version;
>+struct sbiret {
>+	long error;
>+	long value;
>+};
>
>-static inline void sbi_set_timer(uint64_t stime_value) -{ -#if __riscv_xlen == 32
>-	SBI_CALL_2(SBI_EXT_0_1_SET_TIMER, stime_value, stime_value >>
>32);
>-#else
>-	SBI_CALL_1(SBI_EXT_0_1_SET_TIMER, stime_value);
>-#endif
>-}
>-
>-static inline void sbi_shutdown(void)
>-{
>-	SBI_CALL_0(SBI_EXT_0_1_SHUTDOWN);
>-}
>-
>-static inline void sbi_clear_ipi(void)
>-{
>-	SBI_CALL_0(SBI_EXT_0_1_CLEAR_IPI);
>-}
>-
>-static inline void sbi_send_ipi(const unsigned long *hart_mask) -{
>-	SBI_CALL_1(SBI_EXT_0_1_SEND_IPI, hart_mask);
>-}
>-
>-static inline void sbi_remote_fence_i(const unsigned long *hart_mask) -{
>-	SBI_CALL_1(SBI_EXT_0_1_REMOTE_FENCE_I, hart_mask);
>-}
>+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>+			unsigned long arg1, unsigned long arg2,
>+			unsigned long arg3, unsigned long arg4,
>+			unsigned long arg5);
>
>-static inline void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>-					 unsigned long start,
>-					 unsigned long size)
>-{
>-	SBI_CALL_3(SBI_EXT_0_1_REMOTE_SFENCE_VMA, hart_mask, start,
>size);
>-}
>+void sbi_console_putchar(int ch);
>+int sbi_console_getchar(void);
>+void sbi_clear_ipi(void);
>+void sbi_shutdown(void);
>+void sbi_set_timer(uint64_t stime_value); void sbi_send_ipi(const
>+unsigned long *hart_mask); void sbi_remote_fence_i(const unsigned long
>+*hart_mask); void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>+			   unsigned long start,
>+			   unsigned long size);
>+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
>+				unsigned long start,
>+				unsigned long size,
>+				unsigned long asid);
>
>-static inline void sbi_remote_sfence_vma_asid(const unsigned long
>*hart_mask,
>-					      unsigned long start,
>-					      unsigned long size,
>-					      unsigned long asid)
>-{
>-	SBI_CALL_4(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, hart_mask,
>-		   start, size, asid);
>-}
>+int sbi_probe_extension(int ext);
>
> #endif
>diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index
>c9179a5..adadbf4 100644
>--- a/arch/riscv/lib/Makefile
>+++ b/arch/riscv/lib/Makefile
>@@ -16,6 +16,7 @@ obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o  else
> obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
>+obj-$(CONFIG_SBI) += sbi.o
> obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
> endif
> obj-y	+= interrupts.o
>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c new file mode 100644
>index 0000000..4b6a9e0
>--- /dev/null
>+++ b/arch/riscv/lib/sbi.c
>@@ -0,0 +1,181 @@
>+// SPDX-License-Identifier: GPL-2.0-only
>+/*
>+ * SBI initialilization and all extension implementation.
>+ *
>+ * Copyright (c) 2020 Western Digital Corporation or its affiliates.
>+ *
>+ * Taken from Linux arch/riscv/kernel/sbi.c  */
>+
>+#include <common.h>
>+#include <asm/encoding.h>
>+#include <asm/sbi.h>
>+
>+/* default SBI version is 0.1 */
>+unsigned long sbi_spec_version = SBI_SPEC_VERSION_DEFAULT;
>+
>+struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
>+			unsigned long arg1, unsigned long arg2,
>+			unsigned long arg3, unsigned long arg4,
>+			unsigned long arg5)
>+{
>+	struct sbiret ret;
>+
>+	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
>+	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
>+	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
>+	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
>+	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
>+	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
>+	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
>+	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
>+	asm volatile ("ecall"
>+		      : "+r" (a0), "+r" (a1)
>+		      : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
>+		      : "memory");
>+	ret.error = a0;
>+	ret.value = a1;
>+
>+	return ret;
>+}
>+
>+/**
>+ * sbi_console_putchar() - Writes given character to the console device.
>+ * @ch: The data to be written to the console.
>+ *
>+ * Return: None
>+ */
>+void sbi_console_putchar(int ch)
>+{
>+	sbi_ecall(SBI_EXT_0_1_CONSOLE_PUTCHAR, 0, ch, 0, 0, 0, 0, 0); }
>+
>+/**
>+ * sbi_console_getchar() - Reads a byte from console device.
>+ *
>+ * Returns the value read from console.
>+ */
>+int sbi_console_getchar(void)
>+{
>+	struct sbiret ret;
>+
>+	ret = sbi_ecall(SBI_EXT_0_1_CONSOLE_GETCHAR, 0, 0, 0, 0, 0, 0, 0);
>+
>+	return ret.error;
>+}
>+
>+/**
>+ * sbi_clear_ipi() - Clear any pending IPIs for the calling hart.
>+ *
>+ * Return: None
>+ */
>+void sbi_clear_ipi(void)
>+{
>+	sbi_ecall(SBI_EXT_0_1_CLEAR_IPI, 0, 0, 0, 0, 0, 0, 0); }
>+
>+/**
>+ * sbi_shutdown() - Remove all the harts from executing supervisor code.
>+ *
>+ * Return: None
>+ */
>+void sbi_shutdown(void)
>+{
>+	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0); }
>+
>+/**
>+ * sbi_set_timer() - Program the timer for next timer event.
>+ * @stime_value: The value after which next timer event should fire.
>+ *
>+ * Return: None
>+ */
>+void sbi_set_timer(uint64_t stime_value) { #if __riscv_xlen == 32
>+	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
>+		  stime_value >> 32, 0, 0, 0, 0);
>+#else
>+	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
>+#endif }
>+
>+/**
>+ * sbi_send_ipi() - Send an IPI to any hart.
>+ * @hart_mask: A cpu mask containing all the target harts.
>+ *
>+ * Return: None
>+ */
>+void sbi_send_ipi(const unsigned long *hart_mask) {
>+	sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
>+		  0, 0, 0, 0, 0);
>+}
>+
>+/**
>+ * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
>+ * @hart_mask: A cpu mask containing all the target harts.
>+ *
>+ * Return: None
>+ */
>+void sbi_remote_fence_i(const unsigned long *hart_mask) {
>+	sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned
>long)hart_mask,
>+		  0, 0, 0, 0, 0);
>+}
>+
>+/**
>+ * sbi_remote_sfence_vma() - Execute SFENCE.VMA instructions on given
>remote
>+ *			     harts for the specified virtual address range.
>+ * @hart_mask: A cpu mask containing all the target harts.
>+ * @start: Start of the virtual address
>+ * @size: Total size of the virtual address range.
>+ *
>+ * Return: None
>+ */
>+void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>+			   unsigned long start,
>+			   unsigned long size)
>+{
>+	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
>+		  (unsigned long)hart_mask, start, size, 0, 0, 0); }
>+
>+/**
>+ * sbi_remote_sfence_vma_asid() - Execute SFENCE.VMA instructions on
>+given
>+ * remote harts for a virtual address range belonging to a specific ASID.
>+ *
>+ * @hart_mask: A cpu mask containing all the target harts.
>+ * @start: Start of the virtual address
>+ * @size: Total size of the virtual address range.
>+ * @asid: The value of address space identifier (ASID).
>+ *
>+ * Return: None
>+ */
>+void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
>+				unsigned long start,
>+				unsigned long size,
>+				unsigned long asid)
>+{
>+	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
>+		  (unsigned long)hart_mask, start, size, asid, 0, 0); }
>+
>+/**
>+ * sbi_probe_extension() - Check if an SBI extension ID is supported or not.
>+ * @extid: The extension ID to be probed.
>+ *
>+ * Return: Extension specific nonzero value f yes, -ENOTSUPP otherwise.
>+ */
>+int sbi_probe_extension(int extid)
>+{
>+	struct sbiret ret;
>+
>+	ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, extid,
>+			0, 0, 0, 0, 0);
>+	if (!ret.error)
>+		if (ret.value)
>+			return ret.value;
>+
>+	return -ENOTSUPP;
>+}

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

>--
>2.7.4

[PATCH 3/5] riscv: Add SBI v0.2 extension definitions

[Pragnesh Patel]

Hi Bin,

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng
>Sent: 10 March 2020 08:05
>To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>;
>Atish Patra <atish.patra@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u-
>boot at lists.denx.de>
>Subject: [PATCH 3/5] riscv: Add SBI v0.2 extension definitions
>
>Few v0.1 SBI calls are being replaced by new SBI calls that follows
>v0.2 calling convention.
>
>This patch just defines these new extensions.
>
>This commit is inspired from Linux kernel patch:
>https://patchwork.kernel.org/patch/11407359/
>
>Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>---
>
> arch/riscv/include/asm/sbi.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>fc8637c..6d3114c 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -22,6 +22,9 @@ enum sbi_ext_id {
> 	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> 	SBI_EXT_0_1_SHUTDOWN = 0x8,
> 	SBI_EXT_BASE = 0x10,
>+	SBI_EXT_TIME = 0x54494D45,
>+	SBI_EXT_IPI = 0x735049,
>+	SBI_EXT_RFENCE = 0x52464E43,
> };
>
> enum sbi_ext_base_fid {
>@@ -34,6 +37,20 @@ enum sbi_ext_base_fid {
> 	SBI_EXT_BASE_GET_MIMPID,
> };
>
>+enum sbi_ext_time_fid {
>+	SBI_EXT_TIME_SET_TIMER = 0,
>+};
>+
>+enum sbi_ext_ipi_fid {
>+	SBI_EXT_IPI_SEND_IPI = 0,
>+};
>+
>+enum sbi_ext_rfence_fid {
>+	SBI_EXT_RFENCE_REMOTE_FENCE_I = 0,
>+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA,
>+	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
>+};
>+
> #define SBI_SPEC_VERSION_DEFAULT	0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
> #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

>--
>2.7.4

[PATCH 4/5] riscv: Introduce a new config for SBI v0.1

[Pragnesh Patel]

Hi Bin,

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng
>Sent: 10 March 2020 08:06
>To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>;
>Atish Patra <atish.patra@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u-
>boot at lists.denx.de>
>Subject: [PATCH 4/5] riscv: Introduce a new config for SBI v0.1
>
>We now have SBI v0.2 which is more scalable and extendable to handle future
>needs for RISC-V supervisor interfaces.
>
>Introduce a new config and move all SBI v0.1 code under that config.
>This allows to implement the new replacement SBI extensions cleanly and
>remove v0.1 extensions easily in future. Currently, the config is enabled by
>default. Once all M-mode software, with v0.1, is no longer in use, this config
>option and all relevant code can be easily removed.
>
>This commit is inspired from Linux kernel patch:
>https://patchwork.kernel.org/patch/11407361/
>
>Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>---
>
> arch/riscv/Kconfig           | 8 ++++++++
> arch/riscv/include/asm/sbi.h | 4 ++++
> arch/riscv/lib/sbi.c         | 4 ++++
> 3 files changed, 16 insertions(+)
>
>diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 09fff05..cc87da7
>100644
>--- a/arch/riscv/Kconfig
>+++ b/arch/riscv/Kconfig
>@@ -214,6 +214,14 @@ config SBI
> 	bool
> 	default y if RISCV_SMODE || SPL_RISCV_SMODE
>
>+config SBI_V01
>+	bool "SBI v0.1 support"
>+	default y
>+	depends on SBI
>+	help
>+	  This config allows kernel to use SBI v0.1 APIs. This will be
>+	  deprecated in future once legacy M-mode software are no longer in
>use.
>+
> config SBI_IPI
> 	bool
> 	depends on SBI
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>6d3114c..c65104f 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -12,6 +12,7 @@
> #include <linux/types.h>
>
> enum sbi_ext_id {
>+#ifdef CONFIG_SBI_V01
> 	SBI_EXT_0_1_SET_TIMER = 0x0,
> 	SBI_EXT_0_1_CONSOLE_PUTCHAR = 0x1,
> 	SBI_EXT_0_1_CONSOLE_GETCHAR = 0x2,
>@@ -21,6 +22,7 @@ enum sbi_ext_id {
> 	SBI_EXT_0_1_REMOTE_SFENCE_VMA = 0x6,
> 	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID = 0x7,
> 	SBI_EXT_0_1_SHUTDOWN = 0x8,
>+#endif
> 	SBI_EXT_BASE = 0x10,
> 	SBI_EXT_TIME = 0x54494D45,
> 	SBI_EXT_IPI = 0x735049,
>@@ -75,10 +77,12 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long
>arg0,
> 			unsigned long arg3, unsigned long arg4,
> 			unsigned long arg5);
>
>+#ifdef CONFIG_SBI_V01
> void sbi_console_putchar(int ch);
> int sbi_console_getchar(void);
> void sbi_clear_ipi(void);
> void sbi_shutdown(void);
>+#endif
> void sbi_set_timer(uint64_t stime_value);  void sbi_send_ipi(const unsigned
>long *hart_mask);  void sbi_remote_fence_i(const unsigned long *hart_mask);
>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 4b6a9e0..604a3a8
>100644
>--- a/arch/riscv/lib/sbi.c
>+++ b/arch/riscv/lib/sbi.c
>@@ -39,6 +39,8 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0,
> 	return ret;
> }
>
>+#ifdef CONFIG_SBI_V01
>+
> /**
>  * sbi_console_putchar() - Writes given character to the console device.
>  * @ch: The data to be written to the console.
>@@ -84,6 +86,8 @@ void sbi_shutdown(void)
> 	sbi_ecall(SBI_EXT_0_1_SHUTDOWN, 0, 0, 0, 0, 0, 0, 0);  }
>
>+#endif /* CONFIG_SBI_V01 */
>+
> /**
>  * sbi_set_timer() - Program the timer for next timer event.
>  * @stime_value: The value after which next timer event should fire.

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

>--
>2.7.4

[PATCH 5/5] riscv: Implement new SBI v0.2 extensions

[Pragnesh Patel]

Hi Bin,

>-----Original Message-----
>From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Bin Meng
>Sent: 10 March 2020 08:06
>To: Rick Chen <rick@andestech.com>; Anup Patel <anup.patel@wdc.com>;
>Atish Patra <atish.patra@wdc.com>; Lukas Auer
><lukas.auer@aisec.fraunhofer.de>; U-Boot Mailing List <u-
>boot at lists.denx.de>
>Subject: [PATCH 5/5] riscv: Implement new SBI v0.2 extensions
>
>Few v0.1 SBI calls are being replaced by new SBI calls that follows
>v0.2 calling convention.
>
>Implement the replacement extensions and few additional new SBI function
>calls that makes way for a better SBI interface in future.
>
>Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
>---
>
> arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++
> arch/riscv/lib/sbi.c         | 16 +++++++++-------
> 2 files changed, 33 insertions(+), 7 deletions(-)
>
>diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index
>c65104f..3595ee8 100644
>--- a/arch/riscv/include/asm/sbi.h
>+++ b/arch/riscv/include/asm/sbi.h
>@@ -53,6 +53,30 @@ enum sbi_ext_rfence_fid {
> 	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
> };
>
>+#ifdef CONFIG_SBI_V01
>+#define SBI_EXT_SET_TIMER		SBI_EXT_0_1_SET_TIMER
>+#define SBI_FID_SET_TIMER		0
>+#define SBI_EXT_SEND_IPI		SBI_EXT_0_1_SEND_IPI
>+#define SBI_FID_SEND_IPI		0
>+#define SBI_EXT_REMOTE_FENCE_I
>	SBI_EXT_0_1_REMOTE_FENCE_I
>+#define SBI_FID_REMOTE_FENCE_I		0
>+#define SBI_EXT_REMOTE_SFENCE_VMA
>	SBI_EXT_0_1_REMOTE_SFENCE_VMA
>+#define SBI_FID_REMOTE_SFENCE_VMA	0
>+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID
>	SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID
>+#define SBI_FID_REMOTE_SFENCE_VMA_ASID	0
>+#else
>+#define SBI_EXT_SET_TIMER		SBI_EXT_TIME
>+#define SBI_FID_SET_TIMER		SBI_EXT_TIME_SET_TIMER
>+#define SBI_EXT_SEND_IPI		SBI_EXT_IPI
>+#define SBI_FID_SEND_IPI		SBI_EXT_IPI_SEND_IPI
>+#define SBI_EXT_REMOTE_FENCE_I		SBI_EXT_RFENCE
>+#define SBI_FID_REMOTE_FENCE_I
>	SBI_EXT_RFENCE_REMOTE_FENCE_I
>+#define SBI_EXT_REMOTE_SFENCE_VMA	SBI_EXT_RFENCE
>+#define SBI_FID_REMOTE_SFENCE_VMA
>	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA
>+#define SBI_EXT_REMOTE_SFENCE_VMA_ASID	SBI_EXT_RFENCE
>+#define SBI_FID_REMOTE_SFENCE_VMA_ASID
>	SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
>+#endif
>+
> #define SBI_SPEC_VERSION_DEFAULT	0x1
> #define SBI_SPEC_VERSION_MAJOR_SHIFT	24
> #define SBI_SPEC_VERSION_MAJOR_MASK	0x7f
>diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 604a3a8..7bdf071
>100644
>--- a/arch/riscv/lib/sbi.c
>+++ b/arch/riscv/lib/sbi.c
>@@ -97,10 +97,11 @@ void sbi_shutdown(void)  void sbi_set_timer(uint64_t
>stime_value)  {  #if __riscv_xlen == 32
>-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
>+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
> 		  stime_value >> 32, 0, 0, 0, 0);
> #else
>-	sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
>+	sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
>+		  0, 0, 0, 0, 0);
> #endif
> }
>
>@@ -112,7 +113,7 @@ void sbi_set_timer(uint64_t stime_value)
>  */
> void sbi_send_ipi(const unsigned long *hart_mask)  {
>-	sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
>+	sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned
>+long)hart_mask,
> 		  0, 0, 0, 0, 0);
> }
>
>@@ -124,8 +125,8 @@ void sbi_send_ipi(const unsigned long *hart_mask)
>  */
> void sbi_remote_fence_i(const unsigned long *hart_mask)  {
>-	sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned
>long)hart_mask,
>-		  0, 0, 0, 0, 0);
>+	sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I,
>+		  (unsigned long)hart_mask, 0, 0, 0, 0, 0);
> }
>
> /**
>@@ -141,7 +142,7 @@ void sbi_remote_sfence_vma(const unsigned long
>*hart_mask,
> 			   unsigned long start,
> 			   unsigned long size)
> {
>-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
>+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA,
>SBI_FID_REMOTE_SFENCE_VMA,
> 		  (unsigned long)hart_mask, start, size, 0, 0, 0);  }
>
>@@ -161,7 +162,8 @@ void sbi_remote_sfence_vma_asid(const unsigned
>long *hart_mask,
> 				unsigned long size,
> 				unsigned long asid)
> {
>-	sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
>+	sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID,
>+		  SBI_FID_REMOTE_SFENCE_VMA_ASID,
> 		  (unsigned long)hart_mask, start, size, asid, 0, 0);  }
>

Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>

>--
>2.7.4

[PATCH 5/5] riscv: Implement new SBI v0.2 extensions

[Atish Patra]

On Mon, Mar 9, 2020 at 7:36 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Few v0.1 SBI calls are being replaced by new SBI calls that follows
> v0.2 calling convention.
>
> Implement the replacement extensions and few additional new SBI
> function calls that makes way for a better SBI interface in future.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/riscv/include/asm/sbi.h | 24 ++++++++++++++++++++++++
>  arch/riscv/lib/sbi.c         | 16 +++++++++-------
>  2 files changed, 33 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index c65104f..3595ee8 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -53,6 +53,30 @@ enum sbi_ext_rfence_fid {
>         SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID,
>  };
>
> +#ifdef CONFIG_SBI_V01
> +#define SBI_EXT_SET_TIMER              SBI_EXT_0_1_SET_TIMER
> +#define SBI_FID_SET_TIMER              0
> +#define SBI_EXT_SEND_IPI               SBI_EXT_0_1_SEND_IPI
> +#define SBI_FID_SEND_IPI               0
> +#define SBI_EXT_REMOTE_FENCE_I         SBI_EXT_0_1_REMOTE_FENCE_I
> +#define SBI_FID_REMOTE_FENCE_I         0
> +#define SBI_EXT_REMOTE_SFENCE_VMA      SBI_EXT_0_1_REMOTE_SFENCE_VMA
> +#define SBI_FID_REMOTE_SFENCE_VMA      0
> +#define SBI_EXT_REMOTE_SFENCE_VMA_ASID SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID
> +#define SBI_FID_REMOTE_SFENCE_VMA_ASID 0
> +#else
> +#define SBI_EXT_SET_TIMER              SBI_EXT_TIME
> +#define SBI_FID_SET_TIMER              SBI_EXT_TIME_SET_TIMER
> +#define SBI_EXT_SEND_IPI               SBI_EXT_IPI
> +#define SBI_FID_SEND_IPI               SBI_EXT_IPI_SEND_IPI
> +#define SBI_EXT_REMOTE_FENCE_I         SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_FENCE_I         SBI_EXT_RFENCE_REMOTE_FENCE_I
> +#define SBI_EXT_REMOTE_SFENCE_VMA      SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_SFENCE_VMA      SBI_EXT_RFENCE_REMOTE_SFENCE_VMA
> +#define SBI_EXT_REMOTE_SFENCE_VMA_ASID SBI_EXT_RFENCE
> +#define SBI_FID_REMOTE_SFENCE_VMA_ASID SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID
> +#endif
> +
>  #define SBI_SPEC_VERSION_DEFAULT       0x1
>  #define SBI_SPEC_VERSION_MAJOR_SHIFT   24
>  #define SBI_SPEC_VERSION_MAJOR_MASK    0x7f
> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c
> index 604a3a8..7bdf071 100644
> --- a/arch/riscv/lib/sbi.c
> +++ b/arch/riscv/lib/sbi.c
> @@ -97,10 +97,11 @@ void sbi_shutdown(void)
>  void sbi_set_timer(uint64_t stime_value)
>  {
>  #if __riscv_xlen == 32
> -       sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value,
> +       sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
>                   stime_value >> 32, 0, 0, 0, 0);
>  #else
> -       sbi_ecall(SBI_EXT_0_1_SET_TIMER, 0, stime_value, 0, 0, 0, 0, 0);
> +       sbi_ecall(SBI_EXT_SET_TIMER, SBI_FID_SET_TIMER, stime_value,
> +                 0, 0, 0, 0, 0);
>  #endif
>  }
>
> @@ -112,7 +113,7 @@ void sbi_set_timer(uint64_t stime_value)
>   */
>  void sbi_send_ipi(const unsigned long *hart_mask)
>  {
> -       sbi_ecall(SBI_EXT_0_1_SEND_IPI, 0, (unsigned long)hart_mask,
> +       sbi_ecall(SBI_EXT_SEND_IPI, SBI_FID_SEND_IPI, (unsigned long)hart_mask,
>                   0, 0, 0, 0, 0);
>  }
>
> @@ -124,8 +125,8 @@ void sbi_send_ipi(const unsigned long *hart_mask)
>   */
>  void sbi_remote_fence_i(const unsigned long *hart_mask)
>  {
> -       sbi_ecall(SBI_EXT_0_1_REMOTE_FENCE_I, 0, (unsigned long)hart_mask,
> -                 0, 0, 0, 0, 0);
> +       sbi_ecall(SBI_EXT_REMOTE_FENCE_I, SBI_FID_REMOTE_FENCE_I,
> +                 (unsigned long)hart_mask, 0, 0, 0, 0, 0);
>  }
>
>  /**
> @@ -141,7 +142,7 @@ void sbi_remote_sfence_vma(const unsigned long *hart_mask,
>                            unsigned long start,
>                            unsigned long size)
>  {
> -       sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA, 0,
> +       sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA, SBI_FID_REMOTE_SFENCE_VMA,
>                   (unsigned long)hart_mask, start, size, 0, 0, 0);
>  }
>
> @@ -161,7 +162,8 @@ void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
>                                 unsigned long size,
>                                 unsigned long asid)
>  {
> -       sbi_ecall(SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID, 0,
> +       sbi_ecall(SBI_EXT_REMOTE_SFENCE_VMA_ASID,
> +                 SBI_FID_REMOTE_SFENCE_VMA_ASID,
>                   (unsigned long)hart_mask, start, size, asid, 0, 0);
>  }
>
This is incorrect. IPI and SFENCE extension in SBI v0.2 accepts hart
mask as a value compared to a pointer to virtual address in SBI v0.1.
Maybe we should move this code to SBI_V01 given that SMP will be
enabled only for M-mode or  SBI_V01 as per your latest patch ?

> --
> 2.7.4
>


-- 
Regards,
Atish