* [PATCH 0/2] Add RZ/G2L POEG support
@ 2022-07-13 13:55 Biju Das
2022-07-13 13:55 ` [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Biju Das
2022-07-13 13:55 ` [PATCH 2/2] drivers: pinctrl: renesas: Add POEG driver support Biju Das
0 siblings, 2 replies; 9+ messages in thread
From: Biju Das @ 2022-07-13 13:55 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Uwe Kleine-König,
linux-renesas-soc, linux-gpio, devicetree, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad
The output pins of the general PWM timer (GPT) can be disabled by using the port
output enabling function for the GPT (POEG). Specifically, either of the
following ways can be used.
* Input level detection of the GTETRGA to GTETRGD pins.
* Output-disable request from the GPT.
* Register settings.
This patch series add support for controlling output disable function using sysfs.
For output disable operation, POEG group needs to be linked with GPT.
Plan to send a follow up patch with renesas,poeg-group as numeric
property in pwm bindings for linking both GPT and POEG devices.
REF->v1:
* Modelled as pincontrol as most of its configuration is intended to be
static and moved driver files from soc to pincontrol directory.
* Updated reg size in dt binding example.
* Updated Kconfig
REF:
https://lore.kernel.org/linux-renesas-soc/20220510151112.16249-1-biju.das.jz@bp.renesas.com/
Biju Das (2):
dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
drivers: pinctrl: renesas: Add POEG driver support
.../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65 ++++++++
drivers/pinctrl/renesas/Kconfig | 2 +
drivers/pinctrl/renesas/Makefile | 2 +
drivers/pinctrl/renesas/poeg/Kconfig | 12 ++
drivers/pinctrl/renesas/poeg/Makefile | 2 +
drivers/pinctrl/renesas/poeg/poeg-rzg2l.c | 147 ++++++++++++++++++
6 files changed, 230 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig
create mode 100644 drivers/pinctrl/renesas/poeg/Makefile
create mode 100644 drivers/pinctrl/renesas/poeg/poeg-rzg2l.c
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-13 13:55 [PATCH 0/2] Add RZ/G2L POEG support Biju Das
@ 2022-07-13 13:55 ` Biju Das
2022-07-15 9:58 ` Krzysztof Kozlowski
2022-07-13 13:55 ` [PATCH 2/2] drivers: pinctrl: renesas: Add POEG driver support Biju Das
1 sibling, 1 reply; 9+ messages in thread
From: Biju Das @ 2022-07-13 13:55 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Uwe Kleine-König,
linux-renesas-soc, linux-gpio, devicetree, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad
Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
REF->v1:
* Modelled as pincontrol as most of its configuration is intended to be
static.
* Updated reg size in example.
---
.../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
new file mode 100644
index 000000000000..7607dd87fa68
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ The output pins of the general PWM timer (GPT) can be disabled by using
+ the port output enabling function for the GPT (POEG). Specifically,
+ either of the following ways can be used.
+ * Input level detection of the GTETRGA to GTETRGD pins.
+ * Output-disable request from the GPT.
+ * Register settings.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-poeg # RZ/G2{L,LC}
+ - renesas,r9a07g054-poeg # RZ/V2L
+ - const: renesas,rzg2l-poeg
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ poeggd: poeg@10049400 {
+ compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
+ reg = <0x10049400 0x400>;
+ interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_POEG_D_RST>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] drivers: pinctrl: renesas: Add POEG driver support
2022-07-13 13:55 [PATCH 0/2] Add RZ/G2L POEG support Biju Das
2022-07-13 13:55 ` [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Biju Das
@ 2022-07-13 13:55 ` Biju Das
1 sibling, 0 replies; 9+ messages in thread
From: Biju Das @ 2022-07-13 13:55 UTC (permalink / raw)
To: Linus Walleij, Philipp Zabel
Cc: Biju Das, Geert Uytterhoeven, Uwe Kleine-König,
linux-renesas-soc, linux-gpio, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
The output pins of the general PWM timer (GPT) can be disabled by
using the port output enabling function for the GPT (POEG).
This patch series add basic support using s/w control through
sysfs to enable/disable output from GPT.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Ref->v1:
* Moved driver files from soc to pincontrol directory
* Updated KConfig
---
drivers/pinctrl/renesas/Kconfig | 2 +
drivers/pinctrl/renesas/Makefile | 2 +
drivers/pinctrl/renesas/poeg/Kconfig | 12 ++
drivers/pinctrl/renesas/poeg/Makefile | 2 +
drivers/pinctrl/renesas/poeg/poeg-rzg2l.c | 147 ++++++++++++++++++++++
5 files changed, 165 insertions(+)
create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig
create mode 100644 drivers/pinctrl/renesas/poeg/Makefile
create mode 100644 drivers/pinctrl/renesas/poeg/poeg-rzg2l.c
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 961007ce7b3a..3e75a7ee7658 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -290,4 +290,6 @@ config PINCTRL_PFC_SHX3
bool "pin control support for SH-X3" if COMPILE_TEST
select PINCTRL_SH_FUNC_GPIO
+source "drivers/pinctrl/renesas/poeg/Kconfig"
+
endmenu
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 5d936c154a6f..53b78c22acad 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -50,6 +50,8 @@ obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
obj-$(CONFIG_PINCTRL_RZG2L) += pinctrl-rzg2l.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
+obj-$(CONFIG_POEG_RZG2L) += poeg/
+
ifeq ($(CONFIG_COMPILE_TEST),y)
CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a
CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a
diff --git a/drivers/pinctrl/renesas/poeg/Kconfig b/drivers/pinctrl/renesas/poeg/Kconfig
new file mode 100644
index 000000000000..efea83a60a11
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0
+config POEG_RZG2L
+ tristate "RZ/G2L poeg support"
+ depends on ARCH_RZG2L
+ depends on PWM_RZG2L_GPT
+ depends on HAS_IOMEM
+ help
+ This driver exposes the General Port Output Enable for PWM found
+ in RZ/G2L.
+
+ To compile this driver as a module, choose M here: the module
+ will be called poeg-rzg2l.
diff --git a/drivers/pinctrl/renesas/poeg/Makefile b/drivers/pinctrl/renesas/poeg/Makefile
new file mode 100644
index 000000000000..cc1ec08d2021
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_POEG_RZG2L) += poeg-rzg2l.o
diff --git a/drivers/pinctrl/renesas/poeg/poeg-rzg2l.c b/drivers/pinctrl/renesas/poeg/poeg-rzg2l.c
new file mode 100644
index 000000000000..3ef6d68be7cf
--- /dev/null
+++ b/drivers/pinctrl/renesas/poeg/poeg-rzg2l.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L Port Output Enable for GPT (POEG) driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#define POEGG 0
+#define POEGG_SSF BIT(3)
+
+struct rzg2l_poeg_chip {
+ struct reset_control *rstc;
+ void __iomem *mmio;
+};
+
+static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 reg, u32 data)
+{
+ iowrite32(data, chip->mmio + reg);
+}
+
+static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip, u32 reg)
+{
+ return ioread32(chip->mmio + reg);
+}
+
+static ssize_t output_disable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev);
+ unsigned int val;
+ u32 reg;
+ int ret;
+
+ ret = kstrtouint(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ reg = rzg2l_poeg_read(chip, POEGG);
+ if (val)
+ reg |= POEGG_SSF;
+ else
+ reg &= ~POEGG_SSF;
+
+ rzg2l_poeg_write(chip, POEGG, reg);
+
+ return ret ? : count;
+}
+
+static ssize_t output_disable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev);
+ u32 reg;
+
+ reg = rzg2l_poeg_read(chip, POEGG);
+
+ return sprintf(buf, "%u\n", (reg & POEGG_SSF) ? 1 : 0);
+}
+static DEVICE_ATTR_RW(output_disable);
+
+static const struct of_device_id rzg2l_poeg_of_table[] = {
+ { .compatible = "renesas,rzg2l-poeg", },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzg2l_poeg_of_table);
+
+static int rzg2l_poeg_probe(struct platform_device *pdev)
+{
+ struct rzg2l_poeg_chip *chip;
+ int ret;
+
+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->mmio = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(chip->mmio))
+ return PTR_ERR(chip->mmio);
+
+ chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(chip->rstc))
+ return dev_err_probe(&pdev->dev, PTR_ERR(chip->rstc),
+ "get reset failed\n");
+
+ ret = reset_control_deassert(chip->rstc);
+ if (ret)
+ return ret;
+
+ pm_runtime_enable(&pdev->dev);
+ platform_set_drvdata(pdev, chip);
+
+ ret = pm_runtime_resume_and_get(&pdev->dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
+ goto err;
+ }
+
+ ret = device_create_file(&pdev->dev, &dev_attr_output_disable);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to create poeg sysfs: %d\n", ret);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(chip->rstc);
+
+ return ret;
+}
+
+static int rzg2l_poeg_remove(struct platform_device *pdev)
+{
+ struct rzg2l_poeg_chip *chip = platform_get_drvdata(pdev);
+
+ device_remove_file(&pdev->dev, &dev_attr_output_disable);
+ pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(chip->rstc);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_poeg_driver = {
+ .driver = {
+ .name = "poeg-rzg2l",
+ .of_match_table = of_match_ptr(rzg2l_poeg_of_table),
+ },
+ .probe = rzg2l_poeg_probe,
+ .remove = rzg2l_poeg_remove,
+};
+module_platform_driver(rzg2l_poeg_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L POEG Driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-13 13:55 ` [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Biju Das
@ 2022-07-15 9:58 ` Krzysztof Kozlowski
2022-07-15 10:17 ` Biju Das
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-15 9:58 UTC (permalink / raw)
To: Biju Das, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On 13/07/2022 15:55, Biju Das wrote:
> Add device tree bindings for the RZ/G2L Port Output Enable for GPT (POEG).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> REF->v1:
> * Modelled as pincontrol as most of its configuration is intended to be
> static.
> * Updated reg size in example.
> ---
> .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> new file mode 100644
> index 000000000000..7607dd87fa68
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description: |
> + The output pins of the general PWM timer (GPT) can be disabled by using
> + the port output enabling function for the GPT (POEG). Specifically,
> + either of the following ways can be used.
> + * Input level detection of the GTETRGA to GTETRGD pins.
> + * Output-disable request from the GPT.
Shouldn't this all be part of GPT? Is this a real separate device in the
SoC?
> + * Register settings.
This is confusing... so you can use POEG to mess up registers of GPT
independently, so GPT does not know it?
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-poeg # RZ/G2{L,LC}
> + - renesas,r9a07g054-poeg # RZ/V2L
> + - const: renesas,rzg2l-poeg
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-15 9:58 ` Krzysztof Kozlowski
@ 2022-07-15 10:17 ` Biju Das
2022-07-18 13:03 ` Krzysztof Kozlowski
0 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2022-07-15 10:17 UTC (permalink / raw)
To: Krzysztof Kozlowski, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Krzysztof Kozlowski,
Thanks for the feedback.
> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
>
> On 13/07/2022 15:55, Biju Das wrote:
> > Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> (POEG).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > REF->v1:
> > * Modelled as pincontrol as most of its configuration is intended to
> be
> > static.
> > * Updated reg size in example.
> > ---
> > .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65
> > +++++++++++++++++++
> > 1 file changed, 65 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> > new file mode 100644
> > index 000000000000..7607dd87fa68
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> > +++ l
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description: |
> > + The output pins of the general PWM timer (GPT) can be disabled by
> > +using
> > + the port output enabling function for the GPT (POEG). Specifically,
> > + either of the following ways can be used.
> > + * Input level detection of the GTETRGA to GTETRGD pins.
> > + * Output-disable request from the GPT.
>
> Shouldn't this all be part of GPT? Is this a real separate device in the
> SoC?
No, It is separate IP block, having its own register block, interrupts and resets.
Please see RFC discussion here[1]
[1] https://lore.kernel.org/linux-renesas-soc/20220517210407.GA1635524-robh@kernel.org/
>
> > + * Register settings.
>
> This is confusing... so you can use POEG to mess up registers of GPT
> independently, so GPT does not know it?
POEG does not mess up registers of GPT. It is basically for protection.
Using POEG register, it is possible to disable GPT output without the knowledge of GPT, after configuring the Output disable source select in the GTINTAD (General PWM Timer Interrupt Output Setting Register) register present in GPT.
Cheers,
Biju
>
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-poeg # RZ/G2{L,LC}
> > + - renesas,r9a07g054-poeg # RZ/V2L
> > + - const: renesas,rzg2l-poeg
> > +
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-15 10:17 ` Biju Das
@ 2022-07-18 13:03 ` Krzysztof Kozlowski
2022-07-18 13:13 ` Biju Das
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-18 13:03 UTC (permalink / raw)
To: Biju Das, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On 15/07/2022 12:17, Biju Das wrote:
> Hi Krzysztof Kozlowski,
>
> Thanks for the feedback.
>
>> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
>> binding
>>
>> On 13/07/2022 15:55, Biju Das wrote:
>>> Add device tree bindings for the RZ/G2L Port Output Enable for GPT
>> (POEG).
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>> ---
>>> REF->v1:
>>> * Modelled as pincontrol as most of its configuration is intended to
>> be
>>> static.
>>> * Updated reg size in example.
>>> ---
>>> .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65
>>> +++++++++++++++++++
>>> 1 file changed, 65 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>> new file mode 100644
>>> index 000000000000..7607dd87fa68
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
>>> +++ l
>>> @@ -0,0 +1,65 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>>> +---
>>> +$id:
>>> +
>>> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
>>> +
>>> +maintainers:
>>> + - Biju Das <biju.das.jz@bp.renesas.com>
>>> +
>>> +description: |
>>> + The output pins of the general PWM timer (GPT) can be disabled by
>>> +using
>>> + the port output enabling function for the GPT (POEG). Specifically,
>>> + either of the following ways can be used.
>>> + * Input level detection of the GTETRGA to GTETRGD pins.
>>> + * Output-disable request from the GPT.
>>
>> Shouldn't this all be part of GPT? Is this a real separate device in the
>> SoC?
>
> No, It is separate IP block, having its own register block, interrupts and resets.
>
> Please see RFC discussion here[1]
>
> [1] https://lore.kernel.org/linux-renesas-soc/20220517210407.GA1635524-robh@kernel.org/
>
>>
>>> + * Register settings.
>>
>> This is confusing... so you can use POEG to mess up registers of GPT
>> independently, so GPT does not know it?
>
> POEG does not mess up registers of GPT. It is basically for protection.
>
> Using POEG register, it is possible to disable GPT output without the knowledge of GPT, after configuring the Output disable source select in the GTINTAD (General PWM Timer Interrupt Output Setting Register) register present in GPT.
Then what does it mean:
"...following ways can be used. Register settings."
I cannot parse it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-18 13:03 ` Krzysztof Kozlowski
@ 2022-07-18 13:13 ` Biju Das
2022-07-21 9:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 9+ messages in thread
From: Biju Das @ 2022-07-18 13:13 UTC (permalink / raw)
To: Krzysztof Kozlowski, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Krzysztof Kozlowski,
> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
>
> On 15/07/2022 12:17, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> > Thanks for the feedback.
> >
> >> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
> >> POEG binding
> >>
> >> On 13/07/2022 15:55, Biju Das wrote:
> >>> Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> >> (POEG).
> >>>
> >>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>> ---
> >>> REF->v1:
> >>> * Modelled as pincontrol as most of its configuration is intended
> >>> to
> >> be
> >>> static.
> >>> * Updated reg size in example.
> >>> ---
> >>> .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65
> >>> +++++++++++++++++++
> >>> 1 file changed, 65 insertions(+)
> >>> create mode 100644
> >>> Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >>>
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >>> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >>> new file mode 100644
> >>> index 000000000000..7607dd87fa68
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.y
> >>> +++ am
> >>> +++ l
> >>> @@ -0,0 +1,65 @@
> >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> >>> +---
> >>> +$id:
> >>> +
> >>> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> >>> +
> >>> +maintainers:
> >>> + - Biju Das <biju.das.jz@bp.renesas.com>
> >>> +
> >>> +description: |
> >>> + The output pins of the general PWM timer (GPT) can be disabled by
> >>> +using
> >>> + the port output enabling function for the GPT (POEG).
> >>> +Specifically,
> >>> + either of the following ways can be used.
> >>> + * Input level detection of the GTETRGA to GTETRGD pins.
> >>> + * Output-disable request from the GPT.
> >>
> >> Shouldn't this all be part of GPT? Is this a real separate device in
> >> the SoC?
> >
> > No, It is separate IP block, having its own register block, interrupts
> and resets.
> >
> > Please see RFC discussion here[1]
> >
> > [1]
> >
> >>
> >>> + * Register settings.
> >>
> >> This is confusing... so you can use POEG to mess up registers of GPT
> >> independently, so GPT does not know it?
> >
> > POEG does not mess up registers of GPT. It is basically for protection.
> >
> > Using POEG register, it is possible to disable GPT output without the
> knowledge of GPT, after configuring the Output disable source select in
> the GTINTAD (General PWM Timer Interrupt Output Setting Register)
> register present in GPT.
>
> Then what does it mean:
> "...following ways can be used. Register settings."
> I cannot parse it.
Threre 3 methods mentioned in chapter 19.3 of RZ/G2L HW manual for Output-Disable Control Operation.
"Register settings" referred to the 3rd method as mentioned below.
19.3 Output-Disable Control Operation
The output of the GTIOCxA and GTIOCxB pins can be disabled when any of the following conditions are satisfied.
1) Input level or edge detection of the GTETRGn pins
When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
2) Output-disable request from the GPT
When POEGGn.IOCE is 1, the POEGGn.IOCF flag is set to 1.
The output-disable requests enabled by GRPDTE, GRPABH, and GRPABL bits of the GTINTAD register in the
GPT are applied to the group selected by GRP[1:0] bits of the GTINTAD register.
3) SSF bit setting
When POEGGn.SSF is set to 1.
The state of the GTIOCxA and the GTIOCxB pins when the output is disabled is controlled by the GPT module.
Please let me know if you need any info.
Cheers,
Biju
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-18 13:13 ` Biju Das
@ 2022-07-21 9:22 ` Krzysztof Kozlowski
2022-07-22 9:18 ` Biju Das
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-21 9:22 UTC (permalink / raw)
To: Biju Das, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On 18/07/2022 15:13, Biju Das wrote:
> Hi Krzysztof Kozlowski,
>
>> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
>> binding
>>
>> On 15/07/2022 12:17, Biju Das wrote:
>>> Hi Krzysztof Kozlowski,
>>>
>>> Thanks for the feedback.
>>>
>>>> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
>>>> POEG binding
>>>>
>>>> On 13/07/2022 15:55, Biju Das wrote:
>>>>> Add device tree bindings for the RZ/G2L Port Output Enable for GPT
>>>> (POEG).
>>>>>
>>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>>>>> ---
>>>>> REF->v1:
>>>>> * Modelled as pincontrol as most of its configuration is intended
>>>>> to
>>>> be
>>>>> static.
>>>>> * Updated reg size in example.
>>>>> ---
>>>>> .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65
>>>>> +++++++++++++++++++
>>>>> 1 file changed, 65 insertions(+)
>>>>> create mode 100644
>>>>> Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>>>> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..7607dd87fa68
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.y
>>>>> +++ am
>>>>> +++ l
>>>>> @@ -0,0 +1,65 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>>>>> +---
>>>>> +$id:
>>>>> +
>>>>> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
>>>>> +
>>>>> +maintainers:
>>>>> + - Biju Das <biju.das.jz@bp.renesas.com>
>>>>> +
>>>>> +description: |
>>>>> + The output pins of the general PWM timer (GPT) can be disabled by
>>>>> +using
>>>>> + the port output enabling function for the GPT (POEG).
>>>>> +Specifically,
>>>>> + either of the following ways can be used.
>>>>> + * Input level detection of the GTETRGA to GTETRGD pins.
>>>>> + * Output-disable request from the GPT.
>>>>
>>>> Shouldn't this all be part of GPT? Is this a real separate device in
>>>> the SoC?
>>>
>>> No, It is separate IP block, having its own register block, interrupts
>> and resets.
>>>
>>> Please see RFC discussion here[1]
>>>
>>> [1]
>>>
>>>>
>>>>> + * Register settings.
>>>>
>>>> This is confusing... so you can use POEG to mess up registers of GPT
>>>> independently, so GPT does not know it?
>>>
>>> POEG does not mess up registers of GPT. It is basically for protection.
>>>
>>> Using POEG register, it is possible to disable GPT output without the
>> knowledge of GPT, after configuring the Output disable source select in
>> the GTINTAD (General PWM Timer Interrupt Output Setting Register)
>> register present in GPT.
>>
>> Then what does it mean:
>> "...following ways can be used. Register settings."
>> I cannot parse it.
>
> Threre 3 methods mentioned in chapter 19.3 of RZ/G2L HW manual for Output-Disable Control Operation.
> "Register settings" referred to the 3rd method as mentioned below.
>
> 19.3 Output-Disable Control Operation
> The output of the GTIOCxA and GTIOCxB pins can be disabled when any of the following conditions are satisfied.
>
> 1) Input level or edge detection of the GTETRGn pins
> When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
>
> 2) Output-disable request from the GPT
> When POEGGn.IOCE is 1, the POEGGn.IOCF flag is set to 1.
> The output-disable requests enabled by GRPDTE, GRPABH, and GRPABL bits of the GTINTAD register in the
> GPT are applied to the group selected by GRP[1:0] bits of the GTINTAD register.
>
> 3) SSF bit setting
> When POEGGn.SSF is set to 1.
>
> The state of the GTIOCxA and the GTIOCxB pins when the output is disabled is controlled by the GPT module.
>
> Please let me know if you need any info.
Yes, more info is needed in your patch. The "...following ways can be
used. (...) Register settings." does not explain anything.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* RE: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding
2022-07-21 9:22 ` Krzysztof Kozlowski
@ 2022-07-22 9:18 ` Biju Das
0 siblings, 0 replies; 9+ messages in thread
From: Biju Das @ 2022-07-22 9:18 UTC (permalink / raw)
To: Krzysztof Kozlowski, Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Uwe Kleine-König, linux-renesas-soc,
linux-gpio, devicetree, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Krzysztof Kozlowski,
Thanks for the feedback.
> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG
> binding
>
> On 18/07/2022 15:13, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
> >> POEG binding
> >>
> >> On 15/07/2022 12:17, Biju Das wrote:
> >>> Hi Krzysztof Kozlowski,
> >>>
> >>> Thanks for the feedback.
> >>>
> >>>> Subject: Re: [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L
> >>>> POEG binding
> >>>>
> >>>> On 13/07/2022 15:55, Biju Das wrote:
> >>>>> Add device tree bindings for the RZ/G2L Port Output Enable for GPT
> >>>> (POEG).
> >>>>>
> >>>>> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >>>>> ---
> >>>>> REF->v1:
> >>>>> * Modelled as pincontrol as most of its configuration is intended
> >>>>> to
> >>>> be
> >>>>> static.
> >>>>> * Updated reg size in example.
> >>>>> ---
> >>>>> .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 65
> >>>>> +++++++++++++++++++
> >>>>> 1 file changed, 65 insertions(+)
> >>>>> create mode 100644
> >>>>> Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml
> >>>>>
> >>>>> diff --git
> >>>>> a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> >>>>> l
> >>>>> b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yam
> >>>>> l
> >>>>> new file mode 100644
> >>>>> index 000000000000..7607dd87fa68
> >>>>> --- /dev/null
> >>>>> +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg
> >>>>> +++ .y
> >>>>> +++ am
> >>>>> +++ l
> >>>>> @@ -0,0 +1,65 @@
> >>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> >>>>> +1.2
> >>>>> +---
> >>>>> +$id:
> >>>>> +
> >>>>> +title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
> >>>>> +
> >>>>> +maintainers:
> >>>>> + - Biju Das <biju.das.jz@bp.renesas.com>
> >>>>> +
> >>>>> +description: |
> >>>>> + The output pins of the general PWM timer (GPT) can be disabled
> >>>>> +by using
> >>>>> + the port output enabling function for the GPT (POEG).
> >>>>> +Specifically,
> >>>>> + either of the following ways can be used.
> >>>>> + * Input level detection of the GTETRGA to GTETRGD pins.
> >>>>> + * Output-disable request from the GPT.
> >>>>
> >>>> Shouldn't this all be part of GPT? Is this a real separate device
> >>>> in the SoC?
> >>>
> >>> No, It is separate IP block, having its own register block,
> >>> interrupts
> >> and resets.
> >>>
> >>> Please see RFC discussion here[1]
> >>>
> >>> [1]
> >>>
> >>>>
> >>>>> + * Register settings.
> >>>>
> >>>> This is confusing... so you can use POEG to mess up registers of
> >>>> GPT independently, so GPT does not know it?
> >>>
> >>> POEG does not mess up registers of GPT. It is basically for
> protection.
> >>>
> >>> Using POEG register, it is possible to disable GPT output without
> >>> the
> >> knowledge of GPT, after configuring the Output disable source select
> >> in the GTINTAD (General PWM Timer Interrupt Output Setting Register)
> >> register present in GPT.
> >>
> >> Then what does it mean:
> >> "...following ways can be used. Register settings."
> >> I cannot parse it.
> >
> > Threre 3 methods mentioned in chapter 19.3 of RZ/G2L HW manual for
> Output-Disable Control Operation.
> > "Register settings" referred to the 3rd method as mentioned below.
> >
> > 19.3 Output-Disable Control Operation
> > The output of the GTIOCxA and GTIOCxB pins can be disabled when any of
> the following conditions are satisfied.
> >
> > 1) Input level or edge detection of the GTETRGn pins
> > When POEGGn.PIDE is 1, the POEGGn.PIDF flag is set to 1.
> >
> > 2) Output-disable request from the GPT When POEGGn.IOCE is 1, the
> > POEGGn.IOCF flag is set to 1.
> > The output-disable requests enabled by GRPDTE, GRPABH, and GRPABL bits
> > of the GTINTAD register in the GPT are applied to the group selected
> by GRP[1:0] bits of the GTINTAD register.
> >
> > 3) SSF bit setting
> > When POEGGn.SSF is set to 1.
> >
> > The state of the GTIOCxA and the GTIOCxB pins when the output is
> disabled is controlled by the GPT module.
> >
> > Please let me know if you need any info.
>
> Yes, more info is needed in your patch. The "...following ways can be
> used. (...) Register settings." does not explain anything.
Ok will update bindings with POEGGn.SSF in "Register settings" section to make it clear.
Cheers,
Biju
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-07-22 9:29 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-13 13:55 [PATCH 0/2] Add RZ/G2L POEG support Biju Das
2022-07-13 13:55 ` [PATCH 1/2] dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding Biju Das
2022-07-15 9:58 ` Krzysztof Kozlowski
2022-07-15 10:17 ` Biju Das
2022-07-18 13:03 ` Krzysztof Kozlowski
2022-07-18 13:13 ` Biju Das
2022-07-21 9:22 ` Krzysztof Kozlowski
2022-07-22 9:18 ` Biju Das
2022-07-13 13:55 ` [PATCH 2/2] drivers: pinctrl: renesas: Add POEG driver support Biju Das
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