* [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-08 0:54 ` Rob Herring
2022-03-03 16:26 ` [PATCH V2 2/7] soc: renesas: Identify " Biju Das
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Lad Prabhakar, devicetree,
Chris Paterson, Biju Das, linux-renesas-soc
Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
SYSC controller found on the RZ/G2UL SoC is almost identical to one found
on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
core0 reset vector address configuration register.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1->V2:
* No change
---
.../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
index bb433e75a0ee..ce372378ff97 100644
--- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
@@ -4,14 +4,14 @@
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
+title: Renesas RZ/{G2L, G2UL, V2L} System Controller (SYSC)
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
- The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
- and supports following functions,
+ The RZ/{G2L, G2UL, V2L} System Controller (SYSC) performs system control of
+ the LSI and supports following functions,
- External terminal state capture function
- 34-bit address space access function
- Low power consumption control
@@ -20,8 +20,9 @@ description:
properties:
compatible:
enum:
- - renesas,r9a07g044-sysc # RZ/G2{L,LC}
- - renesas,r9a07g054-sysc # RZ/V2L
+ - renesas,r9a07g043u-sysc # RZ/G2UL
+ - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+ - renesas,r9a07g054-sysc # RZ/V2L
reg:
maxItems: 1
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
2022-03-03 16:26 ` [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
@ 2022-03-08 0:54 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2022-03-08 0:54 UTC (permalink / raw)
To: Biju Das
Cc: Lad Prabhakar, linux-renesas-soc, Geert Uytterhoeven, devicetree,
Chris Paterson, Biju Das, Rob Herring
On Thu, 03 Mar 2022 16:26:28 +0000, Biju Das wrote:
> Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
> SYSC controller found on the RZ/G2UL SoC is almost identical to one found
> on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
> core0 reset vector address configuration register.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> V1->V2:
> * No change
> ---
> .../devicetree/bindings/power/renesas,rzg2l-sysc.yaml | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V2 2/7] soc: renesas: Identify RZ/G2UL SoC
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
2022-03-03 16:26 ` [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-04 13:06 ` Geert Uytterhoeven
2022-03-03 16:26 ` [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions Biju Das
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Biju Das, Magnus Damm, linux-renesas-soc, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad
Add support for identifying the RZ/G2UL (R9A07G043U) SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Change compatible from r9a07g043u->r9a07g043u11.
---
drivers/soc/renesas/Kconfig | 6 ++++++
drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
2 files changed, 19 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fdc99a05a7e0..f81905d86986 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -296,6 +296,12 @@ config ARCH_R8A774B1
help
This enables support for the Renesas RZ/G2N SoC.
+config ARCH_R9A07G043U
+ bool "ARM64 Platform support for RZ/G2UL"
+ select ARCH_RZG2L
+ help
+ This enables support for the Renesas RZ/G2UL SoC variants.
+
config ARCH_R9A07G044
bool "ARM64 Platform support for RZ/G2L"
select ARCH_RZG2L
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 92c7b42250ee..c667baf4fc59 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
.name = "RZ/G2L",
};
+static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
+ .name = "RZ/G2UL",
+};
+
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
@@ -148,6 +152,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
.id = 0x841c447,
};
+static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
+ .family = &fam_rzg2ul,
+ .id = 0x8450447,
+};
+
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
@@ -340,6 +349,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
#ifdef CONFIG_ARCH_R8A779F0
{ .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
#endif
+#if defined(CONFIG_ARCH_R9A07G043U)
+ { .compatible = "renesas,r9a07g043u11", .data = &soc_rz_g2ul },
+#endif
#if defined(CONFIG_ARCH_R9A07G044)
{ .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
#endif
@@ -378,6 +390,7 @@ static const struct renesas_id id_prr __initconst = {
static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,bsid", .data = &id_bsid },
+ { .compatible = "renesas,r9a07g043u-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,prr", .data = &id_prr },
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH V2 2/7] soc: renesas: Identify RZ/G2UL SoC
2022-03-03 16:26 ` [PATCH V2 2/7] soc: renesas: Identify " Biju Das
@ 2022-03-04 13:06 ` Geert Uytterhoeven
2022-03-04 13:16 ` Biju Das
0 siblings, 1 reply; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-03-04 13:06 UTC (permalink / raw)
To: Biju Das
Cc: Magnus Damm, Linux-Renesas, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Biju,
On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add support for identifying the RZ/G2UL (R9A07G043U) SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -296,6 +296,12 @@ config ARCH_R8A774B1
> help
> This enables support for the Renesas RZ/G2N SoC.
>
> +config ARCH_R9A07G043U
Likewise (cfr. my comments on 1/7), I think this should use
ARCH_R9A07G043 instead.
> + bool "ARM64 Platform support for RZ/G2UL"
> + select ARCH_RZG2L
> + help
> + This enables support for the Renesas RZ/G2UL SoC variants.
> +
> config ARCH_R9A07G044
> bool "ARM64 Platform support for RZ/G2L"
> select ARCH_RZG2L
> diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
> index 92c7b42250ee..c667baf4fc59 100644
> --- a/drivers/soc/renesas/renesas-soc.c
> +++ b/drivers/soc/renesas/renesas-soc.c
> @@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> .name = "RZ/G2L",
> };
>
> +static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
> + .name = "RZ/G2UL",
> +};
> +
> static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
> .name = "RZ/V2L",
> };
> @@ -148,6 +152,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = {
> .id = 0x841c447,
> };
>
> +static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
> + .family = &fam_rzg2ul,
> + .id = 0x8450447,
Rev. 0.51 of the RZ/G2UL Hardware User's Manual still lists the same
ID as RZ/G2L, so I can't check this :-(
> +};
> +
> static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
> .family = &fam_rzv2l,
> .id = 0x8447447,
> @@ -340,6 +349,9 @@ static const struct of_device_id renesas_socs[] __initconst = {
> #ifdef CONFIG_ARCH_R8A779F0
> { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
> #endif
> +#if defined(CONFIG_ARCH_R9A07G043U)
> + { .compatible = "renesas,r9a07g043u11", .data = &soc_rz_g2ul },
"renesas,r9a07g043", so it catches both Type-1 and Type-2 SoCs?
> +#endif
> #if defined(CONFIG_ARCH_R9A07G044)
> { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
> #endif
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread* RE: [PATCH V2 2/7] soc: renesas: Identify RZ/G2UL SoC
2022-03-04 13:06 ` Geert Uytterhoeven
@ 2022-03-04 13:16 ` Biju Das
0 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-03-04 13:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Linux-Renesas, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH V2 2/7] soc: renesas: Identify RZ/G2UL SoC
>
> Hi Biju,
>
> On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add support for identifying the RZ/G2UL (R9A07G043U) SoC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -296,6 +296,12 @@ config ARCH_R8A774B1
> > help
> > This enables support for the Renesas RZ/G2N SoC.
> >
> > +config ARCH_R9A07G043U
>
> Likewise (cfr. my comments on 1/7), I think this should use
> ARCH_R9A07G043 instead.
OK, I will use ARCH_R9A07G043.
>
> > + bool "ARM64 Platform support for RZ/G2UL"
> > + select ARCH_RZG2L
> > + help
> > + This enables support for the Renesas RZ/G2UL SoC variants.
> > +
> > config ARCH_R9A07G044
> > bool "ARM64 Platform support for RZ/G2L"
> > select ARCH_RZG2L
> > diff --git a/drivers/soc/renesas/renesas-soc.c
> > b/drivers/soc/renesas/renesas-soc.c
> > index 92c7b42250ee..c667baf4fc59 100644
> > --- a/drivers/soc/renesas/renesas-soc.c
> > +++ b/drivers/soc/renesas/renesas-soc.c
> > @@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l
> __initconst __maybe_unused = {
> > .name = "RZ/G2L",
> > };
> >
> > +static const struct renesas_family fam_rzg2ul __initconst
> __maybe_unused = {
> > + .name = "RZ/G2UL",
> > +};
> > +
> > static const struct renesas_family fam_rzv2l __initconst __maybe_unused
> = {
> > .name = "RZ/V2L",
> > };
> > @@ -148,6 +152,11 @@ static const struct renesas_soc soc_rz_g2l
> __initconst __maybe_unused = {
> > .id = 0x841c447,
> > };
> >
> > +static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused
> = {
> > + .family = &fam_rzg2ul,
> > + .id = 0x8450447,
>
> Rev. 0.51 of the RZ/G2UL Hardware User's Manual still lists the same ID as
> RZ/G2L, so I can't check this :-(
I got confirmation from HW people this is wrong in HW user's manual and will be fixed in the next version
Of RZ/G2UL Hardware User's Manual.
U-Boot 2020.10 (Feb 25 2022 - 08:13:09 +0000)
CPU: Renesas Electronics CPU rev 1.0
Model: smarc-rzg2ul
DRAM: 896 MiB
SW_ET0_EN: OFF
MMC: sh-sdhi: 0, sh-sdhi: 1
Loading Environment from MMC... OK
In: serial@1004b800
Out: serial@1004b800
Err: serial@1004b800
Net: eth0: ethernet@11c30000
Hit any key to stop autoboot: 0
=> md 0x11020A04
11020a04: 08450447 00001101 00000000 00000000 G.E.............
>
> > +};
> > +
> > static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused =
> {
> > .family = &fam_rzv2l,
> > .id = 0x8447447,
> > @@ -340,6 +349,9 @@ static const struct of_device_id renesas_socs[]
> > __initconst = { #ifdef CONFIG_ARCH_R8A779F0
> > { .compatible = "renesas,r8a779f0", .data = &soc_rcar_s4 },
> > #endif
> > +#if defined(CONFIG_ARCH_R9A07G043U)
> > + { .compatible = "renesas,r9a07g043u11", .data = &soc_rz_g2ul
> > +},
>
> "renesas,r9a07g043", so it catches both Type-1 and Type-2 SoCs?
OK, Will change it to renesas,r9a07g043"
Cheers,
Biju
>
> > +#endif
> > #if defined(CONFIG_ARCH_R9A07G044)
> > { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l },
> > #endif
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
2022-03-03 16:26 ` [PATCH V2 1/7] dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC Biju Das
2022-03-03 16:26 ` [PATCH V2 2/7] soc: renesas: Identify " Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-04 14:00 ` Geert Uytterhoeven
2022-03-03 16:26 ` [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC Biju Das
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, devicetree, Geert Uytterhoeven, Chris Paterson,
Biju Das, Prabhakar Mahadev Lad, linux-renesas-soc
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change
---
include/dt-bindings/clock/r9a07g043u-cpg.h | 186 +++++++++++++++++++++
1 file changed, 186 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a07g043u-cpg.h
diff --git a/include/dt-bindings/clock/r9a07g043u-cpg.h b/include/dt-bindings/clock/r9a07g043u-cpg.h
new file mode 100644
index 000000000000..447f0c2471d3
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G043U CPG Core Clocks */
+#define R9A07G043U_CLK_I 0
+#define R9A07G043U_CLK_I2 1
+#define R9A07G043U_CLK_S0 2
+#define R9A07G043U_CLK_SPI0 3
+#define R9A07G043U_CLK_SPI1 4
+#define R9A07G043U_CLK_SD0 5
+#define R9A07G043U_CLK_SD1 6
+#define R9A07G043U_CLK_M0 7
+#define R9A07G043U_CLK_M2 8
+#define R9A07G043U_CLK_M3 9
+#define R9A07G043U_CLK_HP 10
+#define R9A07G043U_CLK_TSU 11
+#define R9A07G043U_CLK_ZT 12
+#define R9A07G043U_CLK_P0 13
+#define R9A07G043U_CLK_P1 14
+#define R9A07G043U_CLK_P2 15
+#define R9A07G043U_CLK_AT 16
+#define R9A07G043U_OSCCLK 17
+#define R9A07G043U_CLK_P0_DIV2 18
+
+/* R9A07G043U Module Clocks */
+#define R9A07G043U_CA55_SCLK 0
+#define R9A07G043U_CA55_PCLK 1
+#define R9A07G043U_CA55_ATCLK 2
+#define R9A07G043U_CA55_GICCLK 3
+#define R9A07G043U_CA55_PERICLK 4
+#define R9A07G043U_CA55_ACLK 5
+#define R9A07G043U_CA55_TSCLK 6
+#define R9A07G043U_GIC600_GICCLK 7
+#define R9A07G043U_IA55_CLK 8
+#define R9A07G043U_IA55_PCLK 9
+#define R9A07G043U_MHU_PCLK 10
+#define R9A07G043U_SYC_CNT_CLK 11
+#define R9A07G043U_DMAC_ACLK 12
+#define R9A07G043U_DMAC_PCLK 13
+#define R9A07G043U_OSTM0_PCLK 14
+#define R9A07G043U_OSTM1_PCLK 15
+#define R9A07G043U_OSTM2_PCLK 16
+#define R9A07G043U_MTU_X_MCK_MTU3 17
+#define R9A07G043U_POE3_CLKM_POE 18
+#define R9A07G043U_WDT0_PCLK 19
+#define R9A07G043U_WDT0_CLK 20
+#define R9A07G043U_WDT2_PCLK 21
+#define R9A07G043U_WDT2_CLK 22
+#define R9A07G043U_SPI_CLK2 23
+#define R9A07G043U_SPI_CLK 24
+#define R9A07G043U_SDHI0_IMCLK 25
+#define R9A07G043U_SDHI0_IMCLK2 26
+#define R9A07G043U_SDHI0_CLK_HS 27
+#define R9A07G043U_SDHI0_ACLK 28
+#define R9A07G043U_SDHI1_IMCLK 29
+#define R9A07G043U_SDHI1_IMCLK2 30
+#define R9A07G043U_SDHI1_CLK_HS 31
+#define R9A07G043U_SDHI1_ACLK 32
+#define R9A07G043U_ISU_ACLK 33
+#define R9A07G043U_ISU_PCLK 34
+#define R9A07G043U_CRU_SYSCLK 35
+#define R9A07G043U_CRU_VCLK 36
+#define R9A07G043U_CRU_PCLK 37
+#define R9A07G043U_CRU_ACLK 38
+#define R9A07G043U_LCDC_CLK_A 39
+#define R9A07G043U_LCDC_CLK_P 40
+#define R9A07G043U_LCDC_CLK_D 41
+#define R9A07G043U_SSI0_PCLK2 42
+#define R9A07G043U_SSI0_PCLK_SFR 43
+#define R9A07G043U_SSI1_PCLK2 44
+#define R9A07G043U_SSI1_PCLK_SFR 45
+#define R9A07G043U_SSI2_PCLK2 46
+#define R9A07G043U_SSI2_PCLK_SFR 47
+#define R9A07G043U_SSI3_PCLK2 48
+#define R9A07G043U_SSI3_PCLK_SFR 49
+#define R9A07G043U_SRC_CLKP 50
+#define R9A07G043U_USB_U2H0_HCLK 51
+#define R9A07G043U_USB_U2H1_HCLK 52
+#define R9A07G043U_USB_U2P_EXR_CPUCLK 53
+#define R9A07G043U_USB_PCLK 54
+#define R9A07G043U_ETH0_CLK_AXI 55
+#define R9A07G043U_ETH0_CLK_CHI 56
+#define R9A07G043U_ETH1_CLK_AXI 57
+#define R9A07G043U_ETH1_CLK_CHI 58
+#define R9A07G043U_I2C0_PCLK 59
+#define R9A07G043U_I2C1_PCLK 60
+#define R9A07G043U_I2C2_PCLK 61
+#define R9A07G043U_I2C3_PCLK 62
+#define R9A07G043U_SCIF0_CLK_PCK 63
+#define R9A07G043U_SCIF1_CLK_PCK 64
+#define R9A07G043U_SCIF2_CLK_PCK 65
+#define R9A07G043U_SCIF3_CLK_PCK 66
+#define R9A07G043U_SCIF4_CLK_PCK 67
+#define R9A07G043U_SCI0_CLKP 68
+#define R9A07G043U_SCI1_CLKP 69
+#define R9A07G043U_IRDA_CLKP 70
+#define R9A07G043U_RSPI0_CLKB 71
+#define R9A07G043U_RSPI1_CLKB 72
+#define R9A07G043U_RSPI2_CLKB 73
+#define R9A07G043U_CANFD_PCLK 74
+#define R9A07G043U_GPIO_HCLK 75
+#define R9A07G043U_ADC_ADCLK 76
+#define R9A07G043U_ADC_PCLK 77
+#define R9A07G043U_TSU_PCLK 78
+
+/* R9A07G043U Resets */
+#define R9A07G043U_CA55_RST_1_0 0
+#define R9A07G043U_CA55_RST_1_1 1
+#define R9A07G043U_CA55_RST_3_0 2
+#define R9A07G043U_CA55_RST_3_1 3
+#define R9A07G043U_CA55_RST_4 4
+#define R9A07G043U_CA55_RST_5 5
+#define R9A07G043U_CA55_RST_6 6
+#define R9A07G043U_CA55_RST_7 7
+#define R9A07G043U_CA55_RST_8 8
+#define R9A07G043U_CA55_RST_9 9
+#define R9A07G043U_CA55_RST_10 10
+#define R9A07G043U_CA55_RST_11 11
+#define R9A07G043U_CA55_RST_12 12
+#define R9A07G043U_GIC600_GICRESET_N 13
+#define R9A07G043U_GIC600_DBG_GICRESET_N 14
+#define R9A07G043U_IA55_RESETN 15
+#define R9A07G043U_MHU_RESETN 16
+#define R9A07G043U_DMAC_ARESETN 17
+#define R9A07G043U_DMAC_RST_ASYNC 18
+#define R9A07G043U_SYC_RESETN 19
+#define R9A07G043U_OSTM0_PRESETZ 20
+#define R9A07G043U_OSTM1_PRESETZ 21
+#define R9A07G043U_OSTM2_PRESETZ 22
+#define R9A07G043U_MTU_X_PRESET_MTU3 23
+#define R9A07G043U_POE3_RST_M_REG 24
+#define R9A07G043U_WDT0_PRESETN 25
+#define R9A07G043U_WDT2_PRESETN 26
+#define R9A07G043U_SPI_RST 27
+#define R9A07G043U_SDHI0_IXRST 28
+#define R9A07G043U_SDHI1_IXRST 29
+#define R9A07G043U_ISU_ARESETN 30
+#define R9A07G043U_ISU_PRESETN 31
+#define R9A07G043U_CRU_CMN_RSTB 32
+#define R9A07G043U_CRU_PRESETN 33
+#define R9A07G043U_CRU_ARESETN 34
+#define R9A07G043U_SRC_RST 35
+#define R9A07G043U_USB_U2H0_HRESETN 36
+#define R9A07G043U_USB_U2H1_HRESETN 37
+#define R9A07G043U_USB_U2P_EXL_SYSRST 38
+#define R9A07G043U_USB_PRESETN 39
+#define R9A07G043U_I2C0_MRST 40
+#define R9A07G043U_I2C1_MRST 41
+#define R9A07G043U_I2C2_MRST 42
+#define R9A07G043U_I2C3_MRST 43
+#define R9A07G043U_SCI0_RST 44
+#define R9A07G043U_SCI1_RST 45
+#define R9A07G043U_IRDA_RST 46
+#define R9A07G043U_RSPI0_RST 46
+#define R9A07G043U_RSPI1_RST 48
+#define R9A07G043U_RSPI2_RST 49
+#define R9A07G043U_CANFD_RSTP_N 50
+#define R9A07G043U_CANFD_RSTC_N 51
+#define R9A07G043U_GPIO_RSTN 52
+#define R9A07G043U_GPIO_PORT_RESETN 53
+#define R9A07G043U_GPIO_SPARE_RESETN 54
+#define R9A07G043U_TSU_PRESETN 55
+#define R9A07G043U_SSI0_RST_M2_REG 56
+#define R9A07G043U_SSI1_RST_M2_REG 57
+#define R9A07G043U_SSI2_RST_M2_REG 58
+#define R9A07G043U_ETH0_RST_HW_N 59
+#define R9A07G043U_SCIF0_RST_SYSTEM_N 60
+#define R9A07G043U_SCIF1_RST_SYSTEM_N 61
+#define R9A07G043U_SCIF2_RST_SYSTEM_N 62
+#define R9A07G043U_SCIF3_RST_SYSTEM_N 63
+
+/* Type-1 Specific */
+#define R9A07G043U_SSI3_RST_M2_REG 64
+#define R9A07G043U_ETH1_RST_HW_N 65
+#define R9A07G043U_SCIF4_RST_SYSTEM_N 66
+#define R9A07G043U_ADC_PRESETN 67
+#define R9A07G043U_ADC_ADRST_N 68
+#define R9A07G043U_LCDC_RESET_N 69
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions
2022-03-03 16:26 ` [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions Biju Das
@ 2022-03-04 14:00 ` Geert Uytterhoeven
2022-03-15 11:25 ` Biju Das
0 siblings, 1 reply; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-03-04 14:00 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
> clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
> add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
> ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
> 0.51, Nov. 2021).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
> @@ -0,0 +1,186 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2022 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A07G043U CPG Core Clocks */
> +#define R9A07G043U_CLK_I 0
Likewise, please drop the trailing (upper/lower case) "u".
Unfortunately I cannot comment on the list of clocks, as I don't have
access to that part of the documentation yet.
I think it would be good to compare the RZ/G2UL and RZ/Five clock
lists, so we know if we can handle them in a common driver, possibly
even sharing binding definitions, or need to differentiate.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread* RE: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions
2022-03-04 14:00 ` Geert Uytterhoeven
@ 2022-03-15 11:25 ` Biju Das
0 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-03-15 11:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, Linux-Renesas
Hi Geert,
Thanks for the feedback.
@bp.renesas.com>; Linux-
> Renesas <linux-renesas-soc@vger.kernel.org>
> Subject: Re: [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock
> and Reset Definitions
>
> Hi Biju,
>
> On Thu, Mar 3, 2022 at 5:26 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and
> > module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51")
> > and also add Reset definitions referring to registers CPG_RST_* in
> > Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's
> Manual (Rev.
> > 0.51, Nov. 2021).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a07g043u-cpg.h
> > @@ -0,0 +1,186 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2022 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A07G043U_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* R9A07G043U CPG Core Clocks */
> > +#define R9A07G043U_CLK_I 0
>
> Likewise, please drop the trailing (upper/lower case) "u".
>
OK.
> Unfortunately I cannot comment on the list of clocks, as I don't have
> access to that part of the documentation yet.
>
> I think it would be good to compare the RZ/G2UL and RZ/Five clock lists,
> so we know if we can handle them in a common driver, possibly even sharing
> binding definitions, or need to differentiate.
>
OK, I will prepare the patch with
1) Module Clocks/resets common to RZ/G2UL and RZ/Five
2) Module Clocks/resets specifics to RZ/G2UL
Later when we add RZ/Five, will add Module Clocks/resets specifics to RZ/Five.
Is it ok?
Cheers,
Biju
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (2 preceding siblings ...)
2022-03-03 16:26 ` [PATCH V2 3/7] dt-bindings: clock: Add R9A07G043U CPG Clock and Reset Definitions Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-08 0:55 ` Rob Herring
2022-03-03 16:26 ` [PATCH V2 5/7] clk: renesas: Add support for " Biju Das
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change
---
.../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index bd3af8fc616b..256258025c26 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -4,13 +4,13 @@
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode
+title: Renesas RZ/{G2L,G2UL,V2L} Clock Pulse Generator / Module Standby Mode
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description: |
- On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module
+ On Renesas RZ/{G2L,G2UL,V2L} SoC, the CPG (Clock Pulse Generator) and Module
Standby Mode share the same register block.
They provide the following functionalities:
@@ -23,8 +23,9 @@ description: |
properties:
compatible:
enum:
- - renesas,r9a07g044-cpg # RZ/G2{L,LC}
- - renesas,r9a07g054-cpg # RZ/V2L
+ - renesas,r9a07g043u-cpg # RZ/G2UL{Type-1,Type-2}
+ - renesas,r9a07g044-cpg # RZ/G2{L,LC}
+ - renesas,r9a07g054-cpg # RZ/V2L
reg:
maxItems: 1
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC
2022-03-03 16:26 ` [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC Biju Das
@ 2022-03-08 0:55 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2022-03-08 0:55 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Prabhakar Mahadev Lad, devicetree,
Chris Paterson, Stephen Boyd, linux-clk, Michael Turquette,
Biju Das, Rob Herring, linux-renesas-soc
On Thu, 03 Mar 2022 16:26:31 +0000, Biju Das wrote:
> Document the device tree binding for the Renesas RZ/G2UL Type-1
> and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
> SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * No change
> ---
> .../devicetree/bindings/clock/renesas,rzg2l-cpg.yaml | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V2 5/7] clk: renesas: Add support for RZ/G2UL SoC
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (3 preceding siblings ...)
2022-03-03 16:26 ` [PATCH V2 4/7] dt-bindings: clock: renesas: Document RZ/G2UL SoC Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-03 16:26 ` [PATCH V2 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
2022-03-03 16:26 ` [PATCH V2 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
6 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* No change
---
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g043-cpg.c | 157 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.c | 6 ++
drivers/clk/renesas/rzg2l-cpg.h | 1 +
5 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r9a07g043-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index c281f3af5716..63c78f2518e6 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -33,6 +33,7 @@ config CLK_RENESAS
select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R8A779F0 if ARCH_R8A779F0
select CLK_R9A06G032 if ARCH_R9A06G032
+ select CLK_R9A07G043U if ARCH_R9A07G043U
select CLK_R9A07G044 if ARCH_R9A07G044
select CLK_R9A07G054 if ARCH_R9A07G054
select CLK_SH73A0 if ARCH_SH73A0
@@ -160,6 +161,10 @@ config CLK_R8A779F0
config CLK_R9A06G032
bool "RZ/N1D clock support" if COMPILE_TEST
+config CLK_R9A07G043U
+ bool "RZ/G2UL clock support" if COMPILE_TEST
+ select CLK_RZG2L
+
config CLK_R9A07G044
bool "RZ/G2L clock support" if COMPILE_TEST
select CLK_RZG2L
@@ -200,7 +205,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
- bool "Renesas RZ/{G2L,V2L} family clock support" if COMPILE_TEST
+ bool "Renesas RZ/{G2L,G2UL,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index d5e571699a30..814bbdd195dc 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
+obj-$(CONFIG_CLK_R9A07G043U) += r9a07g043-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
new file mode 100644
index 000000000000..2f731e0d5be3
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2UL CPG driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a07g043u-cpg.h>
+
+#include "rzg2l-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R9A07G043U_CLK_P0_DIV2,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+
+ /* Internal Core Clocks */
+ CLK_OSC_DIV1000,
+ CLK_PLL1,
+ CLK_PLL2,
+ CLK_PLL2_DIV2,
+ CLK_PLL2_DIV2_8,
+ CLK_PLL3,
+ CLK_PLL3_DIV2,
+ CLK_PLL3_DIV2_4,
+ CLK_PLL3_DIV2_4_2,
+ CLK_PLL5,
+ CLK_PLL6,
+ CLK_P1_DIV2,
+
+ /* Module Clocks */
+ MOD_CLK_BASE,
+};
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+static const struct cpg_core_clk r9a07g043u_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+
+ /* Internal Core Clocks */
+ DEF_FIXED(".osc", R9A07G043U_OSCCLK, CLK_EXTAL, 1, 1),
+ DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
+ DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
+ DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
+ DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
+ DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
+ DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
+ DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
+ DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
+ DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
+
+ /* Core output clk */
+ DEF_DIV("I", R9A07G043U_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
+ CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("P0", R9A07G043U_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
+ dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_DIV("P1", R9A07G043U_CLK_P1, CLK_PLL3_DIV2_4,
+ DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043U_CLK_P1, 1, 2),
+ DEF_DIV("P2", R9A07G043U_CLK_P2, CLK_PLL3_DIV2_4_2,
+ DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+};
+
+static struct rzg2l_mod_clk r9a07g043u_mod_clks[] = {
+ DEF_MOD("gic", R9A07G043U_GIC600_GICCLK, R9A07G043U_CLK_P1,
+ 0x514, 0),
+ DEF_MOD("ia55_pclk", R9A07G043U_IA55_PCLK, R9A07G043U_CLK_P2,
+ 0x518, 0),
+ DEF_MOD("ia55_clk", R9A07G043U_IA55_CLK, R9A07G043U_CLK_P1,
+ 0x518, 1),
+ DEF_MOD("dmac_aclk", R9A07G043U_DMAC_ACLK, R9A07G043U_CLK_P1,
+ 0x52c, 0),
+ DEF_MOD("dmac_pclk", R9A07G043U_DMAC_PCLK, CLK_P1_DIV2,
+ 0x52c, 1),
+ DEF_MOD("scif0", R9A07G043U_SCIF0_CLK_PCK, R9A07G043U_CLK_P0,
+ 0x584, 0),
+ DEF_MOD("scif1", R9A07G043U_SCIF1_CLK_PCK, R9A07G043U_CLK_P0,
+ 0x584, 1),
+ DEF_MOD("scif2", R9A07G043U_SCIF2_CLK_PCK, R9A07G043U_CLK_P0,
+ 0x584, 2),
+ DEF_MOD("scif3", R9A07G043U_SCIF3_CLK_PCK, R9A07G043U_CLK_P0,
+ 0x584, 3),
+ DEF_MOD("scif4", R9A07G043U_SCIF4_CLK_PCK, R9A07G043U_CLK_P0,
+ 0x584, 4),
+ DEF_MOD("sci0", R9A07G043U_SCI0_CLKP, R9A07G043U_CLK_P0,
+ 0x588, 0),
+ DEF_MOD("sci1", R9A07G043U_SCI1_CLKP, R9A07G043U_CLK_P0,
+ 0x588, 1),
+};
+
+static struct rzg2l_reset r9a07g043u_resets[] = {
+ DEF_RST(R9A07G043U_GIC600_GICRESET_N, 0x814, 0),
+ DEF_RST(R9A07G043U_GIC600_DBG_GICRESET_N, 0x814, 1),
+ DEF_RST(R9A07G043U_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A07G043U_DMAC_ARESETN, 0x82c, 0),
+ DEF_RST(R9A07G043U_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G043U_SCIF0_RST_SYSTEM_N, 0x884, 0),
+ DEF_RST(R9A07G043U_SCIF1_RST_SYSTEM_N, 0x884, 1),
+ DEF_RST(R9A07G043U_SCIF2_RST_SYSTEM_N, 0x884, 2),
+ DEF_RST(R9A07G043U_SCIF3_RST_SYSTEM_N, 0x884, 3),
+ DEF_RST(R9A07G043U_SCIF4_RST_SYSTEM_N, 0x884, 4),
+ DEF_RST(R9A07G043U_SCI0_RST, 0x888, 0),
+ DEF_RST(R9A07G043U_SCI1_RST, 0x888, 1),
+};
+
+static const unsigned int r9a07g043u_crit_mod_clks[] __initconst = {
+ MOD_CLK_BASE + R9A07G043U_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A07G043U_IA55_CLK,
+ MOD_CLK_BASE + R9A07G043U_DMAC_ACLK,
+};
+
+const struct rzg2l_cpg_info r9a07g043u_cpg_info = {
+ /* Core Clocks */
+ .core_clks = r9a07g043u_core_clks,
+ .num_core_clks = ARRAY_SIZE(r9a07g043u_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Critical Module Clocks */
+ .crit_mod_clks = r9a07g043u_crit_mod_clks,
+ .num_crit_mod_clks = ARRAY_SIZE(r9a07g043u_crit_mod_clks),
+
+ /* Module Clocks */
+ .mod_clks = r9a07g043u_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r9a07g043u_mod_clks),
+ .num_hw_mod_clks = R9A07G043U_TSU_PCLK + 1,
+
+ /* Resets */
+ .resets = r9a07g043u_resets,
+ .num_resets = R9A07G043U_LCDC_RESET_N + 1, /* Last reset ID + 1 */
+};
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 486d0656c58a..648eb670e6db 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -947,6 +947,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
}
static const struct of_device_id rzg2l_cpg_match[] = {
+#ifdef CONFIG_CLK_R9A07G043U
+ {
+ .compatible = "renesas,r9a07g043u-cpg",
+ .data = &r9a07g043u_cpg_info,
+ },
+#endif
#ifdef CONFIG_CLK_R9A07G044
{
.compatible = "renesas,r9a07g044-cpg",
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index ce657beaf160..c7f9a37c4156 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -202,6 +202,7 @@ struct rzg2l_cpg_info {
unsigned int num_crit_mod_clks;
};
+extern const struct rzg2l_cpg_info r9a07g043u_cpg_info;
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V2 6/7] arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (4 preceding siblings ...)
2022-03-03 16:26 ` [PATCH V2 5/7] clk: renesas: Add support for " Biju Das
@ 2022-03-03 16:26 ` Biju Das
2022-03-03 16:26 ` [PATCH V2 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Biju Das
6 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add initial DTSI for RZ/G2UL SoC.
Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share
the common dtsi (rz-smarc.dtsi) file. Place holders are added in
device nodes to avoid compilation errors for the devices which have
not been enabled yet on RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Changed soc compatible from r9a07g043u->r9a07g043.
---
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 413 ++++++++++++++++++++
1 file changed, 413 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
new file mode 100644
index 000000000000..b162cc74becd
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SoC
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g043u-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g043";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio_clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio_clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ clocks = <&cpg CPG_CORE R9A07G043U_CLK_I>;
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ssi0: ssi@10049c00 {
+ reg = <0 0x10049c00 0 0x400>;
+ #sound-dai-cells = <0>;
+ /* place holder */
+ };
+
+ spi1: spi@1004b000 {
+ reg = <0 0x1004b000 0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif1: serial@1004bc00 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004bc00 0 0x400>;
+ interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCIF1_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCIF1_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif2: serial@1004c000 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c000 0 0x400>;
+ interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCIF2_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCIF2_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif3: serial@1004c400 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c400 0 0x400>;
+ interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCIF3_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCIF3_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ scif4: serial@1004c800 {
+ compatible = "renesas,scif-r9a07g043",
+ "renesas,scif-r9a07g044";
+ reg = <0 0x1004c800 0 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCIF4_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCIF4_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ sci0: serial@1004d000 {
+ compatible = "renesas,r9a07g043-sci", "renesas,sci";
+ reg = <0 0x1004d000 0 0x400>;
+ interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCI0_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCI0_RST>;
+ status = "disabled";
+ };
+
+ sci1: serial@1004d400 {
+ compatible = "renesas,r9a07g043-sci", "renesas,sci";
+ reg = <0 0x1004d400 0 0x400>;
+ interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD R9A07G043U_SCI1_CLKP>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_SCI1_RST>;
+ status = "disabled";
+ };
+
+ canfd: can@10050000 {
+ reg = <0 0x10050000 0 0x8000>;
+ /* place holder */
+ };
+
+ i2c0: i2c@10058000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058000 0 0x400>;
+ /* place holder */
+ };
+
+ i2c1: i2c@10058400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058400 0 0x400>;
+ /* place holder */
+ };
+
+ i2c3: i2c@10058c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x10058c00 0 0x400>;
+ /* place holder */
+ };
+
+ adc: adc@10059000 {
+ reg = <0 0x10059000 0 0x400>;
+ /* place holder */
+ };
+
+ sbc: spi@10060000 {
+ reg = <0 0x10060000 0 0x10000>,
+ <0 0x20000000 0 0x10000000>,
+ <0 0x10070000 0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* place holder */
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g043u-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g043u-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* place holder */
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a07g043-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A07G043U_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A07G043U_DMAC_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G043U_DMAC_ARESETN>,
+ <&cpg R9A07G043U_DMAC_RST_ASYNC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ sdhi0: mmc@11c00000 {
+ reg = <0x0 0x11c00000 0 0x10000>;
+ /* place holder */
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ /* place holder */
+ };
+
+ phyrst: usbphy-ctrl@11c40000 {
+ reg = <0 0x11c40000 0 0x10000>;
+ /* place holder */
+ };
+
+ ohci0: usb@11c50000 {
+ reg = <0 0x11c50000 0 0x100>;
+ /* place holder */
+ };
+
+ ohci1: usb@11c70000 {
+ reg = <0 0x11c70000 0 0x100>;
+ /* place holder */
+ };
+
+ ehci0: usb@11c50100 {
+ reg = <0 0x11c50100 0 0x100>;
+ /* place holder */
+ };
+
+ ehci1: usb@11c70100 {
+ reg = <0 0x11c70100 0 0x100>;
+ /* place holder */
+ };
+
+ usb2_phy0: usb-phy@11c50200 {
+ reg = <0 0x11c50200 0 0x700>;
+ /* place holder */
+ };
+
+ usb2_phy1: usb-phy@11c70200 {
+ reg = <0 0x11c70200 0 0x700>;
+ /* place holder */
+ };
+
+ hsusb: usb@11c60000 {
+ reg = <0 0x11c60000 0 0x10000>;
+ /* place holder */
+ };
+
+ wdt0: watchdog@12800800 {
+ reg = <0 0x12800800 0 0x400>;
+ /* place holder */
+ };
+
+ wdt2: watchdog@12800400 {
+ reg = <0 0x12800400 0 0x400>;
+ /* place holder */
+ };
+
+ ostm0: timer@12801000 {
+ reg = <0x0 0x12801000 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm1: timer@12801400 {
+ reg = <0x0 0x12801400 0x0 0x400>;
+ /* place holder */
+ };
+
+ ostm2: timer@12801800 {
+ reg = <0x0 0x12801800 0x0 0x400>;
+ /* place holder */
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V2 7/7] arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
2022-03-03 16:26 [PATCH V2 0/7] Add Renesas RZ/G2UL Type-1 {SoC,SMARC EVK} support Biju Das
` (5 preceding siblings ...)
2022-03-03 16:26 ` [PATCH V2 6/7] arm64: dts: renesas: Add initial DTSI " Biju Das
@ 2022-03-03 16:26 ` Biju Das
6 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-03-03 16:26 UTC (permalink / raw)
To: Rob Herring
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11):
- memory
- External input clock
- CPG
- DMA
- SCIF
It shares the same carrier board with RZ/G2L, but the pin mapping is
different. Disable the device nodes which are not tested and delete the
corresponding pinctrl definitions.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Changed soc compatible from r9a07g043u->r9a07g043.
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a07g043u11-smarc.dts | 111 ++++++++++++++++++
.../boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 ++++
3 files changed, 138 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d000f6b131dc..a1217df9cd10 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R9A07G043U) += r9a07g043u11-smarc.dtb
+
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
new file mode 100644
index 000000000000..762bf26d679b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g043u.dtsi"
+#include "rzg2ul-smarc-som.dtsi"
+#include "rz-smarc-common.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043u11";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
+};
+
+&canfd {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ehci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&hsusb {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&i2c1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+
+ wm8978: codec@1a {
+ compatible = "wlf,wm8978";
+ #sound-dai-cells = <0>;
+ reg = <0x1a>;
+ };
+};
+
+&ohci0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ohci1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&phyrst {
+ status = "disabled";
+};
+
+&scif0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+};
+
+&sdhi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-1;
+ /delete-property/ pinctrl-names;
+ /delete-property/ vmmc-supply;
+ status = "disabled";
+};
+
+&spi1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&ssi0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
+
+&usb2_phy1 {
+ /delete-property/ pinctrl-0;
+ /delete-property/ pinctrl-names;
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
new file mode 100644
index 000000000000..3bbb8fcd604c
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2UL SMARC SOM common parts
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/ {
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x38000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread