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From: "tarumizu.kohei@fujitsu.com" <tarumizu.kohei@fujitsu.com>
To: 'Borislav Petkov' <bp@alien8.de>
Cc: "'catalin.marinas@arm.com'" <catalin.marinas@arm.com>,
	"'will@kernel.org'" <will@kernel.org>,
	"'tglx@linutronix.de'" <tglx@linutronix.de>,
	"'mingo@redhat.com'" <mingo@redhat.com>,
	"'dave.hansen@linux.intel.com'" <dave.hansen@linux.intel.com>,
	"'x86@kernel.org'" <x86@kernel.org>,
	"'hpa@zytor.com'" <hpa@zytor.com>,
	"'linux-arm-kernel@lists.infradead.org'" 
	<linux-arm-kernel@lists.infradead.org>,
	"'linux-kernel@vger.kernel.org'" <linux-kernel@vger.kernel.org>
Subject: RE: [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and Intel processors
Date: Mon, 6 Dec 2021 09:30:12 +0000	[thread overview]
Message-ID: <OSBPR01MB203786A1B30C94950DFC50C2806D9@OSBPR01MB2037.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <OSBPR01MB2037B293667A782CEC31C8D9809B9@OSBPR01MB2037.jpnprd01.prod.outlook.com>

>> Also, as dhansen points out, we have already
>> 
>>   /sys/devices/system/cpu/cpu*/cache
>> 
>> so all those knobs belong there on x86.
> 
> Intel MSR and A64FX have hardware prefetcher that affect L1d cache and
> L2 cache. Does it suit your intention to create a prefetcher directory
> under the cache directory as below?
> 
> /sys/devices/system/cpu/cpu*/cache/
>                 index0/prefetcher/enable
>                 index2/prefetcher/enable
> 
> The above example presumes that the L1d cache is at index0 (level: 1,
> type: Data) and the L2 cache is at index2 (level:2, type: Unified).

Any comment or suggestion would be much appreciated. In particular,
is our using cache/index directory above match your intent?

WARNING: multiple messages have this Message-ID (diff)
From: "tarumizu.kohei@fujitsu.com" <tarumizu.kohei@fujitsu.com>
To: 'Borislav Petkov' <bp@alien8.de>
Cc: "'catalin.marinas@arm.com'" <catalin.marinas@arm.com>,
	"'will@kernel.org'" <will@kernel.org>,
	"'tglx@linutronix.de'" <tglx@linutronix.de>,
	"'mingo@redhat.com'" <mingo@redhat.com>,
	"'dave.hansen@linux.intel.com'" <dave.hansen@linux.intel.com>,
	"'x86@kernel.org'" <x86@kernel.org>,
	"'hpa@zytor.com'" <hpa@zytor.com>,
	"'linux-arm-kernel@lists.infradead.org'"
	<linux-arm-kernel@lists.infradead.org>,
	"'linux-kernel@vger.kernel.org'" <linux-kernel@vger.kernel.org>
Subject: RE: [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and Intel processors
Date: Mon, 6 Dec 2021 09:30:12 +0000	[thread overview]
Message-ID: <OSBPR01MB203786A1B30C94950DFC50C2806D9@OSBPR01MB2037.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <OSBPR01MB2037B293667A782CEC31C8D9809B9@OSBPR01MB2037.jpnprd01.prod.outlook.com>

>> Also, as dhansen points out, we have already
>> 
>>   /sys/devices/system/cpu/cpu*/cache
>> 
>> so all those knobs belong there on x86.
> 
> Intel MSR and A64FX have hardware prefetcher that affect L1d cache and
> L2 cache. Does it suit your intention to create a prefetcher directory
> under the cache directory as below?
> 
> /sys/devices/system/cpu/cpu*/cache/
>                 index0/prefetcher/enable
>                 index2/prefetcher/enable
> 
> The above example presumes that the L1d cache is at index0 (level: 1,
> type: Data) and the L2 cache is at index2 (level:2, type: Unified).

Any comment or suggestion would be much appreciated. In particular,
is our using cache/index directory above match your intent?
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-12-06  9:30 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-04  5:21 [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and Intel processors Kohei Tarumizu
2021-11-04  5:21 ` Kohei Tarumizu
2021-11-04  5:21 ` [RFC PATCH v2 1/5] driver: hwpf: Add hardware prefetch core driver register/unregister functions Kohei Tarumizu
2021-11-04  5:21   ` Kohei Tarumizu
2021-11-04  5:21 ` [RFC PATCH v2 2/5] driver: hwpf: Add support for A64FX to hardware prefetch driver Kohei Tarumizu
2021-11-04  5:21   ` Kohei Tarumizu
2021-11-04  5:21 ` [RFC PATCH v2 3/5] driver: hwpf: Add support for Intel " Kohei Tarumizu
2021-11-04  5:21   ` Kohei Tarumizu
2021-11-08  1:51   ` Dave Hansen
2021-11-08  1:51     ` Dave Hansen
2021-11-09  9:44     ` tarumizu.kohei
2021-11-09  9:44       ` tarumizu.kohei
2021-11-04  5:21 ` [RFC PATCH v2 4/5] driver: hwpf: Add Kconfig/Makefile to build " Kohei Tarumizu
2021-11-04  5:21   ` Kohei Tarumizu
2021-11-04  5:21 ` [RFC PATCH v2 5/5] docs: ABI: Add sysfs documentation interface of " Kohei Tarumizu
2021-11-04  5:21   ` Kohei Tarumizu
2021-11-04 14:55   ` Dave Hansen
2021-11-04 14:55     ` Dave Hansen
2021-11-08  1:29     ` tarumizu.kohei
2021-11-08  1:29       ` tarumizu.kohei
2021-11-08  1:49       ` Dave Hansen
2021-11-08  1:49         ` Dave Hansen
2021-11-09  9:41         ` tarumizu.kohei
2021-11-09  9:41           ` tarumizu.kohei
2021-11-09 17:44           ` Dave Hansen
2021-11-09 17:44             ` Dave Hansen
2021-11-10  9:25             ` tarumizu.kohei
2021-11-10  9:25               ` tarumizu.kohei
2021-11-04 15:13 ` [RFC PATCH v2 0/5] Add hardware prefetch driver for A64FX and Intel processors Borislav Petkov
2021-11-04 15:13   ` Borislav Petkov
2021-11-08  2:17   ` tarumizu.kohei
2021-11-08  2:17     ` tarumizu.kohei
2021-11-10  8:34     ` Borislav Petkov
2021-11-10  8:34       ` Borislav Petkov
2021-11-18  6:14       ` tarumizu.kohei
2021-11-18  6:14         ` tarumizu.kohei
2021-11-18  7:09         ` tarumizu.kohei
2021-11-18  7:09           ` tarumizu.kohei
2021-12-06  9:30           ` tarumizu.kohei [this message]
2021-12-06  9:30             ` tarumizu.kohei
2021-11-04 17:10 ` Peter Zijlstra
2021-11-04 17:10   ` Peter Zijlstra
2021-11-08  2:36   ` tarumizu.kohei
2021-11-08  2:36     ` tarumizu.kohei

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